2 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * Designware High-Definition Multimedia Interface (HDMI) driver
16 #include <linux/module.h>
17 #include <linux/irq.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/hdmi.h>
22 #include <linux/mutex.h>
23 #include <linux/of_device.h>
24 #include <linux/spinlock.h>
26 #include <drm/drm_of.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_encoder_slave.h>
32 #include <drm/drm_scdc_helper.h>
33 #include <drm/bridge/dw_hdmi.h>
35 #include <linux/switch.h>
39 #include "dw-hdmi-audio.h"
41 #define HDMI_EDID_LEN 512
42 #define DDC_SEGMENT_ADDR 0x30
46 #define YCBCR422_16BITS 2
47 #define YCBCR422_8BITS 3
66 * Unless otherwise noted, entries in this table are 100% optimization.
67 * Values can be obtained from hdmi_compute_n() but that function is
68 * slow so we pre-compute values we expect to see.
70 * All 32k and 48k values are expected to be the same (due to the way
71 * the math works) for any rate that's an exact kHz.
73 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
74 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
75 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
76 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
77 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
78 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
79 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
80 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
81 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
82 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
83 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
84 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
85 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
86 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
87 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
88 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
89 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
90 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
91 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
92 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
93 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
94 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
95 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
96 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
97 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
98 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
99 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
100 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
101 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
102 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
103 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
104 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
105 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
106 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
107 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
108 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
109 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
110 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
112 /* For 297 MHz+ HDMI spec have some other rule for setting N */
113 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
114 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
117 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
121 static const u16 csc_coeff_default[3][4] = {
122 { 0x2000, 0x0000, 0x0000, 0x0000 },
123 { 0x0000, 0x2000, 0x0000, 0x0000 },
124 { 0x0000, 0x0000, 0x2000, 0x0000 }
127 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
128 { 0x2000, 0x6926, 0x74fd, 0x010e },
129 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
130 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
133 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
134 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
135 { 0x2000, 0x3264, 0x0000, 0x7e6d },
136 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
139 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
140 { 0x2591, 0x1322, 0x074b, 0x0000 },
141 { 0x6535, 0x2000, 0x7acc, 0x0200 },
142 { 0x6acd, 0x7534, 0x2000, 0x0200 }
145 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
146 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
147 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
148 { 0x6756, 0x78ab, 0x2000, 0x0200 }
152 bool mdataenablepolarity;
154 unsigned int mpixelclock;
155 unsigned int mpixelrepetitioninput;
156 unsigned int mpixelrepetitionoutput;
159 struct hdmi_data_info {
160 unsigned int enc_in_format;
161 unsigned int enc_out_format;
162 unsigned int enc_color_depth;
163 unsigned int colorimetry;
164 unsigned int pix_repet_factor;
165 unsigned int hdcp_enable;
166 struct hdmi_vmode video_mode;
170 struct i2c_adapter adap;
173 struct completion cmp;
182 struct drm_connector connector;
183 struct drm_encoder *encoder;
184 struct drm_bridge *bridge;
186 struct platform_device *audio;
187 enum dw_hdmi_devtype dev_type;
189 struct clk *isfr_clk;
190 struct clk *iahb_clk;
191 struct dw_hdmi_i2c *i2c;
193 struct hdmi_data_info hdmi_data;
194 const struct dw_hdmi_plat_data *plat_data;
198 u8 edid[HDMI_EDID_LEN];
202 struct drm_display_mode previous_mode;
204 struct i2c_adapter *ddc;
209 struct mutex mutex; /* for state below and previous_mode */
210 enum drm_connector_force force; /* mutex-protected force state */
211 bool disabled; /* DRM has disabled our bridge */
212 bool bridge_is_on; /* indicates the bridge is on */
213 bool rxsense; /* rxsense state */
214 u8 phy_mask; /* desired phy int mask settings */
216 spinlock_t audio_lock;
217 struct mutex audio_mutex;
218 unsigned int sample_rate;
219 unsigned int audio_cts;
220 unsigned int audio_n;
224 struct switch_dev switchdev;
228 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
229 u8 (*read)(struct dw_hdmi *hdmi, int offset);
232 #define HDMI_IH_PHY_STAT0_RX_SENSE \
233 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
234 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
236 #define HDMI_PHY_RX_SENSE \
237 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
238 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
240 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
242 writel(val, hdmi->regs + (offset << 2));
245 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
247 return readl(hdmi->regs + (offset << 2));
250 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
252 writeb(val, hdmi->regs + offset);
255 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
257 return readb(hdmi->regs + offset);
260 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
262 hdmi->write(hdmi, val, offset);
265 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
267 return hdmi->read(hdmi, offset);
270 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
272 u8 val = hdmi_readb(hdmi, reg) & ~mask;
275 hdmi_writeb(hdmi, val, reg);
278 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
281 hdmi_modb(hdmi, data << shift, mask, reg);
284 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
287 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
289 /* Set Standard Mode speed */
290 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
291 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
293 /* Set done, not acknowledged and arbitration interrupt polarities */
294 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
295 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
298 /* Clear DONE and ERROR interrupts */
299 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
302 /* Mute DONE and ERROR interrupts */
303 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
304 HDMI_IH_MUTE_I2CM_STAT0);
307 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
308 unsigned char *buf, unsigned int length)
310 struct dw_hdmi_i2c *i2c = hdmi->i2c;
313 if (!i2c->is_regaddr) {
314 dev_dbg(hdmi->dev, "set read register address to 0\n");
315 i2c->slave_reg = 0x00;
316 i2c->is_regaddr = true;
320 reinit_completion(&i2c->cmp);
322 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
324 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
325 HDMI_I2CM_OPERATION);
327 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
328 HDMI_I2CM_OPERATION);
330 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
334 /* Check for error condition on the bus */
335 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
338 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
340 i2c->is_segment = false;
345 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
346 unsigned char *buf, unsigned int length)
348 struct dw_hdmi_i2c *i2c = hdmi->i2c;
351 if (!i2c->is_regaddr) {
352 /* Use the first write byte as register address */
353 i2c->slave_reg = buf[0];
356 i2c->is_regaddr = true;
360 reinit_completion(&i2c->cmp);
362 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
363 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
364 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
365 HDMI_I2CM_OPERATION);
367 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
371 /* Check for error condition on the bus */
372 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
379 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
380 struct i2c_msg *msgs, int num)
382 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
383 struct dw_hdmi_i2c *i2c = hdmi->i2c;
384 u8 addr = msgs[0].addr;
387 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
389 for (i = 0; i < num; i++) {
390 if (msgs[i].len == 0) {
392 "unsupported transfer %d/%d, no data\n",
398 mutex_lock(&i2c->lock);
400 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
402 /* Set slave device address taken from the first I2C message */
403 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
405 /* Set slave device register address on transfer */
406 i2c->is_regaddr = false;
408 /* Set segment pointer for I2C extended read mode operation */
409 i2c->is_segment = false;
411 for (i = 0; i < num; i++) {
412 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
413 i + 1, num, msgs[i].len, msgs[i].flags);
414 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
415 i2c->is_segment = true;
416 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
417 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
419 if (msgs[i].flags & I2C_M_RD)
420 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
423 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
433 /* Mute DONE and ERROR interrupts */
434 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
435 HDMI_IH_MUTE_I2CM_STAT0);
437 mutex_unlock(&i2c->lock);
442 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
444 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
447 static const struct i2c_algorithm dw_hdmi_algorithm = {
448 .master_xfer = dw_hdmi_i2c_xfer,
449 .functionality = dw_hdmi_i2c_func,
452 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
454 struct i2c_adapter *adap;
455 struct dw_hdmi_i2c *i2c;
458 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
460 return ERR_PTR(-ENOMEM);
462 mutex_init(&i2c->lock);
463 init_completion(&i2c->cmp);
466 adap->class = I2C_CLASS_DDC;
467 adap->owner = THIS_MODULE;
468 adap->dev.parent = hdmi->dev;
469 adap->dev.of_node = hdmi->dev->of_node;
470 adap->algo = &dw_hdmi_algorithm;
471 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
472 i2c_set_adapdata(adap, hdmi);
474 ret = i2c_add_adapter(adap);
476 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
477 devm_kfree(hdmi->dev, i2c);
483 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
488 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
491 /* Must be set/cleared first */
492 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
494 /* nshift factor = 0 */
495 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
497 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
498 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
499 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
500 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
502 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
503 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
504 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
507 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
508 unsigned long pixel_clk,
511 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
512 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
515 if (plat_data->tmds_n_table) {
516 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
517 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
518 tmds_n = &plat_data->tmds_n_table[i];
524 if (tmds_n == NULL) {
525 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
526 if (pixel_clk == common_tmds_n_table[i].tmds) {
527 tmds_n = &common_tmds_n_table[i];
538 return tmds_n->n_32k;
542 return (freq / 44100) * tmds_n->n_44k1;
546 return (freq / 48000) * tmds_n->n_48k;
552 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
553 unsigned int pixel_clk)
558 final = (u64)pixel_clk * n;
561 do_div(cts, 128 * freq);
563 diff = final - (u64)cts * (128 * freq);
568 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
569 unsigned long pixel_clk,
572 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
573 unsigned int max_n = (128 * freq) / 300;
574 unsigned int ideal_n = (128 * freq) / 1000;
575 unsigned int best_n_distance = ideal_n;
576 unsigned int best_n = 0;
577 u64 best_diff = U64_MAX;
580 /* If the ideal N could satisfy the audio math, then just take it */
581 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
584 for (n = min_n; n <= max_n; n++) {
585 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
587 if (diff < best_diff || (diff == best_diff &&
588 abs(n - ideal_n) < best_n_distance)) {
591 best_n_distance = abs(best_n - ideal_n);
595 * The best N already satisfy the audio math, and also be
596 * the closest value to ideal N, so just cut the loop.
598 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
605 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
606 unsigned long sample_rate)
610 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
614 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
617 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
620 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
621 unsigned long pixel_clk, unsigned int sample_rate)
623 unsigned long ftdms = pixel_clk;
627 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
630 * Compute the CTS value from the N value. Note that CTS and N
631 * can be up to 20 bits in total, so we need 64-bit math. Also
632 * note that our TDMS clock is not fully accurate; it is accurate
633 * to kHz. This can introduce an unnecessary remainder in the
634 * calculation below, so we don't try to warn about that.
636 tmp = (u64)ftdms * n;
637 do_div(tmp, 128 * sample_rate);
640 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
641 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
644 spin_lock_irq(&hdmi->audio_lock);
646 hdmi->audio_cts = cts;
647 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
648 spin_unlock_irq(&hdmi->audio_lock);
651 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
653 mutex_lock(&hdmi->audio_mutex);
654 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
655 mutex_unlock(&hdmi->audio_mutex);
658 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
660 mutex_lock(&hdmi->audio_mutex);
661 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
663 mutex_unlock(&hdmi->audio_mutex);
666 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
668 mutex_lock(&hdmi->audio_mutex);
669 hdmi->sample_rate = rate;
670 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
672 mutex_unlock(&hdmi->audio_mutex);
674 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
676 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
680 spin_lock_irqsave(&hdmi->audio_lock, flags);
681 hdmi->audio_enable = true;
682 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
683 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
685 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
687 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
691 spin_lock_irqsave(&hdmi->audio_lock, flags);
692 hdmi->audio_enable = false;
693 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
694 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
696 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
699 * this submodule is responsible for the video data synchronization.
700 * for example, for RGB 4:4:4 input, the data map is defined as
701 * pin{47~40} <==> R[7:0]
702 * pin{31~24} <==> G[7:0]
703 * pin{15~8} <==> B[7:0]
705 static void hdmi_video_sample(struct dw_hdmi *hdmi)
707 int color_format = 0;
710 if (hdmi->hdmi_data.enc_in_format == RGB) {
711 if (hdmi->hdmi_data.enc_color_depth == 8)
713 else if (hdmi->hdmi_data.enc_color_depth == 10)
715 else if (hdmi->hdmi_data.enc_color_depth == 12)
717 else if (hdmi->hdmi_data.enc_color_depth == 16)
721 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444 ||
722 hdmi->hdmi_data.enc_in_format == YCBCR420) {
723 if (hdmi->hdmi_data.enc_color_depth == 8)
725 else if (hdmi->hdmi_data.enc_color_depth == 10)
727 else if (hdmi->hdmi_data.enc_color_depth == 12)
729 else if (hdmi->hdmi_data.enc_color_depth == 16)
733 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
734 if (hdmi->hdmi_data.enc_color_depth == 8)
736 else if (hdmi->hdmi_data.enc_color_depth == 10)
738 else if (hdmi->hdmi_data.enc_color_depth == 12)
744 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
745 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
746 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
747 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
749 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
750 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
751 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
752 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
753 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
754 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
755 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
756 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
757 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
758 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
759 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
762 static int is_color_space_conversion(struct dw_hdmi *hdmi)
764 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
767 static int is_color_space_decimation(struct dw_hdmi *hdmi)
769 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
771 if (hdmi->hdmi_data.enc_in_format == RGB ||
772 hdmi->hdmi_data.enc_in_format == YCBCR444)
777 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
779 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
781 if (hdmi->hdmi_data.enc_out_format == RGB ||
782 hdmi->hdmi_data.enc_out_format == YCBCR444)
787 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
789 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
793 if (is_color_space_conversion(hdmi)) {
794 if (hdmi->hdmi_data.enc_out_format == RGB) {
795 if (hdmi->hdmi_data.colorimetry ==
796 HDMI_COLORIMETRY_ITU_601)
797 csc_coeff = &csc_coeff_rgb_out_eitu601;
799 csc_coeff = &csc_coeff_rgb_out_eitu709;
800 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
801 if (hdmi->hdmi_data.colorimetry ==
802 HDMI_COLORIMETRY_ITU_601)
803 csc_coeff = &csc_coeff_rgb_in_eitu601;
805 csc_coeff = &csc_coeff_rgb_in_eitu709;
810 /* The CSC registers are sequential, alternating MSB then LSB */
811 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
812 u16 coeff_a = (*csc_coeff)[0][i];
813 u16 coeff_b = (*csc_coeff)[1][i];
814 u16 coeff_c = (*csc_coeff)[2][i];
816 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
817 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
818 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
819 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
820 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
821 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
824 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
828 static void hdmi_video_csc(struct dw_hdmi *hdmi)
831 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
834 /* YCC422 interpolation to 444 mode */
835 if (is_color_space_interpolation(hdmi))
836 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
837 else if (is_color_space_decimation(hdmi))
838 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
840 if (hdmi->hdmi_data.enc_color_depth == 8)
841 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
842 else if (hdmi->hdmi_data.enc_color_depth == 10)
843 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
844 else if (hdmi->hdmi_data.enc_color_depth == 12)
845 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
846 else if (hdmi->hdmi_data.enc_color_depth == 16)
847 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
851 /* Configure the CSC registers */
852 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
853 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
856 dw_hdmi_update_csc_coeffs(hdmi);
860 * HDMI video packetizer is used to packetize the data.
861 * for example, if input is YCC422 mode or repeater is used,
862 * data should be repacked this module can be bypassed.
864 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
866 unsigned int color_depth = 0;
867 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
868 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
869 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
872 if (hdmi_data->enc_out_format == RGB ||
873 hdmi_data->enc_out_format == YCBCR444 ||
874 hdmi_data->enc_out_format == YCBCR420) {
875 if (!hdmi_data->enc_color_depth) {
876 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
877 } else if (hdmi_data->enc_color_depth == 8) {
879 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
880 } else if (hdmi_data->enc_color_depth == 10) {
882 } else if (hdmi_data->enc_color_depth == 12) {
884 } else if (hdmi_data->enc_color_depth == 16) {
889 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
890 if (!hdmi_data->enc_color_depth ||
891 hdmi_data->enc_color_depth == 8)
892 remap_size = HDMI_VP_REMAP_YCC422_16bit;
893 else if (hdmi_data->enc_color_depth == 10)
894 remap_size = HDMI_VP_REMAP_YCC422_20bit;
895 else if (hdmi_data->enc_color_depth == 12)
896 remap_size = HDMI_VP_REMAP_YCC422_24bit;
899 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
904 /* set the packetizer registers */
905 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
906 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
907 ((hdmi_data->pix_repet_factor <<
908 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
909 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
910 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
912 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
913 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
915 /* Data from pixel repeater block */
916 if (hdmi_data->pix_repet_factor > 0) {
917 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
918 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
919 } else { /* data from packetizer block */
920 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
921 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
924 hdmi_modb(hdmi, vp_conf,
925 HDMI_VP_CONF_PR_EN_MASK |
926 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
928 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
929 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
931 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
933 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
934 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
935 HDMI_VP_CONF_PP_EN_ENABLE |
936 HDMI_VP_CONF_YCC422_EN_DISABLE;
937 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
938 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
939 HDMI_VP_CONF_PP_EN_DISABLE |
940 HDMI_VP_CONF_YCC422_EN_ENABLE;
941 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
942 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
943 HDMI_VP_CONF_PP_EN_DISABLE |
944 HDMI_VP_CONF_YCC422_EN_DISABLE;
949 hdmi_modb(hdmi, vp_conf,
950 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
951 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
953 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
954 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
955 HDMI_VP_STUFF_PP_STUFFING_MASK |
956 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
958 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
962 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
965 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
966 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
969 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
972 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
973 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
976 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
979 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
980 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
983 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
986 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
989 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
992 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
995 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
999 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1004 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1009 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1012 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1013 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1014 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1015 HDMI_PHY_I2CM_DATAO_1_ADDR);
1016 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1017 HDMI_PHY_I2CM_DATAO_0_ADDR);
1018 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1019 HDMI_PHY_I2CM_OPERATION_ADDR);
1020 hdmi_phy_wait_i2c_done(hdmi, 1000);
1023 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1026 __hdmi_phy_i2c_write(hdmi, data, addr);
1030 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1032 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1033 HDMI_PHY_CONF0_PDZ_OFFSET,
1034 HDMI_PHY_CONF0_PDZ_MASK);
1037 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1039 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1040 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1041 HDMI_PHY_CONF0_ENTMDS_MASK);
1044 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1046 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1047 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1048 HDMI_PHY_CONF0_SPARECTRL_MASK);
1051 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1053 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1054 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1055 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1058 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1060 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1061 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1062 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1065 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1067 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1068 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1069 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1072 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1074 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1075 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1076 HDMI_PHY_CONF0_SELDIPIF_MASK);
1079 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1080 unsigned char res, int cscon)
1083 u8 val, msec, tmds_cfg;
1084 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1085 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1086 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1087 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1093 case 0: /* color resolution 0 is 8 bit colour depth */
1095 res_idx = DW_HDMI_RES_8;
1098 res_idx = DW_HDMI_RES_10;
1101 res_idx = DW_HDMI_RES_12;
1107 /* PLL/MPLL Cfg - always match on final entry */
1108 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1109 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1110 mpll_config->mpixelclock)
1113 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1114 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1115 curr_ctrl->mpixelclock)
1118 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1119 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1120 phy_config->mpixelclock)
1123 if (mpll_config->mpixelclock == ~0UL ||
1124 curr_ctrl->mpixelclock == ~0UL ||
1125 phy_config->mpixelclock == ~0UL) {
1126 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1127 hdmi->hdmi_data.video_mode.mpixelclock);
1131 /* Enable csc path */
1133 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1135 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1137 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1139 /* gen2 tx power off */
1140 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1143 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1145 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1146 if (hdmi->connector.scdc_present) {
1147 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1148 if (mpll_config->mpixelclock > 340000000)
1152 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1156 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1157 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1159 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1161 hdmi_phy_test_clear(hdmi, 1);
1162 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1163 HDMI_PHY_I2CM_SLAVE_ADDR);
1164 hdmi_phy_test_clear(hdmi, 0);
1166 * RK3399 mpll clock source is vpll, also is vop clock source.
1167 * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1168 * to enable mpll pre-divider.
1170 if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
1171 hdmi->dev_type == RK3399_HDMI)
1172 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
1175 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1176 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1179 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1181 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
1182 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1184 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
1185 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1186 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1188 /* REMOVE CLK TERM */
1189 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
1191 dw_hdmi_phy_enable_powerdown(hdmi, false);
1193 /* toggle TMDS disable */
1194 dw_hdmi_phy_enable_tmds(hdmi, 0);
1196 /* Wait for resuming transmission of TMDS clock and data */
1197 if (mpll_config->mpixelclock > 340000000)
1200 /* toggle TMDS enable */
1201 dw_hdmi_phy_enable_tmds(hdmi, 1);
1203 /* gen2 tx power on */
1204 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1205 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1207 if (is_rockchip(hdmi->dev_type))
1208 dw_hdmi_phy_enable_spare(hdmi, 1);
1210 /* Wait for PHY PLL lock */
1213 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1218 dev_err(hdmi->dev, "PHY PLL not locked\n");
1229 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1234 /*check csc whether needed activated in HDMI mode */
1235 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1237 /* HDMI Phy spec says to do the phy initialization sequence twice */
1238 for (i = 0; i < 2; i++) {
1239 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1240 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1241 dw_hdmi_phy_enable_tmds(hdmi, 0);
1242 dw_hdmi_phy_enable_powerdown(hdmi, true);
1245 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1250 hdmi->phy_enabled = true;
1254 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1258 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1259 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1261 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1263 /* disable rx detect */
1264 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1265 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1267 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1269 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1270 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1273 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1275 struct hdmi_avi_infoframe frame;
1278 /* Initialise info frame from DRM mode */
1279 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1281 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1282 frame.colorspace = HDMI_COLORSPACE_YUV444;
1283 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1284 frame.colorspace = HDMI_COLORSPACE_YUV422;
1285 else if (hdmi->hdmi_data.enc_out_format == YCBCR420)
1286 frame.colorspace = HDMI_COLORSPACE_YUV420;
1288 frame.colorspace = HDMI_COLORSPACE_RGB;
1290 /* Set up colorimetry */
1291 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1292 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1293 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1294 frame.extended_colorimetry =
1295 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1296 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1297 frame.extended_colorimetry =
1298 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1299 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1300 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1301 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1302 } else { /* Carries no data */
1303 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1304 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1307 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1310 * The Designware IP uses a different byte format from standard
1311 * AVI info frames, though generally the bits are in the correct
1316 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1317 * 5,6,7, active aspect present in bit 6 rather than 4.
1319 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1320 if (frame.active_aspect & 15)
1321 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1322 if (frame.top_bar || frame.bottom_bar)
1323 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1324 if (frame.left_bar || frame.right_bar)
1325 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1326 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1328 /* AVI data byte 2 differences: none */
1329 val = ((frame.colorimetry & 0x3) << 6) |
1330 ((frame.picture_aspect & 0x3) << 4) |
1331 (frame.active_aspect & 0xf);
1332 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1334 /* AVI data byte 3 differences: none */
1335 val = ((frame.extended_colorimetry & 0x7) << 4) |
1336 ((frame.quantization_range & 0x3) << 2) |
1339 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1340 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1342 /* AVI data byte 4 differences: none */
1343 val = frame.video_code & 0x7f;
1344 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1346 /* AVI Data Byte 5- set up input and output pixel repetition */
1347 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1348 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1349 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1350 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1351 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1352 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1353 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1356 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1357 * ycc range in bits 2,3 rather than 6,7
1359 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1360 (frame.content_type & 0x3);
1361 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1363 /* AVI Data Bytes 6-13 */
1364 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1365 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1366 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1367 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1368 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1369 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1370 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1371 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1374 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1375 const struct drm_display_mode *mode)
1378 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1379 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1380 unsigned int hdisplay, vdisplay;
1382 vmode->mpixelclock = mode->crtc_clock * 1000;
1383 if (mode->flags & DRM_MODE_FLAG_420_MASK)
1384 vmode->mpixelclock /= 2;
1385 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1387 /* Set up HDMI_FC_INVIDCONF
1388 * fc_invidconf.HDCP_keepout must be set (1'b1)
1389 * when activate the scrambler feature.
1391 inv_val = (hdmi->hdmi_data.hdcp_enable ||
1392 vmode->mpixelclock > 340000000 ||
1393 hdmi->connector.lte_340mcsc_scramble ?
1394 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1395 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1397 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1398 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1399 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1401 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1402 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1403 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1405 inv_val |= (vmode->mdataenablepolarity ?
1406 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1407 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1409 if (hdmi->vic == 39)
1410 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1412 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1413 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1414 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1416 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1417 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1418 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1420 inv_val |= hdmi->sink_is_hdmi ?
1421 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1422 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1424 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1426 hdisplay = mode->hdisplay;
1427 hblank = mode->htotal - mode->hdisplay;
1428 h_de_hs = mode->hsync_start - mode->hdisplay;
1429 hsync_len = mode->hsync_end - mode->hsync_start;
1432 * When we're setting a YCbCr420 mode, we need
1433 * to adjust the horizontal timing to suit.
1435 if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1442 vdisplay = mode->vdisplay;
1443 vblank = mode->vtotal - mode->vdisplay;
1444 v_de_vs = mode->vsync_start - mode->vdisplay;
1445 vsync_len = mode->vsync_end - mode->vsync_start;
1448 * When we're setting an interlaced mode, we need
1449 * to adjust the vertical timing to suit.
1451 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1458 /* Scrambling Control */
1459 if (hdmi->connector.scdc_present) {
1460 if (vmode->mpixelclock > 340000000 ||
1461 hdmi->connector.lte_340mcsc_scramble) {
1462 drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1464 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1466 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1467 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1469 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1471 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1472 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1474 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1478 /* Set up horizontal active pixel width */
1479 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1480 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1482 /* Set up vertical active lines */
1483 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1484 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1486 /* Set up horizontal blanking pixel region width */
1487 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1488 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1490 /* Set up vertical blanking pixel region width */
1491 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1493 /* Set up HSYNC active edge delay width (in pixel clks) */
1494 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1495 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1497 /* Set up VSYNC active edge delay (in lines) */
1498 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1500 /* Set up HSYNC active pulse width (in pixel clks) */
1501 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1502 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1504 /* Set up VSYNC active edge delay (in lines) */
1505 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1508 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1510 if (!hdmi->phy_enabled)
1513 dw_hdmi_phy_enable_tmds(hdmi, 0);
1514 dw_hdmi_phy_enable_powerdown(hdmi, true);
1516 hdmi->phy_enabled = false;
1519 /* HDMI Initialization Step B.4 */
1520 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1524 /* control period minimum duration */
1525 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1526 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1527 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1529 /* Set to fill TMDS data channels */
1530 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1531 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1532 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1534 /* Enable pixel clock and tmds data path */
1536 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1537 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1539 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1540 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1542 /* Enable csc path */
1543 if (is_color_space_conversion(hdmi)) {
1544 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1545 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1548 /* Enable pixel repetition path */
1549 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1550 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1551 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1555 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1557 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1560 /* Workaround to clear the overflow condition */
1561 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1566 /* TMDS software reset */
1567 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1569 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1570 if (hdmi->dev_type == IMX6DL_HDMI) {
1571 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1575 for (count = 0; count < 4; count++)
1576 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1579 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1581 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1582 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1585 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1587 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1588 HDMI_IH_MUTE_FC_STAT2);
1591 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1595 hdmi_disable_overflow_interrupts(hdmi);
1597 hdmi->vic = drm_match_cea_mode(mode);
1600 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1602 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1605 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1606 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1607 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1608 (hdmi->vic == 17) || (hdmi->vic == 18))
1609 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1611 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1613 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1614 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1615 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1617 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1618 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1620 /* TODO: Get input format from IPU (via FB driver interface) */
1621 if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1622 hdmi->hdmi_data.enc_in_format = YCBCR420;
1623 hdmi->hdmi_data.enc_out_format = YCBCR420;
1625 hdmi->hdmi_data.enc_in_format = RGB;
1626 hdmi->hdmi_data.enc_out_format = RGB;
1628 hdmi->hdmi_data.enc_color_depth = 8;
1630 * According to the dw-hdmi specification 6.4.2
1632 * 0000b: No pixel repetition (pixel sent only once)
1633 * 0001b: Pixel sent two times (pixel repeated once)
1635 hdmi->hdmi_data.pix_repet_factor =
1636 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1637 hdmi->hdmi_data.hdcp_enable = 0;
1638 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1640 /* HDMI Initialization Step B.1 */
1641 hdmi_av_composer(hdmi, mode);
1643 /* HDMI Initializateion Step B.2 */
1644 ret = dw_hdmi_phy_init(hdmi);
1648 /* HDMI Initialization Step B.3 */
1649 dw_hdmi_enable_video_path(hdmi);
1651 if (hdmi->sink_has_audio) {
1652 dev_dbg(hdmi->dev, "sink has audio support\n");
1654 /* HDMI Initialization Step E - Configure audio */
1655 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1656 hdmi_enable_audio_clk(hdmi);
1659 /* not for DVI mode */
1660 if (hdmi->sink_is_hdmi) {
1661 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1663 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1664 hdmi_config_AVI(hdmi, mode);
1666 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1669 hdmi_video_packetize(hdmi);
1670 hdmi_video_csc(hdmi);
1671 hdmi_video_sample(hdmi);
1672 hdmi_tx_hdcp_config(hdmi);
1674 dw_hdmi_clear_overflow(hdmi);
1675 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1676 hdmi_enable_overflow_interrupts(hdmi);
1681 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1686 * Boot up defaults are:
1687 * HDMI_IH_MUTE = 0x03 (disabled)
1688 * HDMI_IH_MUTE_* = 0x00 (enabled)
1690 * Disable top level interrupt bits in HDMI block
1692 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1693 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1694 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1696 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1698 /* by default mask all interrupts */
1699 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1700 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1701 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1702 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1703 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1704 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1705 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1706 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1707 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1708 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1709 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1710 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1711 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1712 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1713 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1715 /* Disable interrupts in the IH_MUTE_* registers */
1716 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1717 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1718 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1719 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1720 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1721 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1722 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1723 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1724 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1725 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1727 /* Enable top level interrupt bits in HDMI block */
1728 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1729 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1730 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1733 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1735 hdmi->bridge_is_on = true;
1736 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1739 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1741 dw_hdmi_phy_disable(hdmi);
1742 hdmi->bridge_is_on = false;
1745 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1747 int force = hdmi->force;
1749 if (hdmi->disabled) {
1750 force = DRM_FORCE_OFF;
1751 } else if (force == DRM_FORCE_UNSPECIFIED) {
1753 force = DRM_FORCE_ON;
1755 force = DRM_FORCE_OFF;
1758 if (force == DRM_FORCE_OFF) {
1759 if (hdmi->bridge_is_on)
1760 dw_hdmi_poweroff(hdmi);
1762 if (!hdmi->bridge_is_on)
1763 dw_hdmi_poweron(hdmi);
1768 * Adjust the detection of RXSENSE according to whether we have a forced
1769 * connection mode enabled, or whether we have been disabled. There is
1770 * no point processing RXSENSE interrupts if we have a forced connection
1771 * state, or DRM has us disabled.
1773 * We also disable rxsense interrupts when we think we're disconnected
1774 * to avoid floating TDMS signals giving false rxsense interrupts.
1776 * Note: we still need to listen for HPD interrupts even when DRM has us
1777 * disabled so that we can detect a connect event.
1779 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1781 u8 old_mask = hdmi->phy_mask;
1783 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1784 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1786 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1788 if (old_mask != hdmi->phy_mask)
1789 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1792 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1793 struct drm_display_mode *orig_mode,
1794 struct drm_display_mode *mode)
1796 struct dw_hdmi *hdmi = bridge->driver_private;
1798 mutex_lock(&hdmi->mutex);
1800 /* Store the display mode for plugin/DKMS poweron events */
1801 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1803 mutex_unlock(&hdmi->mutex);
1806 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1808 struct dw_hdmi *hdmi = bridge->driver_private;
1810 mutex_lock(&hdmi->mutex);
1811 hdmi->disabled = true;
1812 dw_hdmi_update_power(hdmi);
1813 dw_hdmi_update_phy_mask(hdmi);
1814 mutex_unlock(&hdmi->mutex);
1817 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1819 struct dw_hdmi *hdmi = bridge->driver_private;
1821 mutex_lock(&hdmi->mutex);
1822 hdmi->disabled = false;
1823 dw_hdmi_update_power(hdmi);
1824 dw_hdmi_update_phy_mask(hdmi);
1825 mutex_unlock(&hdmi->mutex);
1828 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1833 static enum drm_connector_status
1834 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1836 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1839 mutex_lock(&hdmi->mutex);
1840 hdmi->force = DRM_FORCE_UNSPECIFIED;
1841 dw_hdmi_update_power(hdmi);
1842 dw_hdmi_update_phy_mask(hdmi);
1843 mutex_unlock(&hdmi->mutex);
1845 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1846 connector_status_connected : connector_status_disconnected;
1849 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1851 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1859 edid = drm_get_edid(connector, hdmi->ddc);
1861 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1862 edid->width_cm, edid->height_cm);
1864 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1865 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1866 drm_mode_connector_update_edid_property(connector, edid);
1867 ret = drm_add_edid_modes(connector, edid);
1869 drm_edid_to_eld(connector, edid);
1872 dev_dbg(hdmi->dev, "failed to get edid\n");
1878 static enum drm_mode_status
1879 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1880 struct drm_display_mode *mode)
1882 struct dw_hdmi *hdmi = container_of(connector,
1883 struct dw_hdmi, connector);
1884 enum drm_mode_status mode_status = MODE_OK;
1886 if (hdmi->plat_data->mode_valid)
1887 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1892 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1895 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1898 return hdmi->encoder;
1901 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1903 drm_connector_unregister(connector);
1904 drm_connector_cleanup(connector);
1907 static void dw_hdmi_connector_force(struct drm_connector *connector)
1909 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1912 mutex_lock(&hdmi->mutex);
1913 hdmi->force = connector->force;
1914 dw_hdmi_update_power(hdmi);
1915 dw_hdmi_update_phy_mask(hdmi);
1916 mutex_unlock(&hdmi->mutex);
1919 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1920 .dpms = drm_helper_connector_dpms,
1921 .fill_modes = drm_helper_probe_single_connector_modes,
1922 .detect = dw_hdmi_connector_detect,
1923 .destroy = dw_hdmi_connector_destroy,
1924 .force = dw_hdmi_connector_force,
1927 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1928 .dpms = drm_atomic_helper_connector_dpms,
1929 .fill_modes = drm_helper_probe_single_connector_modes,
1930 .detect = dw_hdmi_connector_detect,
1931 .destroy = dw_hdmi_connector_destroy,
1932 .force = dw_hdmi_connector_force,
1933 .reset = drm_atomic_helper_connector_reset,
1934 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1935 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1938 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1939 .get_modes = dw_hdmi_connector_get_modes,
1940 .mode_valid = dw_hdmi_connector_mode_valid,
1941 .best_encoder = dw_hdmi_connector_best_encoder,
1944 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1945 .enable = dw_hdmi_bridge_enable,
1946 .disable = dw_hdmi_bridge_disable,
1947 .pre_enable = dw_hdmi_bridge_nop,
1948 .post_disable = dw_hdmi_bridge_nop,
1949 .mode_set = dw_hdmi_bridge_mode_set,
1952 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1954 struct dw_hdmi_i2c *i2c = hdmi->i2c;
1957 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1961 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1965 complete(&i2c->cmp);
1970 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1972 struct dw_hdmi *hdmi = dev_id;
1974 irqreturn_t ret = IRQ_NONE;
1977 ret = dw_hdmi_i2c_irq(hdmi);
1979 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1981 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1982 return IRQ_WAKE_THREAD;
1988 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1990 struct dw_hdmi *hdmi = dev_id;
1991 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1993 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1994 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1995 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1998 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1999 phy_pol_mask |= HDMI_PHY_HPD;
2000 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2001 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2002 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2003 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2004 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2005 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2006 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2007 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2010 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2013 * RX sense tells us whether the TDMS transmitters are detecting
2014 * load - in other words, there's something listening on the
2015 * other end of the link. Use this to decide whether we should
2016 * power on the phy as HPD may be toggled by the sink to merely
2017 * ask the source to re-read the EDID.
2020 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2021 mutex_lock(&hdmi->mutex);
2022 if (!hdmi->bridge_is_on && !hdmi->force) {
2024 * If the RX sense status indicates we're disconnected,
2025 * clear the software rxsense status.
2027 if (!(phy_stat & HDMI_PHY_RX_SENSE))
2028 hdmi->rxsense = false;
2031 * Only set the software rxsense status when both
2032 * rxsense and hpd indicates we're connected.
2033 * This avoids what seems to be bad behaviour in
2034 * at least iMX6S versions of the phy.
2036 if (phy_stat & HDMI_PHY_HPD)
2037 hdmi->rxsense = true;
2039 dw_hdmi_update_power(hdmi);
2040 dw_hdmi_update_phy_mask(hdmi);
2042 mutex_unlock(&hdmi->mutex);
2045 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2046 dev_dbg(hdmi->dev, "EVENT=%s\n",
2047 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2048 drm_helper_hpd_irq_event(hdmi->bridge->dev);
2049 #ifdef CONFIG_SWITCH
2050 if (phy_int_pol & HDMI_PHY_HPD)
2051 switch_set_state(&hdmi->switchdev, 1);
2053 switch_set_state(&hdmi->switchdev, 0);
2057 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2058 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2059 HDMI_IH_MUTE_PHY_STAT0);
2064 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2066 struct drm_encoder *encoder = hdmi->encoder;
2067 struct drm_bridge *bridge;
2070 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2072 DRM_ERROR("Failed to allocate drm bridge\n");
2076 hdmi->bridge = bridge;
2077 bridge->driver_private = hdmi;
2078 bridge->funcs = &dw_hdmi_bridge_funcs;
2079 ret = drm_bridge_attach(drm, bridge);
2081 DRM_ERROR("Failed to initialize bridge with drm\n");
2085 encoder->bridge = bridge;
2086 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2087 hdmi->connector.port = hdmi->dev->of_node;
2089 drm_connector_helper_add(&hdmi->connector,
2090 &dw_hdmi_connector_helper_funcs);
2092 if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2093 drm_connector_init(drm, &hdmi->connector,
2094 &dw_hdmi_atomic_connector_funcs,
2095 DRM_MODE_CONNECTOR_HDMIA);
2097 drm_connector_init(drm, &hdmi->connector,
2098 &dw_hdmi_connector_funcs,
2099 DRM_MODE_CONNECTOR_HDMIA);
2101 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2106 int dw_hdmi_bind(struct device *dev, struct device *master,
2107 void *data, struct drm_encoder *encoder,
2108 struct resource *iores, int irq,
2109 const struct dw_hdmi_plat_data *plat_data)
2111 struct drm_device *drm = data;
2112 struct device_node *np = dev->of_node;
2113 struct platform_device_info pdevinfo;
2114 struct device_node *ddc_node;
2115 struct dw_hdmi *hdmi;
2121 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2125 hdmi->connector.interlace_allowed = 1;
2127 hdmi->plat_data = plat_data;
2129 hdmi->dev_type = plat_data->dev_type;
2130 hdmi->sample_rate = 48000;
2131 hdmi->encoder = encoder;
2132 hdmi->disabled = true;
2133 hdmi->rxsense = true;
2134 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2137 mutex_init(&hdmi->mutex);
2138 mutex_init(&hdmi->audio_mutex);
2139 spin_lock_init(&hdmi->audio_lock);
2141 of_property_read_u32(np, "reg-io-width", &val);
2145 hdmi->write = dw_hdmi_writel;
2146 hdmi->read = dw_hdmi_readl;
2149 hdmi->write = dw_hdmi_writeb;
2150 hdmi->read = dw_hdmi_readb;
2153 dev_err(dev, "reg-io-width must be 1 or 4\n");
2157 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2159 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2160 of_node_put(ddc_node);
2162 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2163 return -EPROBE_DEFER;
2167 dev_dbg(hdmi->dev, "no ddc property found\n");
2170 /* If DDC bus is not specified, try to register HDMI I2C bus */
2172 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2173 if (IS_ERR(hdmi->ddc))
2177 hdmi->regs = devm_ioremap_resource(dev, iores);
2178 if (IS_ERR(hdmi->regs))
2179 return PTR_ERR(hdmi->regs);
2181 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2182 if (IS_ERR(hdmi->isfr_clk)) {
2183 ret = PTR_ERR(hdmi->isfr_clk);
2184 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2188 ret = clk_prepare_enable(hdmi->isfr_clk);
2190 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2194 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2195 if (IS_ERR(hdmi->iahb_clk)) {
2196 ret = PTR_ERR(hdmi->iahb_clk);
2197 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2201 ret = clk_prepare_enable(hdmi->iahb_clk);
2203 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2207 /* Product and revision IDs */
2209 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2210 hdmi_readb(hdmi, HDMI_DESIGN_ID),
2211 hdmi_readb(hdmi, HDMI_REVISION_ID),
2212 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2213 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2215 initialize_hdmi_ih_mutes(hdmi);
2217 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2218 dw_hdmi_irq, IRQF_SHARED,
2219 dev_name(dev), hdmi);
2224 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2225 * N and cts values before enabling phy
2227 hdmi_init_clk_regenerator(hdmi);
2229 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2230 HDMI_PHY_I2CM_INT_ADDR);
2232 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2233 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2234 HDMI_PHY_I2CM_CTLINT_ADDR);
2236 /* Re-init HPD polarity */
2237 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2239 /* Unmask HPD, clear transitory interrupts, then unmute */
2240 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2242 ret = dw_hdmi_register(drm, hdmi);
2246 #ifdef CONFIG_SWITCH
2247 hdmi->switchdev.name = "hdmi";
2248 switch_dev_register(&hdmi->switchdev);
2251 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2252 HDMI_IH_MUTE_PHY_STAT0);
2254 /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2256 dw_hdmi_i2c_init(hdmi);
2258 memset(&pdevinfo, 0, sizeof(pdevinfo));
2259 pdevinfo.parent = dev;
2260 pdevinfo.id = PLATFORM_DEVID_AUTO;
2262 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2263 config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2265 if (config1 & HDMI_CONFIG1_AHB) {
2266 struct dw_hdmi_audio_data audio;
2268 audio.phys = iores->start;
2269 audio.base = hdmi->regs;
2272 audio.eld = hdmi->connector.eld;
2274 pdevinfo.name = "dw-hdmi-ahb-audio";
2275 pdevinfo.data = &audio;
2276 pdevinfo.size_data = sizeof(audio);
2277 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2278 hdmi->audio = platform_device_register_full(&pdevinfo);
2279 } else if (config0 & HDMI_CONFIG0_I2S) {
2280 struct dw_hdmi_i2s_audio_data audio;
2283 audio.write = hdmi_writeb;
2284 audio.read = hdmi_readb;
2286 pdevinfo.name = "dw-hdmi-i2s-audio";
2287 pdevinfo.data = &audio;
2288 pdevinfo.size_data = sizeof(audio);
2289 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2290 hdmi->audio = platform_device_register_full(&pdevinfo);
2293 dev_set_drvdata(dev, hdmi);
2299 i2c_del_adapter(&hdmi->i2c->adap);
2301 clk_disable_unprepare(hdmi->iahb_clk);
2303 clk_disable_unprepare(hdmi->isfr_clk);
2307 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2309 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2311 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2313 if (hdmi->audio && !IS_ERR(hdmi->audio))
2314 platform_device_unregister(hdmi->audio);
2316 /* Disable all interrupts */
2317 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2319 #ifdef CONFIG_SWITCH
2320 switch_dev_unregister(&hdmi->switchdev);
2322 hdmi->connector.funcs->destroy(&hdmi->connector);
2323 hdmi->encoder->funcs->destroy(hdmi->encoder);
2325 clk_disable_unprepare(hdmi->iahb_clk);
2326 clk_disable_unprepare(hdmi->isfr_clk);
2329 i2c_del_adapter(&hdmi->i2c->adap);
2331 i2c_put_adapter(hdmi->ddc);
2333 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2335 static void dw_hdmi_reg_initial(struct dw_hdmi *hdmi)
2337 if (hdmi_readb(hdmi, HDMI_IH_MUTE)) {
2338 initialize_hdmi_ih_mutes(hdmi);
2339 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2340 HDMI_PHY_I2CM_INT_ADDR);
2342 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2343 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2344 HDMI_PHY_I2CM_CTLINT_ADDR);
2346 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE,
2348 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2349 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD |
2350 HDMI_IH_PHY_STAT0_RX_SENSE),
2351 HDMI_IH_MUTE_PHY_STAT0);
2355 void dw_hdmi_suspend(struct device *dev)
2357 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2359 mutex_lock(&hdmi->mutex);
2361 disable_irq(hdmi->irq);
2362 mutex_unlock(&hdmi->mutex);
2364 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
2366 void dw_hdmi_resume(struct device *dev)
2368 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2370 mutex_lock(&hdmi->mutex);
2371 dw_hdmi_reg_initial(hdmi);
2373 enable_irq(hdmi->irq);
2374 mutex_unlock(&hdmi->mutex);
2376 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2378 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2379 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2380 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2381 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2382 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2383 MODULE_LICENSE("GPL");
2384 MODULE_ALIAS("platform:dw-hdmi");