drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/drm_scdc_helper.h>
  33 #include <drm/bridge/dw_hdmi.h>
  34 #ifdef CONFIG_SWITCH
  35 #include <linux/switch.h>
  36 #endif
  37
  38 #include "dw-hdmi.h"
  39 #include "dw-hdmi-audio.h"
  40
  41 #define HDMI_EDID_LEN           512
  42 #define DDC_SEGMENT_ADDR       0x30
  43
  44 #define RGB                     0
  45 #define YCBCR444                1
  46 #define YCBCR422_16BITS         2
  47 #define YCBCR422_8BITS          3
  48 #define XVYCC444                4
  49 #define YCBCR420                5
  50
  51 enum hdmi_datamap {
  52         RGB444_8B = 0x01,
  53         RGB444_10B = 0x03,
  54         RGB444_12B = 0x05,
  55         RGB444_16B = 0x07,
  56         YCbCr444_8B = 0x09,
  57         YCbCr444_10B = 0x0B,
  58         YCbCr444_12B = 0x0D,
  59         YCbCr444_16B = 0x0F,
  60         YCbCr422_8B = 0x16,
  61         YCbCr422_10B = 0x14,
  62         YCbCr422_12B = 0x12,
  63 };
  64
  65 /*
  66  * Unless otherwise noted, entries in this table are 100% optimization.
  67  * Values can be obtained from hdmi_compute_n() but that function is
  68  * slow so we pre-compute values we expect to see.
  69  *
  70  * All 32k and 48k values are expected to be the same (due to the way
  71  * the math works) for any rate that's an exact kHz.
  72  */
  73 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  74         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  75         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  76         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  77         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  78         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  79         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  80         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  81         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  82         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  83         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  84         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  85         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  86         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  87         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  88         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  89         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  90         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  91         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  92         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  93         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  94         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  95         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  96         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  97         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  98         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  99         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
 100         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
 101         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
 102         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
 103         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 104         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
 105         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 106         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 107         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 108         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 109         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 110         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 111
 112         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 113         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 114         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 115
 116         /* End of table */
 117         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 118 };
 119
 120
 121 static const u16 csc_coeff_default[3][4] = {
 122         { 0x2000, 0x0000, 0x0000, 0x0000 },
 123         { 0x0000, 0x2000, 0x0000, 0x0000 },
 124         { 0x0000, 0x0000, 0x2000, 0x0000 }
 125 };
 126
 127 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 128         { 0x2000, 0x6926, 0x74fd, 0x010e },
 129         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 130         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 131 };
 132
 133 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 134         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 135         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 136         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 137 };
 138
 139 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 140         { 0x2591, 0x1322, 0x074b, 0x0000 },
 141         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 142         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 143 };
 144
 145 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 146         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 147         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 148         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 149 };
 150
 151 struct hdmi_vmode {
 152         bool mdataenablepolarity;
 153
 154         unsigned int mpixelclock;
 155         unsigned int mpixelrepetitioninput;
 156         unsigned int mpixelrepetitionoutput;
 157 };
 158
 159 struct hdmi_data_info {
 160         unsigned int enc_in_format;
 161         unsigned int enc_out_format;
 162         unsigned int enc_color_depth;
 163         unsigned int colorimetry;
 164         unsigned int pix_repet_factor;
 165         unsigned int hdcp_enable;
 166         struct hdmi_vmode video_mode;
 167 };
 168
 169 struct dw_hdmi_i2c {
 170         struct i2c_adapter      adap;
 171
 172         struct mutex            lock;
 173         struct completion       cmp;
 174         u8                      stat;
 175
 176         u8                      slave_reg;
 177         bool                    is_regaddr;
 178         bool                    is_segment;
 179 };
 180
 181 struct dw_hdmi {
 182         struct drm_connector connector;
 183         struct drm_encoder *encoder;
 184         struct drm_bridge *bridge;
 185
 186         struct platform_device *audio;
 187         enum dw_hdmi_devtype dev_type;
 188         struct device *dev;
 189         struct clk *isfr_clk;
 190         struct clk *iahb_clk;
 191         struct dw_hdmi_i2c *i2c;
 192
 193         struct hdmi_data_info hdmi_data;
 194         const struct dw_hdmi_plat_data *plat_data;
 195
 196         int vic;
 197
 198         u8 edid[HDMI_EDID_LEN];
 199         bool cable_plugin;
 200
 201         bool phy_enabled;
 202         struct drm_display_mode previous_mode;
 203
 204         struct i2c_adapter *ddc;
 205         void __iomem *regs;
 206         bool sink_is_hdmi;
 207         bool sink_has_audio;
 208
 209         struct mutex mutex;             /* for state below and previous_mode */
 210         enum drm_connector_force force; /* mutex-protected force state */
 211         bool disabled;                  /* DRM has disabled our bridge */
 212         bool bridge_is_on;              /* indicates the bridge is on */
 213         bool rxsense;                   /* rxsense state */
 214         u8 phy_mask;                    /* desired phy int mask settings */
 215
 216         spinlock_t audio_lock;
 217         struct mutex audio_mutex;
 218         unsigned int sample_rate;
 219         unsigned int audio_cts;
 220         unsigned int audio_n;
 221         bool audio_enable;
 222
 223 #ifdef CONFIG_SWITCH
 224         struct switch_dev switchdev;
 225 #endif
 226
 227         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 228         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 229 };
 230
 231 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 232         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 233          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 234
 235 #define HDMI_PHY_RX_SENSE \
 236         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 237          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 238
 239 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 240 {
 241         writel(val, hdmi->regs + (offset << 2));
 242 }
 243
 244 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 245 {
 246         return readl(hdmi->regs + (offset << 2));
 247 }
 248
 249 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 250 {
 251         writeb(val, hdmi->regs + offset);
 252 }
 253
 254 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 255 {
 256         return readb(hdmi->regs + offset);
 257 }
 258
 259 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 260 {
 261         hdmi->write(hdmi, val, offset);
 262 }
 263
 264 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 265 {
 266         return hdmi->read(hdmi, offset);
 267 }
 268
 269 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 270 {
 271         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 272
 273         val |= data & mask;
 274         hdmi_writeb(hdmi, val, reg);
 275 }
 276
 277 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 278                              u8 shift, u8 mask)
 279 {
 280         hdmi_modb(hdmi, data << shift, mask, reg);
 281 }
 282
 283 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 284 {
 285         /* Software reset */
 286         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 287
 288         /* Set Standard Mode speed */
 289         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
 290                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
 291
 292         /* Set done, not acknowledged and arbitration interrupt polarities */
 293         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 294         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 295                     HDMI_I2CM_CTLINT);
 296
 297         /* Clear DONE and ERROR interrupts */
 298         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 299                     HDMI_IH_I2CM_STAT0);
 300
 301         /* Mute DONE and ERROR interrupts */
 302         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 303                     HDMI_IH_MUTE_I2CM_STAT0);
 304 }
 305
 306 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 307                             unsigned char *buf, unsigned int length)
 308 {
 309         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 310         int stat;
 311
 312         if (!i2c->is_regaddr) {
 313                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 314                 i2c->slave_reg = 0x00;
 315                 i2c->is_regaddr = true;
 316         }
 317
 318         while (length--) {
 319                 reinit_completion(&i2c->cmp);
 320
 321                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 322                 if (i2c->is_segment)
 323                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 324                                     HDMI_I2CM_OPERATION);
 325                 else
 326                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 327                                     HDMI_I2CM_OPERATION);
 328
 329                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 330                 if (!stat)
 331                         return -EAGAIN;
 332
 333                 /* Check for error condition on the bus */
 334                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 335                         return -EIO;
 336
 337                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 338         }
 339         i2c->is_segment = false;
 340
 341         return 0;
 342 }
 343
 344 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 345                              unsigned char *buf, unsigned int length)
 346 {
 347         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 348         int stat;
 349
 350         if (!i2c->is_regaddr) {
 351                 /* Use the first write byte as register address */
 352                 i2c->slave_reg = buf[0];
 353                 length--;
 354                 buf++;
 355                 i2c->is_regaddr = true;
 356         }
 357
 358         while (length--) {
 359                 reinit_completion(&i2c->cmp);
 360
 361                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 362                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 363                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 364                             HDMI_I2CM_OPERATION);
 365
 366         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 367                 if (!stat)
 368                         return -EAGAIN;
 369
 370                 /* Check for error condition on the bus */
 371                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 372                         return -EIO;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 379                             struct i2c_msg *msgs, int num)
 380 {
 381         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 382         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 383         u8 addr = msgs[0].addr;
 384         int i, ret = 0;
 385
 386         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 387
 388         for (i = 0; i < num; i++) {
 389                 if (msgs[i].len == 0) {
 390                         dev_dbg(hdmi->dev,
 391                                 "unsupported transfer %d/%d, no data\n",
 392                                 i + 1, num);
 393                         return -EOPNOTSUPP;
 394                 }
 395         }
 396
 397         mutex_lock(&i2c->lock);
 398
 399         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 400
 401         /* Set slave device address taken from the first I2C message */
 402         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 403
 404         /* Set slave device register address on transfer */
 405         i2c->is_regaddr = false;
 406
 407         /* Set segment pointer for I2C extended read mode operation */
 408         i2c->is_segment = false;
 409
 410         for (i = 0; i < num; i++) {
 411                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 412                         i + 1, num, msgs[i].len, msgs[i].flags);
 413                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 414                         i2c->is_segment = true;
 415                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 416                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 417                 } else {
 418                         if (msgs[i].flags & I2C_M_RD)
 419                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 420                                                        msgs[i].len);
 421                         else
 422                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 423                                                         msgs[i].len);
 424                 }
 425                 if (ret < 0)
 426                         break;
 427         }
 428
 429         if (!ret)
 430                 ret = num;
 431
 432         /* Mute DONE and ERROR interrupts */
 433         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 434                     HDMI_IH_MUTE_I2CM_STAT0);
 435
 436         mutex_unlock(&i2c->lock);
 437
 438         return ret;
 439 }
 440
 441 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 442 {
 443         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 444 }
 445
 446 static const struct i2c_algorithm dw_hdmi_algorithm = {
 447         .master_xfer    = dw_hdmi_i2c_xfer,
 448         .functionality  = dw_hdmi_i2c_func,
 449 };
 450
 451 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 452 {
 453         struct i2c_adapter *adap;
 454         struct dw_hdmi_i2c *i2c;
 455         int ret;
 456
 457         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 458         if (!i2c)
 459                 return ERR_PTR(-ENOMEM);
 460
 461         mutex_init(&i2c->lock);
 462         init_completion(&i2c->cmp);
 463
 464         adap = &i2c->adap;
 465         adap->class = I2C_CLASS_DDC;
 466         adap->owner = THIS_MODULE;
 467         adap->dev.parent = hdmi->dev;
 468         adap->dev.of_node = hdmi->dev->of_node;
 469         adap->algo = &dw_hdmi_algorithm;
 470         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 471         i2c_set_adapdata(adap, hdmi);
 472
 473         ret = i2c_add_adapter(adap);
 474         if (ret) {
 475                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 476                 devm_kfree(hdmi->dev, i2c);
 477                 return ERR_PTR(ret);
 478         }
 479
 480         hdmi->i2c = i2c;
 481
 482         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 483
 484         return adap;
 485 }
 486
 487 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 488                            unsigned int n)
 489 {
 490         /* Must be set/cleared first */
 491         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 492
 493         /* nshift factor = 0 */
 494         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 495
 496         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 497                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 498         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 499         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 500
 501         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 502         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 503         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 504 }
 505
 506 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 507                                    unsigned long pixel_clk,
 508                                    unsigned long freq)
 509 {
 510         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 511         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 512         int i;
 513
 514         if (plat_data->tmds_n_table) {
 515                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 516                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 517                                 tmds_n = &plat_data->tmds_n_table[i];
 518                                 break;
 519                         }
 520                 }
 521         }
 522
 523         if (tmds_n == NULL) {
 524                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 525                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 526                                 tmds_n = &common_tmds_n_table[i];
 527                                 break;
 528                         }
 529                 }
 530         }
 531
 532         if (tmds_n == NULL)
 533                 return -ENOENT;
 534
 535         switch (freq) {
 536         case 32000:
 537                 return tmds_n->n_32k;
 538         case 44100:
 539         case 88200:
 540         case 176400:
 541                 return (freq / 44100) * tmds_n->n_44k1;
 542         case 48000:
 543         case 96000:
 544         case 192000:
 545                 return (freq / 48000) * tmds_n->n_48k;
 546         default:
 547                 return -ENOENT;
 548         }
 549 }
 550
 551 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 552                                 unsigned int pixel_clk)
 553 {
 554         u64 final, diff;
 555         u64 cts;
 556
 557         final = (u64)pixel_clk * n;
 558
 559         cts = final;
 560         do_div(cts, 128 * freq);
 561
 562         diff = final - (u64)cts * (128 * freq);
 563
 564         return diff;
 565 }
 566
 567 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 568                                    unsigned long pixel_clk,
 569                                    unsigned long freq)
 570 {
 571         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 572         unsigned int max_n = (128 * freq) / 300;
 573         unsigned int ideal_n = (128 * freq) / 1000;
 574         unsigned int best_n_distance = ideal_n;
 575         unsigned int best_n = 0;
 576         u64 best_diff = U64_MAX;
 577         int n;
 578
 579         /* If the ideal N could satisfy the audio math, then just take it */
 580         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 581                 return ideal_n;
 582
 583         for (n = min_n; n <= max_n; n++) {
 584                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 585
 586                 if (diff < best_diff || (diff == best_diff &&
 587                     abs(n - ideal_n) < best_n_distance)) {
 588                         best_n = n;
 589                         best_diff = diff;
 590                         best_n_distance = abs(best_n - ideal_n);
 591                 }
 592
 593                 /*
 594                  * The best N already satisfy the audio math, and also be
 595                  * the closest value to ideal N, so just cut the loop.
 596                  */
 597                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 598                         break;
 599         }
 600
 601         return best_n;
 602 }
 603
 604 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 605                                 unsigned long sample_rate)
 606 {
 607         int n;
 608
 609         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 610         if (n > 0)
 611                 return n;
 612
 613         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 614                  pixel_clk);
 615
 616         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 617 }
 618
 619 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 620         unsigned long pixel_clk, unsigned int sample_rate)
 621 {
 622         unsigned long ftdms = pixel_clk;
 623         unsigned int n, cts;
 624         u64 tmp;
 625
 626         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 627
 628         /*
 629          * Compute the CTS value from the N value.  Note that CTS and N
 630          * can be up to 20 bits in total, so we need 64-bit math.  Also
 631          * note that our TDMS clock is not fully accurate; it is accurate
 632          * to kHz.  This can introduce an unnecessary remainder in the
 633          * calculation below, so we don't try to warn about that.
 634          */
 635         tmp = (u64)ftdms * n;
 636         do_div(tmp, 128 * sample_rate);
 637         cts = tmp;
 638
 639         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 640                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 641                 n, cts);
 642
 643         spin_lock_irq(&hdmi->audio_lock);
 644         hdmi->audio_n = n;
 645         hdmi->audio_cts = cts;
 646         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 647         spin_unlock_irq(&hdmi->audio_lock);
 648 }
 649
 650 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 651 {
 652         mutex_lock(&hdmi->audio_mutex);
 653         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 654         mutex_unlock(&hdmi->audio_mutex);
 655 }
 656
 657 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 658 {
 659         mutex_lock(&hdmi->audio_mutex);
 660         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 661                                  hdmi->sample_rate);
 662         mutex_unlock(&hdmi->audio_mutex);
 663 }
 664
 665 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 666 {
 667         mutex_lock(&hdmi->audio_mutex);
 668         hdmi->sample_rate = rate;
 669         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 670                                  hdmi->sample_rate);
 671         mutex_unlock(&hdmi->audio_mutex);
 672 }
 673 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 674
 675 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 676 {
 677         unsigned long flags;
 678
 679         spin_lock_irqsave(&hdmi->audio_lock, flags);
 680         hdmi->audio_enable = true;
 681         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 682         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 683 }
 684 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 685
 686 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 687 {
 688         unsigned long flags;
 689
 690         spin_lock_irqsave(&hdmi->audio_lock, flags);
 691         hdmi->audio_enable = false;
 692         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 693         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 694 }
 695 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 696
 697 /*
 698  * this submodule is responsible for the video data synchronization.
 699  * for example, for RGB 4:4:4 input, the data map is defined as
 700  *                      pin{47~40} <==> R[7:0]
 701  *                      pin{31~24} <==> G[7:0]
 702  *                      pin{15~8}  <==> B[7:0]
 703  */
 704 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 705 {
 706         int color_format = 0;
 707         u8 val;
 708
 709         if (hdmi->hdmi_data.enc_in_format == RGB) {
 710                 if (hdmi->hdmi_data.enc_color_depth == 8)
 711                         color_format = 0x01;
 712                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 713                         color_format = 0x03;
 714                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 715                         color_format = 0x05;
 716                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 717                         color_format = 0x07;
 718                 else
 719                         return;
 720         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444 ||
 721                    hdmi->hdmi_data.enc_in_format == YCBCR420) {
 722                 if (hdmi->hdmi_data.enc_color_depth == 8)
 723                         color_format = 0x09;
 724                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 725                         color_format = 0x0B;
 726                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 727                         color_format = 0x0D;
 728                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 729                         color_format = 0x0F;
 730                 else
 731                         return;
 732         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 733                 if (hdmi->hdmi_data.enc_color_depth == 8)
 734                         color_format = 0x16;
 735                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 736                         color_format = 0x14;
 737                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 738                         color_format = 0x12;
 739                 else
 740                         return;
 741         }
 742
 743         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 744                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 745                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 746         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 747
 748         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 749         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 750                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 751                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 752         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 753         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 754         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 755         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 756         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 757         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 758         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 759 }
 760
 761 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 762 {
 763         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 764 }
 765
 766 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 767 {
 768         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 769                 return 0;
 770         if (hdmi->hdmi_data.enc_in_format == RGB ||
 771             hdmi->hdmi_data.enc_in_format == YCBCR444)
 772                 return 1;
 773         return 0;
 774 }
 775
 776 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 777 {
 778         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 779                 return 0;
 780         if (hdmi->hdmi_data.enc_out_format == RGB ||
 781             hdmi->hdmi_data.enc_out_format == YCBCR444)
 782                 return 1;
 783         return 0;
 784 }
 785
 786 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 787 {
 788         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 789         unsigned i;
 790         u32 csc_scale = 1;
 791
 792         if (is_color_space_conversion(hdmi)) {
 793                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 794                         if (hdmi->hdmi_data.colorimetry ==
 795                                         HDMI_COLORIMETRY_ITU_601)
 796                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 797                         else
 798                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 799                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 800                         if (hdmi->hdmi_data.colorimetry ==
 801                                         HDMI_COLORIMETRY_ITU_601)
 802                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 803                         else
 804                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 805                         csc_scale = 0;
 806                 }
 807         }
 808
 809         /* The CSC registers are sequential, alternating MSB then LSB */
 810         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 811                 u16 coeff_a = (*csc_coeff)[0][i];
 812                 u16 coeff_b = (*csc_coeff)[1][i];
 813                 u16 coeff_c = (*csc_coeff)[2][i];
 814
 815                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 816                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 817                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 818                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 819                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 820                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 821         }
 822
 823         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 824                   HDMI_CSC_SCALE);
 825 }
 826
 827 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 828 {
 829         int color_depth = 0;
 830         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 831         int decimation = 0;
 832
 833         /* YCC422 interpolation to 444 mode */
 834         if (is_color_space_interpolation(hdmi))
 835                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 836         else if (is_color_space_decimation(hdmi))
 837                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 838
 839         if (hdmi->hdmi_data.enc_color_depth == 8)
 840                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 841         else if (hdmi->hdmi_data.enc_color_depth == 10)
 842                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 843         else if (hdmi->hdmi_data.enc_color_depth == 12)
 844                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 845         else if (hdmi->hdmi_data.enc_color_depth == 16)
 846                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 847         else
 848                 return;
 849
 850         /* Configure the CSC registers */
 851         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 852         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 853                   HDMI_CSC_SCALE);
 854
 855         dw_hdmi_update_csc_coeffs(hdmi);
 856 }
 857
 858 /*
 859  * HDMI video packetizer is used to packetize the data.
 860  * for example, if input is YCC422 mode or repeater is used,
 861  * data should be repacked this module can be bypassed.
 862  */
 863 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 864 {
 865         unsigned int color_depth = 0;
 866         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 867         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 868         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 869         u8 val, vp_conf;
 870
 871         if (hdmi_data->enc_out_format == RGB ||
 872             hdmi_data->enc_out_format == YCBCR444 ||
 873             hdmi_data->enc_out_format == YCBCR420) {
 874                 if (!hdmi_data->enc_color_depth) {
 875                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 876                 } else if (hdmi_data->enc_color_depth == 8) {
 877                         color_depth = 4;
 878                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 879                 } else if (hdmi_data->enc_color_depth == 10) {
 880                         color_depth = 5;
 881                 } else if (hdmi_data->enc_color_depth == 12) {
 882                         color_depth = 6;
 883                 } else if (hdmi_data->enc_color_depth == 16) {
 884                         color_depth = 7;
 885                 } else {
 886                         return;
 887                 }
 888         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 889                 if (!hdmi_data->enc_color_depth ||
 890                     hdmi_data->enc_color_depth == 8)
 891                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 892                 else if (hdmi_data->enc_color_depth == 10)
 893                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 894                 else if (hdmi_data->enc_color_depth == 12)
 895                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 896                 else
 897                         return;
 898                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 899         } else {
 900                 return;
 901         }
 902
 903         /* set the packetizer registers */
 904         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 905                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 906                 ((hdmi_data->pix_repet_factor <<
 907                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 908                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 909         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 910
 911         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 912                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 913
 914         /* Data from pixel repeater block */
 915         if (hdmi_data->pix_repet_factor > 0) {
 916                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 917                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 918         } else { /* data from packetizer block */
 919                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 920                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 921         }
 922
 923         hdmi_modb(hdmi, vp_conf,
 924                   HDMI_VP_CONF_PR_EN_MASK |
 925                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 926
 927         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 928                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 929
 930         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 931
 932         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 933                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 934                           HDMI_VP_CONF_PP_EN_ENABLE |
 935                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 936         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 937                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 938                           HDMI_VP_CONF_PP_EN_DISABLE |
 939                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 940         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 941                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 942                           HDMI_VP_CONF_PP_EN_DISABLE |
 943                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 944         } else {
 945                 return;
 946         }
 947
 948         hdmi_modb(hdmi, vp_conf,
 949                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 950                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 951
 952         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 953                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 954                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 955                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 956
 957         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 958                   HDMI_VP_CONF);
 959 }
 960
 961 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 962                                        unsigned char bit)
 963 {
 964         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 965                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 966 }
 967
 968 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 969                                         unsigned char bit)
 970 {
 971         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 972                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 973 }
 974
 975 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 976                                        unsigned char bit)
 977 {
 978         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 979                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 980 }
 981
 982 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 983                                      unsigned char bit)
 984 {
 985         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 986 }
 987
 988 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 989                                       unsigned char bit)
 990 {
 991         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 992 }
 993
 994 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 995 {
 996         u32 val;
 997
 998         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 999                 if (msec-- == 0)
1000                         return false;
1001                 udelay(1000);
1002         }
1003         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1004
1005         return true;
1006 }
1007
1008 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1009                                  unsigned char addr)
1010 {
1011         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1012         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1013         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1014                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1015         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1016                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1017         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1018                     HDMI_PHY_I2CM_OPERATION_ADDR);
1019         hdmi_phy_wait_i2c_done(hdmi, 1000);
1020 }
1021
1022 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1023                               unsigned char addr)
1024 {
1025         __hdmi_phy_i2c_write(hdmi, data, addr);
1026         return 0;
1027 }
1028
1029 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1030 {
1031         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1032                          HDMI_PHY_CONF0_PDZ_OFFSET,
1033                          HDMI_PHY_CONF0_PDZ_MASK);
1034 }
1035
1036 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1037 {
1038         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1039                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1040                          HDMI_PHY_CONF0_ENTMDS_MASK);
1041 }
1042
1043 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1044 {
1045         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1046                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1047                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1048 }
1049
1050 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1051 {
1052         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1053                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1054                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1055 }
1056
1057 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1058 {
1059         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1060                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1061                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1062 }
1063
1064 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1065 {
1066         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1067                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1068                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1069 }
1070
1071 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1072 {
1073         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1074                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1075                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1076 }
1077
1078 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1079                               unsigned char res, int cscon)
1080 {
1081         unsigned res_idx;
1082         u8 val, msec, tmds_cfg;
1083         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1084         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1085         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1086         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1087
1088         if (prep)
1089                 return -EINVAL;
1090
1091         switch (res) {
1092         case 0: /* color resolution 0 is 8 bit colour depth */
1093         case 8:
1094                 res_idx = DW_HDMI_RES_8;
1095                 break;
1096         case 10:
1097                 res_idx = DW_HDMI_RES_10;
1098                 break;
1099         case 12:
1100                 res_idx = DW_HDMI_RES_12;
1101                 break;
1102         default:
1103                 return -EINVAL;
1104         }
1105
1106         /* PLL/MPLL Cfg - always match on final entry */
1107         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1108                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1109                     mpll_config->mpixelclock)
1110                         break;
1111
1112         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1113                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1114                     curr_ctrl->mpixelclock)
1115                         break;
1116
1117         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1118                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1119                     phy_config->mpixelclock)
1120                         break;
1121
1122         if (mpll_config->mpixelclock == ~0UL ||
1123             curr_ctrl->mpixelclock == ~0UL ||
1124             phy_config->mpixelclock == ~0UL) {
1125                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1126                         hdmi->hdmi_data.video_mode.mpixelclock);
1127                 return -EINVAL;
1128         }
1129
1130         /* Enable csc path */
1131         if (cscon)
1132                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1133         else
1134                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1135
1136         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1137
1138         /* gen2 tx power off */
1139         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1140
1141         /* gen2 pddq */
1142         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1143
1144         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1145         if (hdmi->connector.scdc_present) {
1146                 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1147                 if (mpll_config->mpixelclock > 340000000)
1148                         tmds_cfg |= 2;
1149                 else
1150                         tmds_cfg &= 0x1;
1151                 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1152         }
1153
1154         /* PHY reset */
1155         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1156         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1157
1158         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1159
1160         hdmi_phy_test_clear(hdmi, 1);
1161         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1162                     HDMI_PHY_I2CM_SLAVE_ADDR);
1163         hdmi_phy_test_clear(hdmi, 0);
1164         /*
1165          * RK3399 mpll clock source is vpll, also is vop clock source.
1166          * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1167          * to enable mpll pre-divider.
1168          */
1169         if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
1170             hdmi->dev_type == RK3399_HDMI)
1171                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
1172                                    0x06);
1173         else
1174                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1175         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1176
1177         /* CURRCTRL */
1178         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1179
1180         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1181         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1182
1183         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1184         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1185         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1186
1187         /* REMOVE CLK TERM */
1188         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1189
1190         dw_hdmi_phy_enable_powerdown(hdmi, false);
1191
1192         /* toggle TMDS disable */
1193         dw_hdmi_phy_enable_tmds(hdmi, 0);
1194
1195         /* Wait for resuming transmission of TMDS clock and data */
1196         if (mpll_config->mpixelclock > 340000000)
1197                 msleep(100);
1198
1199         /* toggle TMDS enable */
1200         dw_hdmi_phy_enable_tmds(hdmi, 1);
1201
1202         /* gen2 tx power on */
1203         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1204         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1205
1206         if (is_rockchip(hdmi->dev_type))
1207                 dw_hdmi_phy_enable_spare(hdmi, 1);
1208
1209         /* Wait for PHY PLL lock */
1210         msec = 5;
1211         do {
1212                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1213                 if (!val)
1214                         break;
1215
1216                 if (msec == 0) {
1217                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1218                         return -ETIMEDOUT;
1219                 }
1220
1221                 udelay(1000);
1222                 msec--;
1223         } while (1);
1224
1225         return 0;
1226 }
1227
1228 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1229 {
1230         int i, ret;
1231         bool cscon;
1232
1233         /*check csc whether needed activated in HDMI mode */
1234         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1235
1236         /* HDMI Phy spec says to do the phy initialization sequence twice */
1237         for (i = 0; i < 2; i++) {
1238                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1239                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1240                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1241                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1242
1243                 /* Enable CSC */
1244                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1245                 if (ret)
1246                         return ret;
1247         }
1248
1249         hdmi->phy_enabled = true;
1250         return 0;
1251 }
1252
1253 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1254 {
1255         u8 de;
1256
1257         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1258                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1259         else
1260                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1261
1262         /* disable rx detect */
1263         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1264                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1265
1266         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1267
1268         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1269                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1270 }
1271
1272 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1273 {
1274         struct hdmi_avi_infoframe frame;
1275         u8 val;
1276
1277         /* Initialise info frame from DRM mode */
1278         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1279
1280         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1281                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1282         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1283                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1284         else if (hdmi->hdmi_data.enc_out_format == YCBCR420)
1285                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1286         else
1287                 frame.colorspace = HDMI_COLORSPACE_RGB;
1288
1289         /* Set up colorimetry */
1290         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1291                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1292                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1293                         frame.extended_colorimetry =
1294                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1295                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1296                         frame.extended_colorimetry =
1297                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1298         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1299                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1300                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1301         } else { /* Carries no data */
1302                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1303                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1304         }
1305
1306         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1307
1308         /*
1309          * The Designware IP uses a different byte format from standard
1310          * AVI info frames, though generally the bits are in the correct
1311          * bytes.
1312          */
1313
1314         /*
1315          * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1316          * 5,6,7, active aspect present in bit 6 rather than 4.
1317          */
1318         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1319         if (frame.active_aspect & 15)
1320                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1321         if (frame.top_bar || frame.bottom_bar)
1322                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1323         if (frame.left_bar || frame.right_bar)
1324                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1325         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1326
1327         /* AVI data byte 2 differences: none */
1328         val = ((frame.colorimetry & 0x3) << 6) |
1329               ((frame.picture_aspect & 0x3) << 4) |
1330               (frame.active_aspect & 0xf);
1331         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1332
1333         /* AVI data byte 3 differences: none */
1334         val = ((frame.extended_colorimetry & 0x7) << 4) |
1335               ((frame.quantization_range & 0x3) << 2) |
1336               (frame.nups & 0x3);
1337         if (frame.itc)
1338                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1339         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1340
1341         /* AVI data byte 4 differences: none */
1342         val = frame.video_code & 0x7f;
1343         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1344
1345         /* AVI Data Byte 5- set up input and output pixel repetition */
1346         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1347                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1348                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1349                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1350                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1351                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1352         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1353
1354         /*
1355          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1356          * ycc range in bits 2,3 rather than 6,7
1357          */
1358         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1359               (frame.content_type & 0x3);
1360         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1361
1362         /* AVI Data Bytes 6-13 */
1363         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1364         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1365         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1366         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1367         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1368         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1369         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1370         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1371 }
1372
1373 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1374                              const struct drm_display_mode *mode)
1375 {
1376         u8 inv_val, bytes;
1377         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1378         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1379         unsigned int hdisplay, vdisplay;
1380
1381         vmode->mpixelclock = mode->crtc_clock * 1000;
1382         if (mode->flags & DRM_MODE_FLAG_420_MASK)
1383                 vmode->mpixelclock /= 2;
1384         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1385
1386         /* Set up HDMI_FC_INVIDCONF
1387          * fc_invidconf.HDCP_keepout must be set (1'b1)
1388          * when activate the scrambler feature.
1389          */
1390         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1391                    vmode->mpixelclock > 340000000 ||
1392                    hdmi->connector.lte_340mcsc_scramble ?
1393                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1394                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1395
1396         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1397                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1398                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1399
1400         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1401                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1402                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1403
1404         inv_val |= (vmode->mdataenablepolarity ?
1405                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1406                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1407
1408         if (hdmi->vic == 39)
1409                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1410         else
1411                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1412                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1413                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1414
1415         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1416                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1417                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1418
1419         inv_val |= hdmi->sink_is_hdmi ?
1420                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1421                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1422
1423         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1424
1425         hdisplay = mode->hdisplay;
1426         hblank = mode->htotal - mode->hdisplay;
1427         h_de_hs = mode->hsync_start - mode->hdisplay;
1428         hsync_len = mode->hsync_end - mode->hsync_start;
1429
1430         /*
1431          * When we're setting a YCbCr420 mode, we need
1432          * to adjust the horizontal timing to suit.
1433          */
1434         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1435                 hdisplay /= 2;
1436                 hblank /= 2;
1437                 h_de_hs /= 2;
1438                 hsync_len /= 2;
1439         }
1440
1441         vdisplay = mode->vdisplay;
1442         vblank = mode->vtotal - mode->vdisplay;
1443         v_de_vs = mode->vsync_start - mode->vdisplay;
1444         vsync_len = mode->vsync_end - mode->vsync_start;
1445
1446         /*
1447          * When we're setting an interlaced mode, we need
1448          * to adjust the vertical timing to suit.
1449          */
1450         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1451                 vdisplay /= 2;
1452                 vblank /= 2;
1453                 v_de_vs /= 2;
1454                 vsync_len /= 2;
1455         }
1456
1457         /* Scrambling Control */
1458         if (hdmi->connector.scdc_present) {
1459                 if (vmode->mpixelclock > 340000000 ||
1460                     hdmi->connector.lte_340mcsc_scramble) {
1461                         drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1462                                        &bytes);
1463                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1464                                         bytes);
1465                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1466                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1467                                     HDMI_MC_SWRSTZ);
1468                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1469                 } else {
1470                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1471                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1472                                     HDMI_MC_SWRSTZ);
1473                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1474                 }
1475         }
1476
1477         /* Set up horizontal active pixel width */
1478         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1479         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1480
1481         /* Set up vertical active lines */
1482         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1483         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1484
1485         /* Set up horizontal blanking pixel region width */
1486         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1487         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1488
1489         /* Set up vertical blanking pixel region width */
1490         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1491
1492         /* Set up HSYNC active edge delay width (in pixel clks) */
1493         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1494         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1495
1496         /* Set up VSYNC active edge delay (in lines) */
1497         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1498
1499         /* Set up HSYNC active pulse width (in pixel clks) */
1500         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1501         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1502
1503         /* Set up VSYNC active edge delay (in lines) */
1504         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1505 }
1506
1507 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1508 {
1509         if (!hdmi->phy_enabled)
1510                 return;
1511
1512         dw_hdmi_phy_enable_tmds(hdmi, 0);
1513         dw_hdmi_phy_enable_powerdown(hdmi, true);
1514
1515         hdmi->phy_enabled = false;
1516 }
1517
1518 /* HDMI Initialization Step B.4 */
1519 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1520 {
1521         u8 clkdis;
1522
1523         /* control period minimum duration */
1524         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1525         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1526         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1527
1528         /* Set to fill TMDS data channels */
1529         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1530         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1531         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1532
1533         /* Enable pixel clock and tmds data path */
1534         clkdis = 0x7F;
1535         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1536         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1537
1538         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1539         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1540
1541         /* Enable csc path */
1542         if (is_color_space_conversion(hdmi)) {
1543                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1544                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1545         }
1546
1547         /* Enable pixel repetition path */
1548         if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1549                 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1550                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1551         }
1552 }
1553
1554 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1555 {
1556         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1557 }
1558
1559 /* Workaround to clear the overflow condition */
1560 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1561 {
1562         int count;
1563         u8 val;
1564
1565         /* TMDS software reset */
1566         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1567
1568         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1569         if (hdmi->dev_type == IMX6DL_HDMI) {
1570                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1571                 return;
1572         }
1573
1574         for (count = 0; count < 4; count++)
1575                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1576 }
1577
1578 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1579 {
1580         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1581         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1582 }
1583
1584 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1585 {
1586         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1587                     HDMI_IH_MUTE_FC_STAT2);
1588 }
1589
1590 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1591 {
1592         int ret;
1593
1594         hdmi_disable_overflow_interrupts(hdmi);
1595
1596         hdmi->vic = drm_match_cea_mode(mode);
1597
1598         if (!hdmi->vic) {
1599                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1600         } else {
1601                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1602         }
1603
1604         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1605             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1606             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1607             (hdmi->vic == 17) || (hdmi->vic == 18))
1608                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1609         else
1610                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1611
1612         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1613                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1614                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1615         } else {
1616                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1617                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1618         }
1619         /* TODO: Get input format from IPU (via FB driver interface) */
1620         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1621                 hdmi->hdmi_data.enc_in_format = YCBCR420;
1622                 hdmi->hdmi_data.enc_out_format = YCBCR420;
1623         } else {
1624                 hdmi->hdmi_data.enc_in_format = RGB;
1625                 hdmi->hdmi_data.enc_out_format = RGB;
1626         }
1627         hdmi->hdmi_data.enc_color_depth = 8;
1628         /*
1629          * According to the dw-hdmi specification 6.4.2
1630          * vp_pr_cd[3:0]:
1631          * 0000b: No pixel repetition (pixel sent only once)
1632          * 0001b: Pixel sent two times (pixel repeated once)
1633          */
1634         hdmi->hdmi_data.pix_repet_factor =
1635                 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1636         hdmi->hdmi_data.hdcp_enable = 0;
1637         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1638
1639         /* HDMI Initialization Step B.1 */
1640         hdmi_av_composer(hdmi, mode);
1641
1642         /* HDMI Initializateion Step B.2 */
1643         ret = dw_hdmi_phy_init(hdmi);
1644         if (ret)
1645                 return ret;
1646
1647         /* HDMI Initialization Step B.3 */
1648         dw_hdmi_enable_video_path(hdmi);
1649
1650         if (hdmi->sink_has_audio) {
1651                 dev_dbg(hdmi->dev, "sink has audio support\n");
1652
1653                 /* HDMI Initialization Step E - Configure audio */
1654                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1655                 hdmi_enable_audio_clk(hdmi);
1656         }
1657
1658         /* not for DVI mode */
1659         if (hdmi->sink_is_hdmi) {
1660                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1661
1662                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1663                 hdmi_config_AVI(hdmi, mode);
1664         } else {
1665                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1666         }
1667
1668         hdmi_video_packetize(hdmi);
1669         hdmi_video_csc(hdmi);
1670         hdmi_video_sample(hdmi);
1671         hdmi_tx_hdcp_config(hdmi);
1672
1673         dw_hdmi_clear_overflow(hdmi);
1674         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1675                 hdmi_enable_overflow_interrupts(hdmi);
1676
1677         return 0;
1678 }
1679
1680 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1681 {
1682         u8 ih_mute;
1683
1684         /*
1685          * Boot up defaults are:
1686          * HDMI_IH_MUTE   = 0x03 (disabled)
1687          * HDMI_IH_MUTE_* = 0x00 (enabled)
1688          *
1689          * Disable top level interrupt bits in HDMI block
1690          */
1691         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1692                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1693                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1694
1695         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1696
1697         /* by default mask all interrupts */
1698         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1699         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1700         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1701         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1702         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1703         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1704         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1705         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1706         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1707         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1708         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1709         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1710         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1711         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1712         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1713
1714         /* Disable interrupts in the IH_MUTE_* registers */
1715         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1716         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1717         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1718         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1719         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1720         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1721         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1722         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1723         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1724         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1725
1726         /* Enable top level interrupt bits in HDMI block */
1727         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1728                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1729         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1730 }
1731
1732 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1733 {
1734         hdmi->bridge_is_on = true;
1735         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1736 }
1737
1738 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1739 {
1740         dw_hdmi_phy_disable(hdmi);
1741         hdmi->bridge_is_on = false;
1742 }
1743
1744 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1745 {
1746         int force = hdmi->force;
1747
1748         if (hdmi->disabled) {
1749                 force = DRM_FORCE_OFF;
1750         } else if (force == DRM_FORCE_UNSPECIFIED) {
1751                 if (hdmi->rxsense)
1752                         force = DRM_FORCE_ON;
1753                 else
1754                         force = DRM_FORCE_OFF;
1755         }
1756
1757         if (force == DRM_FORCE_OFF) {
1758                 if (hdmi->bridge_is_on)
1759                         dw_hdmi_poweroff(hdmi);
1760         } else {
1761                 if (!hdmi->bridge_is_on)
1762                         dw_hdmi_poweron(hdmi);
1763         }
1764 }
1765
1766 /*
1767  * Adjust the detection of RXSENSE according to whether we have a forced
1768  * connection mode enabled, or whether we have been disabled.  There is
1769  * no point processing RXSENSE interrupts if we have a forced connection
1770  * state, or DRM has us disabled.
1771  *
1772  * We also disable rxsense interrupts when we think we're disconnected
1773  * to avoid floating TDMS signals giving false rxsense interrupts.
1774  *
1775  * Note: we still need to listen for HPD interrupts even when DRM has us
1776  * disabled so that we can detect a connect event.
1777  */
1778 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1779 {
1780         u8 old_mask = hdmi->phy_mask;
1781
1782         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1783                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1784         else
1785                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1786
1787         if (old_mask != hdmi->phy_mask)
1788                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1789 }
1790
1791 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1792                                     struct drm_display_mode *orig_mode,
1793                                     struct drm_display_mode *mode)
1794 {
1795         struct dw_hdmi *hdmi = bridge->driver_private;
1796
1797         mutex_lock(&hdmi->mutex);
1798
1799         /* Store the display mode for plugin/DKMS poweron events */
1800         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1801
1802         mutex_unlock(&hdmi->mutex);
1803 }
1804
1805 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1806 {
1807         struct dw_hdmi *hdmi = bridge->driver_private;
1808
1809         mutex_lock(&hdmi->mutex);
1810         hdmi->disabled = true;
1811         dw_hdmi_update_power(hdmi);
1812         dw_hdmi_update_phy_mask(hdmi);
1813         mutex_unlock(&hdmi->mutex);
1814 }
1815
1816 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1817 {
1818         struct dw_hdmi *hdmi = bridge->driver_private;
1819
1820         mutex_lock(&hdmi->mutex);
1821         hdmi->disabled = false;
1822         dw_hdmi_update_power(hdmi);
1823         dw_hdmi_update_phy_mask(hdmi);
1824         mutex_unlock(&hdmi->mutex);
1825 }
1826
1827 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1828 {
1829         /* do nothing */
1830 }
1831
1832 static enum drm_connector_status
1833 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1834 {
1835         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1836                                              connector);
1837
1838         mutex_lock(&hdmi->mutex);
1839         hdmi->force = DRM_FORCE_UNSPECIFIED;
1840         dw_hdmi_update_power(hdmi);
1841         dw_hdmi_update_phy_mask(hdmi);
1842         mutex_unlock(&hdmi->mutex);
1843
1844         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1845                 connector_status_connected : connector_status_disconnected;
1846 }
1847
1848 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1849 {
1850         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1851                                              connector);
1852         struct edid *edid;
1853         int ret = 0;
1854
1855         if (!hdmi->ddc)
1856                 return 0;
1857
1858         edid = drm_get_edid(connector, hdmi->ddc);
1859         if (edid) {
1860                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1861                         edid->width_cm, edid->height_cm);
1862
1863                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1864                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1865                 drm_mode_connector_update_edid_property(connector, edid);
1866                 ret = drm_add_edid_modes(connector, edid);
1867                 /* Store the ELD */
1868                 drm_edid_to_eld(connector, edid);
1869                 kfree(edid);
1870         } else {
1871                 dev_dbg(hdmi->dev, "failed to get edid\n");
1872         }
1873
1874         return ret;
1875 }
1876
1877 static enum drm_mode_status
1878 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1879                              struct drm_display_mode *mode)
1880 {
1881         struct dw_hdmi *hdmi = container_of(connector,
1882                                            struct dw_hdmi, connector);
1883         enum drm_mode_status mode_status = MODE_OK;
1884
1885         if (hdmi->plat_data->mode_valid)
1886                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1887
1888         return mode_status;
1889 }
1890
1891 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1892                                                            *connector)
1893 {
1894         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1895                                              connector);
1896
1897         return hdmi->encoder;
1898 }
1899
1900 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1901 {
1902         drm_connector_unregister(connector);
1903         drm_connector_cleanup(connector);
1904 }
1905
1906 static void dw_hdmi_connector_force(struct drm_connector *connector)
1907 {
1908         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1909                                              connector);
1910
1911         mutex_lock(&hdmi->mutex);
1912         hdmi->force = connector->force;
1913         dw_hdmi_update_power(hdmi);
1914         dw_hdmi_update_phy_mask(hdmi);
1915         mutex_unlock(&hdmi->mutex);
1916 }
1917
1918 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1919         .dpms = drm_helper_connector_dpms,
1920         .fill_modes = drm_helper_probe_single_connector_modes,
1921         .detect = dw_hdmi_connector_detect,
1922         .destroy = dw_hdmi_connector_destroy,
1923         .force = dw_hdmi_connector_force,
1924 };
1925
1926 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1927         .dpms = drm_atomic_helper_connector_dpms,
1928         .fill_modes = drm_helper_probe_single_connector_modes,
1929         .detect = dw_hdmi_connector_detect,
1930         .destroy = dw_hdmi_connector_destroy,
1931         .force = dw_hdmi_connector_force,
1932         .reset = drm_atomic_helper_connector_reset,
1933         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1934         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1935 };
1936
1937 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1938         .get_modes = dw_hdmi_connector_get_modes,
1939         .mode_valid = dw_hdmi_connector_mode_valid,
1940         .best_encoder = dw_hdmi_connector_best_encoder,
1941 };
1942
1943 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1944         .enable = dw_hdmi_bridge_enable,
1945         .disable = dw_hdmi_bridge_disable,
1946         .pre_enable = dw_hdmi_bridge_nop,
1947         .post_disable = dw_hdmi_bridge_nop,
1948         .mode_set = dw_hdmi_bridge_mode_set,
1949 };
1950
1951 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1952 {
1953         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1954         unsigned int stat;
1955
1956         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1957         if (!stat)
1958                 return IRQ_NONE;
1959
1960         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1961
1962         i2c->stat = stat;
1963
1964         complete(&i2c->cmp);
1965
1966         return IRQ_HANDLED;
1967 }
1968
1969 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1970 {
1971         struct dw_hdmi *hdmi = dev_id;
1972         u8 intr_stat;
1973         irqreturn_t ret = IRQ_NONE;
1974
1975         if (hdmi->i2c)
1976                 ret = dw_hdmi_i2c_irq(hdmi);
1977
1978         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1979         if (intr_stat) {
1980                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1981                 return IRQ_WAKE_THREAD;
1982         }
1983
1984         return ret;
1985 }
1986
1987 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1988 {
1989         struct dw_hdmi *hdmi = dev_id;
1990         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1991
1992         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1993         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1994         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1995
1996         phy_pol_mask = 0;
1997         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1998                 phy_pol_mask |= HDMI_PHY_HPD;
1999         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2000                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2001         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2002                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2003         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2004                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2005         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2006                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2007
2008         if (phy_pol_mask)
2009                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2010
2011         /*
2012          * RX sense tells us whether the TDMS transmitters are detecting
2013          * load - in other words, there's something listening on the
2014          * other end of the link.  Use this to decide whether we should
2015          * power on the phy as HPD may be toggled by the sink to merely
2016          * ask the source to re-read the EDID.
2017          */
2018         if (intr_stat &
2019             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2020                 mutex_lock(&hdmi->mutex);
2021                 if (!hdmi->bridge_is_on && !hdmi->force) {
2022                         /*
2023                          * If the RX sense status indicates we're disconnected,
2024                          * clear the software rxsense status.
2025                          */
2026                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
2027                                 hdmi->rxsense = false;
2028
2029                         /*
2030                          * Only set the software rxsense status when both
2031                          * rxsense and hpd indicates we're connected.
2032                          * This avoids what seems to be bad behaviour in
2033                          * at least iMX6S versions of the phy.
2034                          */
2035                         if (phy_stat & HDMI_PHY_HPD)
2036                                 hdmi->rxsense = true;
2037
2038                         dw_hdmi_update_power(hdmi);
2039                         dw_hdmi_update_phy_mask(hdmi);
2040                 }
2041                 mutex_unlock(&hdmi->mutex);
2042         }
2043
2044         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2045                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2046                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2047                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
2048 #ifdef CONFIG_SWITCH
2049                 if (phy_int_pol & HDMI_PHY_HPD)
2050                         switch_set_state(&hdmi->switchdev, 1);
2051                 else
2052                         switch_set_state(&hdmi->switchdev, 0);
2053 #endif
2054         }
2055
2056         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2057         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2058                     HDMI_IH_MUTE_PHY_STAT0);
2059
2060         return IRQ_HANDLED;
2061 }
2062
2063 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2064 {
2065         struct drm_encoder *encoder = hdmi->encoder;
2066         struct drm_bridge *bridge;
2067         int ret;
2068
2069         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2070         if (!bridge) {
2071                 DRM_ERROR("Failed to allocate drm bridge\n");
2072                 return -ENOMEM;
2073         }
2074
2075         hdmi->bridge = bridge;
2076         bridge->driver_private = hdmi;
2077         bridge->funcs = &dw_hdmi_bridge_funcs;
2078         ret = drm_bridge_attach(drm, bridge);
2079         if (ret) {
2080                 DRM_ERROR("Failed to initialize bridge with drm\n");
2081                 return -EINVAL;
2082         }
2083
2084         encoder->bridge = bridge;
2085         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2086         hdmi->connector.port = hdmi->dev->of_node;
2087
2088         drm_connector_helper_add(&hdmi->connector,
2089                                  &dw_hdmi_connector_helper_funcs);
2090
2091         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2092                 drm_connector_init(drm, &hdmi->connector,
2093                                    &dw_hdmi_atomic_connector_funcs,
2094                                    DRM_MODE_CONNECTOR_HDMIA);
2095         else
2096                 drm_connector_init(drm, &hdmi->connector,
2097                                    &dw_hdmi_connector_funcs,
2098                                    DRM_MODE_CONNECTOR_HDMIA);
2099
2100         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2101
2102         return 0;
2103 }
2104
2105 int dw_hdmi_bind(struct device *dev, struct device *master,
2106                  void *data, struct drm_encoder *encoder,
2107                  struct resource *iores, int irq,
2108                  const struct dw_hdmi_plat_data *plat_data)
2109 {
2110         struct drm_device *drm = data;
2111         struct device_node *np = dev->of_node;
2112         struct platform_device_info pdevinfo;
2113         struct device_node *ddc_node;
2114         struct dw_hdmi *hdmi;
2115         int ret;
2116         u32 val = 1;
2117         u8 config0;
2118         u8 config1;
2119
2120         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2121         if (!hdmi)
2122                 return -ENOMEM;
2123
2124         hdmi->connector.interlace_allowed = 1;
2125
2126         hdmi->plat_data = plat_data;
2127         hdmi->dev = dev;
2128         hdmi->dev_type = plat_data->dev_type;
2129         hdmi->sample_rate = 48000;
2130         hdmi->encoder = encoder;
2131         hdmi->disabled = true;
2132         hdmi->rxsense = true;
2133         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2134
2135         mutex_init(&hdmi->mutex);
2136         mutex_init(&hdmi->audio_mutex);
2137         spin_lock_init(&hdmi->audio_lock);
2138
2139         of_property_read_u32(np, "reg-io-width", &val);
2140
2141         switch (val) {
2142         case 4:
2143                 hdmi->write = dw_hdmi_writel;
2144                 hdmi->read = dw_hdmi_readl;
2145                 break;
2146         case 1:
2147                 hdmi->write = dw_hdmi_writeb;
2148                 hdmi->read = dw_hdmi_readb;
2149                 break;
2150         default:
2151                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2152                 return -EINVAL;
2153         }
2154
2155         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2156         if (ddc_node) {
2157                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2158                 of_node_put(ddc_node);
2159                 if (!hdmi->ddc) {
2160                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2161                         return -EPROBE_DEFER;
2162                 }
2163
2164         } else {
2165                 dev_dbg(hdmi->dev, "no ddc property found\n");
2166         }
2167
2168         /* If DDC bus is not specified, try to register HDMI I2C bus */
2169         if (!hdmi->ddc) {
2170                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2171                 if (IS_ERR(hdmi->ddc))
2172                         hdmi->ddc = NULL;
2173         }
2174
2175         hdmi->regs = devm_ioremap_resource(dev, iores);
2176         if (IS_ERR(hdmi->regs))
2177                 return PTR_ERR(hdmi->regs);
2178
2179         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2180         if (IS_ERR(hdmi->isfr_clk)) {
2181                 ret = PTR_ERR(hdmi->isfr_clk);
2182                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2183                 return ret;
2184         }
2185
2186         ret = clk_prepare_enable(hdmi->isfr_clk);
2187         if (ret) {
2188                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2189                 return ret;
2190         }
2191
2192         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2193         if (IS_ERR(hdmi->iahb_clk)) {
2194                 ret = PTR_ERR(hdmi->iahb_clk);
2195                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2196                 goto err_isfr;
2197         }
2198
2199         ret = clk_prepare_enable(hdmi->iahb_clk);
2200         if (ret) {
2201                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2202                 goto err_isfr;
2203         }
2204
2205         /* Product and revision IDs */
2206         dev_info(dev,
2207                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2208                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2209                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2210                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2211                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2212
2213         initialize_hdmi_ih_mutes(hdmi);
2214
2215         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2216                                         dw_hdmi_irq, IRQF_SHARED,
2217                                         dev_name(dev), hdmi);
2218         if (ret)
2219                 goto err_iahb;
2220
2221         /*
2222          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2223          * N and cts values before enabling phy
2224          */
2225         hdmi_init_clk_regenerator(hdmi);
2226
2227         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2228                     HDMI_PHY_I2CM_INT_ADDR);
2229
2230         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2231                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2232                     HDMI_PHY_I2CM_CTLINT_ADDR);
2233
2234         /* Re-init HPD polarity */
2235         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2236
2237         /* Unmask HPD, clear transitory interrupts, then unmute */
2238         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2239
2240         ret = dw_hdmi_register(drm, hdmi);
2241         if (ret)
2242                 goto err_iahb;
2243
2244 #ifdef CONFIG_SWITCH
2245         hdmi->switchdev.name = "hdmi";
2246         switch_dev_register(&hdmi->switchdev);
2247 #endif
2248
2249         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2250                     HDMI_IH_MUTE_PHY_STAT0);
2251
2252         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2253         if (hdmi->i2c)
2254                 dw_hdmi_i2c_init(hdmi);
2255
2256         memset(&pdevinfo, 0, sizeof(pdevinfo));
2257         pdevinfo.parent = dev;
2258         pdevinfo.id = PLATFORM_DEVID_AUTO;
2259
2260         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2261         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2262
2263         if (config1 & HDMI_CONFIG1_AHB) {
2264                 struct dw_hdmi_audio_data audio;
2265
2266                 audio.phys = iores->start;
2267                 audio.base = hdmi->regs;
2268                 audio.irq = irq;
2269                 audio.hdmi = hdmi;
2270                 audio.eld = hdmi->connector.eld;
2271
2272                 pdevinfo.name = "dw-hdmi-ahb-audio";
2273                 pdevinfo.data = &audio;
2274                 pdevinfo.size_data = sizeof(audio);
2275                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2276                 hdmi->audio = platform_device_register_full(&pdevinfo);
2277         } else if (config0 & HDMI_CONFIG0_I2S) {
2278                 struct dw_hdmi_i2s_audio_data audio;
2279
2280                 audio.hdmi      = hdmi;
2281                 audio.write     = hdmi_writeb;
2282                 audio.read      = hdmi_readb;
2283
2284                 pdevinfo.name = "dw-hdmi-i2s-audio";
2285                 pdevinfo.data = &audio;
2286                 pdevinfo.size_data = sizeof(audio);
2287                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2288                 hdmi->audio = platform_device_register_full(&pdevinfo);
2289         }
2290
2291         dev_set_drvdata(dev, hdmi);
2292
2293         return 0;
2294
2295 err_iahb:
2296         if (hdmi->i2c)
2297                 i2c_del_adapter(&hdmi->i2c->adap);
2298
2299         clk_disable_unprepare(hdmi->iahb_clk);
2300 err_isfr:
2301         clk_disable_unprepare(hdmi->isfr_clk);
2302
2303         return ret;
2304 }
2305 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2306
2307 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2308 {
2309         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2310
2311         if (hdmi->audio && !IS_ERR(hdmi->audio))
2312                 platform_device_unregister(hdmi->audio);
2313
2314         /* Disable all interrupts */
2315         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2316
2317 #ifdef CONFIG_SWITCH
2318         switch_dev_unregister(&hdmi->switchdev);
2319 #endif
2320         hdmi->connector.funcs->destroy(&hdmi->connector);
2321         hdmi->encoder->funcs->destroy(hdmi->encoder);
2322
2323         clk_disable_unprepare(hdmi->iahb_clk);
2324         clk_disable_unprepare(hdmi->isfr_clk);
2325
2326         if (hdmi->i2c)
2327                 i2c_del_adapter(&hdmi->i2c->adap);
2328         else
2329                 i2c_put_adapter(hdmi->ddc);
2330 }
2331 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2332
2333 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2334 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2335 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2336 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2337 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2338 MODULE_LICENSE("GPL");
2339 MODULE_ALIAS("platform:dw-hdmi");