2 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * Designware High-Definition Multimedia Interface (HDMI) driver
16 #include <linux/module.h>
17 #include <linux/irq.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/hdmi.h>
22 #include <linux/mutex.h>
23 #include <linux/of_device.h>
24 #include <linux/spinlock.h>
26 #include <drm/drm_of.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_encoder_slave.h>
32 #include <drm/drm_scdc_helper.h>
33 #include <drm/bridge/dw_hdmi.h>
35 #include <linux/switch.h>
39 #include "dw-hdmi-audio.h"
41 #define HDMI_EDID_LEN 512
42 #define DDC_SEGMENT_ADDR 0x30
46 #define YCBCR422_16BITS 2
47 #define YCBCR422_8BITS 3
66 * Unless otherwise noted, entries in this table are 100% optimization.
67 * Values can be obtained from hdmi_compute_n() but that function is
68 * slow so we pre-compute values we expect to see.
70 * All 32k and 48k values are expected to be the same (due to the way
71 * the math works) for any rate that's an exact kHz.
73 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
74 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
75 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
76 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
77 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
78 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
79 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
80 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
81 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
82 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
83 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
84 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
85 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
86 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
87 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
88 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
89 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
90 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
91 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
92 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
93 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
94 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
95 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
96 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
97 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
98 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
99 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
100 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
101 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
102 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
103 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
104 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
105 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
106 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
107 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
108 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
109 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
110 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
112 /* For 297 MHz+ HDMI spec have some other rule for setting N */
113 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
114 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
117 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
121 static const u16 csc_coeff_default[3][4] = {
122 { 0x2000, 0x0000, 0x0000, 0x0000 },
123 { 0x0000, 0x2000, 0x0000, 0x0000 },
124 { 0x0000, 0x0000, 0x2000, 0x0000 }
127 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
128 { 0x2000, 0x6926, 0x74fd, 0x010e },
129 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
130 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
133 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
134 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
135 { 0x2000, 0x3264, 0x0000, 0x7e6d },
136 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
139 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
140 { 0x2591, 0x1322, 0x074b, 0x0000 },
141 { 0x6535, 0x2000, 0x7acc, 0x0200 },
142 { 0x6acd, 0x7534, 0x2000, 0x0200 }
145 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
146 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
147 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
148 { 0x6756, 0x78ab, 0x2000, 0x0200 }
152 bool mdataenablepolarity;
154 unsigned int mpixelclock;
155 unsigned int mpixelrepetitioninput;
156 unsigned int mpixelrepetitionoutput;
159 struct hdmi_data_info {
160 unsigned int enc_in_format;
161 unsigned int enc_out_format;
162 unsigned int enc_color_depth;
163 unsigned int colorimetry;
164 unsigned int pix_repet_factor;
165 unsigned int hdcp_enable;
166 struct hdmi_vmode video_mode;
170 struct i2c_adapter adap;
173 struct completion cmp;
182 struct drm_connector connector;
183 struct drm_encoder *encoder;
184 struct drm_bridge *bridge;
186 struct platform_device *audio;
187 enum dw_hdmi_devtype dev_type;
189 struct clk *isfr_clk;
190 struct clk *iahb_clk;
191 struct dw_hdmi_i2c *i2c;
193 struct hdmi_data_info hdmi_data;
194 const struct dw_hdmi_plat_data *plat_data;
198 u8 edid[HDMI_EDID_LEN];
202 struct drm_display_mode previous_mode;
204 struct i2c_adapter *ddc;
209 struct mutex mutex; /* for state below and previous_mode */
210 enum drm_connector_force force; /* mutex-protected force state */
211 bool disabled; /* DRM has disabled our bridge */
212 bool bridge_is_on; /* indicates the bridge is on */
213 bool rxsense; /* rxsense state */
214 u8 phy_mask; /* desired phy int mask settings */
216 spinlock_t audio_lock;
217 struct mutex audio_mutex;
218 unsigned int sample_rate;
219 unsigned int audio_cts;
220 unsigned int audio_n;
224 struct switch_dev switchdev;
228 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
229 u8 (*read)(struct dw_hdmi *hdmi, int offset);
232 #define HDMI_IH_PHY_STAT0_RX_SENSE \
233 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
234 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
236 #define HDMI_PHY_RX_SENSE \
237 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
238 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
240 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
242 writel(val, hdmi->regs + (offset << 2));
245 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
247 return readl(hdmi->regs + (offset << 2));
250 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
252 writeb(val, hdmi->regs + offset);
255 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
257 return readb(hdmi->regs + offset);
260 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
262 hdmi->write(hdmi, val, offset);
265 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
267 return hdmi->read(hdmi, offset);
270 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
272 u8 val = hdmi_readb(hdmi, reg) & ~mask;
275 hdmi_writeb(hdmi, val, reg);
278 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
281 hdmi_modb(hdmi, data << shift, mask, reg);
284 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
287 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
289 /* Set Standard Mode speed */
290 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
291 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
293 /* Set done, not acknowledged and arbitration interrupt polarities */
294 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
295 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
298 /* Clear DONE and ERROR interrupts */
299 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
302 /* Mute DONE and ERROR interrupts */
303 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
304 HDMI_IH_MUTE_I2CM_STAT0);
307 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
308 unsigned char *buf, unsigned int length)
310 struct dw_hdmi_i2c *i2c = hdmi->i2c;
313 if (!i2c->is_regaddr) {
314 dev_dbg(hdmi->dev, "set read register address to 0\n");
315 i2c->slave_reg = 0x00;
316 i2c->is_regaddr = true;
320 reinit_completion(&i2c->cmp);
322 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
324 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
325 HDMI_I2CM_OPERATION);
327 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
328 HDMI_I2CM_OPERATION);
330 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
334 /* Check for error condition on the bus */
335 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
338 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
340 i2c->is_segment = false;
345 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
346 unsigned char *buf, unsigned int length)
348 struct dw_hdmi_i2c *i2c = hdmi->i2c;
351 if (!i2c->is_regaddr) {
352 /* Use the first write byte as register address */
353 i2c->slave_reg = buf[0];
356 i2c->is_regaddr = true;
360 reinit_completion(&i2c->cmp);
362 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
363 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
364 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
365 HDMI_I2CM_OPERATION);
367 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
371 /* Check for error condition on the bus */
372 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
379 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
380 struct i2c_msg *msgs, int num)
382 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
383 struct dw_hdmi_i2c *i2c = hdmi->i2c;
384 u8 addr = msgs[0].addr;
387 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
389 for (i = 0; i < num; i++) {
390 if (msgs[i].len == 0) {
392 "unsupported transfer %d/%d, no data\n",
398 mutex_lock(&i2c->lock);
400 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
402 /* Set slave device address taken from the first I2C message */
403 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
405 /* Set slave device register address on transfer */
406 i2c->is_regaddr = false;
408 /* Set segment pointer for I2C extended read mode operation */
409 i2c->is_segment = false;
411 for (i = 0; i < num; i++) {
412 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
413 i + 1, num, msgs[i].len, msgs[i].flags);
414 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
415 i2c->is_segment = true;
416 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
417 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
419 if (msgs[i].flags & I2C_M_RD)
420 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
423 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
433 /* Mute DONE and ERROR interrupts */
434 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
435 HDMI_IH_MUTE_I2CM_STAT0);
437 mutex_unlock(&i2c->lock);
442 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
444 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
447 static const struct i2c_algorithm dw_hdmi_algorithm = {
448 .master_xfer = dw_hdmi_i2c_xfer,
449 .functionality = dw_hdmi_i2c_func,
452 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
454 struct i2c_adapter *adap;
455 struct dw_hdmi_i2c *i2c;
458 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
460 return ERR_PTR(-ENOMEM);
462 mutex_init(&i2c->lock);
463 init_completion(&i2c->cmp);
466 adap->class = I2C_CLASS_DDC;
467 adap->owner = THIS_MODULE;
468 adap->dev.parent = hdmi->dev;
469 adap->dev.of_node = hdmi->dev->of_node;
470 adap->algo = &dw_hdmi_algorithm;
471 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
472 i2c_set_adapdata(adap, hdmi);
474 ret = i2c_add_adapter(adap);
476 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
477 devm_kfree(hdmi->dev, i2c);
483 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
488 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
491 /* Must be set/cleared first */
492 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
494 /* nshift factor = 0 */
495 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
497 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
498 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
499 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
500 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
502 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
503 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
504 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
507 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
508 unsigned long pixel_clk,
511 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
512 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
515 if (plat_data->tmds_n_table) {
516 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
517 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
518 tmds_n = &plat_data->tmds_n_table[i];
524 if (tmds_n == NULL) {
525 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
526 if (pixel_clk == common_tmds_n_table[i].tmds) {
527 tmds_n = &common_tmds_n_table[i];
538 return tmds_n->n_32k;
542 return (freq / 44100) * tmds_n->n_44k1;
546 return (freq / 48000) * tmds_n->n_48k;
552 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
553 unsigned int pixel_clk)
558 final = (u64)pixel_clk * n;
561 do_div(cts, 128 * freq);
563 diff = final - (u64)cts * (128 * freq);
568 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
569 unsigned long pixel_clk,
572 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
573 unsigned int max_n = (128 * freq) / 300;
574 unsigned int ideal_n = (128 * freq) / 1000;
575 unsigned int best_n_distance = ideal_n;
576 unsigned int best_n = 0;
577 u64 best_diff = U64_MAX;
580 /* If the ideal N could satisfy the audio math, then just take it */
581 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
584 for (n = min_n; n <= max_n; n++) {
585 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
587 if (diff < best_diff || (diff == best_diff &&
588 abs(n - ideal_n) < best_n_distance)) {
591 best_n_distance = abs(best_n - ideal_n);
595 * The best N already satisfy the audio math, and also be
596 * the closest value to ideal N, so just cut the loop.
598 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
605 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
606 unsigned long sample_rate)
610 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
614 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
617 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
620 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
621 unsigned long pixel_clk, unsigned int sample_rate)
623 unsigned long ftdms = pixel_clk;
627 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
630 * Compute the CTS value from the N value. Note that CTS and N
631 * can be up to 20 bits in total, so we need 64-bit math. Also
632 * note that our TDMS clock is not fully accurate; it is accurate
633 * to kHz. This can introduce an unnecessary remainder in the
634 * calculation below, so we don't try to warn about that.
636 tmp = (u64)ftdms * n;
637 do_div(tmp, 128 * sample_rate);
640 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
641 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
644 spin_lock_irq(&hdmi->audio_lock);
646 hdmi->audio_cts = cts;
647 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
648 spin_unlock_irq(&hdmi->audio_lock);
651 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
653 mutex_lock(&hdmi->audio_mutex);
654 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
655 mutex_unlock(&hdmi->audio_mutex);
658 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
660 mutex_lock(&hdmi->audio_mutex);
661 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
663 mutex_unlock(&hdmi->audio_mutex);
666 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
668 mutex_lock(&hdmi->audio_mutex);
669 hdmi->sample_rate = rate;
670 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
672 mutex_unlock(&hdmi->audio_mutex);
674 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
676 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
680 spin_lock_irqsave(&hdmi->audio_lock, flags);
681 hdmi->audio_enable = true;
682 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
683 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
685 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
687 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
691 spin_lock_irqsave(&hdmi->audio_lock, flags);
692 hdmi->audio_enable = false;
693 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
694 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
696 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
699 * this submodule is responsible for the video data synchronization.
700 * for example, for RGB 4:4:4 input, the data map is defined as
701 * pin{47~40} <==> R[7:0]
702 * pin{31~24} <==> G[7:0]
703 * pin{15~8} <==> B[7:0]
705 static void hdmi_video_sample(struct dw_hdmi *hdmi)
707 int color_format = 0;
710 if (hdmi->hdmi_data.enc_in_format == RGB) {
711 if (hdmi->hdmi_data.enc_color_depth == 8)
713 else if (hdmi->hdmi_data.enc_color_depth == 10)
715 else if (hdmi->hdmi_data.enc_color_depth == 12)
717 else if (hdmi->hdmi_data.enc_color_depth == 16)
721 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444 ||
722 hdmi->hdmi_data.enc_in_format == YCBCR420) {
723 if (hdmi->hdmi_data.enc_color_depth == 8)
725 else if (hdmi->hdmi_data.enc_color_depth == 10)
727 else if (hdmi->hdmi_data.enc_color_depth == 12)
729 else if (hdmi->hdmi_data.enc_color_depth == 16)
733 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
734 if (hdmi->hdmi_data.enc_color_depth == 8)
736 else if (hdmi->hdmi_data.enc_color_depth == 10)
738 else if (hdmi->hdmi_data.enc_color_depth == 12)
744 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
745 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
746 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
747 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
749 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
750 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
751 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
752 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
753 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
754 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
755 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
756 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
757 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
758 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
759 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
762 static int is_color_space_conversion(struct dw_hdmi *hdmi)
764 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
767 static int is_color_space_decimation(struct dw_hdmi *hdmi)
769 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
771 if (hdmi->hdmi_data.enc_in_format == RGB ||
772 hdmi->hdmi_data.enc_in_format == YCBCR444)
777 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
779 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
781 if (hdmi->hdmi_data.enc_out_format == RGB ||
782 hdmi->hdmi_data.enc_out_format == YCBCR444)
787 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
789 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
793 if (is_color_space_conversion(hdmi)) {
794 if (hdmi->hdmi_data.enc_out_format == RGB) {
795 if (hdmi->hdmi_data.colorimetry ==
796 HDMI_COLORIMETRY_ITU_601)
797 csc_coeff = &csc_coeff_rgb_out_eitu601;
799 csc_coeff = &csc_coeff_rgb_out_eitu709;
800 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
801 if (hdmi->hdmi_data.colorimetry ==
802 HDMI_COLORIMETRY_ITU_601)
803 csc_coeff = &csc_coeff_rgb_in_eitu601;
805 csc_coeff = &csc_coeff_rgb_in_eitu709;
810 /* The CSC registers are sequential, alternating MSB then LSB */
811 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
812 u16 coeff_a = (*csc_coeff)[0][i];
813 u16 coeff_b = (*csc_coeff)[1][i];
814 u16 coeff_c = (*csc_coeff)[2][i];
816 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
817 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
818 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
819 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
820 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
821 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
824 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
828 static void hdmi_video_csc(struct dw_hdmi *hdmi)
831 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
834 /* YCC422 interpolation to 444 mode */
835 if (is_color_space_interpolation(hdmi))
836 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
837 else if (is_color_space_decimation(hdmi))
838 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
840 if (hdmi->hdmi_data.enc_color_depth == 8)
841 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
842 else if (hdmi->hdmi_data.enc_color_depth == 10)
843 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
844 else if (hdmi->hdmi_data.enc_color_depth == 12)
845 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
846 else if (hdmi->hdmi_data.enc_color_depth == 16)
847 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
851 /* Configure the CSC registers */
852 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
853 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
856 dw_hdmi_update_csc_coeffs(hdmi);
860 * HDMI video packetizer is used to packetize the data.
861 * for example, if input is YCC422 mode or repeater is used,
862 * data should be repacked this module can be bypassed.
864 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
866 unsigned int color_depth = 0;
867 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
868 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
869 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
872 if (hdmi_data->enc_out_format == RGB ||
873 hdmi_data->enc_out_format == YCBCR444 ||
874 hdmi_data->enc_out_format == YCBCR420) {
875 if (!hdmi_data->enc_color_depth) {
876 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
877 } else if (hdmi_data->enc_color_depth == 8) {
879 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
880 } else if (hdmi_data->enc_color_depth == 10) {
882 } else if (hdmi_data->enc_color_depth == 12) {
884 } else if (hdmi_data->enc_color_depth == 16) {
889 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
890 if (!hdmi_data->enc_color_depth ||
891 hdmi_data->enc_color_depth == 8)
892 remap_size = HDMI_VP_REMAP_YCC422_16bit;
893 else if (hdmi_data->enc_color_depth == 10)
894 remap_size = HDMI_VP_REMAP_YCC422_20bit;
895 else if (hdmi_data->enc_color_depth == 12)
896 remap_size = HDMI_VP_REMAP_YCC422_24bit;
899 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
904 /* set the packetizer registers */
905 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
906 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
907 ((hdmi_data->pix_repet_factor <<
908 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
909 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
910 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
912 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
913 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
915 /* Data from pixel repeater block */
916 if (hdmi_data->pix_repet_factor > 0) {
917 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
918 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
919 } else { /* data from packetizer block */
920 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
921 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
924 hdmi_modb(hdmi, vp_conf,
925 HDMI_VP_CONF_PR_EN_MASK |
926 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
928 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
929 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
931 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
933 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
934 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
935 HDMI_VP_CONF_PP_EN_ENABLE |
936 HDMI_VP_CONF_YCC422_EN_DISABLE;
937 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
938 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
939 HDMI_VP_CONF_PP_EN_DISABLE |
940 HDMI_VP_CONF_YCC422_EN_ENABLE;
941 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
942 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
943 HDMI_VP_CONF_PP_EN_DISABLE |
944 HDMI_VP_CONF_YCC422_EN_DISABLE;
949 hdmi_modb(hdmi, vp_conf,
950 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
951 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
953 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
954 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
955 HDMI_VP_STUFF_PP_STUFFING_MASK |
956 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
958 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
962 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
965 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
966 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
969 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
972 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
973 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
976 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
979 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
980 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
983 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
986 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
989 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
992 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
995 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
999 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1004 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1009 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1012 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1013 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1014 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1015 HDMI_PHY_I2CM_DATAO_1_ADDR);
1016 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1017 HDMI_PHY_I2CM_DATAO_0_ADDR);
1018 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1019 HDMI_PHY_I2CM_OPERATION_ADDR);
1020 hdmi_phy_wait_i2c_done(hdmi, 1000);
1023 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1026 __hdmi_phy_i2c_write(hdmi, data, addr);
1030 static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1034 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1035 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1036 hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1037 hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1038 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1039 HDMI_PHY_I2CM_OPERATION_ADDR);
1040 hdmi_phy_wait_i2c_done(hdmi, 1000);
1041 val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1042 val = (val & 0xff) << 8;
1043 val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1047 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1049 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1050 HDMI_PHY_CONF0_PDZ_OFFSET,
1051 HDMI_PHY_CONF0_PDZ_MASK);
1054 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1056 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1057 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1058 HDMI_PHY_CONF0_ENTMDS_MASK);
1061 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1063 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1064 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1065 HDMI_PHY_CONF0_SPARECTRL_MASK);
1068 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1070 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1071 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1072 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1075 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1077 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1078 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1079 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1082 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1084 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1085 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1086 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1089 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1091 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1092 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1093 HDMI_PHY_CONF0_SELDIPIF_MASK);
1096 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1097 unsigned char res, int cscon)
1100 u8 val, msec, tmds_cfg;
1101 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1102 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1103 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1104 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1110 case 0: /* color resolution 0 is 8 bit colour depth */
1112 res_idx = DW_HDMI_RES_8;
1115 res_idx = DW_HDMI_RES_10;
1118 res_idx = DW_HDMI_RES_12;
1124 /* PLL/MPLL Cfg - always match on final entry */
1125 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1126 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1127 mpll_config->mpixelclock)
1130 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1131 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1132 curr_ctrl->mpixelclock)
1135 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1136 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1137 phy_config->mpixelclock)
1140 if (mpll_config->mpixelclock == ~0UL ||
1141 curr_ctrl->mpixelclock == ~0UL ||
1142 phy_config->mpixelclock == ~0UL) {
1143 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1144 hdmi->hdmi_data.video_mode.mpixelclock);
1148 /* Enable csc path */
1150 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1152 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1154 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1156 /* gen2 tx power off */
1157 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1160 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1162 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1163 if (hdmi->connector.scdc_present) {
1164 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1165 if (mpll_config->mpixelclock > 340000000)
1169 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1173 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1174 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1176 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1178 hdmi_phy_test_clear(hdmi, 1);
1179 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1180 HDMI_PHY_I2CM_SLAVE_ADDR);
1181 hdmi_phy_test_clear(hdmi, 0);
1183 * RK3399 mpll clock source is vpll, also is vop clock source.
1184 * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1185 * to enable mpll pre-divider.
1187 if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
1188 hdmi->dev_type == RK3399_HDMI)
1189 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
1192 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1193 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1196 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1198 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
1199 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1201 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
1202 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1203 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1205 /* REMOVE CLK TERM */
1206 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
1208 dw_hdmi_phy_enable_powerdown(hdmi, false);
1210 /* toggle TMDS disable */
1211 dw_hdmi_phy_enable_tmds(hdmi, 0);
1213 /* Wait for resuming transmission of TMDS clock and data */
1214 if (mpll_config->mpixelclock > 340000000)
1217 /* toggle TMDS enable */
1218 dw_hdmi_phy_enable_tmds(hdmi, 1);
1220 /* gen2 tx power on */
1221 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1222 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1224 if (is_rockchip(hdmi->dev_type))
1225 dw_hdmi_phy_enable_spare(hdmi, 1);
1227 /* Wait for PHY PLL lock */
1230 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1235 dev_err(hdmi->dev, "PHY PLL not locked\n");
1246 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1251 /*check csc whether needed activated in HDMI mode */
1252 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1254 /* HDMI Phy spec says to do the phy initialization sequence twice */
1255 for (i = 0; i < 2; i++) {
1256 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1257 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1258 dw_hdmi_phy_enable_tmds(hdmi, 0);
1259 dw_hdmi_phy_enable_powerdown(hdmi, true);
1262 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1267 hdmi->phy_enabled = true;
1271 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1275 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1276 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1278 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1280 /* disable rx detect */
1281 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1282 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1284 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1286 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1287 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1290 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1292 struct hdmi_avi_infoframe frame;
1294 bool is_hdmi2 = false;
1296 if ((mode->flags & DRM_MODE_FLAG_420_MASK) ||
1297 hdmi->connector.scdc_present)
1299 /* Initialise info frame from DRM mode */
1300 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
1302 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1303 frame.colorspace = HDMI_COLORSPACE_YUV444;
1304 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1305 frame.colorspace = HDMI_COLORSPACE_YUV422;
1306 else if (hdmi->hdmi_data.enc_out_format == YCBCR420)
1307 frame.colorspace = HDMI_COLORSPACE_YUV420;
1309 frame.colorspace = HDMI_COLORSPACE_RGB;
1311 /* Set up colorimetry */
1312 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1313 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1314 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1315 frame.extended_colorimetry =
1316 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1317 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1318 frame.extended_colorimetry =
1319 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1320 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1321 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1322 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1323 } else { /* Carries no data */
1324 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1325 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1328 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1331 * The Designware IP uses a different byte format from standard
1332 * AVI info frames, though generally the bits are in the correct
1337 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1338 * 5,6,7, active aspect present in bit 6 rather than 4.
1340 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1341 if (frame.active_aspect & 15)
1342 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1343 if (frame.top_bar || frame.bottom_bar)
1344 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1345 if (frame.left_bar || frame.right_bar)
1346 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1347 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1349 /* AVI data byte 2 differences: none */
1350 val = ((frame.colorimetry & 0x3) << 6) |
1351 ((frame.picture_aspect & 0x3) << 4) |
1352 (frame.active_aspect & 0xf);
1353 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1355 /* AVI data byte 3 differences: none */
1356 val = ((frame.extended_colorimetry & 0x7) << 4) |
1357 ((frame.quantization_range & 0x3) << 2) |
1360 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1361 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1363 /* AVI data byte 4 differences: none */
1364 val = frame.video_code & 0x7f;
1365 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1367 /* AVI Data Byte 5- set up input and output pixel repetition */
1368 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1369 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1370 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1371 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1372 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1373 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1374 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1377 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1378 * ycc range in bits 2,3 rather than 6,7
1380 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1381 (frame.content_type & 0x3);
1382 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1384 /* AVI Data Bytes 6-13 */
1385 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1386 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1387 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1388 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1389 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1390 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1391 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1392 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1395 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1396 struct drm_display_mode *mode)
1398 struct hdmi_vendor_infoframe frame;
1402 /* Disable HDMI vendor specific infoframe send */
1403 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1404 HDMI_FC_DATAUTO0_VSD_MASK);
1406 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1409 * Going into that statement does not means vendor infoframe
1410 * fails. It just informed us that vendor infoframe is not
1411 * needed for the selected mode. Only 4k or stereoscopic 3D
1412 * mode requires vendor infoframe. So just simply return.
1416 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1418 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1423 /* Set the length of HDMI vendor specific InfoFrame payload */
1424 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1426 /* Set 24bit IEEE Registration Identifier */
1427 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1428 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1429 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1431 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1432 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1433 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1435 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1436 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1438 /* Packet frame interpolation */
1439 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1441 /* Auto packets per frame and line spacing */
1442 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1444 /* Configures the Frame Composer On RDRB mode */
1445 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1446 HDMI_FC_DATAUTO0_VSD_MASK);
1449 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1450 const struct drm_display_mode *mode)
1453 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1454 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1455 unsigned int hdisplay, vdisplay;
1457 vmode->mpixelclock = mode->crtc_clock * 1000;
1458 if (mode->flags & DRM_MODE_FLAG_420_MASK)
1459 vmode->mpixelclock /= 2;
1460 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1462 /* Set up HDMI_FC_INVIDCONF
1463 * fc_invidconf.HDCP_keepout must be set (1'b1)
1464 * when activate the scrambler feature.
1466 inv_val = (hdmi->hdmi_data.hdcp_enable ||
1467 vmode->mpixelclock > 340000000 ||
1468 hdmi->connector.lte_340mcsc_scramble ?
1469 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1470 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1472 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1473 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1474 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1476 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1477 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1478 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1480 inv_val |= (vmode->mdataenablepolarity ?
1481 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1482 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1484 if (hdmi->vic == 39)
1485 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1487 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1488 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1489 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1491 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1492 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1493 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1495 inv_val |= hdmi->sink_is_hdmi ?
1496 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1497 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1499 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1501 hdisplay = mode->hdisplay;
1502 hblank = mode->htotal - mode->hdisplay;
1503 h_de_hs = mode->hsync_start - mode->hdisplay;
1504 hsync_len = mode->hsync_end - mode->hsync_start;
1507 * When we're setting a YCbCr420 mode, we need
1508 * to adjust the horizontal timing to suit.
1510 if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1517 vdisplay = mode->vdisplay;
1518 vblank = mode->vtotal - mode->vdisplay;
1519 v_de_vs = mode->vsync_start - mode->vdisplay;
1520 vsync_len = mode->vsync_end - mode->vsync_start;
1523 * When we're setting an interlaced mode, we need
1524 * to adjust the vertical timing to suit.
1526 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1533 /* Scrambling Control */
1534 if (hdmi->connector.scdc_present) {
1535 if (vmode->mpixelclock > 340000000 ||
1536 hdmi->connector.lte_340mcsc_scramble) {
1537 drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1539 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1541 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1542 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1544 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1546 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1547 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1549 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1553 /* Set up horizontal active pixel width */
1554 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1555 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1557 /* Set up vertical active lines */
1558 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1559 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1561 /* Set up horizontal blanking pixel region width */
1562 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1563 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1565 /* Set up vertical blanking pixel region width */
1566 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1568 /* Set up HSYNC active edge delay width (in pixel clks) */
1569 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1570 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1572 /* Set up VSYNC active edge delay (in lines) */
1573 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1575 /* Set up HSYNC active pulse width (in pixel clks) */
1576 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1577 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1579 /* Set up VSYNC active edge delay (in lines) */
1580 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1583 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1585 if (!hdmi->phy_enabled)
1588 dw_hdmi_phy_enable_tmds(hdmi, 0);
1589 dw_hdmi_phy_enable_powerdown(hdmi, true);
1591 hdmi->phy_enabled = false;
1594 /* HDMI Initialization Step B.4 */
1595 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1599 /* control period minimum duration */
1600 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1601 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1602 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1604 /* Set to fill TMDS data channels */
1605 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1606 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1607 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1609 /* Enable pixel clock and tmds data path */
1611 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1612 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1614 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1615 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1617 /* Enable csc path */
1618 if (is_color_space_conversion(hdmi)) {
1619 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1620 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1623 /* Enable pixel repetition path */
1624 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1625 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1626 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1630 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1632 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1635 /* Workaround to clear the overflow condition */
1636 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1641 /* TMDS software reset */
1642 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1644 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1645 if (hdmi->dev_type == IMX6DL_HDMI) {
1646 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1650 for (count = 0; count < 4; count++)
1651 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1654 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1656 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1657 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1660 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1662 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1663 HDMI_IH_MUTE_FC_STAT2);
1666 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1670 hdmi_disable_overflow_interrupts(hdmi);
1672 hdmi->vic = drm_match_cea_mode(mode);
1675 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1677 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1680 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1681 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1682 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1683 (hdmi->vic == 17) || (hdmi->vic == 18))
1684 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1686 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1688 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1689 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1690 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1692 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1693 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1695 /* TODO: Get input format from IPU (via FB driver interface) */
1696 if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1697 hdmi->hdmi_data.enc_in_format = YCBCR420;
1698 hdmi->hdmi_data.enc_out_format = YCBCR420;
1700 hdmi->hdmi_data.enc_in_format = RGB;
1701 hdmi->hdmi_data.enc_out_format = RGB;
1703 hdmi->hdmi_data.enc_color_depth = 8;
1705 * According to the dw-hdmi specification 6.4.2
1707 * 0000b: No pixel repetition (pixel sent only once)
1708 * 0001b: Pixel sent two times (pixel repeated once)
1710 hdmi->hdmi_data.pix_repet_factor =
1711 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1712 hdmi->hdmi_data.hdcp_enable = 0;
1713 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1715 /* HDMI Initialization Step B.1 */
1716 hdmi_av_composer(hdmi, mode);
1718 /* HDMI Initializateion Step B.2 */
1719 ret = dw_hdmi_phy_init(hdmi);
1723 /* HDMI Initialization Step B.3 */
1724 dw_hdmi_enable_video_path(hdmi);
1726 if (hdmi->sink_has_audio) {
1727 dev_dbg(hdmi->dev, "sink has audio support\n");
1729 /* HDMI Initialization Step E - Configure audio */
1730 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1731 hdmi_enable_audio_clk(hdmi);
1734 /* not for DVI mode */
1735 if (hdmi->sink_is_hdmi) {
1736 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1738 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1739 hdmi_config_AVI(hdmi, mode);
1740 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1742 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1745 hdmi_video_packetize(hdmi);
1746 hdmi_video_csc(hdmi);
1747 hdmi_video_sample(hdmi);
1748 hdmi_tx_hdcp_config(hdmi);
1750 dw_hdmi_clear_overflow(hdmi);
1751 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1752 hdmi_enable_overflow_interrupts(hdmi);
1757 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1762 * Boot up defaults are:
1763 * HDMI_IH_MUTE = 0x03 (disabled)
1764 * HDMI_IH_MUTE_* = 0x00 (enabled)
1766 * Disable top level interrupt bits in HDMI block
1768 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1769 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1770 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1772 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1774 /* by default mask all interrupts */
1775 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1776 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1777 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1778 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1779 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1780 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1781 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1782 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1783 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1784 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1785 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1786 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1787 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1788 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1789 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1791 /* Disable interrupts in the IH_MUTE_* registers */
1792 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1793 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1794 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1795 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1796 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1797 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1798 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1799 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1800 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1801 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1803 /* Enable top level interrupt bits in HDMI block */
1804 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1805 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1806 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1809 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1811 hdmi->bridge_is_on = true;
1812 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1815 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1817 dw_hdmi_phy_disable(hdmi);
1818 hdmi->bridge_is_on = false;
1821 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1823 int force = hdmi->force;
1825 if (hdmi->disabled) {
1826 force = DRM_FORCE_OFF;
1827 } else if (force == DRM_FORCE_UNSPECIFIED) {
1829 force = DRM_FORCE_ON;
1831 force = DRM_FORCE_OFF;
1834 if (force == DRM_FORCE_OFF) {
1835 if (hdmi->bridge_is_on)
1836 dw_hdmi_poweroff(hdmi);
1838 if (!hdmi->bridge_is_on)
1839 dw_hdmi_poweron(hdmi);
1844 * Adjust the detection of RXSENSE according to whether we have a forced
1845 * connection mode enabled, or whether we have been disabled. There is
1846 * no point processing RXSENSE interrupts if we have a forced connection
1847 * state, or DRM has us disabled.
1849 * We also disable rxsense interrupts when we think we're disconnected
1850 * to avoid floating TDMS signals giving false rxsense interrupts.
1852 * Note: we still need to listen for HPD interrupts even when DRM has us
1853 * disabled so that we can detect a connect event.
1855 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1857 u8 old_mask = hdmi->phy_mask;
1859 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1860 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1862 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1864 if (old_mask != hdmi->phy_mask)
1865 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1868 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1869 struct drm_display_mode *orig_mode,
1870 struct drm_display_mode *mode)
1872 struct dw_hdmi *hdmi = bridge->driver_private;
1874 mutex_lock(&hdmi->mutex);
1876 /* Store the display mode for plugin/DKMS poweron events */
1877 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1879 mutex_unlock(&hdmi->mutex);
1882 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1884 struct dw_hdmi *hdmi = bridge->driver_private;
1886 mutex_lock(&hdmi->mutex);
1887 hdmi->disabled = true;
1888 dw_hdmi_update_power(hdmi);
1889 dw_hdmi_update_phy_mask(hdmi);
1890 mutex_unlock(&hdmi->mutex);
1893 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1895 struct dw_hdmi *hdmi = bridge->driver_private;
1897 mutex_lock(&hdmi->mutex);
1898 hdmi->disabled = false;
1899 dw_hdmi_update_power(hdmi);
1900 dw_hdmi_update_phy_mask(hdmi);
1901 mutex_unlock(&hdmi->mutex);
1904 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1909 static enum drm_connector_status
1910 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1912 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1915 mutex_lock(&hdmi->mutex);
1916 hdmi->force = DRM_FORCE_UNSPECIFIED;
1917 dw_hdmi_update_power(hdmi);
1918 dw_hdmi_update_phy_mask(hdmi);
1919 mutex_unlock(&hdmi->mutex);
1921 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1922 connector_status_connected : connector_status_disconnected;
1925 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1927 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1935 edid = drm_get_edid(connector, hdmi->ddc);
1937 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1938 edid->width_cm, edid->height_cm);
1940 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1941 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1942 drm_mode_connector_update_edid_property(connector, edid);
1943 ret = drm_add_edid_modes(connector, edid);
1945 drm_edid_to_eld(connector, edid);
1948 dev_dbg(hdmi->dev, "failed to get edid\n");
1954 static enum drm_mode_status
1955 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1956 struct drm_display_mode *mode)
1958 struct dw_hdmi *hdmi = container_of(connector,
1959 struct dw_hdmi, connector);
1960 enum drm_mode_status mode_status = MODE_OK;
1962 if (hdmi->plat_data->mode_valid)
1963 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1968 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1971 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1974 return hdmi->encoder;
1977 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1979 drm_connector_unregister(connector);
1980 drm_connector_cleanup(connector);
1983 static void dw_hdmi_connector_force(struct drm_connector *connector)
1985 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1988 mutex_lock(&hdmi->mutex);
1989 hdmi->force = connector->force;
1990 dw_hdmi_update_power(hdmi);
1991 dw_hdmi_update_phy_mask(hdmi);
1992 mutex_unlock(&hdmi->mutex);
1995 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1996 .dpms = drm_helper_connector_dpms,
1997 .fill_modes = drm_helper_probe_single_connector_modes,
1998 .detect = dw_hdmi_connector_detect,
1999 .destroy = dw_hdmi_connector_destroy,
2000 .force = dw_hdmi_connector_force,
2003 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
2004 .dpms = drm_atomic_helper_connector_dpms,
2005 .fill_modes = drm_helper_probe_single_connector_modes,
2006 .detect = dw_hdmi_connector_detect,
2007 .destroy = dw_hdmi_connector_destroy,
2008 .force = dw_hdmi_connector_force,
2009 .reset = drm_atomic_helper_connector_reset,
2010 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2011 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2014 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2015 .get_modes = dw_hdmi_connector_get_modes,
2016 .mode_valid = dw_hdmi_connector_mode_valid,
2017 .best_encoder = dw_hdmi_connector_best_encoder,
2020 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2021 .enable = dw_hdmi_bridge_enable,
2022 .disable = dw_hdmi_bridge_disable,
2023 .pre_enable = dw_hdmi_bridge_nop,
2024 .post_disable = dw_hdmi_bridge_nop,
2025 .mode_set = dw_hdmi_bridge_mode_set,
2028 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2030 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2033 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2037 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2041 complete(&i2c->cmp);
2046 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2048 struct dw_hdmi *hdmi = dev_id;
2050 irqreturn_t ret = IRQ_NONE;
2053 ret = dw_hdmi_i2c_irq(hdmi);
2055 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2057 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2058 return IRQ_WAKE_THREAD;
2064 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2066 struct dw_hdmi *hdmi = dev_id;
2067 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2069 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2070 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2071 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2074 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2075 phy_pol_mask |= HDMI_PHY_HPD;
2076 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2077 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2078 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2079 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2080 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2081 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2082 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2083 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2086 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2089 * RX sense tells us whether the TDMS transmitters are detecting
2090 * load - in other words, there's something listening on the
2091 * other end of the link. Use this to decide whether we should
2092 * power on the phy as HPD may be toggled by the sink to merely
2093 * ask the source to re-read the EDID.
2096 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2097 mutex_lock(&hdmi->mutex);
2098 if (!hdmi->bridge_is_on && !hdmi->force) {
2100 * If the RX sense status indicates we're disconnected,
2101 * clear the software rxsense status.
2103 if (!(phy_stat & HDMI_PHY_RX_SENSE))
2104 hdmi->rxsense = false;
2107 * Only set the software rxsense status when both
2108 * rxsense and hpd indicates we're connected.
2109 * This avoids what seems to be bad behaviour in
2110 * at least iMX6S versions of the phy.
2112 if (phy_stat & HDMI_PHY_HPD)
2113 hdmi->rxsense = true;
2115 dw_hdmi_update_power(hdmi);
2116 dw_hdmi_update_phy_mask(hdmi);
2118 mutex_unlock(&hdmi->mutex);
2121 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2122 dev_dbg(hdmi->dev, "EVENT=%s\n",
2123 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2124 drm_helper_hpd_irq_event(hdmi->bridge->dev);
2125 #ifdef CONFIG_SWITCH
2126 if (phy_int_pol & HDMI_PHY_HPD)
2127 switch_set_state(&hdmi->switchdev, 1);
2129 switch_set_state(&hdmi->switchdev, 0);
2133 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2134 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2135 HDMI_IH_MUTE_PHY_STAT0);
2140 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2142 struct drm_encoder *encoder = hdmi->encoder;
2143 struct drm_bridge *bridge;
2146 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2148 DRM_ERROR("Failed to allocate drm bridge\n");
2152 hdmi->bridge = bridge;
2153 bridge->driver_private = hdmi;
2154 bridge->funcs = &dw_hdmi_bridge_funcs;
2155 ret = drm_bridge_attach(drm, bridge);
2157 DRM_ERROR("Failed to initialize bridge with drm\n");
2161 encoder->bridge = bridge;
2162 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2163 hdmi->connector.port = hdmi->dev->of_node;
2165 drm_connector_helper_add(&hdmi->connector,
2166 &dw_hdmi_connector_helper_funcs);
2168 if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2169 drm_connector_init(drm, &hdmi->connector,
2170 &dw_hdmi_atomic_connector_funcs,
2171 DRM_MODE_CONNECTOR_HDMIA);
2173 drm_connector_init(drm, &hdmi->connector,
2174 &dw_hdmi_connector_funcs,
2175 DRM_MODE_CONNECTOR_HDMIA);
2177 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2182 #include <linux/fs.h>
2183 #include <linux/debugfs.h>
2184 #include <linux/seq_file.h>
2186 struct dw_hdmi_reg_table {
2191 static const struct dw_hdmi_reg_table hdmi_reg_table[] = {
2192 {HDMI_DESIGN_ID, HDMI_CONFIG3_ID},
2193 {HDMI_IH_FC_STAT0, HDMI_IH_MUTE},
2194 {HDMI_TX_INVID0, HDMI_TX_BCBDATA1},
2195 {HDMI_VP_STATUS, HDMI_VP_POL},
2196 {HDMI_FC_INVIDCONF, HDMI_FC_DBGTMDS2},
2197 {HDMI_PHY_CONF0, HDMI_PHY_POL0},
2198 {HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR},
2199 {HDMI_AUD_CONF0, 0x3624},
2200 {HDMI_MC_SFRDIV, HDMI_MC_HEACPHY_RST},
2201 {HDMI_CSC_CFG, HDMI_CSC_COEF_C4_LSB},
2202 {HDMI_A_HDCPCFG0, 0x52bb},
2205 {HDMI_CEC_CTRL, HDMI_CEC_WKUPCTRL},
2206 {HDMI_I2CM_SLAVE, 0x7e31},
2209 static int dw_hdmi_ctrl_show(struct seq_file *s, void *v)
2211 struct dw_hdmi *hdmi = s->private;
2212 u32 i = 0, j = 0, val = 0;
2214 seq_puts(s, "\n>>>hdmi_ctl reg ");
2215 for (i = 0; i < 16; i++)
2216 seq_printf(s, " %2x", i);
2217 seq_puts(s, "\n---------------------------------------------------");
2219 for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) {
2220 for (j = hdmi_reg_table[i].reg_base;
2221 j <= hdmi_reg_table[i].reg_end; j++) {
2222 val = hdmi_readb(hdmi, j);
2223 if ((j - hdmi_reg_table[i].reg_base) % 16 == 0)
2224 seq_printf(s, "\n>>>hdmi_ctl %04x:", j);
2225 seq_printf(s, " %02x", val);
2228 seq_puts(s, "\n---------------------------------------------------\n");
2233 static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file)
2235 return single_open(file, dw_hdmi_ctrl_show, inode->i_private);
2239 dw_hdmi_ctrl_write(struct file *file, const char __user *buf,
2240 size_t count, loff_t *ppos)
2242 struct dw_hdmi *hdmi =
2243 ((struct seq_file *)file->private_data)->private;
2247 if (copy_from_user(kbuf, buf, count))
2249 if (sscanf(kbuf, "%x%x", ®, &val) == -1)
2251 if ((reg < 0) || (reg > HDMI_I2CM_FS_SCL_LCNT_0_ADDR)) {
2252 dev_err(hdmi->dev, "it is no a hdmi register\n");
2255 dev_info(hdmi->dev, "/**********hdmi register config******/");
2256 dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2257 hdmi_writeb(hdmi, val, reg);
2261 static const struct file_operations dw_hdmi_ctrl_fops = {
2262 .owner = THIS_MODULE,
2263 .open = dw_hdmi_ctrl_open,
2265 .write = dw_hdmi_ctrl_write,
2266 .llseek = seq_lseek,
2267 .release = single_release,
2270 static int dw_hdmi_phy_show(struct seq_file *s, void *v)
2272 struct dw_hdmi *hdmi = s->private;
2275 seq_puts(s, "\n>>>hdmi_phy reg ");
2276 for (i = 0; i < 0x28; i++)
2277 seq_printf(s, "regs %02x val %04x\n",
2278 i, hdmi_phy_i2c_read(hdmi, i));
2282 static int dw_hdmi_phy_open(struct inode *inode, struct file *file)
2284 return single_open(file, dw_hdmi_phy_show, inode->i_private);
2288 dw_hdmi_phy_write(struct file *file, const char __user *buf,
2289 size_t count, loff_t *ppos)
2291 struct dw_hdmi *hdmi =
2292 ((struct seq_file *)file->private_data)->private;
2296 if (copy_from_user(kbuf, buf, count))
2298 if (sscanf(kbuf, "%x%x", ®, &val) == -1)
2300 if ((reg < 0) || (reg > 0x28)) {
2301 dev_err(hdmi->dev, "it is not a hdmi phy register\n");
2304 dev_info(hdmi->dev, "/*******hdmi phy register config******/");
2305 dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2306 hdmi_phy_i2c_write(hdmi, val, reg);
2310 static const struct file_operations dw_hdmi_phy_fops = {
2311 .owner = THIS_MODULE,
2312 .open = dw_hdmi_phy_open,
2314 .write = dw_hdmi_phy_write,
2315 .llseek = seq_lseek,
2316 .release = single_release,
2319 static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi *hdmi)
2321 struct dentry *debugfs_dir;
2323 debugfs_dir = debugfs_create_dir("dw-hdmi", NULL);
2324 if (IS_ERR(debugfs_dir)) {
2325 dev_err(dev, "failed to create debugfs dir!\n");
2328 debugfs_create_file("ctrl", 0400, debugfs_dir,
2329 hdmi, &dw_hdmi_ctrl_fops);
2330 debugfs_create_file("phy", 0400, debugfs_dir,
2331 hdmi, &dw_hdmi_phy_fops);
2334 int dw_hdmi_bind(struct device *dev, struct device *master,
2335 void *data, struct drm_encoder *encoder,
2336 struct resource *iores, int irq,
2337 const struct dw_hdmi_plat_data *plat_data)
2339 struct drm_device *drm = data;
2340 struct device_node *np = dev->of_node;
2341 struct platform_device_info pdevinfo;
2342 struct device_node *ddc_node;
2343 struct dw_hdmi *hdmi;
2349 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2353 hdmi->connector.interlace_allowed = 1;
2354 hdmi->connector.stereo_allowed = 1;
2356 hdmi->plat_data = plat_data;
2358 hdmi->dev_type = plat_data->dev_type;
2359 hdmi->sample_rate = 48000;
2360 hdmi->encoder = encoder;
2361 hdmi->disabled = true;
2362 hdmi->rxsense = true;
2363 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2366 mutex_init(&hdmi->mutex);
2367 mutex_init(&hdmi->audio_mutex);
2368 spin_lock_init(&hdmi->audio_lock);
2370 of_property_read_u32(np, "reg-io-width", &val);
2374 hdmi->write = dw_hdmi_writel;
2375 hdmi->read = dw_hdmi_readl;
2378 hdmi->write = dw_hdmi_writeb;
2379 hdmi->read = dw_hdmi_readb;
2382 dev_err(dev, "reg-io-width must be 1 or 4\n");
2386 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2388 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2389 of_node_put(ddc_node);
2391 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2392 return -EPROBE_DEFER;
2396 dev_dbg(hdmi->dev, "no ddc property found\n");
2399 /* If DDC bus is not specified, try to register HDMI I2C bus */
2401 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2402 if (IS_ERR(hdmi->ddc))
2406 hdmi->regs = devm_ioremap_resource(dev, iores);
2407 if (IS_ERR(hdmi->regs))
2408 return PTR_ERR(hdmi->regs);
2410 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2411 if (IS_ERR(hdmi->isfr_clk)) {
2412 ret = PTR_ERR(hdmi->isfr_clk);
2413 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2417 ret = clk_prepare_enable(hdmi->isfr_clk);
2419 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2423 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2424 if (IS_ERR(hdmi->iahb_clk)) {
2425 ret = PTR_ERR(hdmi->iahb_clk);
2426 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2430 ret = clk_prepare_enable(hdmi->iahb_clk);
2432 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2436 /* Product and revision IDs */
2438 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2439 hdmi_readb(hdmi, HDMI_DESIGN_ID),
2440 hdmi_readb(hdmi, HDMI_REVISION_ID),
2441 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2442 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2444 initialize_hdmi_ih_mutes(hdmi);
2446 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2447 dw_hdmi_irq, IRQF_SHARED,
2448 dev_name(dev), hdmi);
2453 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2454 * N and cts values before enabling phy
2456 hdmi_init_clk_regenerator(hdmi);
2458 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2459 HDMI_PHY_I2CM_INT_ADDR);
2461 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2462 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2463 HDMI_PHY_I2CM_CTLINT_ADDR);
2465 /* Re-init HPD polarity */
2466 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2468 /* Unmask HPD, clear transitory interrupts, then unmute */
2469 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2471 ret = dw_hdmi_register(drm, hdmi);
2475 #ifdef CONFIG_SWITCH
2476 hdmi->switchdev.name = "hdmi";
2477 switch_dev_register(&hdmi->switchdev);
2480 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2481 HDMI_IH_MUTE_PHY_STAT0);
2483 /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2485 dw_hdmi_i2c_init(hdmi);
2487 memset(&pdevinfo, 0, sizeof(pdevinfo));
2488 pdevinfo.parent = dev;
2489 pdevinfo.id = PLATFORM_DEVID_AUTO;
2491 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2492 config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2494 if (config1 & HDMI_CONFIG1_AHB) {
2495 struct dw_hdmi_audio_data audio;
2497 audio.phys = iores->start;
2498 audio.base = hdmi->regs;
2501 audio.eld = hdmi->connector.eld;
2503 pdevinfo.name = "dw-hdmi-ahb-audio";
2504 pdevinfo.data = &audio;
2505 pdevinfo.size_data = sizeof(audio);
2506 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2507 hdmi->audio = platform_device_register_full(&pdevinfo);
2508 } else if (config0 & HDMI_CONFIG0_I2S) {
2509 struct dw_hdmi_i2s_audio_data audio;
2512 audio.write = hdmi_writeb;
2513 audio.read = hdmi_readb;
2515 pdevinfo.name = "dw-hdmi-i2s-audio";
2516 pdevinfo.data = &audio;
2517 pdevinfo.size_data = sizeof(audio);
2518 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2519 hdmi->audio = platform_device_register_full(&pdevinfo);
2522 dev_set_drvdata(dev, hdmi);
2524 dw_hdmi_register_debugfs(dev, hdmi);
2530 i2c_del_adapter(&hdmi->i2c->adap);
2532 clk_disable_unprepare(hdmi->iahb_clk);
2534 clk_disable_unprepare(hdmi->isfr_clk);
2538 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2540 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2542 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2544 if (hdmi->audio && !IS_ERR(hdmi->audio))
2545 platform_device_unregister(hdmi->audio);
2547 /* Disable all interrupts */
2548 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2550 #ifdef CONFIG_SWITCH
2551 switch_dev_unregister(&hdmi->switchdev);
2553 hdmi->connector.funcs->destroy(&hdmi->connector);
2554 hdmi->encoder->funcs->destroy(hdmi->encoder);
2556 clk_disable_unprepare(hdmi->iahb_clk);
2557 clk_disable_unprepare(hdmi->isfr_clk);
2560 i2c_del_adapter(&hdmi->i2c->adap);
2562 i2c_put_adapter(hdmi->ddc);
2564 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2566 static void dw_hdmi_reg_initial(struct dw_hdmi *hdmi)
2568 if (hdmi_readb(hdmi, HDMI_IH_MUTE)) {
2569 initialize_hdmi_ih_mutes(hdmi);
2570 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2571 HDMI_PHY_I2CM_INT_ADDR);
2573 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2574 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2575 HDMI_PHY_I2CM_CTLINT_ADDR);
2577 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE,
2579 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2580 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD |
2581 HDMI_IH_PHY_STAT0_RX_SENSE),
2582 HDMI_IH_MUTE_PHY_STAT0);
2586 void dw_hdmi_suspend(struct device *dev)
2588 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2590 mutex_lock(&hdmi->mutex);
2592 disable_irq(hdmi->irq);
2593 mutex_unlock(&hdmi->mutex);
2595 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
2597 void dw_hdmi_resume(struct device *dev)
2599 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2601 mutex_lock(&hdmi->mutex);
2602 dw_hdmi_reg_initial(hdmi);
2604 enable_irq(hdmi->irq);
2605 mutex_unlock(&hdmi->mutex);
2607 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2609 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2610 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2611 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2612 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2613 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2614 MODULE_LICENSE("GPL");
2615 MODULE_ALIAS("platform:dw-hdmi");