drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/drm_scdc_helper.h>
  33 #include <drm/bridge/dw_hdmi.h>
  34 #ifdef CONFIG_SWITCH
  35 #include <linux/switch.h>
  36 #endif
  37
  38 #include "dw-hdmi.h"
  39 #include "dw-hdmi-audio.h"
  40
  41 #define HDMI_EDID_LEN           512
  42
  43 #define RGB                     0
  44 #define YCBCR444                1
  45 #define YCBCR422_16BITS         2
  46 #define YCBCR422_8BITS          3
  47 #define XVYCC444                4
  48
  49 enum hdmi_datamap {
  50         RGB444_8B = 0x01,
  51         RGB444_10B = 0x03,
  52         RGB444_12B = 0x05,
  53         RGB444_16B = 0x07,
  54         YCbCr444_8B = 0x09,
  55         YCbCr444_10B = 0x0B,
  56         YCbCr444_12B = 0x0D,
  57         YCbCr444_16B = 0x0F,
  58         YCbCr422_8B = 0x16,
  59         YCbCr422_10B = 0x14,
  60         YCbCr422_12B = 0x12,
  61 };
  62
  63 /*
  64  * Unless otherwise noted, entries in this table are 100% optimization.
  65  * Values can be obtained from hdmi_compute_n() but that function is
  66  * slow so we pre-compute values we expect to see.
  67  *
  68  * All 32k and 48k values are expected to be the same (due to the way
  69  * the math works) for any rate that's an exact kHz.
  70  */
  71 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  72         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  73         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  74         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  75         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  76         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  77         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  78         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  79         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  80         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  81         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  82         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  83         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  84         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  85         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  86         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  87         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  88         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  89         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  90         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  91         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  92         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  93         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  94         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  95         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  96         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  97         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  98         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  99         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
 100         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
 101         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 102         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
 103         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 104         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 105         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 106         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 107         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 108         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 109
 110         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 111         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 112         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 113
 114         /* End of table */
 115         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 116 };
 117
 118
 119 static const u16 csc_coeff_default[3][4] = {
 120         { 0x2000, 0x0000, 0x0000, 0x0000 },
 121         { 0x0000, 0x2000, 0x0000, 0x0000 },
 122         { 0x0000, 0x0000, 0x2000, 0x0000 }
 123 };
 124
 125 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 126         { 0x2000, 0x6926, 0x74fd, 0x010e },
 127         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 128         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 129 };
 130
 131 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 132         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 133         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 134         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 135 };
 136
 137 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 138         { 0x2591, 0x1322, 0x074b, 0x0000 },
 139         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 140         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 141 };
 142
 143 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 144         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 145         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 146         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 147 };
 148
 149 struct hdmi_vmode {
 150         bool mdataenablepolarity;
 151
 152         unsigned int mpixelclock;
 153         unsigned int mpixelrepetitioninput;
 154         unsigned int mpixelrepetitionoutput;
 155 };
 156
 157 struct hdmi_data_info {
 158         unsigned int enc_in_format;
 159         unsigned int enc_out_format;
 160         unsigned int enc_color_depth;
 161         unsigned int colorimetry;
 162         unsigned int pix_repet_factor;
 163         unsigned int hdcp_enable;
 164         struct hdmi_vmode video_mode;
 165 };
 166
 167 struct dw_hdmi_i2c {
 168         struct i2c_adapter      adap;
 169
 170         struct mutex            lock;
 171         struct completion       cmp;
 172         u8                      stat;
 173
 174         u8                      slave_reg;
 175         bool                    is_regaddr;
 176 };
 177
 178 struct dw_hdmi {
 179         struct drm_connector connector;
 180         struct drm_encoder *encoder;
 181         struct drm_bridge *bridge;
 182
 183         struct platform_device *audio;
 184         enum dw_hdmi_devtype dev_type;
 185         struct device *dev;
 186         struct clk *isfr_clk;
 187         struct clk *iahb_clk;
 188         struct dw_hdmi_i2c *i2c;
 189
 190         struct hdmi_data_info hdmi_data;
 191         const struct dw_hdmi_plat_data *plat_data;
 192
 193         int vic;
 194
 195         u8 edid[HDMI_EDID_LEN];
 196         bool cable_plugin;
 197
 198         bool phy_enabled;
 199         struct drm_display_mode previous_mode;
 200
 201         struct i2c_adapter *ddc;
 202         void __iomem *regs;
 203         bool sink_is_hdmi;
 204         bool sink_has_audio;
 205
 206         struct mutex mutex;             /* for state below and previous_mode */
 207         enum drm_connector_force force; /* mutex-protected force state */
 208         bool disabled;                  /* DRM has disabled our bridge */
 209         bool bridge_is_on;              /* indicates the bridge is on */
 210         bool rxsense;                   /* rxsense state */
 211         u8 phy_mask;                    /* desired phy int mask settings */
 212
 213         spinlock_t audio_lock;
 214         struct mutex audio_mutex;
 215         unsigned int sample_rate;
 216         unsigned int audio_cts;
 217         unsigned int audio_n;
 218         bool audio_enable;
 219
 220 #ifdef CONFIG_SWITCH
 221         struct switch_dev switchdev;
 222 #endif
 223
 224         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 225         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 226 };
 227
 228 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 229         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 230          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 231
 232 #define HDMI_PHY_RX_SENSE \
 233         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 234          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 235
 236 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 237 {
 238         writel(val, hdmi->regs + (offset << 2));
 239 }
 240
 241 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 242 {
 243         return readl(hdmi->regs + (offset << 2));
 244 }
 245
 246 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 247 {
 248         writeb(val, hdmi->regs + offset);
 249 }
 250
 251 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 252 {
 253         return readb(hdmi->regs + offset);
 254 }
 255
 256 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 257 {
 258         hdmi->write(hdmi, val, offset);
 259 }
 260
 261 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 262 {
 263         return hdmi->read(hdmi, offset);
 264 }
 265
 266 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 267 {
 268         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 269
 270         val |= data & mask;
 271         hdmi_writeb(hdmi, val, reg);
 272 }
 273
 274 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 275                              u8 shift, u8 mask)
 276 {
 277         hdmi_modb(hdmi, data << shift, mask, reg);
 278 }
 279
 280 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 281 {
 282         /* Software reset */
 283         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 284
 285         /* Set Standard Mode speed */
 286         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
 287                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
 288
 289         /* Set done, not acknowledged and arbitration interrupt polarities */
 290         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 291         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 292                     HDMI_I2CM_CTLINT);
 293
 294         /* Clear DONE and ERROR interrupts */
 295         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 296                     HDMI_IH_I2CM_STAT0);
 297
 298         /* Mute DONE and ERROR interrupts */
 299         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 300                     HDMI_IH_MUTE_I2CM_STAT0);
 301 }
 302
 303 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 304                             unsigned char *buf, unsigned int length)
 305 {
 306         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 307         int stat;
 308
 309         if (!i2c->is_regaddr) {
 310                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 311                 i2c->slave_reg = 0x00;
 312                 i2c->is_regaddr = true;
 313         }
 314
 315         while (length--) {
 316                 reinit_completion(&i2c->cmp);
 317
 318                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 319                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 320                             HDMI_I2CM_OPERATION);
 321
 322                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 323                 if (!stat)
 324                         return -EAGAIN;
 325
 326                 /* Check for error condition on the bus */
 327                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 328                         return -EIO;
 329
 330                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 337                              unsigned char *buf, unsigned int length)
 338 {
 339         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 340         int stat;
 341
 342         if (!i2c->is_regaddr) {
 343                 /* Use the first write byte as register address */
 344                 i2c->slave_reg = buf[0];
 345                 length--;
 346                 buf++;
 347                 i2c->is_regaddr = true;
 348         }
 349
 350         while (length--) {
 351                 reinit_completion(&i2c->cmp);
 352
 353                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 354                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 355                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 356                             HDMI_I2CM_OPERATION);
 357
 358         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 359                 if (!stat)
 360                         return -EAGAIN;
 361
 362                 /* Check for error condition on the bus */
 363                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 364                         return -EIO;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 371                             struct i2c_msg *msgs, int num)
 372 {
 373         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 374         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 375         u8 addr = msgs[0].addr;
 376         int i, ret = 0;
 377
 378         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 379
 380         for (i = 0; i < num; i++) {
 381                 if (msgs[i].addr != addr) {
 382                         dev_warn(hdmi->dev,
 383                                  "unsupported transfer, changed slave address\n");
 384                         return -EOPNOTSUPP;
 385                 }
 386
 387                 if (msgs[i].len == 0) {
 388                         dev_dbg(hdmi->dev,
 389                                 "unsupported transfer %d/%d, no data\n",
 390                                 i + 1, num);
 391                         return -EOPNOTSUPP;
 392                 }
 393         }
 394
 395         mutex_lock(&i2c->lock);
 396
 397         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 398
 399         /* Set slave device address taken from the first I2C message */
 400         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 401
 402         /* Set slave device register address on transfer */
 403         i2c->is_regaddr = false;
 404
 405         for (i = 0; i < num; i++) {
 406                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 407                         i + 1, num, msgs[i].len, msgs[i].flags);
 408
 409                 if (msgs[i].flags & I2C_M_RD)
 410                         ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
 411                 else
 412                         ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
 413
 414                 if (ret < 0)
 415                         break;
 416         }
 417
 418         if (!ret)
 419                 ret = num;
 420
 421         /* Mute DONE and ERROR interrupts */
 422         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 423                     HDMI_IH_MUTE_I2CM_STAT0);
 424
 425         mutex_unlock(&i2c->lock);
 426
 427         return ret;
 428 }
 429
 430 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 431 {
 432         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 433 }
 434
 435 static const struct i2c_algorithm dw_hdmi_algorithm = {
 436         .master_xfer    = dw_hdmi_i2c_xfer,
 437         .functionality  = dw_hdmi_i2c_func,
 438 };
 439
 440 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 441 {
 442         struct i2c_adapter *adap;
 443         struct dw_hdmi_i2c *i2c;
 444         int ret;
 445
 446         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 447         if (!i2c)
 448                 return ERR_PTR(-ENOMEM);
 449
 450         mutex_init(&i2c->lock);
 451         init_completion(&i2c->cmp);
 452
 453         adap = &i2c->adap;
 454         adap->class = I2C_CLASS_DDC;
 455         adap->owner = THIS_MODULE;
 456         adap->dev.parent = hdmi->dev;
 457         adap->dev.of_node = hdmi->dev->of_node;
 458         adap->algo = &dw_hdmi_algorithm;
 459         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 460         i2c_set_adapdata(adap, hdmi);
 461
 462         ret = i2c_add_adapter(adap);
 463         if (ret) {
 464                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 465                 devm_kfree(hdmi->dev, i2c);
 466                 return ERR_PTR(ret);
 467         }
 468
 469         hdmi->i2c = i2c;
 470
 471         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 472
 473         return adap;
 474 }
 475
 476 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 477                            unsigned int n)
 478 {
 479         /* Must be set/cleared first */
 480         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 481
 482         /* nshift factor = 0 */
 483         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 484
 485         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 486                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 487         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 488         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 489
 490         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 491         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 492         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 493 }
 494
 495 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 496                                    unsigned long pixel_clk,
 497                                    unsigned long freq)
 498 {
 499         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 500         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 501         int i;
 502
 503         if (plat_data->tmds_n_table) {
 504                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 505                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 506                                 tmds_n = &plat_data->tmds_n_table[i];
 507                                 break;
 508                         }
 509                 }
 510         }
 511
 512         if (tmds_n == NULL) {
 513                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 514                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 515                                 tmds_n = &common_tmds_n_table[i];
 516                                 break;
 517                         }
 518                 }
 519         }
 520
 521         if (tmds_n == NULL)
 522                 return -ENOENT;
 523
 524         switch (freq) {
 525         case 32000:
 526                 return tmds_n->n_32k;
 527         case 44100:
 528         case 88200:
 529         case 176400:
 530                 return (freq / 44100) * tmds_n->n_44k1;
 531         case 48000:
 532         case 96000:
 533         case 192000:
 534                 return (freq / 48000) * tmds_n->n_48k;
 535         default:
 536                 return -ENOENT;
 537         }
 538 }
 539
 540 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 541                                 unsigned int pixel_clk)
 542 {
 543         u64 final, diff;
 544         u64 cts;
 545
 546         final = (u64)pixel_clk * n;
 547
 548         cts = final;
 549         do_div(cts, 128 * freq);
 550
 551         diff = final - (u64)cts * (128 * freq);
 552
 553         return diff;
 554 }
 555
 556 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 557                                    unsigned long pixel_clk,
 558                                    unsigned long freq)
 559 {
 560         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 561         unsigned int max_n = (128 * freq) / 300;
 562         unsigned int ideal_n = (128 * freq) / 1000;
 563         unsigned int best_n_distance = ideal_n;
 564         unsigned int best_n = 0;
 565         u64 best_diff = U64_MAX;
 566         int n;
 567
 568         /* If the ideal N could satisfy the audio math, then just take it */
 569         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 570                 return ideal_n;
 571
 572         for (n = min_n; n <= max_n; n++) {
 573                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 574
 575                 if (diff < best_diff || (diff == best_diff &&
 576                     abs(n - ideal_n) < best_n_distance)) {
 577                         best_n = n;
 578                         best_diff = diff;
 579                         best_n_distance = abs(best_n - ideal_n);
 580                 }
 581
 582                 /*
 583                  * The best N already satisfy the audio math, and also be
 584                  * the closest value to ideal N, so just cut the loop.
 585                  */
 586                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 587                         break;
 588         }
 589
 590         return best_n;
 591 }
 592
 593 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 594                                 unsigned long sample_rate)
 595 {
 596         int n;
 597
 598         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 599         if (n > 0)
 600                 return n;
 601
 602         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 603                  pixel_clk);
 604
 605         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 606 }
 607
 608 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 609         unsigned long pixel_clk, unsigned int sample_rate)
 610 {
 611         unsigned long ftdms = pixel_clk;
 612         unsigned int n, cts;
 613         u64 tmp;
 614
 615         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 616
 617         /*
 618          * Compute the CTS value from the N value.  Note that CTS and N
 619          * can be up to 20 bits in total, so we need 64-bit math.  Also
 620          * note that our TDMS clock is not fully accurate; it is accurate
 621          * to kHz.  This can introduce an unnecessary remainder in the
 622          * calculation below, so we don't try to warn about that.
 623          */
 624         tmp = (u64)ftdms * n;
 625         do_div(tmp, 128 * sample_rate);
 626         cts = tmp;
 627
 628         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 629                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 630                 n, cts);
 631
 632         spin_lock_irq(&hdmi->audio_lock);
 633         hdmi->audio_n = n;
 634         hdmi->audio_cts = cts;
 635         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 636         spin_unlock_irq(&hdmi->audio_lock);
 637 }
 638
 639 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 640 {
 641         mutex_lock(&hdmi->audio_mutex);
 642         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 643         mutex_unlock(&hdmi->audio_mutex);
 644 }
 645
 646 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 647 {
 648         mutex_lock(&hdmi->audio_mutex);
 649         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 650                                  hdmi->sample_rate);
 651         mutex_unlock(&hdmi->audio_mutex);
 652 }
 653
 654 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 655 {
 656         mutex_lock(&hdmi->audio_mutex);
 657         hdmi->sample_rate = rate;
 658         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 659                                  hdmi->sample_rate);
 660         mutex_unlock(&hdmi->audio_mutex);
 661 }
 662 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 663
 664 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 665 {
 666         unsigned long flags;
 667
 668         spin_lock_irqsave(&hdmi->audio_lock, flags);
 669         hdmi->audio_enable = true;
 670         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 671         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 672 }
 673 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 674
 675 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 676 {
 677         unsigned long flags;
 678
 679         spin_lock_irqsave(&hdmi->audio_lock, flags);
 680         hdmi->audio_enable = false;
 681         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 682         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 683 }
 684 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 685
 686 /*
 687  * this submodule is responsible for the video data synchronization.
 688  * for example, for RGB 4:4:4 input, the data map is defined as
 689  *                      pin{47~40} <==> R[7:0]
 690  *                      pin{31~24} <==> G[7:0]
 691  *                      pin{15~8}  <==> B[7:0]
 692  */
 693 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 694 {
 695         int color_format = 0;
 696         u8 val;
 697
 698         if (hdmi->hdmi_data.enc_in_format == RGB) {
 699                 if (hdmi->hdmi_data.enc_color_depth == 8)
 700                         color_format = 0x01;
 701                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 702                         color_format = 0x03;
 703                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 704                         color_format = 0x05;
 705                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 706                         color_format = 0x07;
 707                 else
 708                         return;
 709         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 710                 if (hdmi->hdmi_data.enc_color_depth == 8)
 711                         color_format = 0x09;
 712                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 713                         color_format = 0x0B;
 714                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 715                         color_format = 0x0D;
 716                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 717                         color_format = 0x0F;
 718                 else
 719                         return;
 720         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 721                 if (hdmi->hdmi_data.enc_color_depth == 8)
 722                         color_format = 0x16;
 723                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 724                         color_format = 0x14;
 725                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 726                         color_format = 0x12;
 727                 else
 728                         return;
 729         }
 730
 731         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 732                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 733                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 734         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 735
 736         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 737         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 738                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 739                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 740         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 741         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 742         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 743         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 744         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 745         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 746         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 747 }
 748
 749 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 750 {
 751         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 752 }
 753
 754 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 755 {
 756         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 757                 return 0;
 758         if (hdmi->hdmi_data.enc_in_format == RGB ||
 759             hdmi->hdmi_data.enc_in_format == YCBCR444)
 760                 return 1;
 761         return 0;
 762 }
 763
 764 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 765 {
 766         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 767                 return 0;
 768         if (hdmi->hdmi_data.enc_out_format == RGB ||
 769             hdmi->hdmi_data.enc_out_format == YCBCR444)
 770                 return 1;
 771         return 0;
 772 }
 773
 774 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 775 {
 776         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 777         unsigned i;
 778         u32 csc_scale = 1;
 779
 780         if (is_color_space_conversion(hdmi)) {
 781                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 782                         if (hdmi->hdmi_data.colorimetry ==
 783                                         HDMI_COLORIMETRY_ITU_601)
 784                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 785                         else
 786                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 787                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 788                         if (hdmi->hdmi_data.colorimetry ==
 789                                         HDMI_COLORIMETRY_ITU_601)
 790                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 791                         else
 792                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 793                         csc_scale = 0;
 794                 }
 795         }
 796
 797         /* The CSC registers are sequential, alternating MSB then LSB */
 798         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 799                 u16 coeff_a = (*csc_coeff)[0][i];
 800                 u16 coeff_b = (*csc_coeff)[1][i];
 801                 u16 coeff_c = (*csc_coeff)[2][i];
 802
 803                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 804                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 805                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 806                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 807                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 808                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 809         }
 810
 811         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 812                   HDMI_CSC_SCALE);
 813 }
 814
 815 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 816 {
 817         int color_depth = 0;
 818         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 819         int decimation = 0;
 820
 821         /* YCC422 interpolation to 444 mode */
 822         if (is_color_space_interpolation(hdmi))
 823                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 824         else if (is_color_space_decimation(hdmi))
 825                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 826
 827         if (hdmi->hdmi_data.enc_color_depth == 8)
 828                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 829         else if (hdmi->hdmi_data.enc_color_depth == 10)
 830                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 831         else if (hdmi->hdmi_data.enc_color_depth == 12)
 832                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 833         else if (hdmi->hdmi_data.enc_color_depth == 16)
 834                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 835         else
 836                 return;
 837
 838         /* Configure the CSC registers */
 839         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 840         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 841                   HDMI_CSC_SCALE);
 842
 843         dw_hdmi_update_csc_coeffs(hdmi);
 844 }
 845
 846 /*
 847  * HDMI video packetizer is used to packetize the data.
 848  * for example, if input is YCC422 mode or repeater is used,
 849  * data should be repacked this module can be bypassed.
 850  */
 851 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 852 {
 853         unsigned int color_depth = 0;
 854         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 855         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 856         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 857         u8 val, vp_conf;
 858
 859         if (hdmi_data->enc_out_format == RGB ||
 860             hdmi_data->enc_out_format == YCBCR444) {
 861                 if (!hdmi_data->enc_color_depth) {
 862                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 863                 } else if (hdmi_data->enc_color_depth == 8) {
 864                         color_depth = 4;
 865                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 866                 } else if (hdmi_data->enc_color_depth == 10) {
 867                         color_depth = 5;
 868                 } else if (hdmi_data->enc_color_depth == 12) {
 869                         color_depth = 6;
 870                 } else if (hdmi_data->enc_color_depth == 16) {
 871                         color_depth = 7;
 872                 } else {
 873                         return;
 874                 }
 875         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 876                 if (!hdmi_data->enc_color_depth ||
 877                     hdmi_data->enc_color_depth == 8)
 878                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 879                 else if (hdmi_data->enc_color_depth == 10)
 880                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 881                 else if (hdmi_data->enc_color_depth == 12)
 882                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 883                 else
 884                         return;
 885                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 886         } else {
 887                 return;
 888         }
 889
 890         /* set the packetizer registers */
 891         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 892                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 893                 ((hdmi_data->pix_repet_factor <<
 894                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 895                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 896         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 897
 898         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 899                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 900
 901         /* Data from pixel repeater block */
 902         if (hdmi_data->pix_repet_factor > 0) {
 903                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 904                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 905         } else { /* data from packetizer block */
 906                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 907                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 908         }
 909
 910         hdmi_modb(hdmi, vp_conf,
 911                   HDMI_VP_CONF_PR_EN_MASK |
 912                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 913
 914         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 915                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 916
 917         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 918
 919         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 920                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 921                           HDMI_VP_CONF_PP_EN_ENABLE |
 922                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 923         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 924                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 925                           HDMI_VP_CONF_PP_EN_DISABLE |
 926                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 927         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 928                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 929                           HDMI_VP_CONF_PP_EN_DISABLE |
 930                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 931         } else {
 932                 return;
 933         }
 934
 935         hdmi_modb(hdmi, vp_conf,
 936                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 937                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 938
 939         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 940                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 941                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 942                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 943
 944         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 945                   HDMI_VP_CONF);
 946 }
 947
 948 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 949                                        unsigned char bit)
 950 {
 951         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 952                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 953 }
 954
 955 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 956                                         unsigned char bit)
 957 {
 958         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 959                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 960 }
 961
 962 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 963                                        unsigned char bit)
 964 {
 965         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 966                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 967 }
 968
 969 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 970                                      unsigned char bit)
 971 {
 972         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 973 }
 974
 975 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 976                                       unsigned char bit)
 977 {
 978         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 979 }
 980
 981 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 982 {
 983         u32 val;
 984
 985         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 986                 if (msec-- == 0)
 987                         return false;
 988                 udelay(1000);
 989         }
 990         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 991
 992         return true;
 993 }
 994
 995 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 996                                  unsigned char addr)
 997 {
 998         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 999         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1000         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1001                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1002         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1003                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1004         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1005                     HDMI_PHY_I2CM_OPERATION_ADDR);
1006         hdmi_phy_wait_i2c_done(hdmi, 1000);
1007 }
1008
1009 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1010                               unsigned char addr)
1011 {
1012         __hdmi_phy_i2c_write(hdmi, data, addr);
1013         return 0;
1014 }
1015
1016 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1017 {
1018         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1019                          HDMI_PHY_CONF0_PDZ_OFFSET,
1020                          HDMI_PHY_CONF0_PDZ_MASK);
1021 }
1022
1023 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1024 {
1025         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1026                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1027                          HDMI_PHY_CONF0_ENTMDS_MASK);
1028 }
1029
1030 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1031 {
1032         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1033                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1034                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1035 }
1036
1037 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1038 {
1039         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1040                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1041                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1042 }
1043
1044 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1045 {
1046         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1047                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1048                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1049 }
1050
1051 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1052 {
1053         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1054                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1055                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1056 }
1057
1058 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1059 {
1060         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1061                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1062                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1063 }
1064
1065 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1066                               unsigned char res, int cscon)
1067 {
1068         unsigned res_idx;
1069         u8 val, msec, tmds_cfg;
1070         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1071         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1072         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1073         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1074
1075         if (prep)
1076                 return -EINVAL;
1077
1078         switch (res) {
1079         case 0: /* color resolution 0 is 8 bit colour depth */
1080         case 8:
1081                 res_idx = DW_HDMI_RES_8;
1082                 break;
1083         case 10:
1084                 res_idx = DW_HDMI_RES_10;
1085                 break;
1086         case 12:
1087                 res_idx = DW_HDMI_RES_12;
1088                 break;
1089         default:
1090                 return -EINVAL;
1091         }
1092
1093         /* PLL/MPLL Cfg - always match on final entry */
1094         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1095                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1096                     mpll_config->mpixelclock)
1097                         break;
1098
1099         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1100                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1101                     curr_ctrl->mpixelclock)
1102                         break;
1103
1104         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1105                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1106                     phy_config->mpixelclock)
1107                         break;
1108
1109         if (mpll_config->mpixelclock == ~0UL ||
1110             curr_ctrl->mpixelclock == ~0UL ||
1111             phy_config->mpixelclock == ~0UL) {
1112                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1113                         hdmi->hdmi_data.video_mode.mpixelclock);
1114                 return -EINVAL;
1115         }
1116
1117         /* Enable csc path */
1118         if (cscon)
1119                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1120         else
1121                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1122
1123         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1124
1125         /* gen2 tx power off */
1126         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1127
1128         /* gen2 pddq */
1129         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1130
1131         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1132         if (hdmi->connector.scdc_present) {
1133                 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1134                 if (mpll_config->mpixelclock > 340000000)
1135                         tmds_cfg |= 2;
1136                 else
1137                         tmds_cfg &= 0x1;
1138                 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1139         }
1140
1141         /* PHY reset */
1142         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1143         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1144
1145         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1146
1147         hdmi_phy_test_clear(hdmi, 1);
1148         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1149                     HDMI_PHY_I2CM_SLAVE_ADDR);
1150         hdmi_phy_test_clear(hdmi, 0);
1151
1152         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1153         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1154
1155         /* CURRCTRL */
1156         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1157
1158         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1159         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1160
1161         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1162         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1163         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1164
1165         /* REMOVE CLK TERM */
1166         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1167
1168         dw_hdmi_phy_enable_powerdown(hdmi, false);
1169
1170         /* toggle TMDS disable */
1171         dw_hdmi_phy_enable_tmds(hdmi, 0);
1172
1173         /* Wait for resuming transmission of TMDS clock and data */
1174         if (mpll_config->mpixelclock > 340000000)
1175                 msleep(100);
1176
1177         /* toggle TMDS enable */
1178         dw_hdmi_phy_enable_tmds(hdmi, 1);
1179
1180         /* gen2 tx power on */
1181         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1182         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1183
1184         if (is_rockchip(hdmi->dev_type))
1185                 dw_hdmi_phy_enable_spare(hdmi, 1);
1186
1187         /* Wait for PHY PLL lock */
1188         msec = 5;
1189         do {
1190                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1191                 if (!val)
1192                         break;
1193
1194                 if (msec == 0) {
1195                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1196                         return -ETIMEDOUT;
1197                 }
1198
1199                 udelay(1000);
1200                 msec--;
1201         } while (1);
1202
1203         return 0;
1204 }
1205
1206 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1207 {
1208         int i, ret;
1209         bool cscon;
1210
1211         /*check csc whether needed activated in HDMI mode */
1212         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1213
1214         /* HDMI Phy spec says to do the phy initialization sequence twice */
1215         for (i = 0; i < 2; i++) {
1216                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1217                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1218                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1219                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1220
1221                 /* Enable CSC */
1222                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1223                 if (ret)
1224                         return ret;
1225         }
1226
1227         hdmi->phy_enabled = true;
1228         return 0;
1229 }
1230
1231 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1232 {
1233         u8 de;
1234
1235         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1236                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1237         else
1238                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1239
1240         /* disable rx detect */
1241         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1242                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1243
1244         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1245
1246         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1247                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1248 }
1249
1250 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1251 {
1252         struct hdmi_avi_infoframe frame;
1253         u8 val;
1254
1255         /* Initialise info frame from DRM mode */
1256         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1257
1258         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1259                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1260         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1261                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1262         else
1263                 frame.colorspace = HDMI_COLORSPACE_RGB;
1264
1265         /* Set up colorimetry */
1266         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1267                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1268                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1269                         frame.extended_colorimetry =
1270                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1271                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1272                         frame.extended_colorimetry =
1273                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1274         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1275                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1276                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1277         } else { /* Carries no data */
1278                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1279                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1280         }
1281
1282         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1283
1284         /*
1285          * The Designware IP uses a different byte format from standard
1286          * AVI info frames, though generally the bits are in the correct
1287          * bytes.
1288          */
1289
1290         /*
1291          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1292          * active aspect present in bit 6 rather than 4.
1293          */
1294         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1295         if (frame.active_aspect & 15)
1296                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1297         if (frame.top_bar || frame.bottom_bar)
1298                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1299         if (frame.left_bar || frame.right_bar)
1300                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1301         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1302
1303         /* AVI data byte 2 differences: none */
1304         val = ((frame.colorimetry & 0x3) << 6) |
1305               ((frame.picture_aspect & 0x3) << 4) |
1306               (frame.active_aspect & 0xf);
1307         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1308
1309         /* AVI data byte 3 differences: none */
1310         val = ((frame.extended_colorimetry & 0x7) << 4) |
1311               ((frame.quantization_range & 0x3) << 2) |
1312               (frame.nups & 0x3);
1313         if (frame.itc)
1314                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1315         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1316
1317         /* AVI data byte 4 differences: none */
1318         val = frame.video_code & 0x7f;
1319         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1320
1321         /* AVI Data Byte 5- set up input and output pixel repetition */
1322         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1323                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1324                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1325                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1326                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1327                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1328         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1329
1330         /*
1331          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1332          * ycc range in bits 2,3 rather than 6,7
1333          */
1334         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1335               (frame.content_type & 0x3);
1336         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1337
1338         /* AVI Data Bytes 6-13 */
1339         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1340         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1341         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1342         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1343         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1344         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1345         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1346         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1347 }
1348
1349 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1350                              const struct drm_display_mode *mode)
1351 {
1352         u8 inv_val, bytes;
1353         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1354         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1355         unsigned int vdisplay;
1356
1357         vmode->mpixelclock = mode->crtc_clock * 1000;
1358
1359         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1360
1361         /* Set up HDMI_FC_INVIDCONF
1362          * fc_invidconf.HDCP_keepout must be set (1'b1)
1363          * when activate the scrambler feature.
1364          */
1365         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1366                    vmode->mpixelclock > 340000000 ||
1367                    hdmi->connector.lte_340mcsc_scramble ?
1368                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1369                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1370
1371         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1372                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1373                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1374
1375         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1376                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1377                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1378
1379         inv_val |= (vmode->mdataenablepolarity ?
1380                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1381                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1382
1383         if (hdmi->vic == 39)
1384                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1385         else
1386                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1387                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1388                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1389
1390         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1391                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1392                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1393
1394         inv_val |= hdmi->sink_is_hdmi ?
1395                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1396                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1397
1398         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1399
1400         vdisplay = mode->vdisplay;
1401         vblank = mode->vtotal - mode->vdisplay;
1402         v_de_vs = mode->vsync_start - mode->vdisplay;
1403         vsync_len = mode->vsync_end - mode->vsync_start;
1404
1405         /*
1406          * When we're setting an interlaced mode, we need
1407          * to adjust the vertical timing to suit.
1408          */
1409         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1410                 vdisplay /= 2;
1411                 vblank /= 2;
1412                 v_de_vs /= 2;
1413                 vsync_len /= 2;
1414         }
1415
1416         /* Scrambling Control */
1417         if (hdmi->connector.scdc_present) {
1418                 if (vmode->mpixelclock > 340000000 ||
1419                     hdmi->connector.lte_340mcsc_scramble) {
1420                         drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1421                                        &bytes);
1422                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1423                                         bytes);
1424                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1425                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1426                                     HDMI_MC_SWRSTZ);
1427                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1428                 } else {
1429                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1430                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1431                                     HDMI_MC_SWRSTZ);
1432                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1433                 }
1434         }
1435
1436         /* Set up horizontal active pixel width */
1437         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1438         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1439
1440         /* Set up vertical active lines */
1441         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1442         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1443
1444         /* Set up horizontal blanking pixel region width */
1445         hblank = mode->htotal - mode->hdisplay;
1446         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1447         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1448
1449         /* Set up vertical blanking pixel region width */
1450         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1451
1452         /* Set up HSYNC active edge delay width (in pixel clks) */
1453         h_de_hs = mode->hsync_start - mode->hdisplay;
1454         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1455         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1456
1457         /* Set up VSYNC active edge delay (in lines) */
1458         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1459
1460         /* Set up HSYNC active pulse width (in pixel clks) */
1461         hsync_len = mode->hsync_end - mode->hsync_start;
1462         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1463         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1464
1465         /* Set up VSYNC active edge delay (in lines) */
1466         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1467 }
1468
1469 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1470 {
1471         if (!hdmi->phy_enabled)
1472                 return;
1473
1474         dw_hdmi_phy_enable_tmds(hdmi, 0);
1475         dw_hdmi_phy_enable_powerdown(hdmi, true);
1476
1477         hdmi->phy_enabled = false;
1478 }
1479
1480 /* HDMI Initialization Step B.4 */
1481 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1482 {
1483         u8 clkdis;
1484
1485         /* control period minimum duration */
1486         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1487         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1488         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1489
1490         /* Set to fill TMDS data channels */
1491         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1492         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1493         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1494
1495         /* Enable pixel clock and tmds data path */
1496         clkdis = 0x7F;
1497         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1498         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1499
1500         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1501         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1502
1503         /* Enable csc path */
1504         if (is_color_space_conversion(hdmi)) {
1505                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1506                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1507         }
1508
1509         /* Enable pixel repetition path */
1510         if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1511                 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1512                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1513         }
1514 }
1515
1516 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1517 {
1518         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1519 }
1520
1521 /* Workaround to clear the overflow condition */
1522 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1523 {
1524         int count;
1525         u8 val;
1526
1527         /* TMDS software reset */
1528         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1529
1530         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1531         if (hdmi->dev_type == IMX6DL_HDMI) {
1532                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1533                 return;
1534         }
1535
1536         for (count = 0; count < 4; count++)
1537                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1538 }
1539
1540 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1541 {
1542         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1543         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1544 }
1545
1546 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1547 {
1548         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1549                     HDMI_IH_MUTE_FC_STAT2);
1550 }
1551
1552 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1553 {
1554         int ret;
1555
1556         hdmi_disable_overflow_interrupts(hdmi);
1557
1558         hdmi->vic = drm_match_cea_mode(mode);
1559
1560         if (!hdmi->vic) {
1561                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1562         } else {
1563                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1564         }
1565
1566         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1567             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1568             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1569             (hdmi->vic == 17) || (hdmi->vic == 18))
1570                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1571         else
1572                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1573
1574         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1575                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1576                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1577         } else {
1578                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1579                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1580         }
1581         /* TODO: Get input format from IPU (via FB driver interface) */
1582         hdmi->hdmi_data.enc_in_format = RGB;
1583
1584         hdmi->hdmi_data.enc_out_format = RGB;
1585
1586         hdmi->hdmi_data.enc_color_depth = 8;
1587         /*
1588          * According to the dw-hdmi specification 6.4.2
1589          * vp_pr_cd[3:0]:
1590          * 0000b: No pixel repetition (pixel sent only once)
1591          * 0001b: Pixel sent two times (pixel repeated once)
1592          */
1593         hdmi->hdmi_data.pix_repet_factor =
1594                 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1595         hdmi->hdmi_data.hdcp_enable = 0;
1596         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1597
1598         /* HDMI Initialization Step B.1 */
1599         hdmi_av_composer(hdmi, mode);
1600
1601         /* HDMI Initializateion Step B.2 */
1602         ret = dw_hdmi_phy_init(hdmi);
1603         if (ret)
1604                 return ret;
1605
1606         /* HDMI Initialization Step B.3 */
1607         dw_hdmi_enable_video_path(hdmi);
1608
1609         if (hdmi->sink_has_audio) {
1610                 dev_dbg(hdmi->dev, "sink has audio support\n");
1611
1612                 /* HDMI Initialization Step E - Configure audio */
1613                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1614                 hdmi_enable_audio_clk(hdmi);
1615         }
1616
1617         /* not for DVI mode */
1618         if (hdmi->sink_is_hdmi) {
1619                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1620
1621                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1622                 hdmi_config_AVI(hdmi, mode);
1623         } else {
1624                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1625         }
1626
1627         hdmi_video_packetize(hdmi);
1628         hdmi_video_csc(hdmi);
1629         hdmi_video_sample(hdmi);
1630         hdmi_tx_hdcp_config(hdmi);
1631
1632         dw_hdmi_clear_overflow(hdmi);
1633         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1634                 hdmi_enable_overflow_interrupts(hdmi);
1635
1636         return 0;
1637 }
1638
1639 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1640 {
1641         u8 ih_mute;
1642
1643         /*
1644          * Boot up defaults are:
1645          * HDMI_IH_MUTE   = 0x03 (disabled)
1646          * HDMI_IH_MUTE_* = 0x00 (enabled)
1647          *
1648          * Disable top level interrupt bits in HDMI block
1649          */
1650         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1651                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1652                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1653
1654         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1655
1656         /* by default mask all interrupts */
1657         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1658         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1659         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1660         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1661         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1662         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1663         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1664         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1665         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1666         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1667         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1668         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1669         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1670         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1671         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1672
1673         /* Disable interrupts in the IH_MUTE_* registers */
1674         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1675         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1676         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1677         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1678         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1679         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1680         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1681         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1682         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1683         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1684
1685         /* Enable top level interrupt bits in HDMI block */
1686         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1687                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1688         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1689 }
1690
1691 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1692 {
1693         hdmi->bridge_is_on = true;
1694         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1695 }
1696
1697 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1698 {
1699         dw_hdmi_phy_disable(hdmi);
1700         hdmi->bridge_is_on = false;
1701 }
1702
1703 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1704 {
1705         int force = hdmi->force;
1706
1707         if (hdmi->disabled) {
1708                 force = DRM_FORCE_OFF;
1709         } else if (force == DRM_FORCE_UNSPECIFIED) {
1710                 if (hdmi->rxsense)
1711                         force = DRM_FORCE_ON;
1712                 else
1713                         force = DRM_FORCE_OFF;
1714         }
1715
1716         if (force == DRM_FORCE_OFF) {
1717                 if (hdmi->bridge_is_on)
1718                         dw_hdmi_poweroff(hdmi);
1719         } else {
1720                 if (!hdmi->bridge_is_on)
1721                         dw_hdmi_poweron(hdmi);
1722         }
1723 }
1724
1725 /*
1726  * Adjust the detection of RXSENSE according to whether we have a forced
1727  * connection mode enabled, or whether we have been disabled.  There is
1728  * no point processing RXSENSE interrupts if we have a forced connection
1729  * state, or DRM has us disabled.
1730  *
1731  * We also disable rxsense interrupts when we think we're disconnected
1732  * to avoid floating TDMS signals giving false rxsense interrupts.
1733  *
1734  * Note: we still need to listen for HPD interrupts even when DRM has us
1735  * disabled so that we can detect a connect event.
1736  */
1737 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1738 {
1739         u8 old_mask = hdmi->phy_mask;
1740
1741         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1742                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1743         else
1744                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1745
1746         if (old_mask != hdmi->phy_mask)
1747                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1748 }
1749
1750 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1751                                     struct drm_display_mode *orig_mode,
1752                                     struct drm_display_mode *mode)
1753 {
1754         struct dw_hdmi *hdmi = bridge->driver_private;
1755
1756         mutex_lock(&hdmi->mutex);
1757
1758         /* Store the display mode for plugin/DKMS poweron events */
1759         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1760
1761         mutex_unlock(&hdmi->mutex);
1762 }
1763
1764 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1765 {
1766         struct dw_hdmi *hdmi = bridge->driver_private;
1767
1768         mutex_lock(&hdmi->mutex);
1769         hdmi->disabled = true;
1770         dw_hdmi_update_power(hdmi);
1771         dw_hdmi_update_phy_mask(hdmi);
1772         mutex_unlock(&hdmi->mutex);
1773 }
1774
1775 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1776 {
1777         struct dw_hdmi *hdmi = bridge->driver_private;
1778
1779         mutex_lock(&hdmi->mutex);
1780         hdmi->disabled = false;
1781         dw_hdmi_update_power(hdmi);
1782         dw_hdmi_update_phy_mask(hdmi);
1783         mutex_unlock(&hdmi->mutex);
1784 }
1785
1786 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1787 {
1788         /* do nothing */
1789 }
1790
1791 static enum drm_connector_status
1792 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1793 {
1794         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1795                                              connector);
1796
1797         mutex_lock(&hdmi->mutex);
1798         hdmi->force = DRM_FORCE_UNSPECIFIED;
1799         dw_hdmi_update_power(hdmi);
1800         dw_hdmi_update_phy_mask(hdmi);
1801         mutex_unlock(&hdmi->mutex);
1802
1803         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1804                 connector_status_connected : connector_status_disconnected;
1805 }
1806
1807 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1808 {
1809         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1810                                              connector);
1811         struct edid *edid;
1812         int ret = 0;
1813
1814         if (!hdmi->ddc)
1815                 return 0;
1816
1817         edid = drm_get_edid(connector, hdmi->ddc);
1818         if (edid) {
1819                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1820                         edid->width_cm, edid->height_cm);
1821
1822                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1823                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1824                 drm_mode_connector_update_edid_property(connector, edid);
1825                 ret = drm_add_edid_modes(connector, edid);
1826                 /* Store the ELD */
1827                 drm_edid_to_eld(connector, edid);
1828                 kfree(edid);
1829         } else {
1830                 dev_dbg(hdmi->dev, "failed to get edid\n");
1831         }
1832
1833         return ret;
1834 }
1835
1836 static enum drm_mode_status
1837 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1838                              struct drm_display_mode *mode)
1839 {
1840         struct dw_hdmi *hdmi = container_of(connector,
1841                                            struct dw_hdmi, connector);
1842         enum drm_mode_status mode_status = MODE_OK;
1843
1844         if (hdmi->plat_data->mode_valid)
1845                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1846
1847         return mode_status;
1848 }
1849
1850 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1851                                                            *connector)
1852 {
1853         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1854                                              connector);
1855
1856         return hdmi->encoder;
1857 }
1858
1859 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1860 {
1861         drm_connector_unregister(connector);
1862         drm_connector_cleanup(connector);
1863 }
1864
1865 static void dw_hdmi_connector_force(struct drm_connector *connector)
1866 {
1867         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1868                                              connector);
1869
1870         mutex_lock(&hdmi->mutex);
1871         hdmi->force = connector->force;
1872         dw_hdmi_update_power(hdmi);
1873         dw_hdmi_update_phy_mask(hdmi);
1874         mutex_unlock(&hdmi->mutex);
1875 }
1876
1877 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1878         .dpms = drm_helper_connector_dpms,
1879         .fill_modes = drm_helper_probe_single_connector_modes,
1880         .detect = dw_hdmi_connector_detect,
1881         .destroy = dw_hdmi_connector_destroy,
1882         .force = dw_hdmi_connector_force,
1883 };
1884
1885 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1886         .dpms = drm_atomic_helper_connector_dpms,
1887         .fill_modes = drm_helper_probe_single_connector_modes,
1888         .detect = dw_hdmi_connector_detect,
1889         .destroy = dw_hdmi_connector_destroy,
1890         .force = dw_hdmi_connector_force,
1891         .reset = drm_atomic_helper_connector_reset,
1892         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1893         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1894 };
1895
1896 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1897         .get_modes = dw_hdmi_connector_get_modes,
1898         .mode_valid = dw_hdmi_connector_mode_valid,
1899         .best_encoder = dw_hdmi_connector_best_encoder,
1900 };
1901
1902 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1903         .enable = dw_hdmi_bridge_enable,
1904         .disable = dw_hdmi_bridge_disable,
1905         .pre_enable = dw_hdmi_bridge_nop,
1906         .post_disable = dw_hdmi_bridge_nop,
1907         .mode_set = dw_hdmi_bridge_mode_set,
1908 };
1909
1910 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1911 {
1912         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1913         unsigned int stat;
1914
1915         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1916         if (!stat)
1917                 return IRQ_NONE;
1918
1919         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1920
1921         i2c->stat = stat;
1922
1923         complete(&i2c->cmp);
1924
1925         return IRQ_HANDLED;
1926 }
1927
1928 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1929 {
1930         struct dw_hdmi *hdmi = dev_id;
1931         u8 intr_stat;
1932         irqreturn_t ret = IRQ_NONE;
1933
1934         if (hdmi->i2c)
1935                 ret = dw_hdmi_i2c_irq(hdmi);
1936
1937         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1938         if (intr_stat) {
1939                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1940                 return IRQ_WAKE_THREAD;
1941         }
1942
1943         return ret;
1944 }
1945
1946 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1947 {
1948         struct dw_hdmi *hdmi = dev_id;
1949         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1950
1951         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1952         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1953         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1954
1955         phy_pol_mask = 0;
1956         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1957                 phy_pol_mask |= HDMI_PHY_HPD;
1958         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1959                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1960         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1961                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1962         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1963                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1964         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1965                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1966
1967         if (phy_pol_mask)
1968                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1969
1970         /*
1971          * RX sense tells us whether the TDMS transmitters are detecting
1972          * load - in other words, there's something listening on the
1973          * other end of the link.  Use this to decide whether we should
1974          * power on the phy as HPD may be toggled by the sink to merely
1975          * ask the source to re-read the EDID.
1976          */
1977         if (intr_stat &
1978             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1979                 mutex_lock(&hdmi->mutex);
1980                 if (!hdmi->bridge_is_on && !hdmi->force) {
1981                         /*
1982                          * If the RX sense status indicates we're disconnected,
1983                          * clear the software rxsense status.
1984                          */
1985                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1986                                 hdmi->rxsense = false;
1987
1988                         /*
1989                          * Only set the software rxsense status when both
1990                          * rxsense and hpd indicates we're connected.
1991                          * This avoids what seems to be bad behaviour in
1992                          * at least iMX6S versions of the phy.
1993                          */
1994                         if (phy_stat & HDMI_PHY_HPD)
1995                                 hdmi->rxsense = true;
1996
1997                         dw_hdmi_update_power(hdmi);
1998                         dw_hdmi_update_phy_mask(hdmi);
1999                 }
2000                 mutex_unlock(&hdmi->mutex);
2001         }
2002
2003         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2004                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2005                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2006                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
2007 #ifdef CONFIG_SWITCH
2008                 if (phy_int_pol & HDMI_PHY_HPD)
2009                         switch_set_state(&hdmi->switchdev, 1);
2010                 else
2011                         switch_set_state(&hdmi->switchdev, 0);
2012 #endif
2013         }
2014
2015         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2016         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2017                     HDMI_IH_MUTE_PHY_STAT0);
2018
2019         return IRQ_HANDLED;
2020 }
2021
2022 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2023 {
2024         struct drm_encoder *encoder = hdmi->encoder;
2025         struct drm_bridge *bridge;
2026         int ret;
2027
2028         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2029         if (!bridge) {
2030                 DRM_ERROR("Failed to allocate drm bridge\n");
2031                 return -ENOMEM;
2032         }
2033
2034         hdmi->bridge = bridge;
2035         bridge->driver_private = hdmi;
2036         bridge->funcs = &dw_hdmi_bridge_funcs;
2037         ret = drm_bridge_attach(drm, bridge);
2038         if (ret) {
2039                 DRM_ERROR("Failed to initialize bridge with drm\n");
2040                 return -EINVAL;
2041         }
2042
2043         encoder->bridge = bridge;
2044         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2045         hdmi->connector.port = hdmi->dev->of_node;
2046
2047         drm_connector_helper_add(&hdmi->connector,
2048                                  &dw_hdmi_connector_helper_funcs);
2049
2050         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2051                 drm_connector_init(drm, &hdmi->connector,
2052                                    &dw_hdmi_atomic_connector_funcs,
2053                                    DRM_MODE_CONNECTOR_HDMIA);
2054         else
2055                 drm_connector_init(drm, &hdmi->connector,
2056                                    &dw_hdmi_connector_funcs,
2057                                    DRM_MODE_CONNECTOR_HDMIA);
2058
2059         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2060
2061         return 0;
2062 }
2063
2064 int dw_hdmi_bind(struct device *dev, struct device *master,
2065                  void *data, struct drm_encoder *encoder,
2066                  struct resource *iores, int irq,
2067                  const struct dw_hdmi_plat_data *plat_data)
2068 {
2069         struct drm_device *drm = data;
2070         struct device_node *np = dev->of_node;
2071         struct platform_device_info pdevinfo;
2072         struct device_node *ddc_node;
2073         struct dw_hdmi *hdmi;
2074         int ret;
2075         u32 val = 1;
2076         u8 config0;
2077         u8 config1;
2078
2079         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2080         if (!hdmi)
2081                 return -ENOMEM;
2082
2083         hdmi->connector.interlace_allowed = 1;
2084
2085         hdmi->plat_data = plat_data;
2086         hdmi->dev = dev;
2087         hdmi->dev_type = plat_data->dev_type;
2088         hdmi->sample_rate = 48000;
2089         hdmi->encoder = encoder;
2090         hdmi->disabled = true;
2091         hdmi->rxsense = true;
2092         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2093
2094         mutex_init(&hdmi->mutex);
2095         mutex_init(&hdmi->audio_mutex);
2096         spin_lock_init(&hdmi->audio_lock);
2097
2098         of_property_read_u32(np, "reg-io-width", &val);
2099
2100         switch (val) {
2101         case 4:
2102                 hdmi->write = dw_hdmi_writel;
2103                 hdmi->read = dw_hdmi_readl;
2104                 break;
2105         case 1:
2106                 hdmi->write = dw_hdmi_writeb;
2107                 hdmi->read = dw_hdmi_readb;
2108                 break;
2109         default:
2110                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2111                 return -EINVAL;
2112         }
2113
2114         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2115         if (ddc_node) {
2116                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2117                 of_node_put(ddc_node);
2118                 if (!hdmi->ddc) {
2119                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2120                         return -EPROBE_DEFER;
2121                 }
2122
2123         } else {
2124                 dev_dbg(hdmi->dev, "no ddc property found\n");
2125         }
2126
2127         /* If DDC bus is not specified, try to register HDMI I2C bus */
2128         if (!hdmi->ddc) {
2129                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2130                 if (IS_ERR(hdmi->ddc))
2131                         hdmi->ddc = NULL;
2132         }
2133
2134         hdmi->regs = devm_ioremap_resource(dev, iores);
2135         if (IS_ERR(hdmi->regs))
2136                 return PTR_ERR(hdmi->regs);
2137
2138         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2139         if (IS_ERR(hdmi->isfr_clk)) {
2140                 ret = PTR_ERR(hdmi->isfr_clk);
2141                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2142                 return ret;
2143         }
2144
2145         ret = clk_prepare_enable(hdmi->isfr_clk);
2146         if (ret) {
2147                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2148                 return ret;
2149         }
2150
2151         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2152         if (IS_ERR(hdmi->iahb_clk)) {
2153                 ret = PTR_ERR(hdmi->iahb_clk);
2154                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2155                 goto err_isfr;
2156         }
2157
2158         ret = clk_prepare_enable(hdmi->iahb_clk);
2159         if (ret) {
2160                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2161                 goto err_isfr;
2162         }
2163
2164         /* Product and revision IDs */
2165         dev_info(dev,
2166                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2167                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2168                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2169                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2170                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2171
2172         initialize_hdmi_ih_mutes(hdmi);
2173
2174         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2175                                         dw_hdmi_irq, IRQF_SHARED,
2176                                         dev_name(dev), hdmi);
2177         if (ret)
2178                 goto err_iahb;
2179
2180         /*
2181          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2182          * N and cts values before enabling phy
2183          */
2184         hdmi_init_clk_regenerator(hdmi);
2185
2186         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2187                     HDMI_PHY_I2CM_INT_ADDR);
2188
2189         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2190                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2191                     HDMI_PHY_I2CM_CTLINT_ADDR);
2192
2193         /* Re-init HPD polarity */
2194         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2195
2196         /* Unmask HPD, clear transitory interrupts, then unmute */
2197         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2198
2199         ret = dw_hdmi_register(drm, hdmi);
2200         if (ret)
2201                 goto err_iahb;
2202
2203 #ifdef CONFIG_SWITCH
2204         hdmi->switchdev.name = "hdmi";
2205         switch_dev_register(&hdmi->switchdev);
2206 #endif
2207
2208         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2209                     HDMI_IH_MUTE_PHY_STAT0);
2210
2211         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2212         if (hdmi->i2c)
2213                 dw_hdmi_i2c_init(hdmi);
2214
2215         memset(&pdevinfo, 0, sizeof(pdevinfo));
2216         pdevinfo.parent = dev;
2217         pdevinfo.id = PLATFORM_DEVID_AUTO;
2218
2219         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2220         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2221
2222         if (config1 & HDMI_CONFIG1_AHB) {
2223                 struct dw_hdmi_audio_data audio;
2224
2225                 audio.phys = iores->start;
2226                 audio.base = hdmi->regs;
2227                 audio.irq = irq;
2228                 audio.hdmi = hdmi;
2229                 audio.eld = hdmi->connector.eld;
2230
2231                 pdevinfo.name = "dw-hdmi-ahb-audio";
2232                 pdevinfo.data = &audio;
2233                 pdevinfo.size_data = sizeof(audio);
2234                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2235                 hdmi->audio = platform_device_register_full(&pdevinfo);
2236         } else if (config0 & HDMI_CONFIG0_I2S) {
2237                 struct dw_hdmi_i2s_audio_data audio;
2238
2239                 audio.hdmi      = hdmi;
2240                 audio.write     = hdmi_writeb;
2241                 audio.read      = hdmi_readb;
2242
2243                 pdevinfo.name = "dw-hdmi-i2s-audio";
2244                 pdevinfo.data = &audio;
2245                 pdevinfo.size_data = sizeof(audio);
2246                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2247                 hdmi->audio = platform_device_register_full(&pdevinfo);
2248         }
2249
2250         dev_set_drvdata(dev, hdmi);
2251
2252         return 0;
2253
2254 err_iahb:
2255         if (hdmi->i2c)
2256                 i2c_del_adapter(&hdmi->i2c->adap);
2257
2258         clk_disable_unprepare(hdmi->iahb_clk);
2259 err_isfr:
2260         clk_disable_unprepare(hdmi->isfr_clk);
2261
2262         return ret;
2263 }
2264 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2265
2266 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2267 {
2268         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2269
2270         if (hdmi->audio && !IS_ERR(hdmi->audio))
2271                 platform_device_unregister(hdmi->audio);
2272
2273         /* Disable all interrupts */
2274         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2275
2276 #ifdef CONFIG_SWITCH
2277         switch_dev_unregister(&hdmi->switchdev);
2278 #endif
2279         hdmi->connector.funcs->destroy(&hdmi->connector);
2280         hdmi->encoder->funcs->destroy(hdmi->encoder);
2281
2282         clk_disable_unprepare(hdmi->iahb_clk);
2283         clk_disable_unprepare(hdmi->isfr_clk);
2284
2285         if (hdmi->i2c)
2286                 i2c_del_adapter(&hdmi->i2c->adap);
2287         else
2288                 i2c_put_adapter(hdmi->ddc);
2289 }
2290 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2291
2292 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2293 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2294 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2295 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2296 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2297 MODULE_LICENSE("GPL");
2298 MODULE_ALIAS("platform:dw-hdmi");