drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

   1 /*
   2 * Analogix DP (Display Port) core interface driver.
   3 *
   4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5 * Author: Jingoo Han <jg1.han@samsung.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms of the GNU General Public License as published by the
   9 * Free Software Foundation; either version 2 of the License, or (at your
  10 * option) any later version.
  11 */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/of.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/gpio.h>
  22 #include <linux/component.h>
  23 #include <linux/phy/phy.h>
  24
  25 #include <drm/drmP.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_panel.h>
  30
  31 #include <drm/bridge/analogix_dp.h>
  32
  33 #include "analogix_dp_core.h"
  34
  35 #define to_dp(nm)       container_of(nm, struct analogix_dp_device, nm)
  36
  37 struct bridge_init {
  38         struct i2c_client *client;
  39         struct device_node *node;
  40 };
  41
  42 static void analogix_dp_init_dp(struct analogix_dp_device *dp)
  43 {
  44         analogix_dp_reset(dp);
  45
  46         analogix_dp_swreset(dp);
  47
  48         analogix_dp_init_analog_param(dp);
  49         analogix_dp_init_interrupt(dp);
  50
  51         /* SW defined function Normal operation */
  52         analogix_dp_enable_sw_function(dp);
  53
  54         analogix_dp_config_interrupt(dp);
  55         analogix_dp_init_analog_func(dp);
  56
  57         analogix_dp_init_hpd(dp);
  58         analogix_dp_init_aux(dp);
  59 }
  60
  61 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  62 {
  63         int timeout_loop = 0;
  64
  65         while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  66                 if (analogix_dp_get_plug_in_status(dp) == 0)
  67                         return 0;
  68
  69                 timeout_loop++;
  70                 usleep_range(10, 11);
  71         }
  72
  73         /*
  74          * Some edp screen do not have hpd signal, so we can't just
  75          * return failed when hpd plug in detect failed, DT property
  76          * "force-hpd" would indicate whether driver need this.
  77          */
  78         if (!dp->force_hpd)
  79                 return -ETIMEDOUT;
  80
  81         /*
  82          * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  83          * will not work, so we need to give a force hpd action to
  84          * set HPD_STATUS manually.
  85          */
  86         dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  87
  88         analogix_dp_force_hpd(dp);
  89
  90         if (analogix_dp_get_plug_in_status(dp) != 0) {
  91                 dev_err(dp->dev, "failed to get hpd plug in status\n");
  92                 return -EINVAL;
  93         }
  94
  95         dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
  96
  97         return 0;
  98 }
  99
 100 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 101 {
 102         int i;
 103         unsigned char sum = 0;
 104
 105         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
 106                 sum = sum + edid_data[i];
 107
 108         return sum;
 109 }
 110
 111 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 112 {
 113         unsigned char *edid = dp->edid;
 114         unsigned int extend_block = 0;
 115         unsigned char sum;
 116         unsigned char test_vector;
 117         int retval;
 118
 119         /*
 120          * EDID device address is 0x50.
 121          * However, if necessary, you must have set upper address
 122          * into E-EDID in I2C device, 0x30.
 123          */
 124
 125         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 126         retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 127                                                 EDID_EXTENSION_FLAG,
 128                                                 &extend_block);
 129         if (retval)
 130                 return retval;
 131
 132         if (extend_block > 0) {
 133                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 134
 135                 /* Read EDID data */
 136                 retval = analogix_dp_read_bytes_from_i2c(dp,
 137                                                 I2C_EDID_DEVICE_ADDR,
 138                                                 EDID_HEADER_PATTERN,
 139                                                 EDID_BLOCK_LENGTH,
 140                                                 &edid[EDID_HEADER_PATTERN]);
 141                 if (retval != 0) {
 142                         dev_err(dp->dev, "EDID Read failed!\n");
 143                         return -EIO;
 144                 }
 145                 sum = analogix_dp_calc_edid_check_sum(edid);
 146                 if (sum != 0) {
 147                         dev_err(dp->dev, "EDID bad checksum!\n");
 148                         return -EIO;
 149                 }
 150
 151                 /* Read additional EDID data */
 152                 retval = analogix_dp_read_bytes_from_i2c(dp,
 153                                 I2C_EDID_DEVICE_ADDR,
 154                                 EDID_BLOCK_LENGTH,
 155                                 EDID_BLOCK_LENGTH,
 156                                 &edid[EDID_BLOCK_LENGTH]);
 157                 if (retval != 0) {
 158                         dev_err(dp->dev, "EDID Read failed!\n");
 159                         return -EIO;
 160                 }
 161                 sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 162                 if (sum != 0) {
 163                         dev_err(dp->dev, "EDID bad checksum!\n");
 164                         return -EIO;
 165                 }
 166
 167                 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
 168                                                 &test_vector);
 169                 if (test_vector & DP_TEST_LINK_EDID_READ) {
 170                         analogix_dp_write_byte_to_dpcd(dp,
 171                                 DP_TEST_EDID_CHECKSUM,
 172                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 173                         analogix_dp_write_byte_to_dpcd(dp,
 174                                 DP_TEST_RESPONSE,
 175                                 DP_TEST_EDID_CHECKSUM_WRITE);
 176                 }
 177         } else {
 178                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 179
 180                 /* Read EDID data */
 181                 retval = analogix_dp_read_bytes_from_i2c(dp,
 182                                 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
 183                                 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 184                 if (retval != 0) {
 185                         dev_err(dp->dev, "EDID Read failed!\n");
 186                         return -EIO;
 187                 }
 188                 sum = analogix_dp_calc_edid_check_sum(edid);
 189                 if (sum != 0) {
 190                         dev_err(dp->dev, "EDID bad checksum!\n");
 191                         return -EIO;
 192                 }
 193
 194                 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
 195                                                 &test_vector);
 196                 if (test_vector & DP_TEST_LINK_EDID_READ) {
 197                         analogix_dp_write_byte_to_dpcd(dp,
 198                                 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 199                         analogix_dp_write_byte_to_dpcd(dp,
 200                                 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
 201                 }
 202         }
 203
 204         dev_dbg(dp->dev, "EDID Read success!\n");
 205         return 0;
 206 }
 207
 208 static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 209 {
 210         u8 buf[12];
 211         int i;
 212         int retval;
 213
 214         /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 215         retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 216         if (retval)
 217                 return retval;
 218
 219         /* Read EDID */
 220         for (i = 0; i < 3; i++) {
 221                 retval = analogix_dp_read_edid(dp);
 222                 if (!retval)
 223                         break;
 224         }
 225
 226         return retval;
 227 }
 228
 229 static void
 230 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 231                                        bool enable)
 232 {
 233         u8 data;
 234
 235         analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 236
 237         if (enable)
 238                 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 239                                                DP_LANE_COUNT_ENHANCED_FRAME_EN |
 240                                                DPCD_LANE_COUNT_SET(data));
 241         else
 242                 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 243                                                DPCD_LANE_COUNT_SET(data));
 244 }
 245
 246 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
 247 {
 248         u8 data;
 249         int retval;
 250
 251         analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 252         retval = DPCD_ENHANCED_FRAME_CAP(data);
 253
 254         return retval;
 255 }
 256
 257 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 258 {
 259         u8 data;
 260
 261         data = analogix_dp_is_enhanced_mode_available(dp);
 262         analogix_dp_enable_rx_to_enhanced_mode(dp, data);
 263         analogix_dp_enable_enhanced_mode(dp, data);
 264 }
 265
 266 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 267 {
 268         analogix_dp_set_training_pattern(dp, DP_NONE);
 269
 270         analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
 271                                        DP_TRAINING_PATTERN_DISABLE);
 272 }
 273
 274 static void
 275 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 276                                        int pre_emphasis, int lane)
 277 {
 278         switch (lane) {
 279         case 0:
 280                 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 281                 break;
 282         case 1:
 283                 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 284                 break;
 285
 286         case 2:
 287                 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 288                 break;
 289
 290         case 3:
 291                 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 292                 break;
 293         }
 294 }
 295
 296 static int analogix_dp_link_start(struct analogix_dp_device *dp)
 297 {
 298         u8 buf[4];
 299         int lane, lane_count, pll_tries, retval;
 300
 301         lane_count = dp->link_train.lane_count;
 302
 303         dp->link_train.lt_state = CLOCK_RECOVERY;
 304         dp->link_train.eq_loop = 0;
 305
 306         for (lane = 0; lane < lane_count; lane++)
 307                 dp->link_train.cr_loop[lane] = 0;
 308
 309         /* Set link rate and count as you want to establish*/
 310         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 311         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 312
 313         /* Setup RX configuration */
 314         buf[0] = dp->link_train.link_rate;
 315         buf[1] = dp->link_train.lane_count;
 316         retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 317         if (retval)
 318                 return retval;
 319
 320         /* Set TX pre-emphasis to minimum */
 321         for (lane = 0; lane < lane_count; lane++)
 322                 analogix_dp_set_lane_lane_pre_emphasis(dp,
 323                         PRE_EMPHASIS_LEVEL_0, lane);
 324
 325         /* Wait for PLL lock */
 326         pll_tries = 0;
 327         while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 328                 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 329                         dev_err(dp->dev, "Wait for PLL lock timed out\n");
 330                         return -ETIMEDOUT;
 331                 }
 332
 333                 pll_tries++;
 334                 usleep_range(90, 120);
 335         }
 336
 337         /* Set training pattern 1 */
 338         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 339
 340         /* Set RX training pattern */
 341         retval = analogix_dp_write_byte_to_dpcd(dp,
 342                         DP_TRAINING_PATTERN_SET,
 343                         DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
 344         if (retval)
 345                 return retval;
 346
 347         for (lane = 0; lane < lane_count; lane++)
 348                 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 349                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 350
 351         retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 352                                                  lane_count, buf);
 353
 354         return retval;
 355 }
 356
 357 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 358 {
 359         int shift = (lane & 1) * 4;
 360         u8 link_value = link_status[lane >> 1];
 361
 362         return (link_value >> shift) & 0xf;
 363 }
 364
 365 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 366 {
 367         int lane;
 368         u8 lane_status;
 369
 370         for (lane = 0; lane < lane_count; lane++) {
 371                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 372                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 373                         return -EINVAL;
 374         }
 375         return 0;
 376 }
 377
 378 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 379                                      int lane_count)
 380 {
 381         int lane;
 382         u8 lane_status;
 383
 384         if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 385                 return -EINVAL;
 386
 387         for (lane = 0; lane < lane_count; lane++) {
 388                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 389                 lane_status &= DP_CHANNEL_EQ_BITS;
 390                 if (lane_status != DP_CHANNEL_EQ_BITS)
 391                         return -EINVAL;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static unsigned char
 398 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 399 {
 400         int shift = (lane & 1) * 4;
 401         u8 link_value = adjust_request[lane >> 1];
 402
 403         return (link_value >> shift) & 0x3;
 404 }
 405
 406 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 407                                         u8 adjust_request[2],
 408                                         int lane)
 409 {
 410         int shift = (lane & 1) * 4;
 411         u8 link_value = adjust_request[lane >> 1];
 412
 413         return ((link_value >> shift) & 0xc) >> 2;
 414 }
 415
 416 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 417                                                u8 training_lane_set, int lane)
 418 {
 419         switch (lane) {
 420         case 0:
 421                 analogix_dp_set_lane0_link_training(dp, training_lane_set);
 422                 break;
 423         case 1:
 424                 analogix_dp_set_lane1_link_training(dp, training_lane_set);
 425                 break;
 426
 427         case 2:
 428                 analogix_dp_set_lane2_link_training(dp, training_lane_set);
 429                 break;
 430
 431         case 3:
 432                 analogix_dp_set_lane3_link_training(dp, training_lane_set);
 433                 break;
 434         }
 435 }
 436
 437 static unsigned int
 438 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
 439                                    int lane)
 440 {
 441         u32 reg;
 442
 443         switch (lane) {
 444         case 0:
 445                 reg = analogix_dp_get_lane0_link_training(dp);
 446                 break;
 447         case 1:
 448                 reg = analogix_dp_get_lane1_link_training(dp);
 449                 break;
 450         case 2:
 451                 reg = analogix_dp_get_lane2_link_training(dp);
 452                 break;
 453         case 3:
 454                 reg = analogix_dp_get_lane3_link_training(dp);
 455                 break;
 456         default:
 457                 WARN_ON(1);
 458                 return 0;
 459         }
 460
 461         return reg;
 462 }
 463
 464 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 465 {
 466         analogix_dp_training_pattern_dis(dp);
 467         analogix_dp_set_enhanced_mode(dp);
 468
 469         dp->link_train.lt_state = FAILED;
 470 }
 471
 472 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 473                                                  u8 adjust_request[2])
 474 {
 475         int lane, lane_count;
 476         u8 voltage_swing, pre_emphasis, training_lane;
 477
 478         lane_count = dp->link_train.lane_count;
 479         for (lane = 0; lane < lane_count; lane++) {
 480                 voltage_swing = analogix_dp_get_adjust_request_voltage(
 481                                                 adjust_request, lane);
 482                 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 483                                                 adjust_request, lane);
 484                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 485                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 486
 487                 if (voltage_swing == VOLTAGE_LEVEL_3)
 488                         training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 489                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 490                         training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 491
 492                 dp->link_train.training_lane[lane] = training_lane;
 493         }
 494 }
 495
 496 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 497 {
 498         int lane, lane_count, retval;
 499         u8 voltage_swing, pre_emphasis, training_lane;
 500         u8 link_status[2], adjust_request[2];
 501
 502         usleep_range(100, 101);
 503
 504         lane_count = dp->link_train.lane_count;
 505
 506         retval =  analogix_dp_read_bytes_from_dpcd(dp,
 507                         DP_LANE0_1_STATUS, 2, link_status);
 508         if (retval)
 509                 return retval;
 510
 511         retval =  analogix_dp_read_bytes_from_dpcd(dp,
 512                         DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 513         if (retval)
 514                 return retval;
 515
 516         if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 517                 /* set training pattern 2 for EQ */
 518                 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 519
 520                 retval = analogix_dp_write_byte_to_dpcd(dp,
 521                                 DP_TRAINING_PATTERN_SET,
 522                                 DP_LINK_SCRAMBLING_DISABLE |
 523                                 DP_TRAINING_PATTERN_2);
 524                 if (retval)
 525                         return retval;
 526
 527                 dev_info(dp->dev, "Link Training Clock Recovery success\n");
 528                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 529         } else {
 530                 for (lane = 0; lane < lane_count; lane++) {
 531                         training_lane = analogix_dp_get_lane_link_training(
 532                                                         dp, lane);
 533                         voltage_swing = analogix_dp_get_adjust_request_voltage(
 534                                                         adjust_request, lane);
 535                         pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 536                                                         adjust_request, lane);
 537
 538                         if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
 539                                         voltage_swing &&
 540                             DPCD_PRE_EMPHASIS_GET(training_lane) ==
 541                                         pre_emphasis)
 542                                 dp->link_train.cr_loop[lane]++;
 543
 544                         if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 545                             voltage_swing == VOLTAGE_LEVEL_3 ||
 546                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 547                                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 548                                         dp->link_train.cr_loop[lane],
 549                                         voltage_swing, pre_emphasis);
 550                                 analogix_dp_reduce_link_rate(dp);
 551                                 return -EIO;
 552                         }
 553                 }
 554         }
 555
 556         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 557
 558         for (lane = 0; lane < lane_count; lane++)
 559                 analogix_dp_set_lane_link_training(dp,
 560                         dp->link_train.training_lane[lane], lane);
 561
 562         retval = analogix_dp_write_bytes_to_dpcd(dp,
 563                         DP_TRAINING_LANE0_SET, lane_count,
 564                         dp->link_train.training_lane);
 565         if (retval)
 566                 return retval;
 567
 568         return retval;
 569 }
 570
 571 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 572 {
 573         int lane, lane_count, retval;
 574         u32 reg;
 575         u8 link_align, link_status[2], adjust_request[2];
 576
 577         usleep_range(400, 401);
 578
 579         lane_count = dp->link_train.lane_count;
 580
 581         retval = analogix_dp_read_bytes_from_dpcd(dp,
 582                         DP_LANE0_1_STATUS, 2, link_status);
 583         if (retval)
 584                 return retval;
 585
 586         if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
 587                 analogix_dp_reduce_link_rate(dp);
 588                 return -EIO;
 589         }
 590
 591         retval = analogix_dp_read_bytes_from_dpcd(dp,
 592                         DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 593         if (retval)
 594                 return retval;
 595
 596         retval = analogix_dp_read_byte_from_dpcd(dp,
 597                         DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 598         if (retval)
 599                 return retval;
 600
 601         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 602
 603         if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 604                 /* traing pattern Set to Normal */
 605                 analogix_dp_training_pattern_dis(dp);
 606
 607                 dev_info(dp->dev, "Link Training success!\n");
 608
 609                 analogix_dp_get_link_bandwidth(dp, &reg);
 610                 dp->link_train.link_rate = reg;
 611                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 612                         dp->link_train.link_rate);
 613
 614                 analogix_dp_get_lane_count(dp, &reg);
 615                 dp->link_train.lane_count = reg;
 616                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 617                         dp->link_train.lane_count);
 618
 619                 /* set enhanced mode if available */
 620                 analogix_dp_set_enhanced_mode(dp);
 621                 dp->link_train.lt_state = FINISHED;
 622
 623                 return 0;
 624         }
 625
 626         /* not all locked */
 627         dp->link_train.eq_loop++;
 628
 629         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 630                 dev_err(dp->dev, "EQ Max loop\n");
 631                 analogix_dp_reduce_link_rate(dp);
 632                 return -EIO;
 633         }
 634
 635         for (lane = 0; lane < lane_count; lane++)
 636                 analogix_dp_set_lane_link_training(dp,
 637                         dp->link_train.training_lane[lane], lane);
 638
 639         retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 640                         lane_count, dp->link_train.training_lane);
 641
 642         return retval;
 643 }
 644
 645 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 646                                              u8 *bandwidth)
 647 {
 648         u8 data;
 649
 650         /*
 651          * For DP rev.1.1, Maximum link rate of Main Link lanes
 652          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 653          * For DP rev.1.2, Maximum link rate of Main Link lanes
 654          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 655          */
 656         analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 657         *bandwidth = data;
 658 }
 659
 660 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 661                                               u8 *lane_count)
 662 {
 663         u8 data;
 664
 665         /*
 666          * For DP rev.1.1, Maximum number of Main Link lanes
 667          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 668          */
 669         analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 670         *lane_count = DPCD_MAX_LANE_COUNT(data);
 671 }
 672
 673 static void analogix_dp_init_training(struct analogix_dp_device *dp,
 674                                       enum link_lane_count_type max_lane,
 675                                       int max_rate)
 676 {
 677         /*
 678          * MACRO_RST must be applied after the PLL_LOCK to avoid
 679          * the DP inter pair skew issue for at least 10 us
 680          */
 681         analogix_dp_reset_macro(dp);
 682
 683         /* Initialize by reading RX's DPCD */
 684         analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 685         analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 686
 687         if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
 688             (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
 689             (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 690                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 691                         dp->link_train.link_rate);
 692                 dp->link_train.link_rate = DP_LINK_BW_1_62;
 693         }
 694
 695         if (dp->link_train.lane_count == 0) {
 696                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 697                         dp->link_train.lane_count);
 698                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 699         }
 700
 701         /* Setup TX lane count & rate */
 702         if (dp->link_train.lane_count > max_lane)
 703                 dp->link_train.lane_count = max_lane;
 704         if (dp->link_train.link_rate > max_rate)
 705                 dp->link_train.link_rate = max_rate;
 706
 707         /* All DP analog module power up */
 708         analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 709 }
 710
 711 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 712 {
 713         int retval = 0, training_finished = 0;
 714
 715         dp->link_train.lt_state = START;
 716
 717         /* Process here */
 718         while (!retval && !training_finished) {
 719                 switch (dp->link_train.lt_state) {
 720                 case START:
 721                         retval = analogix_dp_link_start(dp);
 722                         if (retval)
 723                                 dev_err(dp->dev, "LT link start failed!\n");
 724                         break;
 725                 case CLOCK_RECOVERY:
 726                         retval = analogix_dp_process_clock_recovery(dp);
 727                         if (retval)
 728                                 dev_err(dp->dev, "LT CR failed!\n");
 729                         break;
 730                 case EQUALIZER_TRAINING:
 731                         retval = analogix_dp_process_equalizer_training(dp);
 732                         if (retval)
 733                                 dev_err(dp->dev, "LT EQ failed!\n");
 734                         break;
 735                 case FINISHED:
 736                         training_finished = 1;
 737                         break;
 738                 case FAILED:
 739                         return -EREMOTEIO;
 740                 }
 741         }
 742         if (retval)
 743                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 744
 745         return retval;
 746 }
 747
 748 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
 749                                       u32 count, u32 bwtype)
 750 {
 751         int i;
 752         int retval;
 753
 754         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 755                 analogix_dp_init_training(dp, count, bwtype);
 756                 retval = analogix_dp_sw_link_training(dp);
 757                 if (retval == 0)
 758                         break;
 759
 760                 usleep_range(100, 110);
 761         }
 762
 763         return retval;
 764 }
 765
 766 static int analogix_dp_config_video(struct analogix_dp_device *dp)
 767 {
 768         int retval = 0;
 769         int timeout_loop = 0;
 770         int done_count = 0;
 771
 772         analogix_dp_config_video_slave_mode(dp);
 773
 774         analogix_dp_set_video_color_format(dp);
 775
 776         if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 777                 dev_err(dp->dev, "PLL is not locked yet.\n");
 778                 return -EINVAL;
 779         }
 780
 781         for (;;) {
 782                 timeout_loop++;
 783                 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 784                         break;
 785                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 786                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 787                         return -ETIMEDOUT;
 788                 }
 789
 790                 usleep_range(1, 2);
 791         }
 792
 793         /* Set to use the register calculated M/N video */
 794         analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 795
 796         /* For video bist, Video timing must be generated by register */
 797         analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 798
 799         /* Disable video mute */
 800         analogix_dp_enable_video_mute(dp, 0);
 801
 802         /* Configure video slave mode */
 803         analogix_dp_enable_video_master(dp, 0);
 804
 805         timeout_loop = 0;
 806
 807         for (;;) {
 808                 timeout_loop++;
 809                 if (analogix_dp_is_video_stream_on(dp) == 0) {
 810                         done_count++;
 811                         if (done_count > 10)
 812                                 break;
 813                 } else if (done_count) {
 814                         done_count = 0;
 815                 }
 816                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 817                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 818                         return -ETIMEDOUT;
 819                 }
 820
 821                 usleep_range(1000, 1001);
 822         }
 823
 824         if (retval != 0)
 825                 dev_err(dp->dev, "Video stream is not detected!\n");
 826
 827         return retval;
 828 }
 829
 830 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 831                                         bool enable)
 832 {
 833         u8 data;
 834
 835         if (enable) {
 836                 analogix_dp_enable_scrambling(dp);
 837
 838                 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
 839                                                 &data);
 840                 analogix_dp_write_byte_to_dpcd(dp,
 841                         DP_TRAINING_PATTERN_SET,
 842                         (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 843         } else {
 844                 analogix_dp_disable_scrambling(dp);
 845
 846                 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
 847                                                 &data);
 848                 analogix_dp_write_byte_to_dpcd(dp,
 849                         DP_TRAINING_PATTERN_SET,
 850                         (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 851         }
 852 }
 853
 854 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 855 {
 856         struct analogix_dp_device *dp = arg;
 857         irqreturn_t ret = IRQ_NONE;
 858         enum dp_irq_type irq_type;
 859
 860         irq_type = analogix_dp_get_irq_type(dp);
 861         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 862                 analogix_dp_mute_hpd_interrupt(dp);
 863                 ret = IRQ_WAKE_THREAD;
 864         }
 865
 866         return ret;
 867 }
 868
 869 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 870 {
 871         struct analogix_dp_device *dp = arg;
 872         enum dp_irq_type irq_type;
 873
 874         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
 875                 return IRQ_HANDLED;
 876
 877         pm_runtime_get_sync(dp->dev);
 878
 879         irq_type = analogix_dp_get_irq_type(dp);
 880         if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
 881             irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
 882                 dev_dbg(dp->dev, "Detected cable status changed!\n");
 883                 if (dp->drm_dev)
 884                         drm_helper_hpd_irq_event(dp->drm_dev);
 885         }
 886
 887         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 888                 analogix_dp_clear_hotplug_interrupts(dp);
 889                 analogix_dp_unmute_hpd_interrupt(dp);
 890         }
 891
 892         pm_runtime_put(dp->dev);
 893
 894         return IRQ_HANDLED;
 895 }
 896
 897 static void analogix_dp_commit(struct analogix_dp_device *dp)
 898 {
 899         int ret;
 900
 901         /* Keep the panel disabled while we configure video */
 902         if (dp->plat_data->panel) {
 903                 if (drm_panel_disable(dp->plat_data->panel))
 904                         DRM_ERROR("failed to disable the panel\n");
 905         }
 906
 907         ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 908                                          dp->video_info.max_link_rate);
 909         if (ret) {
 910                 dev_err(dp->dev, "unable to do link train\n");
 911                 return;
 912         }
 913
 914         analogix_dp_enable_scramble(dp, 1);
 915         analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 916         analogix_dp_enable_enhanced_mode(dp, 1);
 917
 918         analogix_dp_init_video(dp);
 919         ret = analogix_dp_config_video(dp);
 920         if (ret)
 921                 dev_err(dp->dev, "unable to config video\n");
 922
 923         /* Safe to enable the panel now */
 924         if (dp->plat_data->panel) {
 925                 if (drm_panel_enable(dp->plat_data->panel))
 926                         DRM_ERROR("failed to enable the panel\n");
 927         }
 928
 929         /* Enable video */
 930         analogix_dp_start_video(dp);
 931 }
 932
 933 int analogix_dp_get_modes(struct drm_connector *connector)
 934 {
 935         struct analogix_dp_device *dp = to_dp(connector);
 936         struct edid *edid = (struct edid *)dp->edid;
 937         int num_modes = 0;
 938
 939         pm_runtime_get_sync(dp->dev);
 940
 941         if (dp->plat_data->panel) {
 942                 num_modes += drm_panel_get_modes(dp->plat_data->panel);
 943         } else if (analogix_dp_handle_edid(dp) == 0) {
 944                 drm_mode_connector_update_edid_property(&dp->connector, edid);
 945                 num_modes += drm_add_edid_modes(&dp->connector, edid);
 946         }
 947
 948         if (dp->plat_data->get_modes)
 949                 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
 950
 951         pm_runtime_put(dp->dev);
 952
 953         return num_modes;
 954 }
 955
 956 static struct drm_encoder *
 957 analogix_dp_best_encoder(struct drm_connector *connector)
 958 {
 959         struct analogix_dp_device *dp = to_dp(connector);
 960
 961         return dp->encoder;
 962 }
 963
 964 static int analogix_dp_loader_protect(struct drm_connector *connector, bool on)
 965 {
 966         struct analogix_dp_device *dp = to_dp(connector);
 967
 968         if (on)
 969                 pm_runtime_get_sync(dp->dev);
 970         else
 971                 pm_runtime_put(dp->dev);
 972
 973         return 0;
 974 }
 975
 976 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
 977         .loader_protect = analogix_dp_loader_protect,
 978         .get_modes = analogix_dp_get_modes,
 979         .best_encoder = analogix_dp_best_encoder,
 980 };
 981
 982 enum drm_connector_status
 983 analogix_dp_detect(struct drm_connector *connector, bool force)
 984 {
 985         struct analogix_dp_device *dp = to_dp(connector);
 986         enum drm_connector_status status = connector_status_connected;
 987
 988         pm_runtime_get_sync(dp->dev);
 989
 990         if (analogix_dp_detect_hpd(dp))
 991                 status = connector_status_disconnected;
 992
 993         pm_runtime_put(dp->dev);
 994
 995         return status;
 996 }
 997
 998 static void analogix_dp_connector_destroy(struct drm_connector *connector)
 999 {
1000         drm_connector_unregister(connector);
1001         drm_connector_cleanup(connector);
1002
1003 }
1004
1005 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1006         .dpms = drm_atomic_helper_connector_dpms,
1007         .fill_modes = drm_helper_probe_single_connector_modes,
1008         .detect = analogix_dp_detect,
1009         .destroy = analogix_dp_connector_destroy,
1010         .reset = drm_atomic_helper_connector_reset,
1011         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1012         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1013 };
1014
1015 static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
1016 {
1017         struct analogix_dp_device *dp = bridge->driver_private;
1018         struct drm_encoder *encoder = dp->encoder;
1019         struct drm_connector *connector = &dp->connector;
1020         int ret;
1021
1022         if (!bridge->encoder) {
1023                 DRM_ERROR("Parent encoder object not found");
1024                 return -ENODEV;
1025         }
1026
1027         connector->polled = DRM_CONNECTOR_POLL_HPD;
1028         connector->port = dp->dev->of_node;
1029
1030         ret = drm_connector_init(dp->drm_dev, connector,
1031                                  &analogix_dp_connector_funcs,
1032                                  DRM_MODE_CONNECTOR_eDP);
1033         if (ret) {
1034                 DRM_ERROR("Failed to initialize connector with drm\n");
1035                 return ret;
1036         }
1037
1038         drm_connector_helper_add(connector,
1039                                  &analogix_dp_connector_helper_funcs);
1040         drm_mode_connector_attach_encoder(connector, encoder);
1041
1042         /*
1043          * NOTE: the connector registration is implemented in analogix
1044          * platform driver, that to say connector would be exist after
1045          * plat_data->attch return, that's why we record the connector
1046          * point after plat attached.
1047          */
1048          if (dp->plat_data->attach) {
1049                  ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1050                  if (ret) {
1051                          DRM_ERROR("Failed at platform attch func\n");
1052                          return ret;
1053                  }
1054         }
1055
1056         if (dp->plat_data->panel) {
1057                 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1058                 if (ret) {
1059                         DRM_ERROR("Failed to attach panel\n");
1060                         return ret;
1061                 }
1062         }
1063
1064         return 0;
1065 }
1066
1067 static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
1068 {
1069         struct analogix_dp_device *dp = bridge->driver_private;
1070
1071         if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1072                 return;
1073
1074         pm_runtime_get_sync(dp->dev);
1075
1076         if (dp->plat_data->power_on)
1077                 dp->plat_data->power_on(dp->plat_data);
1078
1079         phy_power_on(dp->phy);
1080         analogix_dp_init_dp(dp);
1081         enable_irq(dp->irq);
1082         analogix_dp_commit(dp);
1083
1084         dp->dpms_mode = DRM_MODE_DPMS_ON;
1085 }
1086
1087 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1088 {
1089         struct analogix_dp_device *dp = bridge->driver_private;
1090
1091         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1092                 return;
1093
1094         if (dp->plat_data->panel) {
1095                 if (drm_panel_disable(dp->plat_data->panel)) {
1096                         DRM_ERROR("failed to disable the panel\n");
1097                         return;
1098                 }
1099         }
1100
1101         disable_irq_nosync(dp->irq);
1102         phy_power_off(dp->phy);
1103
1104         if (dp->plat_data->power_off)
1105                 dp->plat_data->power_off(dp->plat_data);
1106
1107         pm_runtime_put_sync(dp->dev);
1108
1109         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1110 }
1111
1112 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1113                                         struct drm_display_mode *orig_mode,
1114                                         struct drm_display_mode *mode)
1115 {
1116         struct analogix_dp_device *dp = bridge->driver_private;
1117         struct drm_display_info *display_info = &dp->connector.display_info;
1118         struct video_info *video = &dp->video_info;
1119         struct device_node *dp_node = dp->dev->of_node;
1120         int vic;
1121
1122         /* Input video interlaces & hsync pol & vsync pol */
1123         video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1124         video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1125         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1126
1127         /* Input video dynamic_range & colorimetry */
1128         vic = drm_match_cea_mode(mode);
1129         if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1130             (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1131                 video->dynamic_range = CEA;
1132                 video->ycbcr_coeff = COLOR_YCBCR601;
1133         } else if (vic) {
1134                 video->dynamic_range = CEA;
1135                 video->ycbcr_coeff = COLOR_YCBCR709;
1136         } else {
1137                 video->dynamic_range = VESA;
1138                 video->ycbcr_coeff = COLOR_YCBCR709;
1139         }
1140
1141         /* Input vide bpc and color_formats */
1142         switch (display_info->bpc) {
1143         case 12:
1144                 video->color_depth = COLOR_12;
1145                 break;
1146         case 10:
1147                 video->color_depth = COLOR_10;
1148                 break;
1149         case 8:
1150                 video->color_depth = COLOR_8;
1151                 break;
1152         case 6:
1153                 video->color_depth = COLOR_6;
1154                 break;
1155         default:
1156                 video->color_depth = COLOR_8;
1157                 break;
1158         }
1159         if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1160                 video->color_space = COLOR_YCBCR444;
1161         else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1162                 video->color_space = COLOR_YCBCR422;
1163         else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
1164                 video->color_space = COLOR_RGB;
1165         else
1166                 video->color_space = COLOR_RGB;
1167
1168         /*
1169          * NOTE: those property parsing code is used for providing backward
1170          * compatibility for samsung platform.
1171          * Due to we used the "of_property_read_u32" interfaces, when this
1172          * property isn't present, the "video_info" can keep the original
1173          * values and wouldn't be modified.
1174          */
1175         of_property_read_u32(dp_node, "samsung,color-space",
1176                              &video->color_space);
1177         of_property_read_u32(dp_node, "samsung,dynamic-range",
1178                              &video->dynamic_range);
1179         of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1180                              &video->ycbcr_coeff);
1181         of_property_read_u32(dp_node, "samsung,color-depth",
1182                              &video->color_depth);
1183         if (of_property_read_bool(dp_node, "hsync-active-high"))
1184                 video->h_sync_polarity = true;
1185         if (of_property_read_bool(dp_node, "vsync-active-high"))
1186                 video->v_sync_polarity = true;
1187         if (of_property_read_bool(dp_node, "interlaced"))
1188                 video->interlaced = true;
1189 }
1190
1191 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
1192 {
1193         /* do nothing */
1194 }
1195
1196 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1197         .enable = analogix_dp_bridge_enable,
1198         .disable = analogix_dp_bridge_disable,
1199         .pre_enable = analogix_dp_bridge_nop,
1200         .post_disable = analogix_dp_bridge_nop,
1201         .mode_set = analogix_dp_bridge_mode_set,
1202         .attach = analogix_dp_bridge_attach,
1203 };
1204
1205 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1206                                      struct analogix_dp_device *dp)
1207 {
1208         struct drm_bridge *bridge;
1209         int ret;
1210
1211         bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1212         if (!bridge) {
1213                 DRM_ERROR("failed to allocate for drm bridge\n");
1214                 return -ENOMEM;
1215         }
1216
1217         dp->bridge = bridge;
1218
1219         dp->encoder->bridge = bridge;
1220         bridge->driver_private = dp;
1221         bridge->encoder = dp->encoder;
1222         bridge->funcs = &analogix_dp_bridge_funcs;
1223
1224         ret = drm_bridge_attach(drm_dev, bridge);
1225         if (ret) {
1226                 DRM_ERROR("failed to attach drm bridge\n");
1227                 return -EINVAL;
1228         }
1229
1230         return 0;
1231 }
1232
1233 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1234 {
1235         struct device_node *dp_node = dp->dev->of_node;
1236         struct video_info *video_info = &dp->video_info;
1237
1238         switch (dp->plat_data->dev_type) {
1239         case ROCKCHIP_DP:
1240                 /*
1241                  * Like Rockchip DisplayPort TRM indicate that "Main link
1242                  * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1243                  */
1244                 video_info->max_link_rate = 0x0A;
1245                 video_info->max_lane_count = 0x04;
1246                 break;
1247         case EXYNOS_DP:
1248                 /*
1249                  * NOTE: those property parseing code is used for
1250                  * providing backward compatibility for samsung platform.
1251                  */
1252                 of_property_read_u32(dp_node, "samsung,link-rate",
1253                                      &video_info->max_link_rate);
1254                 of_property_read_u32(dp_node, "samsung,lane-count",
1255                                      &video_info->max_lane_count);
1256                 break;
1257         }
1258
1259         return 0;
1260 }
1261
1262 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1263                      struct analogix_dp_plat_data *plat_data)
1264 {
1265         struct platform_device *pdev = to_platform_device(dev);
1266         struct analogix_dp_device *dp;
1267         struct resource *res;
1268         unsigned int irq_flags;
1269         int ret;
1270
1271         if (!plat_data) {
1272                 dev_err(dev, "Invalided input plat_data\n");
1273                 return -EINVAL;
1274         }
1275
1276         dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1277         if (!dp)
1278                 return -ENOMEM;
1279
1280         dev_set_drvdata(dev, dp);
1281
1282         dp->dev = &pdev->dev;
1283         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1284
1285         /*
1286          * platform dp driver need containor_of the plat_data to get
1287          * the driver private data, so we need to store the point of
1288          * plat_data, not the context of plat_data.
1289          */
1290         dp->plat_data = plat_data;
1291
1292         ret = analogix_dp_dt_parse_pdata(dp);
1293         if (ret)
1294                 return ret;
1295
1296         dp->phy = devm_phy_get(dp->dev, "dp");
1297         if (IS_ERR(dp->phy)) {
1298                 dev_err(dp->dev, "no DP phy configured\n");
1299                 ret = PTR_ERR(dp->phy);
1300                 if (ret) {
1301                         /*
1302                          * phy itself is not enabled, so we can move forward
1303                          * assigning NULL to phy pointer.
1304                          */
1305                         if (ret == -ENOSYS || ret == -ENODEV)
1306                                 dp->phy = NULL;
1307                         else
1308                                 return ret;
1309                 }
1310         }
1311
1312         dp->clock = devm_clk_get(&pdev->dev, "dp");
1313         if (IS_ERR(dp->clock)) {
1314                 dev_err(&pdev->dev, "failed to get clock\n");
1315                 return PTR_ERR(dp->clock);
1316         }
1317
1318         clk_prepare_enable(dp->clock);
1319
1320         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1321
1322         dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1323         if (IS_ERR(dp->reg_base))
1324                 return PTR_ERR(dp->reg_base);
1325
1326         dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1327
1328         dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
1329         if (!gpio_is_valid(dp->hpd_gpio))
1330                 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
1331                                                  "samsung,hpd-gpio", 0);
1332
1333         if (gpio_is_valid(dp->hpd_gpio)) {
1334                 /*
1335                  * Set up the hotplug GPIO from the device tree as an interrupt.
1336                  * Simply specifying a different interrupt in the device tree
1337                  * doesn't work since we handle hotplug rather differently when
1338                  * using a GPIO.  We also need the actual GPIO specifier so
1339                  * that we can get the current state of the GPIO.
1340                  */
1341                 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1342                                             "hpd_gpio");
1343                 if (ret) {
1344                         dev_err(&pdev->dev, "failed to get hpd gpio\n");
1345                         return ret;
1346                 }
1347                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1348                 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1349         } else {
1350                 dp->hpd_gpio = -ENODEV;
1351                 dp->irq = platform_get_irq(pdev, 0);
1352                 irq_flags = 0;
1353         }
1354
1355         if (dp->irq == -ENXIO) {
1356                 dev_err(&pdev->dev, "failed to get irq\n");
1357                 return -ENODEV;
1358         }
1359
1360         pm_runtime_enable(dev);
1361
1362         phy_power_on(dp->phy);
1363
1364         if (dp->plat_data->panel) {
1365                 if (drm_panel_prepare(dp->plat_data->panel)) {
1366                         DRM_ERROR("failed to setup the panel\n");
1367                         return -EBUSY;
1368                 }
1369         }
1370
1371         ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1372                                         analogix_dp_hardirq,
1373                                         analogix_dp_irq_thread,
1374                                         irq_flags, "analogix-dp", dp);
1375         if (ret) {
1376                 dev_err(&pdev->dev, "failed to request irq\n");
1377                 goto err_disable_pm_runtime;
1378         }
1379         disable_irq(dp->irq);
1380
1381         dp->drm_dev = drm_dev;
1382         dp->encoder = dp->plat_data->encoder;
1383
1384         ret = analogix_dp_create_bridge(drm_dev, dp);
1385         if (ret) {
1386                 DRM_ERROR("failed to create bridge (%d)\n", ret);
1387                 drm_encoder_cleanup(dp->encoder);
1388                 goto err_disable_pm_runtime;
1389         }
1390
1391         return 0;
1392
1393 err_disable_pm_runtime:
1394         pm_runtime_disable(dev);
1395
1396         return ret;
1397 }
1398 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1399
1400 void analogix_dp_unbind(struct device *dev, struct device *master,
1401                         void *data)
1402 {
1403         struct analogix_dp_device *dp = dev_get_drvdata(dev);
1404
1405         analogix_dp_bridge_disable(dp->bridge);
1406
1407         if (dp->plat_data->panel) {
1408                 if (drm_panel_unprepare(dp->plat_data->panel))
1409                         DRM_ERROR("failed to turnoff the panel\n");
1410         }
1411
1412         pm_runtime_disable(dev);
1413 }
1414 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1415
1416 #ifdef CONFIG_PM
1417 int analogix_dp_suspend(struct device *dev)
1418 {
1419         struct analogix_dp_device *dp = dev_get_drvdata(dev);
1420
1421         clk_disable_unprepare(dp->clock);
1422
1423         if (dp->plat_data->panel) {
1424                 if (drm_panel_unprepare(dp->plat_data->panel))
1425                         DRM_ERROR("failed to turnoff the panel\n");
1426         }
1427
1428         return 0;
1429 }
1430 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1431
1432 int analogix_dp_resume(struct device *dev)
1433 {
1434         struct analogix_dp_device *dp = dev_get_drvdata(dev);
1435         int ret;
1436
1437         ret = clk_prepare_enable(dp->clock);
1438         if (ret < 0) {
1439                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1440                 return ret;
1441         }
1442
1443         if (dp->plat_data->panel) {
1444                 if (drm_panel_prepare(dp->plat_data->panel)) {
1445                         DRM_ERROR("failed to setup the panel\n");
1446                         return -EBUSY;
1447                 }
1448         }
1449
1450         return 0;
1451 }
1452 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1453 #endif
1454
1455 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1456 MODULE_DESCRIPTION("Analogix DP Core Driver");
1457 MODULE_LICENSE("GPL v2");