drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  42
  43 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  44 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  45
  46 /**
  47  * gmc8_mc_wait_for_idle - wait for MC idle callback.
  48  *
  49  * @adev: amdgpu_device pointer
  50  *
  51  * Wait for the MC (memory controller) to be idle.
  52  * (evergreen+).
  53  * Returns 0 if the MC is idle, -1 if not.
  54  */
  55 int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev)
  56 {
  57         unsigned i;
  58         u32 tmp;
  59
  60         for (i = 0; i < adev->usec_timeout; i++) {
  61                 /* read MC_STATUS */
  62                 tmp = RREG32(mmSRBM_STATUS) & 0x1F00;
  63                 if (!tmp)
  64                         return 0;
  65                 udelay(1);
  66         }
  67         return -1;
  68 }
  69
  70 void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
  71                       struct amdgpu_mode_mc_save *save)
  72 {
  73         u32 blackout;
  74
  75         if (adev->mode_info.num_crtc)
  76                 amdgpu_display_stop_mc_access(adev, save);
  77
  78         amdgpu_asic_wait_for_mc_idle(adev);
  79
  80         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  81         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  82                 /* Block CPU access */
  83                 WREG32(mmBIF_FB_EN, 0);
  84                 /* blackout the MC */
  85                 blackout = REG_SET_FIELD(blackout,
  86                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  87                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  88         }
  89         /* wait for the MC to settle */
  90         udelay(100);
  91 }
  92
  93 void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
  94                         struct amdgpu_mode_mc_save *save)
  95 {
  96         u32 tmp;
  97
  98         /* unblackout the MC */
  99         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 100         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 101         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 102         /* allow CPU access */
 103         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 104         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 105         WREG32(mmBIF_FB_EN, tmp);
 106
 107         if (adev->mode_info.num_crtc)
 108                 amdgpu_display_resume_mc_access(adev, save);
 109 }
 110
 111 /**
 112  * gmc_v7_0_init_microcode - load ucode images from disk
 113  *
 114  * @adev: amdgpu_device pointer
 115  *
 116  * Use the firmware interface to load the ucode images into
 117  * the driver (not loaded into hw).
 118  * Returns 0 on success, error on failure.
 119  */
 120 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 121 {
 122         const char *chip_name;
 123         char fw_name[30];
 124         int err;
 125
 126         DRM_DEBUG("\n");
 127
 128         switch (adev->asic_type) {
 129         case CHIP_BONAIRE:
 130                 chip_name = "bonaire";
 131                 break;
 132         case CHIP_HAWAII:
 133                 chip_name = "hawaii";
 134                 break;
 135         case CHIP_KAVERI:
 136         case CHIP_KABINI:
 137                 return 0;
 138         default: BUG();
 139         }
 140
 141         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 142         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 143         if (err)
 144                 goto out;
 145         err = amdgpu_ucode_validate(adev->mc.fw);
 146
 147 out:
 148         if (err) {
 149                 printk(KERN_ERR
 150                        "cik_mc: Failed to load firmware \"%s\"\n",
 151                        fw_name);
 152                 release_firmware(adev->mc.fw);
 153                 adev->mc.fw = NULL;
 154         }
 155         return err;
 156 }
 157
 158 /**
 159  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 160  *
 161  * @adev: amdgpu_device pointer
 162  *
 163  * Load the GDDR MC ucode into the hw (CIK).
 164  * Returns 0 on success, error on failure.
 165  */
 166 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 167 {
 168         const struct mc_firmware_header_v1_0 *hdr;
 169         const __le32 *fw_data = NULL;
 170         const __le32 *io_mc_regs = NULL;
 171         u32 running, blackout = 0;
 172         int i, ucode_size, regs_size;
 173
 174         if (!adev->mc.fw)
 175                 return -EINVAL;
 176
 177         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 178         amdgpu_ucode_print_mc_hdr(&hdr->header);
 179
 180         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 181         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 182         io_mc_regs = (const __le32 *)
 183                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 184         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 185         fw_data = (const __le32 *)
 186                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 187
 188         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 189
 190         if (running == 0) {
 191                 if (running) {
 192                         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 193                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 194                 }
 195
 196                 /* reset the engine and set to writable */
 197                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 198                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 199
 200                 /* load mc io regs */
 201                 for (i = 0; i < regs_size; i++) {
 202                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 203                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 204                 }
 205                 /* load the MC ucode */
 206                 for (i = 0; i < ucode_size; i++)
 207                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 208
 209                 /* put the engine back into the active state */
 210                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 211                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 212                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 213
 214                 /* wait for training to complete */
 215                 for (i = 0; i < adev->usec_timeout; i++) {
 216                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 217                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 218                                 break;
 219                         udelay(1);
 220                 }
 221                 for (i = 0; i < adev->usec_timeout; i++) {
 222                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 223                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 224                                 break;
 225                         udelay(1);
 226                 }
 227
 228                 if (running)
 229                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 230         }
 231
 232         return 0;
 233 }
 234
 235 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 236                                        struct amdgpu_mc *mc)
 237 {
 238         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 239                 /* leave room for at least 1024M GTT */
 240                 dev_warn(adev->dev, "limiting VRAM\n");
 241                 mc->real_vram_size = 0xFFC0000000ULL;
 242                 mc->mc_vram_size = 0xFFC0000000ULL;
 243         }
 244         amdgpu_vram_location(adev, &adev->mc, 0);
 245         adev->mc.gtt_base_align = 0;
 246         amdgpu_gtt_location(adev, mc);
 247 }
 248
 249 /**
 250  * gmc_v7_0_mc_program - program the GPU memory controller
 251  *
 252  * @adev: amdgpu_device pointer
 253  *
 254  * Set the location of vram, gart, and AGP in the GPU's
 255  * physical address space (CIK).
 256  */
 257 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 258 {
 259         struct amdgpu_mode_mc_save save;
 260         u32 tmp;
 261         int i, j;
 262
 263         /* Initialize HDP */
 264         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 265                 WREG32((0xb05 + j), 0x00000000);
 266                 WREG32((0xb06 + j), 0x00000000);
 267                 WREG32((0xb07 + j), 0x00000000);
 268                 WREG32((0xb08 + j), 0x00000000);
 269                 WREG32((0xb09 + j), 0x00000000);
 270         }
 271         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 272
 273         if (adev->mode_info.num_crtc)
 274                 amdgpu_display_set_vga_render_state(adev, false);
 275
 276         gmc_v7_0_mc_stop(adev, &save);
 277         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 278                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 279         }
 280         /* Update configuration */
 281         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 282                adev->mc.vram_start >> 12);
 283         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 284                adev->mc.vram_end >> 12);
 285         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 286                adev->vram_scratch.gpu_addr >> 12);
 287         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 288         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 289         WREG32(mmMC_VM_FB_LOCATION, tmp);
 290         /* XXX double check these! */
 291         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 292         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 293         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 294         WREG32(mmMC_VM_AGP_BASE, 0);
 295         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 296         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 297         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 298                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 299         }
 300         gmc_v7_0_mc_resume(adev, &save);
 301
 302         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 303
 304         tmp = RREG32(mmHDP_MISC_CNTL);
 305         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 306         WREG32(mmHDP_MISC_CNTL, tmp);
 307
 308         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 309         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 310 }
 311
 312 /**
 313  * gmc_v7_0_mc_init - initialize the memory controller driver params
 314  *
 315  * @adev: amdgpu_device pointer
 316  *
 317  * Look up the amount of vram, vram width, and decide how to place
 318  * vram and gart within the GPU's physical address space (CIK).
 319  * Returns 0 for success.
 320  */
 321 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 322 {
 323         u32 tmp;
 324         int chansize, numchan;
 325
 326         /* Get VRAM informations */
 327         tmp = RREG32(mmMC_ARB_RAMCFG);
 328         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 329                 chansize = 64;
 330         } else {
 331                 chansize = 32;
 332         }
 333         tmp = RREG32(mmMC_SHARED_CHMAP);
 334         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 335         case 0:
 336         default:
 337                 numchan = 1;
 338                 break;
 339         case 1:
 340                 numchan = 2;
 341                 break;
 342         case 2:
 343                 numchan = 4;
 344                 break;
 345         case 3:
 346                 numchan = 8;
 347                 break;
 348         case 4:
 349                 numchan = 3;
 350                 break;
 351         case 5:
 352                 numchan = 6;
 353                 break;
 354         case 6:
 355                 numchan = 10;
 356                 break;
 357         case 7:
 358                 numchan = 12;
 359                 break;
 360         case 8:
 361                 numchan = 16;
 362                 break;
 363         }
 364         adev->mc.vram_width = numchan * chansize;
 365         /* Could aper size report 0 ? */
 366         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 367         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 368         /* size in MB on si */
 369         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 370         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 371         adev->mc.visible_vram_size = adev->mc.aper_size;
 372
 373         /* unless the user had overridden it, set the gart
 374          * size equal to the 1024 or vram, whichever is larger.
 375          */
 376         if (amdgpu_gart_size == -1)
 377                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 378         else
 379                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 380
 381         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 382
 383         return 0;
 384 }
 385
 386 /*
 387  * GART
 388  * VMID 0 is the physical GPU addresses as used by the kernel.
 389  * VMIDs 1-15 are used for userspace clients and are handled
 390  * by the amdgpu vm/hsa code.
 391  */
 392
 393 /**
 394  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 395  *
 396  * @adev: amdgpu_device pointer
 397  * @vmid: vm instance to flush
 398  *
 399  * Flush the TLB for the requested page table (CIK).
 400  */
 401 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 402                                         uint32_t vmid)
 403 {
 404         /* flush hdp cache */
 405         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 406
 407         /* bits 0-15 are the VM contexts0-15 */
 408         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 409 }
 410
 411 /**
 412  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 413  *
 414  * @adev: amdgpu_device pointer
 415  * @cpu_pt_addr: cpu address of the page table
 416  * @gpu_page_idx: entry in the page table to update
 417  * @addr: dst addr to write into pte/pde
 418  * @flags: access flags
 419  *
 420  * Update the page tables using the CPU.
 421  */
 422 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 423                                      void *cpu_pt_addr,
 424                                      uint32_t gpu_page_idx,
 425                                      uint64_t addr,
 426                                      uint32_t flags)
 427 {
 428         void __iomem *ptr = (void *)cpu_pt_addr;
 429         uint64_t value;
 430
 431         value = addr & 0xFFFFFFFFFFFFF000ULL;
 432         value |= flags;
 433         writeq(value, ptr + (gpu_page_idx * 8));
 434
 435         return 0;
 436 }
 437
 438 /**
 439  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 440  *
 441  * @adev: amdgpu_device pointer
 442  * @value: true redirects VM faults to the default page
 443  */
 444 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 445                                               bool value)
 446 {
 447         u32 tmp;
 448
 449         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 450         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 451                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 452         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 453                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 454         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 455                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 456         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 457                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 458         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 459                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 460         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 461                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 462         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 463 }
 464
 465 /**
 466  * gmc_v7_0_gart_enable - gart enable
 467  *
 468  * @adev: amdgpu_device pointer
 469  *
 470  * This sets up the TLBs, programs the page tables for VMID0,
 471  * sets up the hw for VMIDs 1-15 which are allocated on
 472  * demand, and sets up the global locations for the LDS, GDS,
 473  * and GPUVM for FSA64 clients (CIK).
 474  * Returns 0 for success, errors for failure.
 475  */
 476 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 477 {
 478         int r, i;
 479         u32 tmp;
 480
 481         if (adev->gart.robj == NULL) {
 482                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 483                 return -EINVAL;
 484         }
 485         r = amdgpu_gart_table_vram_pin(adev);
 486         if (r)
 487                 return r;
 488         /* Setup TLB control */
 489         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 490         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 491         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 492         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 493         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 494         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 495         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 496         /* Setup L2 cache */
 497         tmp = RREG32(mmVM_L2_CNTL);
 498         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 499         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 500         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 501         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 502         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 503         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 504         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 505         WREG32(mmVM_L2_CNTL, tmp);
 506         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 507         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 508         WREG32(mmVM_L2_CNTL2, tmp);
 509         tmp = RREG32(mmVM_L2_CNTL3);
 510         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 511         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 512         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 513         WREG32(mmVM_L2_CNTL3, tmp);
 514         /* setup context0 */
 515         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 516         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1);
 517         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 518         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 519                         (u32)(adev->dummy_page.addr >> 12));
 520         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 521         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 522         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 523         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 524         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 525         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 526
 527         WREG32(0x575, 0);
 528         WREG32(0x576, 0);
 529         WREG32(0x577, 0);
 530
 531         /* empty context1-15 */
 532         /* FIXME start with 4G, once using 2 level pt switch to full
 533          * vm size space
 534          */
 535         /* set vm size, must be a multiple of 4 */
 536         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 537         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 538         for (i = 1; i < 16; i++) {
 539                 if (i < 8)
 540                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 541                                adev->gart.table_addr >> 12);
 542                 else
 543                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 544                                adev->gart.table_addr >> 12);
 545         }
 546
 547         /* enable context1-15 */
 548         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 549                (u32)(adev->dummy_page.addr >> 12));
 550         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 551         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 552         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 553         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 554         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 555                             amdgpu_vm_block_size - 9);
 556         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 557         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 558                 gmc_v7_0_set_fault_enable_default(adev, false);
 559         else
 560                 gmc_v7_0_set_fault_enable_default(adev, true);
 561
 562         if (adev->asic_type == CHIP_KAVERI) {
 563                 tmp = RREG32(mmCHUB_CONTROL);
 564                 tmp &= ~BYPASS_VM;
 565                 WREG32(mmCHUB_CONTROL, tmp);
 566         }
 567
 568         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 569         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 570                  (unsigned)(adev->mc.gtt_size >> 20),
 571                  (unsigned long long)adev->gart.table_addr);
 572         adev->gart.ready = true;
 573         return 0;
 574 }
 575
 576 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 577 {
 578         int r;
 579
 580         if (adev->gart.robj) {
 581                 WARN(1, "R600 PCIE GART already initialized\n");
 582                 return 0;
 583         }
 584         /* Initialize common gart structure */
 585         r = amdgpu_gart_init(adev);
 586         if (r)
 587                 return r;
 588         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 589         return amdgpu_gart_table_vram_alloc(adev);
 590 }
 591
 592 /**
 593  * gmc_v7_0_gart_disable - gart disable
 594  *
 595  * @adev: amdgpu_device pointer
 596  *
 597  * This disables all VM page table (CIK).
 598  */
 599 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 600 {
 601         u32 tmp;
 602
 603         /* Disable all tables */
 604         WREG32(mmVM_CONTEXT0_CNTL, 0);
 605         WREG32(mmVM_CONTEXT1_CNTL, 0);
 606         /* Setup TLB control */
 607         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 608         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 609         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 610         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 611         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 612         /* Setup L2 cache */
 613         tmp = RREG32(mmVM_L2_CNTL);
 614         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 615         WREG32(mmVM_L2_CNTL, tmp);
 616         WREG32(mmVM_L2_CNTL2, 0);
 617         amdgpu_gart_table_vram_unpin(adev);
 618 }
 619
 620 /**
 621  * gmc_v7_0_gart_fini - vm fini callback
 622  *
 623  * @adev: amdgpu_device pointer
 624  *
 625  * Tears down the driver GART/VM setup (CIK).
 626  */
 627 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 628 {
 629         amdgpu_gart_table_vram_free(adev);
 630         amdgpu_gart_fini(adev);
 631 }
 632
 633 /*
 634  * vm
 635  * VMID 0 is the physical GPU addresses as used by the kernel.
 636  * VMIDs 1-15 are used for userspace clients and are handled
 637  * by the amdgpu vm/hsa code.
 638  */
 639 /**
 640  * gmc_v7_0_vm_init - cik vm init callback
 641  *
 642  * @adev: amdgpu_device pointer
 643  *
 644  * Inits cik specific vm parameters (number of VMs, base of vram for
 645  * VMIDs 1-15) (CIK).
 646  * Returns 0 for success.
 647  */
 648 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 649 {
 650         /*
 651          * number of VMs
 652          * VMID 0 is reserved for System
 653          * amdgpu graphics/compute will use VMIDs 1-7
 654          * amdkfd will use VMIDs 8-15
 655          */
 656         adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
 657
 658         /* base offset of vram pages */
 659         if (adev->flags & AMD_IS_APU) {
 660                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 661                 tmp <<= 22;
 662                 adev->vm_manager.vram_base_offset = tmp;
 663         } else
 664                 adev->vm_manager.vram_base_offset = 0;
 665
 666         return 0;
 667 }
 668
 669 /**
 670  * gmc_v7_0_vm_fini - cik vm fini callback
 671  *
 672  * @adev: amdgpu_device pointer
 673  *
 674  * Tear down any asic specific VM setup (CIK).
 675  */
 676 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
 677 {
 678 }
 679
 680 /**
 681  * gmc_v7_0_vm_decode_fault - print human readable fault info
 682  *
 683  * @adev: amdgpu_device pointer
 684  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 685  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 686  *
 687  * Print human readable fault information (CIK).
 688  */
 689 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 690                                      u32 status, u32 addr, u32 mc_client)
 691 {
 692         u32 mc_id;
 693         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 694         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 695                                         PROTECTIONS);
 696         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 697                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 698
 699         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 700                               MEMORY_CLIENT_ID);
 701
 702         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 703                protections, vmid, addr,
 704                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 705                              MEMORY_CLIENT_RW) ?
 706                "write" : "read", block, mc_client, mc_id);
 707 }
 708
 709
 710 static const u32 mc_cg_registers[] = {
 711         mmMC_HUB_MISC_HUB_CG,
 712         mmMC_HUB_MISC_SIP_CG,
 713         mmMC_HUB_MISC_VM_CG,
 714         mmMC_XPB_CLK_GAT,
 715         mmATC_MISC_CG,
 716         mmMC_CITF_MISC_WR_CG,
 717         mmMC_CITF_MISC_RD_CG,
 718         mmMC_CITF_MISC_VM_CG,
 719         mmVM_L2_CG,
 720 };
 721
 722 static const u32 mc_cg_ls_en[] = {
 723         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 724         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 725         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 726         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 727         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 728         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 729         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 730         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 731         VM_L2_CG__MEM_LS_ENABLE_MASK,
 732 };
 733
 734 static const u32 mc_cg_en[] = {
 735         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 736         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 737         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 738         MC_XPB_CLK_GAT__ENABLE_MASK,
 739         ATC_MISC_CG__ENABLE_MASK,
 740         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 741         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 742         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 743         VM_L2_CG__ENABLE_MASK,
 744 };
 745
 746 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 747                                   bool enable)
 748 {
 749         int i;
 750         u32 orig, data;
 751
 752         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 753                 orig = data = RREG32(mc_cg_registers[i]);
 754                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 755                         data |= mc_cg_ls_en[i];
 756                 else
 757                         data &= ~mc_cg_ls_en[i];
 758                 if (data != orig)
 759                         WREG32(mc_cg_registers[i], data);
 760         }
 761 }
 762
 763 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 764                                     bool enable)
 765 {
 766         int i;
 767         u32 orig, data;
 768
 769         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 770                 orig = data = RREG32(mc_cg_registers[i]);
 771                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 772                         data |= mc_cg_en[i];
 773                 else
 774                         data &= ~mc_cg_en[i];
 775                 if (data != orig)
 776                         WREG32(mc_cg_registers[i], data);
 777         }
 778 }
 779
 780 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 781                                      bool enable)
 782 {
 783         u32 orig, data;
 784
 785         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 786
 787         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 788                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 789                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 790                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 791                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 792         } else {
 793                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 794                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 795                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 796                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 797         }
 798
 799         if (orig != data)
 800                 WREG32_PCIE(ixPCIE_CNTL2, data);
 801 }
 802
 803 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 804                                      bool enable)
 805 {
 806         u32 orig, data;
 807
 808         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 809
 810         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 811                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 812         else
 813                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 814
 815         if (orig != data)
 816                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 817 }
 818
 819 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 820                                    bool enable)
 821 {
 822         u32 orig, data;
 823
 824         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 825
 826         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 827                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 828         else
 829                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 830
 831         if (orig != data)
 832                 WREG32(mmHDP_MEM_POWER_LS, data);
 833 }
 834
 835 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 836 {
 837         switch (mc_seq_vram_type) {
 838         case MC_SEQ_MISC0__MT__GDDR1:
 839                 return AMDGPU_VRAM_TYPE_GDDR1;
 840         case MC_SEQ_MISC0__MT__DDR2:
 841                 return AMDGPU_VRAM_TYPE_DDR2;
 842         case MC_SEQ_MISC0__MT__GDDR3:
 843                 return AMDGPU_VRAM_TYPE_GDDR3;
 844         case MC_SEQ_MISC0__MT__GDDR4:
 845                 return AMDGPU_VRAM_TYPE_GDDR4;
 846         case MC_SEQ_MISC0__MT__GDDR5:
 847                 return AMDGPU_VRAM_TYPE_GDDR5;
 848         case MC_SEQ_MISC0__MT__HBM:
 849                 return AMDGPU_VRAM_TYPE_HBM;
 850         case MC_SEQ_MISC0__MT__DDR3:
 851                 return AMDGPU_VRAM_TYPE_DDR3;
 852         default:
 853                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 854         }
 855 }
 856
 857 static int gmc_v7_0_early_init(void *handle)
 858 {
 859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 860
 861         gmc_v7_0_set_gart_funcs(adev);
 862         gmc_v7_0_set_irq_funcs(adev);
 863
 864         if (adev->flags & AMD_IS_APU) {
 865                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 866         } else {
 867                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 868                 tmp &= MC_SEQ_MISC0__MT__MASK;
 869                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 870         }
 871
 872         return 0;
 873 }
 874
 875 static int gmc_v7_0_late_init(void *handle)
 876 {
 877         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 878
 879         return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 880 }
 881
 882 static int gmc_v7_0_sw_init(void *handle)
 883 {
 884         int r;
 885         int dma_bits;
 886         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 887
 888         r = amdgpu_gem_init(adev);
 889         if (r)
 890                 return r;
 891
 892         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 893         if (r)
 894                 return r;
 895
 896         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 897         if (r)
 898                 return r;
 899
 900         /* Adjust VM size here.
 901          * Currently set to 4GB ((1 << 20) 4k pages).
 902          * Max GPUVM size for cayman and SI is 40 bits.
 903          */
 904         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 905
 906         /* Set the internal MC address mask
 907          * This is the max address of the GPU's
 908          * internal address space.
 909          */
 910         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 911
 912         /* set DMA mask + need_dma32 flags.
 913          * PCIE - can handle 40-bits.
 914          * IGP - can handle 40-bits
 915          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 916          */
 917         adev->need_dma32 = false;
 918         dma_bits = adev->need_dma32 ? 32 : 40;
 919         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 920         if (r) {
 921                 adev->need_dma32 = true;
 922                 dma_bits = 32;
 923                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 924         }
 925         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 926         if (r) {
 927                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 928                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 929         }
 930
 931         r = gmc_v7_0_init_microcode(adev);
 932         if (r) {
 933                 DRM_ERROR("Failed to load mc firmware!\n");
 934                 return r;
 935         }
 936
 937         r = gmc_v7_0_mc_init(adev);
 938         if (r)
 939                 return r;
 940
 941         /* Memory manager */
 942         r = amdgpu_bo_init(adev);
 943         if (r)
 944                 return r;
 945
 946         r = gmc_v7_0_gart_init(adev);
 947         if (r)
 948                 return r;
 949
 950         if (!adev->vm_manager.enabled) {
 951                 r = gmc_v7_0_vm_init(adev);
 952                 if (r) {
 953                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 954                         return r;
 955                 }
 956                 adev->vm_manager.enabled = true;
 957         }
 958
 959         return r;
 960 }
 961
 962 static int gmc_v7_0_sw_fini(void *handle)
 963 {
 964         int i;
 965         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 966
 967         if (adev->vm_manager.enabled) {
 968                 for (i = 0; i < AMDGPU_NUM_VM; ++i)
 969                         fence_put(adev->vm_manager.active[i]);
 970                 gmc_v7_0_vm_fini(adev);
 971                 adev->vm_manager.enabled = false;
 972         }
 973         gmc_v7_0_gart_fini(adev);
 974         amdgpu_gem_fini(adev);
 975         amdgpu_bo_fini(adev);
 976
 977         return 0;
 978 }
 979
 980 static int gmc_v7_0_hw_init(void *handle)
 981 {
 982         int r;
 983         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 984
 985         gmc_v7_0_mc_program(adev);
 986
 987         if (!(adev->flags & AMD_IS_APU)) {
 988                 r = gmc_v7_0_mc_load_microcode(adev);
 989                 if (r) {
 990                         DRM_ERROR("Failed to load MC firmware!\n");
 991                         return r;
 992                 }
 993         }
 994
 995         r = gmc_v7_0_gart_enable(adev);
 996         if (r)
 997                 return r;
 998
 999         return r;
1000 }
1001
1002 static int gmc_v7_0_hw_fini(void *handle)
1003 {
1004         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1005
1006         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1007         gmc_v7_0_gart_disable(adev);
1008
1009         return 0;
1010 }
1011
1012 static int gmc_v7_0_suspend(void *handle)
1013 {
1014         int i;
1015         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1016
1017         if (adev->vm_manager.enabled) {
1018                 for (i = 0; i < AMDGPU_NUM_VM; ++i)
1019                         fence_put(adev->vm_manager.active[i]);
1020                 gmc_v7_0_vm_fini(adev);
1021                 adev->vm_manager.enabled = false;
1022         }
1023         gmc_v7_0_hw_fini(adev);
1024
1025         return 0;
1026 }
1027
1028 static int gmc_v7_0_resume(void *handle)
1029 {
1030         int r;
1031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032
1033         r = gmc_v7_0_hw_init(adev);
1034         if (r)
1035                 return r;
1036
1037         if (!adev->vm_manager.enabled) {
1038                 r = gmc_v7_0_vm_init(adev);
1039                 if (r) {
1040                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1041                         return r;
1042                 }
1043                 adev->vm_manager.enabled = true;
1044         }
1045
1046         return r;
1047 }
1048
1049 static bool gmc_v7_0_is_idle(void *handle)
1050 {
1051         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052         u32 tmp = RREG32(mmSRBM_STATUS);
1053
1054         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1055                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1056                 return false;
1057
1058         return true;
1059 }
1060
1061 static int gmc_v7_0_wait_for_idle(void *handle)
1062 {
1063         unsigned i;
1064         u32 tmp;
1065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1066
1067         for (i = 0; i < adev->usec_timeout; i++) {
1068                 /* read MC_STATUS */
1069                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1070                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1071                                                SRBM_STATUS__MCC_BUSY_MASK |
1072                                                SRBM_STATUS__MCD_BUSY_MASK |
1073                                                SRBM_STATUS__VMC_BUSY_MASK);
1074                 if (!tmp)
1075                         return 0;
1076                 udelay(1);
1077         }
1078         return -ETIMEDOUT;
1079
1080 }
1081
1082 static void gmc_v7_0_print_status(void *handle)
1083 {
1084         int i, j;
1085         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1086
1087         dev_info(adev->dev, "GMC 8.x registers\n");
1088         dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
1089                 RREG32(mmSRBM_STATUS));
1090         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1091                 RREG32(mmSRBM_STATUS2));
1092
1093         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1094                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1095         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1096                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1097         dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1098                  RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1099         dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
1100                  RREG32(mmVM_L2_CNTL));
1101         dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
1102                  RREG32(mmVM_L2_CNTL2));
1103         dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
1104                  RREG32(mmVM_L2_CNTL3));
1105         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1106                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1107         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1108                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1109         dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1110                  RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1111         dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
1112                  RREG32(mmVM_CONTEXT0_CNTL2));
1113         dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
1114                  RREG32(mmVM_CONTEXT0_CNTL));
1115         dev_info(adev->dev, "  0x15D4=0x%08X\n",
1116                  RREG32(0x575));
1117         dev_info(adev->dev, "  0x15D8=0x%08X\n",
1118                  RREG32(0x576));
1119         dev_info(adev->dev, "  0x15DC=0x%08X\n",
1120                  RREG32(0x577));
1121         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1122                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1123         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1124                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1125         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1126                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1127         dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
1128                  RREG32(mmVM_CONTEXT1_CNTL2));
1129         dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
1130                  RREG32(mmVM_CONTEXT1_CNTL));
1131         for (i = 0; i < 16; i++) {
1132                 if (i < 8)
1133                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1134                                  i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1135                 else
1136                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1137                                  i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1138         }
1139         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1140                  RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1141         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1142                  RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1143         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1144                  RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1145         dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
1146                  RREG32(mmMC_VM_FB_LOCATION));
1147         dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
1148                  RREG32(mmMC_VM_AGP_BASE));
1149         dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
1150                  RREG32(mmMC_VM_AGP_TOP));
1151         dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
1152                  RREG32(mmMC_VM_AGP_BOT));
1153
1154         if (adev->asic_type == CHIP_KAVERI) {
1155                 dev_info(adev->dev, "  CHUB_CONTROL=0x%08X\n",
1156                          RREG32(mmCHUB_CONTROL));
1157         }
1158
1159         dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1160                  RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1161         dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
1162                  RREG32(mmHDP_NONSURFACE_BASE));
1163         dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
1164                  RREG32(mmHDP_NONSURFACE_INFO));
1165         dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
1166                  RREG32(mmHDP_NONSURFACE_SIZE));
1167         dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
1168                  RREG32(mmHDP_MISC_CNTL));
1169         dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
1170                  RREG32(mmHDP_HOST_PATH_CNTL));
1171
1172         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1173                 dev_info(adev->dev, "  %d:\n", i);
1174                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1175                          0xb05 + j, RREG32(0xb05 + j));
1176                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1177                          0xb06 + j, RREG32(0xb06 + j));
1178                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1179                          0xb07 + j, RREG32(0xb07 + j));
1180                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1181                          0xb08 + j, RREG32(0xb08 + j));
1182                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1183                          0xb09 + j, RREG32(0xb09 + j));
1184         }
1185
1186         dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
1187                  RREG32(mmBIF_FB_EN));
1188 }
1189
1190 static int gmc_v7_0_soft_reset(void *handle)
1191 {
1192         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1193         struct amdgpu_mode_mc_save save;
1194         u32 srbm_soft_reset = 0;
1195         u32 tmp = RREG32(mmSRBM_STATUS);
1196
1197         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1198                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1199                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1200
1201         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1202                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1203                 if (!(adev->flags & AMD_IS_APU))
1204                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1205                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1206         }
1207
1208         if (srbm_soft_reset) {
1209                 gmc_v7_0_print_status((void *)adev);
1210
1211                 gmc_v7_0_mc_stop(adev, &save);
1212                 if (gmc_v7_0_wait_for_idle(adev)) {
1213                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1214                 }
1215
1216
1217                 tmp = RREG32(mmSRBM_SOFT_RESET);
1218                 tmp |= srbm_soft_reset;
1219                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1220                 WREG32(mmSRBM_SOFT_RESET, tmp);
1221                 tmp = RREG32(mmSRBM_SOFT_RESET);
1222
1223                 udelay(50);
1224
1225                 tmp &= ~srbm_soft_reset;
1226                 WREG32(mmSRBM_SOFT_RESET, tmp);
1227                 tmp = RREG32(mmSRBM_SOFT_RESET);
1228
1229                 /* Wait a little for things to settle down */
1230                 udelay(50);
1231
1232                 gmc_v7_0_mc_resume(adev, &save);
1233                 udelay(50);
1234
1235                 gmc_v7_0_print_status((void *)adev);
1236         }
1237
1238         return 0;
1239 }
1240
1241 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1242                                              struct amdgpu_irq_src *src,
1243                                              unsigned type,
1244                                              enum amdgpu_interrupt_state state)
1245 {
1246         u32 tmp;
1247         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1248                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1249                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1250                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1251                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1252                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1253
1254         switch (state) {
1255         case AMDGPU_IRQ_STATE_DISABLE:
1256                 /* system context */
1257                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1258                 tmp &= ~bits;
1259                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1260                 /* VMs */
1261                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1262                 tmp &= ~bits;
1263                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1264                 break;
1265         case AMDGPU_IRQ_STATE_ENABLE:
1266                 /* system context */
1267                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1268                 tmp |= bits;
1269                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1270                 /* VMs */
1271                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1272                 tmp |= bits;
1273                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1274                 break;
1275         default:
1276                 break;
1277         }
1278
1279         return 0;
1280 }
1281
1282 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1283                                       struct amdgpu_irq_src *source,
1284                                       struct amdgpu_iv_entry *entry)
1285 {
1286         u32 addr, status, mc_client;
1287
1288         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1289         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1290         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1291         /* reset addr and status */
1292         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1293
1294         if (!addr && !status)
1295                 return 0;
1296
1297         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1298                 gmc_v7_0_set_fault_enable_default(adev, false);
1299
1300         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1301                 entry->src_id, entry->src_data);
1302         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1303                 addr);
1304         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1305                 status);
1306         gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1307
1308         return 0;
1309 }
1310
1311 static int gmc_v7_0_set_clockgating_state(void *handle,
1312                                           enum amd_clockgating_state state)
1313 {
1314         bool gate = false;
1315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317         if (state == AMD_CG_STATE_GATE)
1318                 gate = true;
1319
1320         if (!(adev->flags & AMD_IS_APU)) {
1321                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1322                 gmc_v7_0_enable_mc_ls(adev, gate);
1323         }
1324         gmc_v7_0_enable_bif_mgls(adev, gate);
1325         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1326         gmc_v7_0_enable_hdp_ls(adev, gate);
1327
1328         return 0;
1329 }
1330
1331 static int gmc_v7_0_set_powergating_state(void *handle,
1332                                           enum amd_powergating_state state)
1333 {
1334         return 0;
1335 }
1336
1337 const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1338         .early_init = gmc_v7_0_early_init,
1339         .late_init = gmc_v7_0_late_init,
1340         .sw_init = gmc_v7_0_sw_init,
1341         .sw_fini = gmc_v7_0_sw_fini,
1342         .hw_init = gmc_v7_0_hw_init,
1343         .hw_fini = gmc_v7_0_hw_fini,
1344         .suspend = gmc_v7_0_suspend,
1345         .resume = gmc_v7_0_resume,
1346         .is_idle = gmc_v7_0_is_idle,
1347         .wait_for_idle = gmc_v7_0_wait_for_idle,
1348         .soft_reset = gmc_v7_0_soft_reset,
1349         .print_status = gmc_v7_0_print_status,
1350         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1351         .set_powergating_state = gmc_v7_0_set_powergating_state,
1352 };
1353
1354 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1355         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1356         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1357 };
1358
1359 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1360         .set = gmc_v7_0_vm_fault_interrupt_state,
1361         .process = gmc_v7_0_process_interrupt,
1362 };
1363
1364 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1365 {
1366         if (adev->gart.gart_funcs == NULL)
1367                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1368 }
1369
1370 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1371 {
1372         adev->mc.vm_fault.num_types = 1;
1373         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1374 }