3 * (C) COPYRIGHT 2010-2016 ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * A copy of the licence is included with the program, and can also be obtained
11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
12 * Boston, MA 02110-1301, USA.
22 * Base structures shared with the kernel.
25 #ifndef _BASE_KERNEL_H_
26 #define _BASE_KERNEL_H_
32 /* Support UK6 IOCTLS */
33 #define BASE_LEGACY_UK6_SUPPORT 1
35 /* Support UK7 IOCTLS */
36 /* NB: To support UK6 we also need to support UK7 */
37 #define BASE_LEGACY_UK7_SUPPORT 1
39 /* Support UK8 IOCTLS */
40 #define BASE_LEGACY_UK8_SUPPORT 1
42 /* Support UK9 IOCTLS */
43 #define BASE_LEGACY_UK9_SUPPORT 1
45 /* Support UK10_2 IOCTLS */
46 #define BASE_LEGACY_UK10_2_SUPPORT 1
48 typedef struct base_mem_handle {
54 #include "mali_base_mem_priv.h"
55 #include "mali_kbase_profiling_gator_api.h"
56 #include "mali_midg_coherency.h"
57 #include "mali_kbase_gpu_id.h"
60 * Dependency stuff, keep it private for now. May want to expose it if
61 * we decide to make the number of semaphores a configurable
64 #define BASE_JD_ATOM_COUNT 256
66 #define BASEP_JD_SEM_PER_WORD_LOG2 5
67 #define BASEP_JD_SEM_PER_WORD (1 << BASEP_JD_SEM_PER_WORD_LOG2)
68 #define BASEP_JD_SEM_WORD_NR(x) ((x) >> BASEP_JD_SEM_PER_WORD_LOG2)
69 #define BASEP_JD_SEM_MASK_IN_WORD(x) (1 << ((x) & (BASEP_JD_SEM_PER_WORD - 1)))
70 #define BASEP_JD_SEM_ARRAY_SIZE BASEP_JD_SEM_WORD_NR(BASE_JD_ATOM_COUNT)
72 /* Set/reset values for a software event */
73 #define BASE_JD_SOFT_EVENT_SET ((unsigned char)1)
74 #define BASE_JD_SOFT_EVENT_RESET ((unsigned char)0)
76 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
78 #define BASE_MAX_COHERENT_GROUPS 16
80 #if defined CDBG_ASSERT
81 #define LOCAL_ASSERT CDBG_ASSERT
82 #elif defined KBASE_DEBUG_ASSERT
83 #define LOCAL_ASSERT KBASE_DEBUG_ASSERT
85 #error assert macro not defined!
89 #define LOCAL_PAGE_LSB ~PAGE_MASK
91 #include <osu/mali_osu.h>
93 #if defined OSU_CONFIG_CPU_PAGE_SIZE_LOG2
94 #define LOCAL_PAGE_LSB ((1ul << OSU_CONFIG_CPU_PAGE_SIZE_LOG2) - 1)
96 #error Failed to find page size
100 /** 32/64-bit neutral way to represent pointers */
101 typedef union kbase_pointer {
102 void __user *value; /**< client should store their pointers here */
103 u32 compat_value; /**< 64-bit kernels should fetch value here when handling 32-bit clients */
104 u64 sizer; /**< Force 64-bit storage for all clients regardless */
108 * @addtogroup base_user_api User-side Base APIs
113 * @addtogroup base_user_api_memory User-side Base Memory APIs
118 * @brief Memory allocation, access/hint flags
120 * A combination of MEM_PROT/MEM_HINT flags must be passed to each allocator
121 * in order to determine the best cache policy. Some combinations are
122 * of course invalid (eg @c MEM_PROT_CPU_WR | @c MEM_HINT_CPU_RD),
123 * which defines a @a write-only region on the CPU side, which is
124 * heavily read by the CPU...
125 * Other flags are only meaningful to a particular allocator.
126 * More flags can be added to this list, as long as they don't clash
127 * (see ::BASE_MEM_FLAGS_NR_BITS for the number of the first free bit).
129 typedef u32 base_mem_alloc_flags;
132 * @brief Memory allocation, access/hint flags
134 * See ::base_mem_alloc_flags.
139 BASE_MEM_PROT_CPU_RD = (1U << 0), /**< Read access CPU side */
140 BASE_MEM_PROT_CPU_WR = (1U << 1), /**< Write access CPU side */
141 BASE_MEM_PROT_GPU_RD = (1U << 2), /**< Read access GPU side */
142 BASE_MEM_PROT_GPU_WR = (1U << 3), /**< Write access GPU side */
143 BASE_MEM_PROT_GPU_EX = (1U << 4), /**< Execute allowed on the GPU
146 /* BASE_MEM_HINT flags have been removed, but their values are reserved
147 * for backwards compatibility with older user-space drivers. The values
148 * can be re-used once support for r5p0 user-space drivers is removed,
149 * presumably in r7p0.
151 * RESERVED: (1U << 5)
152 * RESERVED: (1U << 6)
153 * RESERVED: (1U << 7)
154 * RESERVED: (1U << 8)
157 BASE_MEM_GROW_ON_GPF = (1U << 9), /**< Grow backing store on GPU
160 BASE_MEM_COHERENT_SYSTEM = (1U << 10), /**< Page coherence Outer
161 shareable, if available */
162 BASE_MEM_COHERENT_LOCAL = (1U << 11), /**< Page coherence Inner
164 BASE_MEM_CACHED_CPU = (1U << 12), /**< Should be cached on the
168 BASE_MEM_SAME_VA = (1U << 13), /**< Must have same VA on both the GPU
171 BASE_MEM_NEED_MMAP = (1U << 14), /**< Must call mmap to aquire a GPU
172 address for the alloc */
174 BASE_MEM_COHERENT_SYSTEM_REQUIRED = (1U << 15), /**< Page coherence
175 Outer shareable, required. */
176 BASE_MEM_SECURE = (1U << 16), /**< Secure memory */
177 BASE_MEM_DONT_NEED = (1U << 17), /**< Not needed physical
179 BASE_MEM_IMPORT_SHARED = (1U << 18), /**< Must use shared CPU/GPU zone
180 (SAME_VA zone) but doesn't
181 require the addresses to
186 * @brief Number of bits used as flags for base memory management
188 * Must be kept in sync with the ::base_mem_alloc_flags flags
190 #define BASE_MEM_FLAGS_NR_BITS 19
193 * A mask for all output bits, excluding IN/OUT bits.
195 #define BASE_MEM_FLAGS_OUTPUT_MASK BASE_MEM_NEED_MMAP
198 * A mask for all input bits, including IN/OUT bits.
200 #define BASE_MEM_FLAGS_INPUT_MASK \
201 (((1 << BASE_MEM_FLAGS_NR_BITS) - 1) & ~BASE_MEM_FLAGS_OUTPUT_MASK)
204 * A mask for all the flags which are modifiable via the base_mem_set_flags
207 #define BASE_MEM_FLAGS_MODIFIABLE \
208 (BASE_MEM_DONT_NEED | BASE_MEM_COHERENT_SYSTEM | \
209 BASE_MEM_COHERENT_LOCAL)
212 * enum base_mem_import_type - Memory types supported by @a base_mem_import
214 * @BASE_MEM_IMPORT_TYPE_INVALID: Invalid type
215 * @BASE_MEM_IMPORT_TYPE_UMP: UMP import. Handle type is ump_secure_id.
216 * @BASE_MEM_IMPORT_TYPE_UMM: UMM import. Handle type is a file descriptor (int)
217 * @BASE_MEM_IMPORT_TYPE_USER_BUFFER: User buffer import. Handle is a
218 * base_mem_import_user_buffer
220 * Each type defines what the supported handle type is.
222 * If any new type is added here ARM must be contacted
223 * to allocate a numeric value for it.
224 * Do not just add a new type without synchronizing with ARM
225 * as future releases from ARM might include other new types
226 * which could clash with your custom types.
228 typedef enum base_mem_import_type {
229 BASE_MEM_IMPORT_TYPE_INVALID = 0,
230 BASE_MEM_IMPORT_TYPE_UMP = 1,
231 BASE_MEM_IMPORT_TYPE_UMM = 2,
232 BASE_MEM_IMPORT_TYPE_USER_BUFFER = 3
233 } base_mem_import_type;
236 * struct base_mem_import_user_buffer - Handle of an imported user buffer
238 * @ptr: kbase_pointer to imported user buffer
239 * @length: length of imported user buffer in bytes
241 * This structure is used to represent a handle of an imported user buffer.
244 struct base_mem_import_user_buffer {
250 * @brief Invalid memory handle.
252 * Return value from functions returning @ref base_mem_handle on error.
254 * @warning @ref base_mem_handle_new_invalid must be used instead of this macro
255 * in C++ code or other situations where compound literals cannot be used.
257 #define BASE_MEM_INVALID_HANDLE ((base_mem_handle) { {BASEP_MEM_INVALID_HANDLE} })
260 * @brief Special write-alloc memory handle.
262 * A special handle is used to represent a region where a special page is mapped
263 * with a write-alloc cache setup, typically used when the write result of the
264 * GPU isn't needed, but the GPU must write anyway.
266 * @warning @ref base_mem_handle_new_write_alloc must be used instead of this macro
267 * in C++ code or other situations where compound literals cannot be used.
269 #define BASE_MEM_WRITE_ALLOC_PAGES_HANDLE ((base_mem_handle) { {BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE} })
271 #define BASEP_MEM_INVALID_HANDLE (0ull << 12)
272 #define BASE_MEM_MMU_DUMP_HANDLE (1ull << 12)
273 #define BASE_MEM_TRACE_BUFFER_HANDLE (2ull << 12)
274 #define BASE_MEM_MAP_TRACKING_HANDLE (3ull << 12)
275 #define BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE (4ull << 12)
276 /* reserved handles ..-64<<PAGE_SHIFT> for future special handles */
277 #define BASE_MEM_COOKIE_BASE (64ul << 12)
278 #define BASE_MEM_FIRST_FREE_ADDRESS ((BITS_PER_LONG << 12) + \
279 BASE_MEM_COOKIE_BASE)
281 /* Mask to detect 4GB boundary alignment */
282 #define BASE_MEM_MASK_4GB 0xfffff000UL
285 /* Bit mask of cookies used for for memory allocation setup */
286 #define KBASE_COOKIE_MASK ~1UL /* bit 0 is reserved */
290 * @brief Result codes of changing the size of the backing store allocated to a tmem region
292 typedef enum base_backing_threshold_status {
293 BASE_BACKING_THRESHOLD_OK = 0, /**< Resize successful */
294 BASE_BACKING_THRESHOLD_ERROR_NOT_GROWABLE = -1, /**< Not a growable tmem object */
295 BASE_BACKING_THRESHOLD_ERROR_OOM = -2, /**< Increase failed due to an out-of-memory condition */
296 BASE_BACKING_THRESHOLD_ERROR_INVALID_ARGUMENTS = -4 /**< Invalid arguments (not tmem, illegal size request, etc.) */
297 } base_backing_threshold_status;
300 * @addtogroup base_user_api_memory_defered User-side Base Defered Memory Coherency APIs
305 * @brief a basic memory operation (sync-set).
307 * The content of this structure is private, and should only be used
310 typedef struct base_syncset {
311 struct basep_syncset basep_sset;
314 /** @} end group base_user_api_memory_defered */
317 * Handle to represent imported memory object.
318 * Simple opague handle to imported memory, can't be used
319 * with anything but base_external_resource_init to bind to an atom.
321 typedef struct base_import_handle {
325 } base_import_handle;
327 /** @} end group base_user_api_memory */
330 * @addtogroup base_user_api_job_dispatch User-side Base Job Dispatcher APIs
334 typedef int platform_fence_type;
335 #define INVALID_PLATFORM_FENCE ((platform_fence_type)-1)
338 * Base stream handle.
340 * References an underlying base stream object.
342 typedef struct base_stream {
351 * References an underlying base fence object.
353 typedef struct base_fence {
361 * @brief Per-job data
363 * This structure is used to store per-job data, and is completly unused
364 * by the Base driver. It can be used to store things such as callback
365 * function pointer, data to handle job completion. It is guaranteed to be
366 * untouched by the Base driver.
368 typedef struct base_jd_udata {
369 u64 blob[2]; /**< per-job data array */
373 * @brief Memory aliasing info
375 * Describes a memory handle to be aliased.
376 * A subset of the handle can be chosen for aliasing, given an offset and a
378 * A special handle BASE_MEM_WRITE_ALLOC_PAGES_HANDLE is used to represent a
379 * region where a special page is mapped with a write-alloc cache setup,
380 * typically used when the write result of the GPU isn't needed, but the GPU
383 * Offset and length are specified in pages.
384 * Offset must be within the size of the handle.
385 * Offset+length must not overrun the size of the handle.
387 * @handle Handle to alias, can be BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
388 * @offset Offset within the handle to start aliasing from, in pages.
389 * Not used with BASE_MEM_WRITE_ALLOC_PAGES_HANDLE.
390 * @length Length to alias, in pages. For BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
391 * specifies the number of times the special page is needed.
393 struct base_mem_aliasing_info {
394 base_mem_handle handle;
400 * struct base_jit_alloc_info - Structure which describes a JIT allocation
402 * @gpu_alloc_addr: The GPU virtual address to write the JIT
403 * allocated GPU virtual address to.
404 * @va_pages: The minimum number of virtual pages required.
405 * @commit_pages: The minimum number of physical pages which
406 * should back the allocation.
407 * @extent: Granularity of physical pages to grow the
408 * allocation by during a fault.
409 * @id: Unique ID provided by the caller, this is used
410 * to pair allocation and free requests.
411 * Zero is not a valid value.
413 struct base_jit_alloc_info {
422 * @brief Job dependency type.
424 * A flags field will be inserted into the atom structure to specify whether a dependency is a data or
425 * ordering dependency (by putting it before/after 'core_req' in the structure it should be possible to add without
426 * changing the structure size).
427 * When the flag is set for a particular dependency to signal that it is an ordering only dependency then
428 * errors will not be propagated.
430 typedef u8 base_jd_dep_type;
433 #define BASE_JD_DEP_TYPE_INVALID (0) /**< Invalid dependency */
434 #define BASE_JD_DEP_TYPE_DATA (1U << 0) /**< Data dependency */
435 #define BASE_JD_DEP_TYPE_ORDER (1U << 1) /**< Order dependency */
438 * @brief Job chain hardware requirements.
440 * A job chain must specify what GPU features it needs to allow the
441 * driver to schedule the job correctly. By not specifying the
442 * correct settings can/will cause an early job termination. Multiple
443 * values can be ORed together to specify multiple requirements.
444 * Special case is ::BASE_JD_REQ_DEP, which is used to express complex
445 * dependencies, and that doesn't execute anything on the hardware.
447 typedef u32 base_jd_core_req;
449 /* Requirements that come from the HW */
452 * No requirement, dependency only
454 #define BASE_JD_REQ_DEP ((base_jd_core_req)0)
457 * Requires fragment shaders
459 #define BASE_JD_REQ_FS ((base_jd_core_req)1 << 0)
462 * Requires compute shaders
463 * This covers any of the following Midgard Job types:
464 * - Vertex Shader Job
465 * - Geometry Shader Job
466 * - An actual Compute Shader Job
468 * Compare this with @ref BASE_JD_REQ_ONLY_COMPUTE, which specifies that the
469 * job is specifically just the "Compute Shader" job type, and not the "Vertex
470 * Shader" nor the "Geometry Shader" job type.
472 #define BASE_JD_REQ_CS ((base_jd_core_req)1 << 1)
473 #define BASE_JD_REQ_T ((base_jd_core_req)1 << 2) /**< Requires tiling */
474 #define BASE_JD_REQ_CF ((base_jd_core_req)1 << 3) /**< Requires cache flushes */
475 #define BASE_JD_REQ_V ((base_jd_core_req)1 << 4) /**< Requires value writeback */
477 /* SW-only requirements - the HW does not expose these as part of the job slot capabilities */
479 /* Requires fragment job with AFBC encoding */
480 #define BASE_JD_REQ_FS_AFBC ((base_jd_core_req)1 << 13)
483 * SW-only requirement: coalesce completion events.
484 * If this bit is set then completion of this atom will not cause an event to
485 * be sent to userspace, whether successful or not; completion events will be
486 * deferred until an atom completes which does not have this bit set.
488 * This bit may not be used in combination with BASE_JD_REQ_EXTERNAL_RESOURCES.
490 #define BASE_JD_REQ_EVENT_COALESCE ((base_jd_core_req)1 << 5)
493 * SW Only requirement: the job chain requires a coherent core group. We don't
494 * mind which coherent core group is used.
496 #define BASE_JD_REQ_COHERENT_GROUP ((base_jd_core_req)1 << 6)
499 * SW Only requirement: The performance counters should be enabled only when
500 * they are needed, to reduce power consumption.
503 #define BASE_JD_REQ_PERMON ((base_jd_core_req)1 << 7)
506 * SW Only requirement: External resources are referenced by this atom.
507 * When external resources are referenced no syncsets can be bundled with the atom
508 * but should instead be part of a NULL jobs inserted into the dependency tree.
509 * The first pre_dep object must be configured for the external resouces to use,
510 * the second pre_dep object can be used to create other dependencies.
512 * This bit may not be used in combination with BASE_JD_REQ_EVENT_COALESCE.
514 #define BASE_JD_REQ_EXTERNAL_RESOURCES ((base_jd_core_req)1 << 8)
517 * SW Only requirement: Software defined job. Jobs with this bit set will not be submitted
518 * to the hardware but will cause some action to happen within the driver
520 #define BASE_JD_REQ_SOFT_JOB ((base_jd_core_req)1 << 9)
522 #define BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME (BASE_JD_REQ_SOFT_JOB | 0x1)
523 #define BASE_JD_REQ_SOFT_FENCE_TRIGGER (BASE_JD_REQ_SOFT_JOB | 0x2)
524 #define BASE_JD_REQ_SOFT_FENCE_WAIT (BASE_JD_REQ_SOFT_JOB | 0x3)
527 * SW Only requirement : Replay job.
529 * If the preceeding job fails, the replay job will cause the jobs specified in
530 * the list of base_jd_replay_payload pointed to by the jc pointer to be
533 * A replay job will only cause jobs to be replayed up to BASEP_JD_REPLAY_LIMIT
534 * times. If a job fails more than BASEP_JD_REPLAY_LIMIT times then the replay
535 * job is failed, as well as any following dependencies.
537 * The replayed jobs will require a number of atom IDs. If there are not enough
538 * free atom IDs then the replay job will fail.
540 * If the preceeding job does not fail, then the replay job is returned as
543 * The replayed jobs will never be returned to userspace. The preceeding failed
544 * job will be returned to userspace as failed; the status of this job should
545 * be ignored. Completion should be determined by the status of the replay soft
548 * In order for the jobs to be replayed, the job headers will have to be
549 * modified. The Status field will be reset to NOT_STARTED. If the Job Type
550 * field indicates a Vertex Shader Job then it will be changed to Null Job.
552 * The replayed jobs have the following assumptions :
554 * - No external resources. Any required external resources will be held by the
556 * - Pre-dependencies are created based on job order.
557 * - Atom numbers are automatically assigned.
558 * - device_nr is set to 0. This is not relevant as
559 * BASE_JD_REQ_SPECIFIC_COHERENT_GROUP should not be set.
560 * - Priority is inherited from the replay job.
562 #define BASE_JD_REQ_SOFT_REPLAY (BASE_JD_REQ_SOFT_JOB | 0x4)
564 * SW only requirement: event wait/trigger job.
566 * - BASE_JD_REQ_SOFT_EVENT_WAIT: this job will block until the event is set.
567 * - BASE_JD_REQ_SOFT_EVENT_SET: this job sets the event, thus unblocks the
568 * other waiting jobs. It completes immediately.
569 * - BASE_JD_REQ_SOFT_EVENT_RESET: this job resets the event, making it
570 * possible for other jobs to wait upon. It completes immediately.
572 #define BASE_JD_REQ_SOFT_EVENT_WAIT (BASE_JD_REQ_SOFT_JOB | 0x5)
573 #define BASE_JD_REQ_SOFT_EVENT_SET (BASE_JD_REQ_SOFT_JOB | 0x6)
574 #define BASE_JD_REQ_SOFT_EVENT_RESET (BASE_JD_REQ_SOFT_JOB | 0x7)
576 #define BASE_JD_REQ_SOFT_DEBUG_COPY (BASE_JD_REQ_SOFT_JOB | 0x8)
579 * SW only requirement: Just In Time allocation
581 * This job requests a JIT allocation based on the request in the
582 * @base_jit_alloc_info structure which is passed via the jc element of
585 * It should be noted that the id entry in @base_jit_alloc_info must not
586 * be reused until it has been released via @BASE_JD_REQ_SOFT_JIT_FREE.
588 * Should this soft job fail it is expected that a @BASE_JD_REQ_SOFT_JIT_FREE
589 * soft job to free the JIT allocation is still made.
591 * The job will complete immediately.
593 #define BASE_JD_REQ_SOFT_JIT_ALLOC (BASE_JD_REQ_SOFT_JOB | 0x9)
595 * SW only requirement: Just In Time free
597 * This job requests a JIT allocation created by @BASE_JD_REQ_SOFT_JIT_ALLOC
598 * to be freed. The ID of the JIT allocation is passed via the jc element of
601 * The job will complete immediately.
603 #define BASE_JD_REQ_SOFT_JIT_FREE (BASE_JD_REQ_SOFT_JOB | 0xa)
606 * SW only requirement: Map external resource
608 * This job requests external resource(s) are mapped once the dependencies
609 * of the job have been satisfied. The list of external resources are
610 * passed via the jc element of the atom which is a pointer to a
611 * @base_external_resource_list.
613 #define BASE_JD_REQ_SOFT_EXT_RES_MAP (BASE_JD_REQ_SOFT_JOB | 0xb)
615 * SW only requirement: Unmap external resource
617 * This job requests external resource(s) are unmapped once the dependencies
618 * of the job has been satisfied. The list of external resources are
619 * passed via the jc element of the atom which is a pointer to a
620 * @base_external_resource_list.
622 #define BASE_JD_REQ_SOFT_EXT_RES_UNMAP (BASE_JD_REQ_SOFT_JOB | 0xc)
625 * HW Requirement: Requires Compute shaders (but not Vertex or Geometry Shaders)
627 * This indicates that the Job Chain contains Midgard Jobs of the 'Compute Shaders' type.
629 * In contrast to @ref BASE_JD_REQ_CS, this does \b not indicate that the Job
630 * Chain contains 'Geometry Shader' or 'Vertex Shader' jobs.
632 #define BASE_JD_REQ_ONLY_COMPUTE ((base_jd_core_req)1 << 10)
635 * HW Requirement: Use the base_jd_atom::device_nr field to specify a
636 * particular core group
638 * If both @ref BASE_JD_REQ_COHERENT_GROUP and this flag are set, this flag takes priority
640 * This is only guaranteed to work for @ref BASE_JD_REQ_ONLY_COMPUTE atoms.
642 * If the core availability policy is keeping the required core group turned off, then
643 * the job will fail with a @ref BASE_JD_EVENT_PM_EVENT error code.
645 #define BASE_JD_REQ_SPECIFIC_COHERENT_GROUP ((base_jd_core_req)1 << 11)
648 * SW Flag: If this bit is set then the successful completion of this atom
649 * will not cause an event to be sent to userspace
651 #define BASE_JD_REQ_EVENT_ONLY_ON_FAILURE ((base_jd_core_req)1 << 12)
654 * SW Flag: If this bit is set then completion of this atom will not cause an
655 * event to be sent to userspace, whether successful or not.
657 #define BASEP_JD_REQ_EVENT_NEVER ((base_jd_core_req)1 << 14)
660 * SW Flag: Skip GPU cache clean and invalidation before starting a GPU job.
662 * If this bit is set then the GPU's cache will not be cleaned and invalidated
663 * until a GPU job starts which does not have this bit set or a job completes
664 * which does not have the @ref BASE_JD_REQ_SKIP_CACHE_END bit set. Do not use if
665 * the CPU may have written to memory addressed by the job since the last job
666 * without this bit set was submitted.
668 #define BASE_JD_REQ_SKIP_CACHE_START ((base_jd_core_req)1 << 15)
671 * SW Flag: Skip GPU cache clean and invalidation after a GPU job completes.
673 * If this bit is set then the GPU's cache will not be cleaned and invalidated
674 * until a GPU job completes which does not have this bit set or a job starts
675 * which does not have the @ref BASE_JD_REQ_SKIP_CACHE_START bti set. Do not use if
676 * the CPU may read from or partially overwrite memory addressed by the job
677 * before the next job without this bit set completes.
679 #define BASE_JD_REQ_SKIP_CACHE_END ((base_jd_core_req)1 << 16)
682 * These requirement bits are currently unused in base_jd_core_req
684 #define BASEP_JD_REQ_RESERVED \
685 (~(BASE_JD_REQ_ATOM_TYPE | BASE_JD_REQ_EXTERNAL_RESOURCES | \
686 BASE_JD_REQ_EVENT_ONLY_ON_FAILURE | BASEP_JD_REQ_EVENT_NEVER | \
687 BASE_JD_REQ_EVENT_COALESCE | \
688 BASE_JD_REQ_COHERENT_GROUP | BASE_JD_REQ_SPECIFIC_COHERENT_GROUP | \
689 BASE_JD_REQ_FS_AFBC | BASE_JD_REQ_PERMON | \
690 BASE_JD_REQ_SKIP_CACHE_START | BASE_JD_REQ_SKIP_CACHE_END))
693 * Mask of all bits in base_jd_core_req that control the type of the atom.
695 * This allows dependency only atoms to have flags set
697 #define BASE_JD_REQ_ATOM_TYPE \
698 (BASE_JD_REQ_FS | BASE_JD_REQ_CS | BASE_JD_REQ_T | BASE_JD_REQ_CF | \
699 BASE_JD_REQ_V | BASE_JD_REQ_SOFT_JOB | BASE_JD_REQ_ONLY_COMPUTE)
702 * Mask of all bits in base_jd_core_req that control the type of a soft job.
704 #define BASE_JD_REQ_SOFT_JOB_TYPE (BASE_JD_REQ_SOFT_JOB | 0x1f)
707 * @brief States to model state machine processed by kbasep_js_job_check_ref_cores(), which
708 * handles retaining cores for power management and affinity management.
710 * The state @ref KBASE_ATOM_COREREF_STATE_RECHECK_AFFINITY prevents an attack
711 * where lots of atoms could be submitted before powerup, and each has an
712 * affinity chosen that causes other atoms to have an affinity
713 * violation. Whilst the affinity was not causing violations at the time it
714 * was chosen, it could cause violations thereafter. For example, 1000 jobs
715 * could have had their affinity chosen during the powerup time, so any of
716 * those 1000 jobs could cause an affinity violation later on.
718 * The attack would otherwise occur because other atoms/contexts have to wait for:
719 * -# the currently running atoms (which are causing the violation) to
721 * -# and, the atoms that had their affinity chosen during powerup to
722 * finish. These are run preferrentially because they don't cause a
723 * violation, but instead continue to cause the violation in others.
724 * -# or, the attacker is scheduled out (which might not happen for just 2
727 * By re-choosing the affinity (which is designed to avoid violations at the
728 * time it's chosen), we break condition (2) of the wait, which minimizes the
729 * problem to just waiting for current jobs to finish (which can be bounded if
730 * the Job Scheduling Policy has a timer).
732 enum kbase_atom_coreref_state {
733 /** Starting state: No affinity chosen, and cores must be requested. kbase_jd_atom::affinity==0 */
734 KBASE_ATOM_COREREF_STATE_NO_CORES_REQUESTED,
735 /** Cores requested, but waiting for them to be powered. Requested cores given by kbase_jd_atom::affinity */
736 KBASE_ATOM_COREREF_STATE_WAITING_FOR_REQUESTED_CORES,
737 /** Cores given by kbase_jd_atom::affinity are powered, but affinity might be out-of-date, so must recheck */
738 KBASE_ATOM_COREREF_STATE_RECHECK_AFFINITY,
739 /** Cores given by kbase_jd_atom::affinity are powered, and affinity is up-to-date, but must check for violations */
740 KBASE_ATOM_COREREF_STATE_CHECK_AFFINITY_VIOLATIONS,
741 /** Cores are powered, kbase_jd_atom::affinity up-to-date, no affinity violations: atom can be submitted to HW */
742 KBASE_ATOM_COREREF_STATE_READY
748 * Only certain priority levels are actually implemented, as specified by the
749 * BASE_JD_PRIO_<...> definitions below. It is undefined to use a priority
750 * level that is not one of those defined below.
752 * Priority levels only affect scheduling between atoms of the same type within
753 * a base context, and only after the atoms have had dependencies resolved.
754 * Fragment atoms does not affect non-frament atoms with lower priorities, and
755 * the other way around. For example, a low priority atom that has had its
756 * dependencies resolved might run before a higher priority atom that has not
757 * had its dependencies resolved.
759 * The scheduling between base contexts/processes and between atoms from
760 * different base contexts/processes is unaffected by atom priority.
762 * The atoms are scheduled as follows with respect to their priorities:
763 * - Let atoms 'X' and 'Y' be for the same job slot who have dependencies
764 * resolved, and atom 'X' has a higher priority than atom 'Y'
765 * - If atom 'Y' is currently running on the HW, then it is interrupted to
766 * allow atom 'X' to run soon after
767 * - If instead neither atom 'Y' nor atom 'X' are running, then when choosing
768 * the next atom to run, atom 'X' will always be chosen instead of atom 'Y'
769 * - Any two atoms that have the same priority could run in any order with
770 * respect to each other. That is, there is no ordering constraint between
771 * atoms of the same priority.
773 typedef u8 base_jd_prio;
775 /* Medium atom priority. This is a priority higher than BASE_JD_PRIO_LOW */
776 #define BASE_JD_PRIO_MEDIUM ((base_jd_prio)0)
777 /* High atom priority. This is a priority higher than BASE_JD_PRIO_MEDIUM and
778 * BASE_JD_PRIO_LOW */
779 #define BASE_JD_PRIO_HIGH ((base_jd_prio)1)
780 /* Low atom priority. */
781 #define BASE_JD_PRIO_LOW ((base_jd_prio)2)
783 /* Count of the number of priority levels. This itself is not a valid
784 * base_jd_prio setting */
785 #define BASE_JD_NR_PRIO_LEVELS 3
787 enum kbase_jd_atom_state {
788 /** Atom is not used */
789 KBASE_JD_ATOM_STATE_UNUSED,
790 /** Atom is queued in JD */
791 KBASE_JD_ATOM_STATE_QUEUED,
792 /** Atom has been given to JS (is runnable/running) */
793 KBASE_JD_ATOM_STATE_IN_JS,
794 /** Atom has been completed, but not yet handed back to job dispatcher
795 * for dependency resolution */
796 KBASE_JD_ATOM_STATE_HW_COMPLETED,
797 /** Atom has been completed, but not yet handed back to userspace */
798 KBASE_JD_ATOM_STATE_COMPLETED
801 typedef u8 base_atom_id; /**< Type big enough to store an atom number in */
803 struct base_dependency {
804 base_atom_id atom_id; /**< An atom number */
805 base_jd_dep_type dependency_type; /**< Dependency type */
808 /* This structure has changed since UK 10.2 for which base_jd_core_req was a u16 value.
809 * In order to keep the size of the structure same, padding field has been adjusted
810 * accordingly and core_req field of a u32 type (to which UK 10.3 base_jd_core_req defines)
811 * is added at the end of the structure. Place in the structure previously occupied by u16 core_req
812 * is kept but renamed to compat_core_req and as such it can be used in ioctl call for job submission
813 * as long as UK 10.2 legacy is supported. Once when this support ends, this field can be left
814 * for possible future use. */
815 typedef struct base_jd_atom_v2 {
816 u64 jc; /**< job-chain GPU address */
817 struct base_jd_udata udata; /**< user data */
818 kbase_pointer extres_list; /**< list of external resources */
819 u16 nr_extres; /**< nr of external resources */
820 u16 compat_core_req; /**< core requirements which correspond to the legacy support for UK 10.2 */
821 struct base_dependency pre_dep[2]; /**< pre-dependencies, one need to use SETTER function to assign this field,
822 this is done in order to reduce possibility of improper assigment of a dependency field */
823 base_atom_id atom_number; /**< unique number to identify the atom */
824 base_jd_prio prio; /**< Atom priority. Refer to @ref base_jd_prio for more details */
825 u8 device_nr; /**< coregroup when BASE_JD_REQ_SPECIFIC_COHERENT_GROUP specified */
827 base_jd_core_req core_req; /**< core requirements */
830 #ifdef BASE_LEGACY_UK6_SUPPORT
831 struct base_jd_atom_v2_uk6 {
832 u64 jc; /**< job-chain GPU address */
833 struct base_jd_udata udata; /**< user data */
834 kbase_pointer extres_list; /**< list of external resources */
835 u16 nr_extres; /**< nr of external resources */
836 u16 core_req; /**< core requirements */
837 base_atom_id pre_dep[2]; /**< pre-dependencies */
838 base_atom_id atom_number; /**< unique number to identify the atom */
839 base_jd_prio prio; /**< priority - smaller is higher priority */
840 u8 device_nr; /**< coregroup when BASE_JD_REQ_SPECIFIC_COHERENT_GROUP specified */
843 #endif /* BASE_LEGACY_UK6_SUPPORT */
845 typedef enum base_external_resource_access {
846 BASE_EXT_RES_ACCESS_SHARED,
847 BASE_EXT_RES_ACCESS_EXCLUSIVE
848 } base_external_resource_access;
850 typedef struct base_external_resource {
852 } base_external_resource;
856 * The maximum number of external resources which can be mapped/unmapped
857 * in a single request.
859 #define BASE_EXT_RES_COUNT_MAX 10
862 * struct base_external_resource_list - Structure which describes a list of
863 * external resources.
864 * @count: The number of resources.
865 * @ext_res: Array of external resources which is
866 * sized at allocation time.
868 struct base_external_resource_list {
870 struct base_external_resource ext_res[1];
873 struct base_jd_debug_copy_buffer {
876 struct base_external_resource extres;
880 * @brief Setter for a dependency structure
882 * @param[in] dep The kbase jd atom dependency to be initialized.
883 * @param id The atom_id to be assigned.
884 * @param dep_type The dep_type to be assigned.
887 static inline void base_jd_atom_dep_set(struct base_dependency *dep,
888 base_atom_id id, base_jd_dep_type dep_type)
890 LOCAL_ASSERT(dep != NULL);
893 * make sure we don't set not allowed combinations
894 * of atom_id/dependency_type.
896 LOCAL_ASSERT((id == 0 && dep_type == BASE_JD_DEP_TYPE_INVALID) ||
897 (id > 0 && dep_type != BASE_JD_DEP_TYPE_INVALID));
900 dep->dependency_type = dep_type;
904 * @brief Make a copy of a dependency structure
906 * @param[in,out] dep The kbase jd atom dependency to be written.
907 * @param[in] from The dependency to make a copy from.
910 static inline void base_jd_atom_dep_copy(struct base_dependency *dep,
911 const struct base_dependency *from)
913 LOCAL_ASSERT(dep != NULL);
915 base_jd_atom_dep_set(dep, from->atom_id, from->dependency_type);
919 * @brief Soft-atom fence trigger setup.
921 * Sets up an atom to be a SW-only atom signaling a fence
922 * when it reaches the run state.
924 * Using the existing base dependency system the fence can
925 * be set to trigger when a GPU job has finished.
927 * The base fence object must not be terminated until the atom
928 * has been submitted to @a base_jd_submit_bag and @a base_jd_submit_bag has returned.
930 * @a fence must be a valid fence set up with @a base_fence_init.
931 * Calling this function with a uninitialized fence results in undefined behavior.
933 * @param[out] atom A pre-allocated atom to configure as a fence trigger SW atom
934 * @param[in] fence The base fence object to trigger.
936 static inline void base_jd_fence_trigger_setup_v2(struct base_jd_atom_v2 *atom, struct base_fence *fence)
940 LOCAL_ASSERT(fence->basep.fd == INVALID_PLATFORM_FENCE);
941 LOCAL_ASSERT(fence->basep.stream_fd >= 0);
942 atom->jc = (uintptr_t) fence;
943 atom->core_req = BASE_JD_REQ_SOFT_FENCE_TRIGGER;
947 * @brief Soft-atom fence wait setup.
949 * Sets up an atom to be a SW-only atom waiting on a fence.
950 * When the fence becomes triggered the atom becomes runnable
951 * and completes immediately.
953 * Using the existing base dependency system the fence can
954 * be set to block a GPU job until it has been triggered.
956 * The base fence object must not be terminated until the atom
957 * has been submitted to @a base_jd_submit_bag and @a base_jd_submit_bag has returned.
959 * @a fence must be a valid fence set up with @a base_fence_init or @a base_fence_import.
960 * Calling this function with a uninitialized fence results in undefined behavior.
962 * @param[out] atom A pre-allocated atom to configure as a fence wait SW atom
963 * @param[in] fence The base fence object to wait on
965 static inline void base_jd_fence_wait_setup_v2(struct base_jd_atom_v2 *atom, struct base_fence *fence)
969 LOCAL_ASSERT(fence->basep.fd >= 0);
970 atom->jc = (uintptr_t) fence;
971 atom->core_req = BASE_JD_REQ_SOFT_FENCE_WAIT;
975 * @brief External resource info initialization.
977 * Sets up an external resource object to reference
978 * a memory allocation and the type of access requested.
980 * @param[in] res The resource object to initialize
981 * @param handle The handle to the imported memory object, must be
982 * obtained by calling @ref base_mem_as_import_handle().
983 * @param access The type of access requested
985 static inline void base_external_resource_init(struct base_external_resource *res, struct base_import_handle handle, base_external_resource_access access)
989 address = handle.basep.handle;
991 LOCAL_ASSERT(res != NULL);
992 LOCAL_ASSERT(0 == (address & LOCAL_PAGE_LSB));
993 LOCAL_ASSERT(access == BASE_EXT_RES_ACCESS_SHARED || access == BASE_EXT_RES_ACCESS_EXCLUSIVE);
995 res->ext_resource = address | (access & LOCAL_PAGE_LSB);
999 * @brief Job chain event code bits
1000 * Defines the bits used to create ::base_jd_event_code
1003 BASE_JD_SW_EVENT_KERNEL = (1u << 15), /**< Kernel side event */
1004 BASE_JD_SW_EVENT = (1u << 14), /**< SW defined event */
1005 BASE_JD_SW_EVENT_SUCCESS = (1u << 13), /**< Event idicates success (SW events only) */
1006 BASE_JD_SW_EVENT_JOB = (0u << 11), /**< Job related event */
1007 BASE_JD_SW_EVENT_BAG = (1u << 11), /**< Bag related event */
1008 BASE_JD_SW_EVENT_INFO = (2u << 11), /**< Misc/info event */
1009 BASE_JD_SW_EVENT_RESERVED = (3u << 11), /**< Reserved event type */
1010 BASE_JD_SW_EVENT_TYPE_MASK = (3u << 11) /**< Mask to extract the type from an event code */
1014 * @brief Job chain event codes
1016 * HW and low-level SW events are represented by event codes.
1017 * The status of jobs which succeeded are also represented by
1018 * an event code (see ::BASE_JD_EVENT_DONE).
1019 * Events are usually reported as part of a ::base_jd_event.
1021 * The event codes are encoded in the following way:
1022 * @li 10:0 - subtype
1024 * @li 13 - SW success (only valid if the SW bit is set)
1025 * @li 14 - SW event (HW event if not set)
1026 * @li 15 - Kernel event (should never be seen in userspace)
1028 * Events are split up into ranges as follows:
1029 * - BASE_JD_EVENT_RANGE_\<description\>_START
1030 * - BASE_JD_EVENT_RANGE_\<description\>_END
1032 * \a code is in \<description\>'s range when:
1033 * - <tt>BASE_JD_EVENT_RANGE_\<description\>_START <= code < BASE_JD_EVENT_RANGE_\<description\>_END </tt>
1035 * Ranges can be asserted for adjacency by testing that the END of the previous
1036 * is equal to the START of the next. This is useful for optimizing some tests
1039 * A limitation is that the last member of this enum must explicitly be handled
1040 * (with an assert-unreachable statement) in switch statements that use
1041 * variables of this type. Otherwise, the compiler warns that we have not
1042 * handled that enum value.
1044 typedef enum base_jd_event_code {
1045 /* HW defined exceptions */
1047 /** Start of HW Non-fault status codes
1049 * @note Obscurely, BASE_JD_EVENT_TERMINATED indicates a real fault,
1050 * because the job was hard-stopped
1052 BASE_JD_EVENT_RANGE_HW_NONFAULT_START = 0,
1054 /* non-fatal exceptions */
1055 BASE_JD_EVENT_NOT_STARTED = 0x00, /**< Can't be seen by userspace, treated as 'previous job done' */
1056 BASE_JD_EVENT_DONE = 0x01,
1057 BASE_JD_EVENT_STOPPED = 0x03, /**< Can't be seen by userspace, becomes TERMINATED, DONE or JOB_CANCELLED */
1058 BASE_JD_EVENT_TERMINATED = 0x04, /**< This is actually a fault status code - the job was hard stopped */
1059 BASE_JD_EVENT_ACTIVE = 0x08, /**< Can't be seen by userspace, jobs only returned on complete/fail/cancel */
1061 /** End of HW Non-fault status codes
1063 * @note Obscurely, BASE_JD_EVENT_TERMINATED indicates a real fault,
1064 * because the job was hard-stopped
1066 BASE_JD_EVENT_RANGE_HW_NONFAULT_END = 0x40,
1068 /** Start of HW fault and SW Error status codes */
1069 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_START = 0x40,
1071 /* job exceptions */
1072 BASE_JD_EVENT_JOB_CONFIG_FAULT = 0x40,
1073 BASE_JD_EVENT_JOB_POWER_FAULT = 0x41,
1074 BASE_JD_EVENT_JOB_READ_FAULT = 0x42,
1075 BASE_JD_EVENT_JOB_WRITE_FAULT = 0x43,
1076 BASE_JD_EVENT_JOB_AFFINITY_FAULT = 0x44,
1077 BASE_JD_EVENT_JOB_BUS_FAULT = 0x48,
1078 BASE_JD_EVENT_INSTR_INVALID_PC = 0x50,
1079 BASE_JD_EVENT_INSTR_INVALID_ENC = 0x51,
1080 BASE_JD_EVENT_INSTR_TYPE_MISMATCH = 0x52,
1081 BASE_JD_EVENT_INSTR_OPERAND_FAULT = 0x53,
1082 BASE_JD_EVENT_INSTR_TLS_FAULT = 0x54,
1083 BASE_JD_EVENT_INSTR_BARRIER_FAULT = 0x55,
1084 BASE_JD_EVENT_INSTR_ALIGN_FAULT = 0x56,
1085 BASE_JD_EVENT_DATA_INVALID_FAULT = 0x58,
1086 BASE_JD_EVENT_TILE_RANGE_FAULT = 0x59,
1087 BASE_JD_EVENT_STATE_FAULT = 0x5A,
1088 BASE_JD_EVENT_OUT_OF_MEMORY = 0x60,
1089 BASE_JD_EVENT_UNKNOWN = 0x7F,
1091 /* GPU exceptions */
1092 BASE_JD_EVENT_DELAYED_BUS_FAULT = 0x80,
1093 BASE_JD_EVENT_SHAREABILITY_FAULT = 0x88,
1095 /* MMU exceptions */
1096 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL1 = 0xC1,
1097 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL2 = 0xC2,
1098 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL3 = 0xC3,
1099 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL4 = 0xC4,
1100 BASE_JD_EVENT_PERMISSION_FAULT = 0xC8,
1101 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL1 = 0xD1,
1102 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL2 = 0xD2,
1103 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL3 = 0xD3,
1104 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL4 = 0xD4,
1105 BASE_JD_EVENT_ACCESS_FLAG = 0xD8,
1107 /* SW defined exceptions */
1108 BASE_JD_EVENT_MEM_GROWTH_FAILED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000,
1109 BASE_JD_EVENT_TIMED_OUT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x001,
1110 BASE_JD_EVENT_JOB_CANCELLED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002,
1111 BASE_JD_EVENT_JOB_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003,
1112 BASE_JD_EVENT_PM_EVENT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x004,
1113 BASE_JD_EVENT_FORCE_REPLAY = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x005,
1115 BASE_JD_EVENT_BAG_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_BAG | 0x003,
1117 /** End of HW fault and SW Error status codes */
1118 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
1120 /** Start of SW Success status codes */
1121 BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | 0x000,
1123 BASE_JD_EVENT_PROGRESS_REPORT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_JOB | 0x000,
1124 BASE_JD_EVENT_BAG_DONE = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_BAG | 0x000,
1125 BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_INFO | 0x000,
1127 /** End of SW Success status codes */
1128 BASE_JD_EVENT_RANGE_SW_SUCCESS_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
1130 /** Start of Kernel-only status codes. Such codes are never returned to user-space */
1131 BASE_JD_EVENT_RANGE_KERNEL_ONLY_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | 0x000,
1132 BASE_JD_EVENT_REMOVED_FROM_NEXT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x000,
1134 /** End of Kernel-only status codes. */
1135 BASE_JD_EVENT_RANGE_KERNEL_ONLY_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_RESERVED | 0x3FF
1136 } base_jd_event_code;
1139 * @brief Event reporting structure
1141 * This structure is used by the kernel driver to report information
1142 * about GPU events. The can either be HW-specific events or low-level
1143 * SW events, such as job-chain completion.
1145 * The event code contains an event type field which can be extracted
1146 * by ANDing with ::BASE_JD_SW_EVENT_TYPE_MASK.
1148 * Based on the event type base_jd_event::data holds:
1149 * @li ::BASE_JD_SW_EVENT_JOB : the offset in the ring-buffer for the completed
1151 * @li ::BASE_JD_SW_EVENT_BAG : The address of the ::base_jd_bag that has
1152 * been completed (ie all contained job-chains have been completed).
1153 * @li ::BASE_JD_SW_EVENT_INFO : base_jd_event::data not used
1155 typedef struct base_jd_event_v2 {
1156 base_jd_event_code event_code; /**< event code */
1157 base_atom_id atom_number; /**< the atom number that has completed */
1158 struct base_jd_udata udata; /**< user data */
1162 * Padding required to ensure that the @ref struct base_dump_cpu_gpu_counters structure fills
1163 * a full cache line.
1166 #define BASE_CPU_GPU_CACHE_LINE_PADDING (36)
1170 * @brief Structure for BASE_JD_REQ_SOFT_DUMP_CPU_GPU_COUNTERS jobs.
1172 * This structure is stored into the memory pointed to by the @c jc field of @ref base_jd_atom.
1174 * This structure must be padded to ensure that it will occupy whole cache lines. This is to avoid
1175 * cases where access to pages containing the structure is shared between cached and un-cached
1176 * memory regions, which would cause memory corruption. Here we set the structure size to be 64 bytes
1177 * which is the cache line for ARM A15 processors.
1180 typedef struct base_dump_cpu_gpu_counters {
1185 u8 padding[BASE_CPU_GPU_CACHE_LINE_PADDING];
1186 } base_dump_cpu_gpu_counters;
1190 /** @} end group base_user_api_job_dispatch */
1192 #define GPU_MAX_JOB_SLOTS 16
1195 * @page page_base_user_api_gpuprops User-side Base GPU Property Query API
1197 * The User-side Base GPU Property Query API encapsulates two
1200 * - @ref base_user_api_gpuprops_dyn "Dynamic GPU Properties"
1201 * - @ref base_plat_config_gpuprops "Base Platform Config GPU Properties"
1203 * There is a related third module outside of Base, which is owned by the MIDG
1205 * - @ref gpu_props_static "Midgard Compile-time GPU Properties"
1207 * Base only deals with properties that vary between different Midgard
1208 * implementations - the Dynamic GPU properties and the Platform Config
1211 * For properties that are constant for the Midgard Architecture, refer to the
1212 * MIDG module. However, we will discuss their relevance here <b>just to
1213 * provide background information.</b>
1215 * @section sec_base_user_api_gpuprops_about About the GPU Properties in Base and MIDG modules
1217 * The compile-time properties (Platform Config, Midgard Compile-time
1218 * properties) are exposed as pre-processor macros.
1220 * Complementing the compile-time properties are the Dynamic GPU
1221 * Properties, which act as a conduit for the Midgard Configuration
1224 * In general, the dynamic properties are present to verify that the platform
1225 * has been configured correctly with the right set of Platform Config
1226 * Compile-time Properties.
1228 * As a consistant guide across the entire DDK, the choice for dynamic or
1229 * compile-time should consider the following, in order:
1230 * -# Can the code be written so that it doesn't need to know the
1231 * implementation limits at all?
1232 * -# If you need the limits, get the information from the Dynamic Property
1233 * lookup. This should be done once as you fetch the context, and then cached
1234 * as part of the context data structure, so it's cheap to access.
1235 * -# If there's a clear and arguable inefficiency in using Dynamic Properties,
1236 * then use a Compile-Time Property (Platform Config, or Midgard Compile-time
1237 * property). Examples of where this might be sensible follow:
1238 * - Part of a critical inner-loop
1239 * - Frequent re-use throughout the driver, causing significant extra load
1240 * instructions or control flow that would be worthwhile optimizing out.
1242 * We cannot provide an exhaustive set of examples, neither can we provide a
1243 * rule for every possible situation. Use common sense, and think about: what
1244 * the rest of the driver will be doing; how the compiler might represent the
1245 * value if it is a compile-time constant; whether an OEM shipping multiple
1246 * devices would benefit much more from a single DDK binary, instead of
1247 * insignificant micro-optimizations.
1249 * @section sec_base_user_api_gpuprops_dyn Dynamic GPU Properties
1251 * Dynamic GPU properties are presented in two sets:
1252 * -# the commonly used properties in @ref base_gpu_props, which have been
1253 * unpacked from GPU register bitfields.
1254 * -# The full set of raw, unprocessed properties in @ref gpu_raw_gpu_props
1255 * (also a member of @ref base_gpu_props). All of these are presented in
1256 * the packed form, as presented by the GPU registers themselves.
1258 * @usecase The raw properties in @ref gpu_raw_gpu_props are necessary to
1259 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device
1260 * behaving differently?". In this case, all information about the
1261 * configuration is potentially useful, but it <b>does not need to be processed
1262 * by the driver</b>. Instead, the raw registers can be processed by the Mali
1263 * Tools software on the host PC.
1265 * The properties returned extend the Midgard Configuration Discovery
1266 * registers. For example, GPU clock speed is not specified in the Midgard
1267 * Architecture, but is <b>necessary for OpenCL's clGetDeviceInfo() function</b>.
1269 * The GPU properties are obtained by a call to
1270 * _mali_base_get_gpu_props(). This simply returns a pointer to a const
1271 * base_gpu_props structure. It is constant for the life of a base
1272 * context. Multiple calls to _mali_base_get_gpu_props() to a base context
1273 * return the same pointer to a constant structure. This avoids cache pollution
1274 * of the common data.
1276 * This pointer must not be freed, because it does not point to the start of a
1277 * region allocated by the memory allocator; instead, just close the @ref
1281 * @section sec_base_user_api_gpuprops_config Platform Config Compile-time Properties
1283 * The Platform Config File sets up gpu properties that are specific to a
1284 * certain platform. Properties that are 'Implementation Defined' in the
1285 * Midgard Architecture spec are placed here.
1287 * @note Reference configurations are provided for Midgard Implementations, such as
1288 * the Mali-T600 family. The customer need not repeat this information, and can select one of
1289 * these reference configurations. For example, VA_BITS, PA_BITS and the
1290 * maximum number of samples per pixel might vary between Midgard Implementations, but
1291 * \b not for platforms using the Mali-T604. This information is placed in
1292 * the reference configuration files.
1294 * The System Integrator creates the following structure:
1296 * - platform_XYZ/plat
1297 * - platform_XYZ/plat/plat_config.h
1299 * They then edit plat_config.h, using the example plat_config.h files as a
1302 * At the very least, the customer must set @ref CONFIG_GPU_CORE_TYPE, and will
1303 * receive a helpful \#error message if they do not do this correctly. This
1304 * selects the Reference Configuration for the Midgard Implementation. The rationale
1305 * behind this decision (against asking the customer to write \#include
1306 * <gpus/mali_t600.h> in their plat_config.h) is as follows:
1307 * - This mechanism 'looks' like a regular config file (such as Linux's
1309 * - It is difficult to get wrong in a way that will produce strange build
1311 * - They need not know where the mali_t600.h, other_midg_gpu.h etc. files are stored - and
1312 * so they won't accidentally pick another file with 'mali_t600' in its name
1313 * - When the build doesn't work, the System Integrator may think the DDK is
1314 * doesn't work, and attempt to fix it themselves:
1315 * - For the @ref CONFIG_GPU_CORE_TYPE mechanism, the only way to get past the
1316 * error is to set @ref CONFIG_GPU_CORE_TYPE, and this is what the \#error tells
1318 * - For a \#include mechanism, checks must still be made elsewhere, which the
1319 * System Integrator may try working around by setting \#defines (such as
1320 * VA_BITS) themselves in their plat_config.h. In the worst case, they may
1321 * set the prevention-mechanism \#define of
1322 * "A_CORRECT_MIDGARD_CORE_WAS_CHOSEN".
1323 * - In this case, they would believe they are on the right track, because
1324 * the build progresses with their fix, but with errors elsewhere.
1326 * However, there is nothing to prevent the customer using \#include to organize
1327 * their own configurations files hierarchically.
1329 * The mechanism for the header file processing is as follows:
1332 digraph plat_config_mechanism {
1341 rank = same; ordering = out;
1343 "gpu/mali_gpu_props.h";
1344 "base/midg_gpus/mali_t600.h";
1345 "base/midg_gpus/other_midg_gpu.h";
1347 { rank = same; "plat/plat_config.h"; }
1350 "gpu/mali_gpu.h" [ shape=box ];
1351 gpu_chooser [ label="" style="invisible" width=0 height=0 fixedsize=true ];
1352 select_gpu [ label="Mali-T600 | Other\n(select_gpu.h)" shape=polygon,sides=4,distortion=0.25 width=3.3 height=0.99 fixedsize=true ] ;
1355 { rank = same; "plat/plat_config.h"; }
1356 { rank = same; "mali_base.h"; }
1358 "mali_base.h" -> "gpu/mali_gpu.h" -> "gpu/mali_gpu_props.h";
1359 "mali_base.h" -> "plat/plat_config.h" ;
1360 "mali_base.h" -> select_gpu ;
1362 "plat/plat_config.h" -> gpu_chooser [style="dotted,bold" dir=none weight=4] ;
1363 gpu_chooser -> select_gpu [style="dotted,bold"] ;
1365 select_gpu -> "base/midg_gpus/mali_t600.h" ;
1366 select_gpu -> "base/midg_gpus/other_midg_gpu.h" ;
1371 * @section sec_base_user_api_gpuprops_kernel Kernel Operation
1373 * During Base Context Create time, user-side makes a single kernel call:
1374 * - A call to fill user memory with GPU information structures
1376 * The kernel-side will fill the provided the entire processed @ref base_gpu_props
1377 * structure, because this information is required in both
1378 * user and kernel side; it does not make sense to decode it twice.
1380 * Coherency groups must be derived from the bitmasks, but this can be done
1381 * kernel side, and just once at kernel startup: Coherency groups must already
1382 * be known kernel-side, to support chains that specify a 'Only Coherent Group'
1383 * SW requirement, or 'Only Coherent Group with Tiler' SW requirement.
1385 * @section sec_base_user_api_gpuprops_cocalc Coherency Group calculation
1386 * Creation of the coherent group data is done at device-driver startup, and so
1387 * is one-time. This will most likely involve a loop with CLZ, shifting, and
1388 * bit clearing on the L2_PRESENT mask, depending on whether the
1389 * system is L2 Coherent. The number of shader cores is done by a
1390 * population count, since faulty cores may be disabled during production,
1391 * producing a non-contiguous mask.
1393 * The memory requirements for this algoirthm can be determined either by a u64
1394 * population count on the L2_PRESENT mask (a LUT helper already is
1395 * requried for the above), or simple assumption that there can be no more than
1396 * 16 coherent groups, since core groups are typically 4 cores.
1400 * @addtogroup base_user_api_gpuprops User-side Base GPU Property Query APIs
1405 * @addtogroup base_user_api_gpuprops_dyn Dynamic HW Properties
1409 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
1411 #define BASE_MAX_COHERENT_GROUPS 16
1413 struct mali_base_gpu_core_props {
1415 * Product specific value.
1420 * Status of the GPU release.
1421 * No defined values, but starts at 0 and increases by one for each release
1422 * status (alpha, beta, EAC, etc.).
1423 * 4 bit values (0-15).
1428 * Minor release number of the GPU. "P" part of an "RnPn" release number.
1429 * 8 bit values (0-255).
1434 * Major release number of the GPU. "R" part of an "RnPn" release number.
1435 * 4 bit values (0-15).
1442 * @usecase GPU clock speed is not specified in the Midgard Architecture, but is
1443 * <b>necessary for OpenCL's clGetDeviceInfo() function</b>.
1448 * @usecase GPU clock max/min speed is required for computing best/worst case
1449 * in tasks as job scheduling ant irq_throttling. (It is not specified in the
1450 * Midgard Architecture).
1452 u32 gpu_freq_khz_max;
1453 u32 gpu_freq_khz_min;
1456 * Size of the shader program counter, in bits.
1458 u32 log2_program_counter_size;
1461 * TEXTURE_FEATURES_x registers, as exposed by the GPU. This is a
1462 * bitpattern where a set bit indicates that the format is supported.
1464 * Before using a texture format, it is recommended that the corresponding
1467 u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
1470 * Theoretical maximum memory available to the GPU. It is unlikely that a
1471 * client will be able to allocate all of this memory for their own
1472 * purposes, but this at least provides an upper bound on the memory
1473 * available to the GPU.
1475 * This is required for OpenCL's clGetDeviceInfo() call when
1476 * CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL GPU devices. The
1477 * client will not be expecting to allocate anywhere near this value.
1479 u64 gpu_available_memory_size;
1484 * More information is possible - but associativity and bus width are not
1485 * required by upper-level apis.
1487 struct mali_base_gpu_l2_cache_props {
1490 u8 num_l2_slices; /* Number of L2C slices. 1 or higher */
1494 struct mali_base_gpu_tiler_props {
1495 u32 bin_size_bytes; /* Max is 4*2^15 */
1496 u32 max_active_levels; /* Max is 2^15 */
1500 * GPU threading system details.
1502 struct mali_base_gpu_thread_props {
1503 u32 max_threads; /* Max. number of threads per core */
1504 u32 max_workgroup_size; /* Max. number of threads per workgroup */
1505 u32 max_barrier_size; /* Max. number of threads that can synchronize on a simple barrier */
1506 u16 max_registers; /* Total size [1..65535] of the register file available per core. */
1507 u8 max_task_queue; /* Max. tasks [1..255] which may be sent to a core before it becomes blocked. */
1508 u8 max_thread_group_split; /* Max. allowed value [1..15] of the Thread Group Split field. */
1509 u8 impl_tech; /* 0 = Not specified, 1 = Silicon, 2 = FPGA, 3 = SW Model/Emulation */
1514 * @brief descriptor for a coherent group
1516 * \c core_mask exposes all cores in that coherent group, and \c num_cores
1517 * provides a cached population-count for that mask.
1519 * @note Whilst all cores are exposed in the mask, not all may be available to
1520 * the application, depending on the Kernel Power policy.
1522 * @note if u64s must be 8-byte aligned, then this structure has 32-bits of wastage.
1524 struct mali_base_gpu_coherent_group {
1525 u64 core_mask; /**< Core restriction mask required for the group */
1526 u16 num_cores; /**< Number of cores in the group */
1531 * @brief Coherency group information
1533 * Note that the sizes of the members could be reduced. However, the \c group
1534 * member might be 8-byte aligned to ensure the u64 core_mask is 8-byte
1535 * aligned, thus leading to wastage if the other members sizes were reduced.
1537 * The groups are sorted by core mask. The core masks are non-repeating and do
1540 struct mali_base_gpu_coherent_group_info {
1544 * Number of core groups (coherent or not) in the GPU. Equivalent to the number of L2 Caches.
1546 * The GPU Counter dumping writes 2048 bytes per core group, regardless of
1547 * whether the core groups are coherent or not. Hence this member is needed
1548 * to calculate how much memory is required for dumping.
1550 * @note Do not use it to work out how many valid elements are in the
1551 * group[] member. Use num_groups instead.
1553 u32 num_core_groups;
1556 * Coherency features of the memory, accessed by @ref gpu_mem_features
1564 * Descriptors of coherent groups
1566 struct mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS];
1570 * A complete description of the GPU's Hardware Configuration Discovery
1573 * The information is presented inefficiently for access. For frequent access,
1574 * the values should be better expressed in an unpacked form in the
1575 * base_gpu_props structure.
1577 * @usecase The raw properties in @ref gpu_raw_gpu_props are necessary to
1578 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device
1579 * behaving differently?". In this case, all information about the
1580 * configuration is potentially useful, but it <b>does not need to be processed
1581 * by the driver</b>. Instead, the raw registers can be processed by the Mali
1582 * Tools software on the host PC.
1585 struct gpu_raw_gpu_props {
1589 u64 unused_1; /* keep for backward compatibility */
1592 u32 suspend_size; /* API 8.2+ */
1599 u32 js_features[GPU_MAX_JOB_SLOTS];
1601 u32 texture_features[3];
1605 u32 thread_max_threads;
1606 u32 thread_max_workgroup_size;
1607 u32 thread_max_barrier_size;
1608 u32 thread_features;
1611 * Note: This is the _selected_ coherency mode rather than the
1612 * available modes as exposed in the coherency_features register.
1618 * Return structure for _mali_base_get_gpu_props().
1620 * NOTE: the raw_props member in this datastructure contains the register
1621 * values from which the value of the other members are derived. The derived
1622 * members exist to allow for efficient access and/or shielding the details
1623 * of the layout of the registers.
1626 typedef struct mali_base_gpu_props {
1627 struct mali_base_gpu_core_props core_props;
1628 struct mali_base_gpu_l2_cache_props l2_props;
1629 u64 unused_1; /* keep for backwards compatibility */
1630 struct mali_base_gpu_tiler_props tiler_props;
1631 struct mali_base_gpu_thread_props thread_props;
1633 /** This member is large, likely to be 128 bytes */
1634 struct gpu_raw_gpu_props raw_props;
1636 /** This must be last member of the structure */
1637 struct mali_base_gpu_coherent_group_info coherency_info;
1640 /** @} end group base_user_api_gpuprops_dyn */
1642 /** @} end group base_user_api_gpuprops */
1645 * @addtogroup base_user_api_core User-side Base core APIs
1650 * \enum base_context_create_flags
1652 * Flags to pass to ::base_context_init.
1653 * Flags can be ORed together to enable multiple things.
1655 * These share the same space as BASEP_CONTEXT_FLAG_*, and so must
1656 * not collide with them.
1658 enum base_context_create_flags {
1660 BASE_CONTEXT_CREATE_FLAG_NONE = 0,
1662 /** Base context is embedded in a cctx object (flag used for CINSTR software counter macros) */
1663 BASE_CONTEXT_CCTX_EMBEDDED = (1u << 0),
1665 /** Base context is a 'System Monitor' context for Hardware counters.
1667 * One important side effect of this is that job submission is disabled. */
1668 BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED = (1u << 1)
1672 * Bitpattern describing the ::base_context_create_flags that can be passed to base_context_init()
1674 #define BASE_CONTEXT_CREATE_ALLOWED_FLAGS \
1675 (((u32)BASE_CONTEXT_CCTX_EMBEDDED) | \
1676 ((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED))
1679 * Bitpattern describing the ::base_context_create_flags that can be passed to the kernel
1681 #define BASE_CONTEXT_CREATE_KERNEL_FLAGS \
1682 ((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED)
1685 * Private flags used on the base context
1687 * These start at bit 31, and run down to zero.
1689 * They share the same space as @ref base_context_create_flags, and so must
1690 * not collide with them.
1692 /** Private flag tracking whether job descriptor dumping is disabled */
1693 #define BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED ((u32)(1 << 31))
1695 /** @} end group base_user_api_core */
1697 /** @} end group base_user_api */
1700 * @addtogroup base_plat_config_gpuprops Base Platform Config GPU Properties
1703 * C Pre-processor macros are exposed here to do with Platform
1707 * - GPU Properties that are constant on a particular Midgard Family
1708 * Implementation e.g. Maximum samples per pixel on Mali-T600.
1709 * - General platform config for the GPU, such as the GPU major and minor
1713 /** @} end group base_plat_config_gpuprops */
1716 * @addtogroup base_api Base APIs
1721 * @brief The payload for a replay job. This must be in GPU memory.
1723 typedef struct base_jd_replay_payload {
1725 * Pointer to the first entry in the base_jd_replay_jc list. These
1726 * will be replayed in @b reverse order (so that extra ones can be added
1727 * to the head in future soft jobs without affecting this soft job)
1732 * Pointer to the fragment job chain.
1737 * Pointer to the tiler heap free FBD field to be modified.
1739 u64 tiler_heap_free;
1742 * Hierarchy mask for the replayed fragment jobs. May be zero.
1744 u16 fragment_hierarchy_mask;
1747 * Hierarchy mask for the replayed tiler jobs. May be zero.
1749 u16 tiler_hierarchy_mask;
1752 * Default weight to be used for hierarchy levels not in the original
1755 u32 hierarchy_default_weight;
1758 * Core requirements for the tiler job chain
1760 base_jd_core_req tiler_core_req;
1763 * Core requirements for the fragment job chain
1765 base_jd_core_req fragment_core_req;
1766 } base_jd_replay_payload;
1768 #ifdef BASE_LEGACY_UK10_2_SUPPORT
1769 typedef struct base_jd_replay_payload_uk10_2 {
1772 u64 tiler_heap_free;
1773 u16 fragment_hierarchy_mask;
1774 u16 tiler_hierarchy_mask;
1775 u32 hierarchy_default_weight;
1777 u16 fragment_core_req;
1779 } base_jd_replay_payload_uk10_2;
1780 #endif /* BASE_LEGACY_UK10_2_SUPPORT */
1783 * @brief An entry in the linked list of job chains to be replayed. This must
1786 typedef struct base_jd_replay_jc {
1788 * Pointer to next entry in the list. A setting of NULL indicates the
1794 * Pointer to the job chain.
1798 } base_jd_replay_jc;
1800 /* Maximum number of jobs allowed in a fragment chain in the payload of a
1802 #define BASE_JD_REPLAY_F_CHAIN_JOB_LIMIT 256
1804 /** @} end group base_api */
1806 typedef struct base_profiling_controls {
1807 u32 profiling_controls[FBDUMP_CONTROL_MAX];
1808 } base_profiling_controls;
1810 #endif /* _BASE_KERNEL_H_ */