1 /* arch/arm/mach-rk29/gpio.c
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
26 #include <linux/syscore_ops.h>
28 #include <mach/hardware.h>
29 #include <mach/gpio.h>
31 #include <mach/iomux.h>
33 #include <asm/mach/irq.h>
35 #ifdef CONFIG_ARCH_RK30
36 #define MAX_PIN RK30_PIN6_PB7
38 #ifdef CONFIG_ARCH_RK2928
39 #define MAX_PIN RK2928_PIN3_PD7
42 #define to_rk30_gpio_bank(c) container_of(c, struct rk30_gpio_bank, chip)
44 struct rk30_gpio_bank {
45 struct gpio_chip chip;
48 void __iomem *regbase; /* Base of register bank */
55 static struct lock_class_key gpio_lock_class;
57 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
58 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
59 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset);
60 static int rk30_gpiolib_direction_output(struct gpio_chip *chip,unsigned offset, int val);
61 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset);
62 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable);
63 static int rk30_gpiolib_to_irq(struct gpio_chip *chip,unsigned offset);
65 #ifdef CONFIG_ARCH_RK30
66 #define RK30_GPIO_BANK(ID) \
69 .label = "gpio" #ID, \
70 .direction_input = rk30_gpiolib_direction_input, \
71 .direction_output = rk30_gpiolib_direction_output, \
72 .get = rk30_gpiolib_get, \
73 .set = rk30_gpiolib_set, \
74 .pull_updown = rk30_gpiolib_pull_updown, \
75 .dbg_show = rk30_gpiolib_dbg_show, \
76 .to_irq = rk30_gpiolib_to_irq, \
77 .base = ID < 6 ? PIN_BASE + ID*NUM_GROUP : PIN_BASE + 5*NUM_GROUP, \
78 .ngpio = ID < 6 ? NUM_GROUP : 16, \
81 .irq = IRQ_GPIO##ID, \
82 .regbase = (unsigned char __iomem *) RK30_GPIO##ID##_BASE, \
85 #ifdef CONFIG_ARCH_RK2928
86 #define RK30_GPIO_BANK(ID) \
89 .label = "gpio" #ID, \
90 .direction_input = rk30_gpiolib_direction_input, \
91 .direction_output = rk30_gpiolib_direction_output, \
92 .get = rk30_gpiolib_get, \
93 .set = rk30_gpiolib_set, \
94 .pull_updown = rk30_gpiolib_pull_updown, \
95 .dbg_show = rk30_gpiolib_dbg_show, \
96 .to_irq = rk30_gpiolib_to_irq, \
97 .base = ID < 6 ? PIN_BASE + ID*NUM_GROUP : PIN_BASE + 5*NUM_GROUP, \
98 .ngpio = ID < 6 ? NUM_GROUP : 16, \
101 .irq = IRQ_GPIO##ID, \
102 .regbase = (unsigned char __iomem *) RK2928_GPIO##ID##_BASE, \
106 static struct rk30_gpio_bank rk30_gpio_banks[] = {
111 #ifdef CONFIG_ARCH_RK30
117 static inline void rk30_gpio_bit_op(void __iomem *regbase, unsigned int offset, u32 bit, unsigned char flag)
119 u32 val = __raw_readl(regbase + offset);
124 __raw_writel(val, regbase + offset);
127 static inline struct gpio_chip *pin_to_gpio_chip(unsigned pin)
129 if (pin < PIN_BASE || pin > MAX_PIN)
134 if (likely(pin < ARRAY_SIZE(rk30_gpio_banks)))
135 return &(rk30_gpio_banks[pin].chip);
139 static inline unsigned gpio_to_bit(unsigned gpio)
142 return 1u << (gpio % NUM_GROUP);
145 static inline unsigned offset_to_bit(unsigned offset)
150 static void GPIOSetPinLevel(void __iomem *regbase, unsigned int bit, eGPIOPinLevel_t level)
152 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, 1);
153 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DR, bit, level);
156 static int GPIOGetPinLevel(void __iomem *regbase, unsigned int bit)
158 return ((__raw_readl(regbase + GPIO_EXT_PORT) & bit) != 0);
161 static void GPIOSetPinDirection(void __iomem *regbase, unsigned int bit, eGPIOPinDirection_t direction)
163 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, direction);
164 /* Enable debounce may halt cpu on wfi, disable it by default */
165 //rk30_gpio_bit_op(regbase, GPIO_DEBOUNCE, bit, 1);
168 static void GPIOEnableIntr(void __iomem *regbase, unsigned int bit)
170 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 1);
173 static void GPIODisableIntr(void __iomem *regbase, unsigned int bit)
175 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 0);
178 static void GPIOAckIntr(void __iomem *regbase, unsigned int bit)
180 rk30_gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);
183 static void GPIOSetIntrType(void __iomem *regbase, unsigned int bit, eGPIOIntType_t type)
187 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
188 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
191 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
192 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
194 case GPIOEdgelFalling:
195 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
196 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
198 case GPIOEdgelRising:
199 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
200 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
205 static int rk30_gpio_irq_set_type(struct irq_data *d, unsigned int type)
207 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
208 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
209 eGPIOIntType_t int_type;
213 case IRQ_TYPE_EDGE_RISING:
214 int_type = GPIOEdgelRising;
216 case IRQ_TYPE_EDGE_FALLING:
217 int_type = GPIOEdgelFalling;
219 case IRQ_TYPE_LEVEL_HIGH:
220 int_type = GPIOLevelHigh;
222 case IRQ_TYPE_LEVEL_LOW:
223 int_type = GPIOLevelLow;
229 spin_lock_irqsave(&bank->lock, flags);
230 //ÉèÖÃΪÖжÏ֮ǰ£¬±ØÐëÏÈÉèÖÃΪÊäÈë״̬
231 GPIOSetPinDirection(bank->regbase, bit, GPIO_IN);
232 GPIOSetIntrType(bank->regbase, bit, int_type);
233 spin_unlock_irqrestore(&bank->lock, flags);
235 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
236 __irq_set_handler_locked(d->irq, handle_level_irq);
237 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
238 __irq_set_handler_locked(d->irq, handle_edge_irq);
243 static int rk30_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
245 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
246 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
249 spin_lock_irqsave(&bank->lock, flags);
251 bank->suspend_wakeup |= bit;
253 bank->suspend_wakeup &= ~bit;
254 spin_unlock_irqrestore(&bank->lock, flags);
259 static void rk30_gpio_irq_unmask(struct irq_data *d)
261 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
262 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
265 spin_lock_irqsave(&bank->lock, flags);
266 GPIOEnableIntr(bank->regbase, bit);
267 spin_unlock_irqrestore(&bank->lock, flags);
270 static void rk30_gpio_irq_mask(struct irq_data *d)
272 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
273 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
276 spin_lock_irqsave(&bank->lock, flags);
277 GPIODisableIntr(bank->regbase, bit);
278 spin_unlock_irqrestore(&bank->lock, flags);
281 static void rk30_gpio_irq_ack(struct irq_data *d)
283 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
284 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
286 GPIOAckIntr(bank->regbase, bit);
289 static int rk30_gpiolib_direction_output(struct gpio_chip *chip, unsigned offset, int val)
291 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
292 u32 bit = offset_to_bit(offset);
295 spin_lock_irqsave(&bank->lock, flags);
296 GPIOSetPinDirection(bank->regbase, bit, GPIO_OUT);
297 GPIOSetPinLevel(bank->regbase, bit, val);
298 spin_unlock_irqrestore(&bank->lock, flags);
302 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset)
304 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
307 spin_lock_irqsave(&bank->lock, flags);
308 GPIOSetPinDirection(bank->regbase, offset_to_bit(offset), GPIO_IN);
309 spin_unlock_irqrestore(&bank->lock, flags);
314 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset)
316 return GPIOGetPinLevel(to_rk30_gpio_bank(chip)->regbase, offset_to_bit(offset));
319 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
321 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
324 spin_lock_irqsave(&bank->lock, flags);
325 GPIOSetPinLevel(bank->regbase, offset_to_bit(offset), val);
326 spin_unlock_irqrestore(&bank->lock, flags);
329 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable)
331 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
334 spin_lock_irqsave(&bank->lock, flags);
335 #ifdef CONFIG_ARCH_RK30
337 rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0H_PULL + bank->id * 8, (1<<offset) | offset_to_bit(offset-16), !enable);
339 rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0L_PULL + bank->id * 8, (1<<(offset+16)) | offset_to_bit(offset), !enable);
341 #ifdef CONFIG_ARCH_RK2928
343 rk30_gpio_bit_op((void *__iomem) RK2928_GRF_BASE, GRF_GPIO0H_PULL + bank->id * 8, (1<<offset) | offset_to_bit(offset-16), !enable);
345 rk30_gpio_bit_op((void *__iomem) RK2928_GRF_BASE, GRF_GPIO0L_PULL + bank->id * 8, (1<<(offset+16)) | offset_to_bit(offset), !enable);
347 spin_unlock_irqrestore(&bank->lock, flags);
352 static int rk30_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
354 return chip->base + offset;
357 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
362 for (i = 0; i < chip->ngpio; i++) {
363 unsigned pin = chip->base + i;
364 struct gpio_chip *chip = pin_to_gpioChip(pin);
365 u32 bit = pin_to_bit(pin);
366 const char *gpio_label;
371 gpio_label = gpiochip_is_requested(chip, i);
373 seq_printf(s, "[%s] GPIO%s%d: ",
374 gpio_label, chip->label, i);
378 seq_printf(s, "!chip || !bit\t");
382 GPIOSetPinDirection(chip,bit,GPIO_IN);
383 seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,bit));
390 static void rk30_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
392 struct rk30_gpio_bank *bank = irq_get_handler_data(irq);
393 struct irq_chip *chip = irq_desc_get_chip(desc);
397 unsigned unmasked = 0;
399 chained_irq_enter(chip, desc);
401 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
402 ilr = __raw_readl(bank->regbase + GPIO_INTTYPE_LEVEL);
404 gpio_irq = gpio_to_irq(bank->chip.base);
408 /* if gpio is edge triggered, clear condition
409 * before executing the hander so that we don't
412 if (ilr & (1 << pin)) {
414 chained_irq_exit(chip, desc);
417 generic_handle_irq(gpio_irq + pin);
422 chained_irq_exit(chip, desc);
425 static struct irq_chip rk30_gpio_irq_chip = {
427 .irq_ack = rk30_gpio_irq_ack,
428 .irq_disable = rk30_gpio_irq_mask,
429 .irq_mask = rk30_gpio_irq_mask,
430 .irq_unmask = rk30_gpio_irq_unmask,
431 .irq_set_type = rk30_gpio_irq_set_type,
432 .irq_set_wake = rk30_gpio_irq_set_wake,
435 void __init rk30_gpio_init(void)
437 unsigned int i, j, pin;
438 struct rk30_gpio_bank *bank;
440 bank = rk30_gpio_banks;
443 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++, bank++) {
444 spin_lock_init(&bank->lock);
445 bank->clk = clk_get(NULL, bank->chip.label);
446 clk_enable(bank->clk);
447 gpiochip_add(&bank->chip);
449 __raw_writel(0, bank->regbase + GPIO_INTEN);
450 for (j = 0; j < 32; j++) {
451 unsigned int irq = gpio_to_irq(pin);
454 irq_set_lockdep_class(irq, &gpio_lock_class);
455 irq_set_chip_data(irq, bank);
456 irq_set_chip_and_handler(irq, &rk30_gpio_irq_chip, handle_level_irq);
457 set_irq_flags(irq, IRQF_VALID);
461 irq_set_handler_data(bank->irq, bank);
462 irq_set_chained_handler(bank->irq, rk30_gpio_irq_handler);
464 printk("%s: %d gpio irqs in %d banks\n", __func__, pin - PIN_BASE, ARRAY_SIZE(rk30_gpio_banks));
468 __weak void rk30_setgpio_suspend_board(void)
472 __weak void rk30_setgpio_resume_board(void)
476 static int rk30_gpio_suspend(void)
480 rk30_setgpio_suspend_board();
482 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
483 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
485 bank->saved_wakeup = __raw_readl(bank->regbase + GPIO_INTEN);
486 __raw_writel(bank->suspend_wakeup, bank->regbase + GPIO_INTEN);
488 if (!bank->suspend_wakeup)
489 clk_disable(bank->clk);
495 static void rk30_gpio_resume(void)
499 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
500 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
503 if (!bank->suspend_wakeup)
504 clk_enable(bank->clk);
506 /* keep enable for resume irq */
507 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
508 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->regbase + GPIO_INTEN);
511 rk30_setgpio_resume_board();
514 static struct syscore_ops rk30_gpio_syscore_ops = {
515 .suspend = rk30_gpio_suspend,
516 .resume = rk30_gpio_resume,
519 static int __init rk30_gpio_sysinit(void)
521 register_syscore_ops(&rk30_gpio_syscore_ops);
525 arch_initcall(rk30_gpio_sysinit);