drivers/devfreq/rockchip_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/arm-smccc.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/devfreq.h>
  19 #include <linux/devfreq-event.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_opp.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/rwsem.h>
  27 #include <linux/slab.h>
  28 #include <linux/suspend.h>
  29
  30 #include <soc/rockchip/rkfb_dmc.h>
  31 #include <soc/rockchip/rockchip_sip.h>
  32
  33 struct dram_timing {
  34         unsigned int ddr3_speed_bin;
  35         unsigned int pd_idle;
  36         unsigned int sr_idle;
  37         unsigned int sr_mc_gate_idle;
  38         unsigned int srpd_lite_idle;
  39         unsigned int standby_idle;
  40         unsigned int dram_dll_dis_freq;
  41         unsigned int phy_dll_dis_freq;
  42         unsigned int ddr3_odt_dis_freq;
  43         unsigned int ddr3_drv;
  44         unsigned int ddr3_odt;
  45         unsigned int phy_ddr3_ca_drv;
  46         unsigned int phy_ddr3_dq_drv;
  47         unsigned int phy_ddr3_odt;
  48         unsigned int lpddr3_odt_dis_freq;
  49         unsigned int lpddr3_drv;
  50         unsigned int lpddr3_odt;
  51         unsigned int phy_lpddr3_ca_drv;
  52         unsigned int phy_lpddr3_dq_drv;
  53         unsigned int phy_lpddr3_odt;
  54         unsigned int lpddr4_odt_dis_freq;
  55         unsigned int lpddr4_drv;
  56         unsigned int lpddr4_dq_odt;
  57         unsigned int lpddr4_ca_odt;
  58         unsigned int phy_lpddr4_ca_drv;
  59         unsigned int phy_lpddr4_ck_cs_drv;
  60         unsigned int phy_lpddr4_dq_drv;
  61         unsigned int phy_lpddr4_odt;
  62 };
  63
  64 struct rockchip_dmcfreq {
  65         struct device *dev;
  66         struct devfreq *devfreq;
  67         struct devfreq_simple_ondemand_data ondemand_data;
  68         struct clk *dmc_clk;
  69         struct devfreq_event_dev *edev;
  70         struct mutex lock; /* scaling frequency lock */
  71         struct dram_timing *timing;
  72         struct regulator *vdd_center;
  73         unsigned long rate, target_rate;
  74         unsigned long volt, target_volt;
  75 };
  76
  77 static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
  78                                    u32 flags)
  79 {
  80         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  81         struct dev_pm_opp *opp;
  82         unsigned long old_clk_rate = dmcfreq->rate;
  83         unsigned long temp_rate, target_volt, target_rate;
  84         int err;
  85
  86         rcu_read_lock();
  87         opp = devfreq_recommended_opp(dev, freq, flags);
  88         if (IS_ERR(opp)) {
  89                 rcu_read_unlock();
  90                 return PTR_ERR(opp);
  91         }
  92
  93         temp_rate = dev_pm_opp_get_freq(opp);
  94         target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
  95         if ((long)target_rate <= 0)
  96                 target_rate = temp_rate;
  97         target_volt = dev_pm_opp_get_voltage(opp);
  98
  99         rcu_read_unlock();
 100
 101         if (dmcfreq->rate == target_rate) {
 102                 if (dmcfreq->volt == target_volt)
 103                         return 0;
 104                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 105                                             INT_MAX);
 106                 if (err) {
 107                         dev_err(dev, "Cannot set voltage %lu uV\n",
 108                                 target_volt);
 109                         goto out;
 110                 }
 111         }
 112
 113         mutex_lock(&dmcfreq->lock);
 114
 115         /*
 116          * If frequency scaling from low to high, adjust voltage first.
 117          * If frequency scaling from high to low, adjust frequency first.
 118          */
 119         if (old_clk_rate < target_rate) {
 120                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 121                                             INT_MAX);
 122                 if (err) {
 123                         dev_err(dev, "Cannot set voltage %lu uV\n",
 124                                 target_volt);
 125                         goto out;
 126                 }
 127         }
 128
 129         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 130         if (err) {
 131                 dev_err(dev, "Cannot set frequency %lu (%d)\n",
 132                         target_rate, err);
 133                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 134                                       INT_MAX);
 135                 goto out;
 136         }
 137
 138         /*
 139          * Check the dpll rate,
 140          * There only two result we will get,
 141          * 1. Ddr frequency scaling fail, we still get the old rate.
 142          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 143          */
 144         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 145
 146         /* If get the incorrect rate, set voltage to old value. */
 147         if (dmcfreq->rate != target_rate) {
 148                 dev_err(dev, "Get wrong frequency, Request %lu, Current %lu\n",
 149                         target_rate, dmcfreq->rate);
 150                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 151                                       INT_MAX);
 152                 goto out;
 153         } else if (old_clk_rate > target_rate) {
 154                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 155                                             INT_MAX);
 156                 if (err) {
 157                         dev_err(dev, "Cannot set vol %lu uV\n", target_volt);
 158                         goto out;
 159                 }
 160         }
 161
 162         dmcfreq->volt = target_volt;
 163 out:
 164         mutex_unlock(&dmcfreq->lock);
 165         return err;
 166 }
 167
 168 static int rockchip_dmcfreq_get_dev_status(struct device *dev,
 169                                            struct devfreq_dev_status *stat)
 170 {
 171         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 172         struct devfreq_event_data edata;
 173         int ret = 0;
 174
 175         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 176         if (ret < 0)
 177                 return ret;
 178
 179         stat->current_frequency = dmcfreq->rate;
 180         stat->busy_time = edata.load_count;
 181         stat->total_time = edata.total_count;
 182
 183         return ret;
 184 }
 185
 186 static int rockchip_dmcfreq_get_cur_freq(struct device *dev,
 187                                          unsigned long *freq)
 188 {
 189         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 190
 191         *freq = dmcfreq->rate;
 192
 193         return 0;
 194 }
 195
 196 static struct devfreq_dev_profile rockchip_devfreq_dmc_profile = {
 197         .polling_ms     = 200,
 198         .target         = rockchip_dmcfreq_target,
 199         .get_dev_status = rockchip_dmcfreq_get_dev_status,
 200         .get_cur_freq   = rockchip_dmcfreq_get_cur_freq,
 201 };
 202
 203 static __maybe_unused int rockchip_dmcfreq_suspend(struct device *dev)
 204 {
 205         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 206         int ret = 0;
 207
 208         ret = devfreq_event_disable_edev(dmcfreq->edev);
 209         if (ret < 0) {
 210                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 211                 return ret;
 212         }
 213
 214         ret = devfreq_suspend_device(dmcfreq->devfreq);
 215         if (ret < 0) {
 216                 dev_err(dev, "failed to suspend the devfreq devices\n");
 217                 return ret;
 218         }
 219
 220         return 0;
 221 }
 222
 223 static __maybe_unused int rockchip_dmcfreq_resume(struct device *dev)
 224 {
 225         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 226         int ret = 0;
 227
 228         ret = devfreq_event_enable_edev(dmcfreq->edev);
 229         if (ret < 0) {
 230                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 231                 return ret;
 232         }
 233
 234         ret = devfreq_resume_device(dmcfreq->devfreq);
 235         if (ret < 0) {
 236                 dev_err(dev, "failed to resume the devfreq devices\n");
 237                 return ret;
 238         }
 239         return ret;
 240 }
 241
 242 static SIMPLE_DEV_PM_OPS(rockchip_dmcfreq_pm, rockchip_dmcfreq_suspend,
 243                          rockchip_dmcfreq_resume);
 244
 245 static struct dram_timing *of_get_ddr_timings(struct device *dev,
 246                                               struct device_node *np)
 247 {
 248         struct dram_timing      *timing = NULL;
 249         struct device_node      *np_tim;
 250         int ret;
 251
 252         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 253         if (np_tim) {
 254                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 255                 if (!timing)
 256                         goto err;
 257
 258                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 259                                            &timing->ddr3_speed_bin);
 260                 ret |= of_property_read_u32(np_tim, "pd_idle",
 261                                             &timing->pd_idle);
 262                 ret |= of_property_read_u32(np_tim, "sr_idle",
 263                                             &timing->sr_idle);
 264                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 265                                             &timing->sr_mc_gate_idle);
 266                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 267                                             &timing->srpd_lite_idle);
 268                 ret |= of_property_read_u32(np_tim, "standby_idle",
 269                                             &timing->standby_idle);
 270                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 271                                             &timing->dram_dll_dis_freq);
 272                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 273                                             &timing->phy_dll_dis_freq);
 274                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 275                                             &timing->ddr3_odt_dis_freq);
 276                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 277                                             &timing->ddr3_drv);
 278                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 279                                             &timing->ddr3_odt);
 280                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 281                                             &timing->phy_ddr3_ca_drv);
 282                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 283                                             &timing->phy_ddr3_dq_drv);
 284                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 285                                             &timing->phy_ddr3_odt);
 286                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 287                                             &timing->lpddr3_odt_dis_freq);
 288                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 289                                             &timing->lpddr3_drv);
 290                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 291                                             &timing->lpddr3_odt);
 292                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 293                                             &timing->phy_lpddr3_ca_drv);
 294                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 295                                             &timing->phy_lpddr3_dq_drv);
 296                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 297                                             &timing->phy_lpddr3_odt);
 298                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 299                                             &timing->lpddr4_odt_dis_freq);
 300                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 301                                             &timing->lpddr4_drv);
 302                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 303                                             &timing->lpddr4_dq_odt);
 304                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 305                                             &timing->lpddr4_ca_odt);
 306                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 307                                             &timing->phy_lpddr4_ca_drv);
 308                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 309                                             &timing->phy_lpddr4_ck_cs_drv);
 310                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 311                                             &timing->phy_lpddr4_dq_drv);
 312                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 313                                             &timing->phy_lpddr4_odt);
 314                 if (ret) {
 315                         devm_kfree(dev, timing);
 316                         goto err;
 317                 }
 318                 of_node_put(np_tim);
 319                 return timing;
 320         }
 321
 322 err:
 323         if (timing) {
 324                 devm_kfree(dev, timing);
 325                 timing = NULL;
 326         }
 327         of_node_put(np_tim);
 328         return timing;
 329 }
 330
 331 static int rockchip_dmcfreq_init_freq_table(struct device *dev,
 332                                             struct devfreq_dev_profile *devp)
 333 {
 334         int count;
 335         int i = 0;
 336         unsigned long freq = 0;
 337         struct dev_pm_opp *opp;
 338
 339         rcu_read_lock();
 340         count = dev_pm_opp_get_opp_count(dev);
 341         if (count < 0) {
 342                 rcu_read_unlock();
 343                 return count;
 344         }
 345         rcu_read_unlock();
 346
 347         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 348                                 GFP_KERNEL);
 349         if (!devp->freq_table)
 350                 return -ENOMEM;
 351
 352         rcu_read_lock();
 353         for (i = 0; i < count; i++, freq++) {
 354                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 355                 if (IS_ERR(opp))
 356                         break;
 357
 358                 devp->freq_table[i] = freq;
 359         }
 360         rcu_read_unlock();
 361
 362         if (count != i)
 363                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 364                          count, i);
 365
 366         devp->max_state = i;
 367         return 0;
 368 }
 369
 370 static int rockchip_dmcfreq_probe(struct platform_device *pdev)
 371 {
 372         struct arm_smccc_res res;
 373         struct device *dev = &pdev->dev;
 374         struct device_node *np = pdev->dev.of_node;
 375         struct rockchip_dmcfreq *data;
 376         int ret, index, size;
 377         u32 *timing;
 378         struct devfreq_dev_profile *devp = &rockchip_devfreq_dmc_profile;
 379
 380         data = devm_kzalloc(dev, sizeof(struct rockchip_dmcfreq), GFP_KERNEL);
 381         if (!data)
 382                 return -ENOMEM;
 383
 384         mutex_init(&data->lock);
 385
 386         data->vdd_center = devm_regulator_get(dev, "center");
 387         if (IS_ERR(data->vdd_center)) {
 388                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 389                 return PTR_ERR(data->vdd_center);
 390         }
 391
 392         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 393         if (IS_ERR(data->dmc_clk)) {
 394                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 395                 return PTR_ERR(data->dmc_clk);
 396         };
 397
 398         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 399         if (IS_ERR(data->edev))
 400                 return -EPROBE_DEFER;
 401
 402         ret = devfreq_event_enable_edev(data->edev);
 403         if (ret < 0) {
 404                 dev_err(dev, "failed to enable devfreq-event devices\n");
 405                 return ret;
 406         }
 407
 408         /*
 409          * Get dram timing and pass it to arm trust firmware,
 410          * the dram drvier in arm trust firmware will get these
 411          * timing and to do dram initial.
 412          */
 413         data->timing = of_get_ddr_timings(dev, np);
 414         if (data->timing) {
 415                 timing = (uint32_t *)data->timing;
 416                 size = sizeof(struct dram_timing) / 4;
 417                 for (index = 0; index < size; index++) {
 418                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 419                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 420                                       0, 0, 0, 0, &res);
 421                         if (res.a0) {
 422                                 dev_err(dev, "Failed to set dram param: %ld\n",
 423                                         res.a0);
 424                                 return -EINVAL;
 425                         }
 426                 }
 427         }
 428
 429         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 430                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 431                       0, 0, 0, 0, &res);
 432
 433         /*
 434          * We add a devfreq driver to our parent since it has a device tree node
 435          * with operating points.
 436          */
 437         if (dev_pm_opp_of_add_table(dev)) {
 438                 dev_err(dev, "Invalid operating-points in device tree.\n");
 439                 return -EINVAL;
 440         }
 441
 442         if (rockchip_dmcfreq_init_freq_table(dev, devp))
 443                 return -EFAULT;
 444
 445         of_property_read_u32(np, "upthreshold",
 446                              &data->ondemand_data.upthreshold);
 447         of_property_read_u32(np, "downdifferential",
 448                              &data->ondemand_data.downdifferential);
 449
 450         data->rate = clk_get_rate(data->dmc_clk);
 451         data->volt = regulator_get_voltage(data->vdd_center);
 452
 453         devp->initial_freq = data->rate;
 454         data->devfreq = devm_devfreq_add_device(dev, devp,
 455                                            "simple_ondemand",
 456                                            &data->ondemand_data);
 457         if (IS_ERR(data->devfreq))
 458                 return PTR_ERR(data->devfreq);
 459         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 460
 461         data->devfreq->min_freq = devp->freq_table[0];
 462         data->devfreq->max_freq =
 463                 devp->freq_table[devp->max_state ? devp->max_state - 1 : 0];
 464
 465         data->dev = dev;
 466         platform_set_drvdata(pdev, data);
 467
 468         if (vop_register_dmc())
 469                 dev_err(dev, "fail to register notify to vop.\n");
 470
 471         return 0;
 472 }
 473
 474 static const struct of_device_id rockchip_dmcfreq_of_match[] = {
 475         { .compatible = "rockchip,rk3399-dmc" },
 476         { },
 477 };
 478 MODULE_DEVICE_TABLE(of, rockchip_dmcfreq_of_match);
 479
 480 static struct platform_driver rockchip_dmcfreq_driver = {
 481         .probe  = rockchip_dmcfreq_probe,
 482         .driver = {
 483                 .name   = "rockchip-dmc",
 484                 .pm     = &rockchip_dmcfreq_pm,
 485                 .of_match_table = rockchip_dmcfreq_of_match,
 486         },
 487 };
 488 module_platform_driver(rockchip_dmcfreq_driver);
 489
 490 MODULE_LICENSE("GPL v2");
 491 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 492 MODULE_DESCRIPTION("rockchip dmcfreq driver with devfreq framework");