drivers/devfreq/rk3399_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/arm-smccc.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/devfreq.h>
  19 #include <linux/devfreq-event.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_opp.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/rwsem.h>
  27 #include <linux/slab.h>
  28 #include <linux/suspend.h>
  29
  30 #include <soc/rockchip/rockchip_sip.h>
  31
  32 struct dram_timing {
  33         unsigned int ddr3_speed_bin;
  34         unsigned int pd_idle;
  35         unsigned int sr_idle;
  36         unsigned int sr_mc_gate_idle;
  37         unsigned int srpd_lite_idle;
  38         unsigned int standby_idle;
  39         unsigned int dram_dll_dis_freq;
  40         unsigned int phy_dll_dis_freq;
  41         unsigned int ddr3_odt_dis_freq;
  42         unsigned int ddr3_drv;
  43         unsigned int ddr3_odt;
  44         unsigned int phy_ddr3_ca_drv;
  45         unsigned int phy_ddr3_dq_drv;
  46         unsigned int phy_ddr3_odt;
  47         unsigned int lpddr3_odt_dis_freq;
  48         unsigned int lpddr3_drv;
  49         unsigned int lpddr3_odt;
  50         unsigned int phy_lpddr3_ca_drv;
  51         unsigned int phy_lpddr3_dq_drv;
  52         unsigned int phy_lpddr3_odt;
  53         unsigned int lpddr4_odt_dis_freq;
  54         unsigned int lpddr4_drv;
  55         unsigned int lpddr4_dq_odt;
  56         unsigned int lpddr4_ca_odt;
  57         unsigned int phy_lpddr4_ca_drv;
  58         unsigned int phy_lpddr4_ck_cs_drv;
  59         unsigned int phy_lpddr4_dq_drv;
  60         unsigned int phy_lpddr4_odt;
  61 };
  62
  63 struct rk3399_dmcfreq {
  64         struct device *dev;
  65         struct devfreq *devfreq;
  66         struct devfreq_simple_ondemand_data ondemand_data;
  67         struct clk *dmc_clk;
  68         struct devfreq_event_dev *edev;
  69         struct mutex lock;
  70         struct dram_timing *timing;
  71
  72         /*
  73          * DDR Converser of Frequency (DCF) is used to implement DDR frequency
  74          * conversion without the participation of CPU, we will implement and
  75          * control it in arm trust firmware.
  76          */
  77         wait_queue_head_t       wait_dcf_queue;
  78         int irq;
  79         int wait_dcf_flag;
  80         struct regulator *vdd_center;
  81         unsigned long rate, target_rate;
  82         unsigned long volt, target_volt;
  83         struct dev_pm_opp *curr_opp;
  84 };
  85
  86 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
  87                                  u32 flags)
  88 {
  89         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  90         struct dev_pm_opp *opp;
  91         unsigned long old_clk_rate = dmcfreq->rate;
  92         unsigned long target_volt, target_rate;
  93         int err;
  94
  95         rcu_read_lock();
  96         opp = devfreq_recommended_opp(dev, freq, flags);
  97         if (IS_ERR(opp)) {
  98                 rcu_read_unlock();
  99                 return PTR_ERR(opp);
 100         }
 101
 102         target_rate = dev_pm_opp_get_freq(opp);
 103         target_volt = dev_pm_opp_get_voltage(opp);
 104
 105         dmcfreq->rate = dev_pm_opp_get_freq(dmcfreq->curr_opp);
 106         dmcfreq->volt = dev_pm_opp_get_voltage(dmcfreq->curr_opp);
 107
 108         rcu_read_unlock();
 109
 110         if (dmcfreq->rate == target_rate)
 111                 return 0;
 112
 113         mutex_lock(&dmcfreq->lock);
 114
 115         /*
 116          * If frequency scaling from low to high, adjust voltage first.
 117          * If frequency scaling from high to low, adjust frequency first.
 118          */
 119         if (old_clk_rate < target_rate) {
 120                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 121                                             target_volt);
 122                 if (err) {
 123                         dev_err(dev, "Cannot to set voltage %lu uV\n",
 124                                 target_volt);
 125                         goto out;
 126                 }
 127         }
 128         dmcfreq->wait_dcf_flag = 1;
 129
 130         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 131         if (err) {
 132                 dev_err(dev, "Cannot to set frequency %lu (%d)\n",
 133                         target_rate, err);
 134                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 135                                       dmcfreq->volt);
 136                 goto out;
 137         }
 138
 139         /*
 140          * Wait until bcf irq happen, it means freq scaling finish in
 141          * arm trust firmware, use 100ms as timeout time.
 142          */
 143         if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
 144                                 !dmcfreq->wait_dcf_flag, HZ / 10))
 145                 dev_warn(dev, "Timeout waiting for dcf interrupt\n");
 146
 147         /*
 148          * Check the dpll rate,
 149          * There only two result we will get,
 150          * 1. Ddr frequency scaling fail, we still get the old rate.
 151          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 152          */
 153         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 154
 155         /* If get the incorrect rate, set voltage to old value. */
 156         if (dmcfreq->rate != target_rate) {
 157                 dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
 158                         Current frequency %lu\n", target_rate, dmcfreq->rate);
 159                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 160                                       dmcfreq->volt);
 161                 goto out;
 162         } else if (old_clk_rate > target_rate)
 163                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 164                                             target_volt);
 165         if (err)
 166                 dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
 167
 168         dmcfreq->curr_opp = opp;
 169 out:
 170         mutex_unlock(&dmcfreq->lock);
 171         return err;
 172 }
 173
 174 static int rk3399_dmcfreq_get_dev_status(struct device *dev,
 175                                          struct devfreq_dev_status *stat)
 176 {
 177         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 178         struct devfreq_event_data edata;
 179         int ret = 0;
 180
 181         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 182         if (ret < 0)
 183                 return ret;
 184
 185         stat->current_frequency = dmcfreq->rate;
 186         stat->busy_time = edata.load_count;
 187         stat->total_time = edata.total_count;
 188
 189         return ret;
 190 }
 191
 192 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
 193 {
 194         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 195
 196         *freq = dmcfreq->rate;
 197
 198         return 0;
 199 }
 200
 201 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
 202         .polling_ms     = 200,
 203         .target         = rk3399_dmcfreq_target,
 204         .get_dev_status = rk3399_dmcfreq_get_dev_status,
 205         .get_cur_freq   = rk3399_dmcfreq_get_cur_freq,
 206 };
 207
 208 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
 209 {
 210         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 211         int ret = 0;
 212
 213         ret = devfreq_event_disable_edev(dmcfreq->edev);
 214         if (ret < 0) {
 215                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 216                 return ret;
 217         }
 218
 219         ret = devfreq_suspend_device(dmcfreq->devfreq);
 220         if (ret < 0) {
 221                 dev_err(dev, "failed to suspend the devfreq devices\n");
 222                 return ret;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
 229 {
 230         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 231         int ret = 0;
 232
 233         ret = devfreq_event_enable_edev(dmcfreq->edev);
 234         if (ret < 0) {
 235                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 236                 return ret;
 237         }
 238
 239         ret = devfreq_resume_device(dmcfreq->devfreq);
 240         if (ret < 0) {
 241                 dev_err(dev, "failed to resume the devfreq devices\n");
 242                 return ret;
 243         }
 244         return ret;
 245 }
 246
 247 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
 248                          rk3399_dmcfreq_resume);
 249
 250 static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
 251 {
 252         struct rk3399_dmcfreq *dmcfreq = dev_id;
 253         struct arm_smccc_res res;
 254
 255         dmcfreq->wait_dcf_flag = 0;
 256         wake_up(&dmcfreq->wait_dcf_queue);
 257
 258         /* Clear the DCF interrupt */
 259         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 260                       ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
 261                       0, 0, 0, 0, &res);
 262
 263         return IRQ_HANDLED;
 264 }
 265
 266 static struct dram_timing *of_get_ddr_timings(struct device *dev,
 267                                               struct device_node *np)
 268 {
 269         struct dram_timing      *timing = NULL;
 270         struct device_node      *np_tim;
 271         int ret;
 272
 273         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 274         if (np_tim) {
 275                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 276                 if (!timing)
 277                         goto err;
 278
 279                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 280                                            &timing->ddr3_speed_bin);
 281                 ret |= of_property_read_u32(np_tim, "pd_idle",
 282                                             &timing->pd_idle);
 283                 ret |= of_property_read_u32(np_tim, "sr_idle",
 284                                             &timing->sr_idle);
 285                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 286                                             &timing->sr_mc_gate_idle);
 287                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 288                                             &timing->srpd_lite_idle);
 289                 ret |= of_property_read_u32(np_tim, "standby_idle",
 290                                             &timing->standby_idle);
 291                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 292                                             &timing->dram_dll_dis_freq);
 293                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 294                                             &timing->phy_dll_dis_freq);
 295                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 296                                             &timing->ddr3_odt_dis_freq);
 297                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 298                                             &timing->ddr3_drv);
 299                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 300                                             &timing->ddr3_odt);
 301                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 302                                             &timing->phy_ddr3_ca_drv);
 303                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 304                                             &timing->phy_ddr3_dq_drv);
 305                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 306                                             &timing->phy_ddr3_odt);
 307                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 308                                             &timing->lpddr3_odt_dis_freq);
 309                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 310                                             &timing->lpddr3_drv);
 311                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 312                                             &timing->lpddr3_odt);
 313                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 314                                             &timing->phy_lpddr3_ca_drv);
 315                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 316                                             &timing->phy_lpddr3_dq_drv);
 317                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 318                                             &timing->phy_lpddr3_odt);
 319                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 320                                             &timing->lpddr4_odt_dis_freq);
 321                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 322                                             &timing->lpddr4_drv);
 323                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 324                                             &timing->lpddr4_dq_odt);
 325                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 326                                             &timing->lpddr4_ca_odt);
 327                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 328                                             &timing->phy_lpddr4_ca_drv);
 329                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 330                                             &timing->phy_lpddr4_ck_cs_drv);
 331                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 332                                             &timing->phy_lpddr4_dq_drv);
 333                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 334                                             &timing->phy_lpddr4_odt);
 335                 if (ret) {
 336                         devm_kfree(dev, timing);
 337                         goto err;
 338                 }
 339                 of_node_put(np_tim);
 340                 return timing;
 341         }
 342
 343 err:
 344         if (timing) {
 345                 devm_kfree(dev, timing);
 346                 timing = NULL;
 347         }
 348         of_node_put(np_tim);
 349         return timing;
 350 }
 351
 352 static int of_get_opp_table(struct device *dev,
 353                             struct devfreq_dev_profile *devp)
 354 {
 355         int count;
 356         int i = 0;
 357         unsigned long freq = 0;
 358         struct dev_pm_opp *opp;
 359
 360         rcu_read_lock();
 361         count = dev_pm_opp_get_opp_count(dev);
 362         if (count < 0) {
 363                 rcu_read_unlock();
 364                 return count;
 365         }
 366         rcu_read_unlock();
 367
 368         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 369                                 GFP_KERNEL);
 370         if (!devp->freq_table)
 371                 return -ENOMEM;
 372
 373         rcu_read_lock();
 374         for (i = 0; i < count; i++, freq++) {
 375                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 376                 if (IS_ERR(opp))
 377                         break;
 378
 379                 devp->freq_table[i] = freq;
 380         }
 381         rcu_read_unlock();
 382
 383         if (count != i)
 384                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 385                          count, i);
 386
 387         devp->max_state = i;
 388         return 0;
 389 }
 390
 391 static int rk3399_dmcfreq_probe(struct platform_device *pdev)
 392 {
 393         struct arm_smccc_res res;
 394         struct device *dev = &pdev->dev;
 395         struct device_node *np = pdev->dev.of_node;
 396         struct rk3399_dmcfreq *data;
 397         int ret, irq, index, size;
 398         uint32_t *timing;
 399         struct dev_pm_opp *opp;
 400         struct devfreq_dev_profile *devp = &rk3399_devfreq_dmc_profile;
 401
 402         irq = platform_get_irq(pdev, 0);
 403         if (irq < 0) {
 404                 dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
 405                 return -EINVAL;
 406         }
 407         data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
 408         if (!data)
 409                 return -ENOMEM;
 410
 411         mutex_init(&data->lock);
 412
 413         data->vdd_center = devm_regulator_get(dev, "center");
 414         if (IS_ERR(data->vdd_center)) {
 415                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 416                 return PTR_ERR(data->vdd_center);
 417         }
 418
 419         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 420         if (IS_ERR(data->dmc_clk)) {
 421                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 422                 return PTR_ERR(data->dmc_clk);
 423         };
 424
 425         data->irq = irq;
 426         ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
 427                                dev_name(dev), data);
 428         if (ret) {
 429                 dev_err(dev, "Failed to request dmc irq: %d\n", ret);
 430                 return ret;
 431         }
 432
 433         init_waitqueue_head(&data->wait_dcf_queue);
 434         data->wait_dcf_flag = 0;
 435
 436         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 437         if (IS_ERR(data->edev))
 438                 return -EPROBE_DEFER;
 439
 440         ret = devfreq_event_enable_edev(data->edev);
 441         if (ret < 0) {
 442                 dev_err(dev, "failed to enable devfreq-event devices\n");
 443                 return ret;
 444         }
 445
 446         /*
 447          * Get dram timing and pass it to arm trust firmware,
 448          * the dram drvier in arm trust firmware will get these
 449          * timing and to do dram initial.
 450          */
 451         data->timing = of_get_ddr_timings(dev, np);
 452         if (data->timing) {
 453                 timing = (uint32_t *)data->timing;
 454                 size = sizeof(struct dram_timing) / 4;
 455                 for (index = 0; index < size; index++) {
 456                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 457                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 458                                       0, 0, 0, 0, &res);
 459                         if (res.a0) {
 460                                 dev_err(dev, "Failed to set dram param: %ld\n",
 461                                         res.a0);
 462                                 return -EINVAL;
 463                         }
 464                 }
 465         }
 466
 467         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 468                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 469                       0, 0, 0, 0, &res);
 470
 471         /*
 472          * We add a devfreq driver to our parent since it has a device tree node
 473          * with operating points.
 474          */
 475         if (dev_pm_opp_of_add_table(dev)) {
 476                 dev_err(dev, "Invalid operating-points in device tree.\n");
 477                 rcu_read_unlock();
 478                 return -EINVAL;
 479         }
 480
 481         if (of_get_opp_table(dev, devp))
 482                 return -EFAULT;
 483
 484         of_property_read_u32(np, "upthreshold",
 485                              &data->ondemand_data.upthreshold);
 486         of_property_read_u32(np, "downdifferential",
 487                              &data->ondemand_data.downdifferential);
 488
 489         data->rate = clk_get_rate(data->dmc_clk);
 490
 491         rcu_read_lock();
 492         opp = devfreq_recommended_opp(dev, &data->rate, 0);
 493         if (IS_ERR(opp)) {
 494                 rcu_read_unlock();
 495                 return PTR_ERR(opp);
 496         }
 497         rcu_read_unlock();
 498
 499         data->curr_opp = opp;
 500         devp->initial_freq = data->rate;
 501         data->devfreq = devfreq_add_device(dev, devp,
 502                                            "simple_ondemand",
 503                                            &data->ondemand_data);
 504         if (IS_ERR(data->devfreq))
 505                 return PTR_ERR(data->devfreq);
 506         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 507
 508         data->dev = dev;
 509         platform_set_drvdata(pdev, data);
 510
 511         return 0;
 512 }
 513
 514 static int rk3399_dmcfreq_remove(struct platform_device *pdev)
 515 {
 516         struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);
 517
 518         regulator_put(dmcfreq->vdd_center);
 519
 520         return 0;
 521 }
 522
 523 static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
 524         { .compatible = "rockchip,rk3399-dmc" },
 525         { },
 526 };
 527
 528 static struct platform_driver rk3399_dmcfreq_driver = {
 529         .probe  = rk3399_dmcfreq_probe,
 530         .remove = rk3399_dmcfreq_remove,
 531         .driver = {
 532                 .name   = "rk3399-dmc-freq",
 533                 .pm     = &rk3399_dmcfreq_pm,
 534                 .of_match_table = rk3399dmc_devfreq_of_match,
 535         },
 536 };
 537 module_platform_driver(rk3399_dmcfreq_driver);
 538
 539 MODULE_LICENSE("GPL v2");
 540 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 541 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");