drivers/devfreq/rk3399_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/arm-smccc.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/devfreq.h>
  19 #include <linux/devfreq-event.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_opp.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/rwsem.h>
  27 #include <linux/slab.h>
  28 #include <linux/suspend.h>
  29
  30 #include <soc/rockchip/rkfb_dmc.h>
  31 #include <soc/rockchip/rockchip_sip.h>
  32
  33 struct dram_timing {
  34         unsigned int ddr3_speed_bin;
  35         unsigned int pd_idle;
  36         unsigned int sr_idle;
  37         unsigned int sr_mc_gate_idle;
  38         unsigned int srpd_lite_idle;
  39         unsigned int standby_idle;
  40         unsigned int dram_dll_dis_freq;
  41         unsigned int phy_dll_dis_freq;
  42         unsigned int ddr3_odt_dis_freq;
  43         unsigned int ddr3_drv;
  44         unsigned int ddr3_odt;
  45         unsigned int phy_ddr3_ca_drv;
  46         unsigned int phy_ddr3_dq_drv;
  47         unsigned int phy_ddr3_odt;
  48         unsigned int lpddr3_odt_dis_freq;
  49         unsigned int lpddr3_drv;
  50         unsigned int lpddr3_odt;
  51         unsigned int phy_lpddr3_ca_drv;
  52         unsigned int phy_lpddr3_dq_drv;
  53         unsigned int phy_lpddr3_odt;
  54         unsigned int lpddr4_odt_dis_freq;
  55         unsigned int lpddr4_drv;
  56         unsigned int lpddr4_dq_odt;
  57         unsigned int lpddr4_ca_odt;
  58         unsigned int phy_lpddr4_ca_drv;
  59         unsigned int phy_lpddr4_ck_cs_drv;
  60         unsigned int phy_lpddr4_dq_drv;
  61         unsigned int phy_lpddr4_odt;
  62 };
  63
  64 struct rk3399_dmcfreq {
  65         struct device *dev;
  66         struct devfreq *devfreq;
  67         struct devfreq_simple_ondemand_data ondemand_data;
  68         struct clk *dmc_clk;
  69         struct devfreq_event_dev *edev;
  70         struct mutex lock;
  71         struct dram_timing *timing;
  72
  73         /*
  74          * DDR Converser of Frequency (DCF) is used to implement DDR frequency
  75          * conversion without the participation of CPU, we will implement and
  76          * control it in arm trust firmware.
  77          */
  78         wait_queue_head_t       wait_dcf_queue;
  79         int irq;
  80         int wait_dcf_flag;
  81         struct regulator *vdd_center;
  82         unsigned long rate, target_rate;
  83         unsigned long volt, target_volt;
  84         struct dev_pm_opp *curr_opp;
  85 };
  86
  87 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
  88                                  u32 flags)
  89 {
  90         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  91         struct dev_pm_opp *opp;
  92         unsigned long old_clk_rate = dmcfreq->rate;
  93         unsigned long target_volt, target_rate;
  94         int err;
  95
  96         rcu_read_lock();
  97         opp = devfreq_recommended_opp(dev, freq, flags);
  98         if (IS_ERR(opp)) {
  99                 rcu_read_unlock();
 100                 return PTR_ERR(opp);
 101         }
 102
 103         target_rate = dev_pm_opp_get_freq(opp);
 104         target_volt = dev_pm_opp_get_voltage(opp);
 105
 106         dmcfreq->rate = dev_pm_opp_get_freq(dmcfreq->curr_opp);
 107         dmcfreq->volt = dev_pm_opp_get_voltage(dmcfreq->curr_opp);
 108
 109         rcu_read_unlock();
 110
 111         if (dmcfreq->rate == target_rate)
 112                 return 0;
 113
 114         mutex_lock(&dmcfreq->lock);
 115
 116         /*
 117          * If frequency scaling from low to high, adjust voltage first.
 118          * If frequency scaling from high to low, adjust frequency first.
 119          */
 120         if (old_clk_rate < target_rate) {
 121                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 122                                             target_volt);
 123                 if (err) {
 124                         dev_err(dev, "Cannot to set voltage %lu uV\n",
 125                                 target_volt);
 126                         goto out;
 127                 }
 128         }
 129
 130         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 131         if (err) {
 132                 dev_err(dev, "Cannot to set frequency %lu (%d)\n",
 133                         target_rate, err);
 134                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 135                                       dmcfreq->volt);
 136                 goto out;
 137         }
 138
 139         /*
 140          * Check the dpll rate,
 141          * There only two result we will get,
 142          * 1. Ddr frequency scaling fail, we still get the old rate.
 143          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 144          */
 145         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 146
 147         /* If get the incorrect rate, set voltage to old value. */
 148         if (dmcfreq->rate != target_rate) {
 149                 dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
 150                         Current frequency %lu\n", target_rate, dmcfreq->rate);
 151                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 152                                       dmcfreq->volt);
 153                 goto out;
 154         } else if (old_clk_rate > target_rate)
 155                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 156                                             target_volt);
 157         if (err)
 158                 dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
 159
 160         dmcfreq->curr_opp = opp;
 161 out:
 162         mutex_unlock(&dmcfreq->lock);
 163         return err;
 164 }
 165
 166 static int rk3399_dmcfreq_get_dev_status(struct device *dev,
 167                                          struct devfreq_dev_status *stat)
 168 {
 169         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 170         struct devfreq_event_data edata;
 171         int ret = 0;
 172
 173         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 174         if (ret < 0)
 175                 return ret;
 176
 177         stat->current_frequency = dmcfreq->rate;
 178         stat->busy_time = edata.load_count;
 179         stat->total_time = edata.total_count;
 180
 181         return ret;
 182 }
 183
 184 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
 185 {
 186         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 187
 188         *freq = dmcfreq->rate;
 189
 190         return 0;
 191 }
 192
 193 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
 194         .polling_ms     = 200,
 195         .target         = rk3399_dmcfreq_target,
 196         .get_dev_status = rk3399_dmcfreq_get_dev_status,
 197         .get_cur_freq   = rk3399_dmcfreq_get_cur_freq,
 198 };
 199
 200 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
 201 {
 202         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 203         int ret = 0;
 204
 205         ret = devfreq_event_disable_edev(dmcfreq->edev);
 206         if (ret < 0) {
 207                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 208                 return ret;
 209         }
 210
 211         ret = devfreq_suspend_device(dmcfreq->devfreq);
 212         if (ret < 0) {
 213                 dev_err(dev, "failed to suspend the devfreq devices\n");
 214                 return ret;
 215         }
 216
 217         return 0;
 218 }
 219
 220 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
 221 {
 222         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 223         int ret = 0;
 224
 225         ret = devfreq_event_enable_edev(dmcfreq->edev);
 226         if (ret < 0) {
 227                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 228                 return ret;
 229         }
 230
 231         ret = devfreq_resume_device(dmcfreq->devfreq);
 232         if (ret < 0) {
 233                 dev_err(dev, "failed to resume the devfreq devices\n");
 234                 return ret;
 235         }
 236         return ret;
 237 }
 238
 239 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
 240                          rk3399_dmcfreq_resume);
 241
 242 static struct dram_timing *of_get_ddr_timings(struct device *dev,
 243                                               struct device_node *np)
 244 {
 245         struct dram_timing      *timing = NULL;
 246         struct device_node      *np_tim;
 247         int ret;
 248
 249         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 250         if (np_tim) {
 251                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 252                 if (!timing)
 253                         goto err;
 254
 255                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 256                                            &timing->ddr3_speed_bin);
 257                 ret |= of_property_read_u32(np_tim, "pd_idle",
 258                                             &timing->pd_idle);
 259                 ret |= of_property_read_u32(np_tim, "sr_idle",
 260                                             &timing->sr_idle);
 261                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 262                                             &timing->sr_mc_gate_idle);
 263                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 264                                             &timing->srpd_lite_idle);
 265                 ret |= of_property_read_u32(np_tim, "standby_idle",
 266                                             &timing->standby_idle);
 267                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 268                                             &timing->dram_dll_dis_freq);
 269                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 270                                             &timing->phy_dll_dis_freq);
 271                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 272                                             &timing->ddr3_odt_dis_freq);
 273                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 274                                             &timing->ddr3_drv);
 275                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 276                                             &timing->ddr3_odt);
 277                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 278                                             &timing->phy_ddr3_ca_drv);
 279                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 280                                             &timing->phy_ddr3_dq_drv);
 281                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 282                                             &timing->phy_ddr3_odt);
 283                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 284                                             &timing->lpddr3_odt_dis_freq);
 285                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 286                                             &timing->lpddr3_drv);
 287                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 288                                             &timing->lpddr3_odt);
 289                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 290                                             &timing->phy_lpddr3_ca_drv);
 291                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 292                                             &timing->phy_lpddr3_dq_drv);
 293                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 294                                             &timing->phy_lpddr3_odt);
 295                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 296                                             &timing->lpddr4_odt_dis_freq);
 297                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 298                                             &timing->lpddr4_drv);
 299                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 300                                             &timing->lpddr4_dq_odt);
 301                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 302                                             &timing->lpddr4_ca_odt);
 303                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 304                                             &timing->phy_lpddr4_ca_drv);
 305                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 306                                             &timing->phy_lpddr4_ck_cs_drv);
 307                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 308                                             &timing->phy_lpddr4_dq_drv);
 309                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 310                                             &timing->phy_lpddr4_odt);
 311                 if (ret) {
 312                         devm_kfree(dev, timing);
 313                         goto err;
 314                 }
 315                 of_node_put(np_tim);
 316                 return timing;
 317         }
 318
 319 err:
 320         if (timing) {
 321                 devm_kfree(dev, timing);
 322                 timing = NULL;
 323         }
 324         of_node_put(np_tim);
 325         return timing;
 326 }
 327
 328 static int of_get_opp_table(struct device *dev,
 329                             struct devfreq_dev_profile *devp)
 330 {
 331         int count;
 332         int i = 0;
 333         unsigned long freq = 0;
 334         struct dev_pm_opp *opp;
 335
 336         rcu_read_lock();
 337         count = dev_pm_opp_get_opp_count(dev);
 338         if (count < 0) {
 339                 rcu_read_unlock();
 340                 return count;
 341         }
 342         rcu_read_unlock();
 343
 344         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 345                                 GFP_KERNEL);
 346         if (!devp->freq_table)
 347                 return -ENOMEM;
 348
 349         rcu_read_lock();
 350         for (i = 0; i < count; i++, freq++) {
 351                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 352                 if (IS_ERR(opp))
 353                         break;
 354
 355                 devp->freq_table[i] = freq;
 356         }
 357         rcu_read_unlock();
 358
 359         if (count != i)
 360                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 361                          count, i);
 362
 363         devp->max_state = i;
 364         return 0;
 365 }
 366
 367 static int rk3399_dmcfreq_probe(struct platform_device *pdev)
 368 {
 369         struct arm_smccc_res res;
 370         struct device *dev = &pdev->dev;
 371         struct device_node *np = pdev->dev.of_node;
 372         struct rk3399_dmcfreq *data;
 373         int ret, index, size;
 374         uint32_t *timing;
 375         struct dev_pm_opp *opp;
 376         struct devfreq_dev_profile *devp = &rk3399_devfreq_dmc_profile;
 377
 378         data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
 379         if (!data)
 380                 return -ENOMEM;
 381
 382         mutex_init(&data->lock);
 383
 384         data->vdd_center = devm_regulator_get(dev, "center");
 385         if (IS_ERR(data->vdd_center)) {
 386                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 387                 return PTR_ERR(data->vdd_center);
 388         }
 389
 390         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 391         if (IS_ERR(data->dmc_clk)) {
 392                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 393                 return PTR_ERR(data->dmc_clk);
 394         };
 395
 396         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 397         if (IS_ERR(data->edev))
 398                 return -EPROBE_DEFER;
 399
 400         ret = devfreq_event_enable_edev(data->edev);
 401         if (ret < 0) {
 402                 dev_err(dev, "failed to enable devfreq-event devices\n");
 403                 return ret;
 404         }
 405
 406         /*
 407          * Get dram timing and pass it to arm trust firmware,
 408          * the dram drvier in arm trust firmware will get these
 409          * timing and to do dram initial.
 410          */
 411         data->timing = of_get_ddr_timings(dev, np);
 412         if (data->timing) {
 413                 timing = (uint32_t *)data->timing;
 414                 size = sizeof(struct dram_timing) / 4;
 415                 for (index = 0; index < size; index++) {
 416                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 417                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 418                                       0, 0, 0, 0, &res);
 419                         if (res.a0) {
 420                                 dev_err(dev, "Failed to set dram param: %ld\n",
 421                                         res.a0);
 422                                 return -EINVAL;
 423                         }
 424                 }
 425         }
 426
 427         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 428                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 429                       0, 0, 0, 0, &res);
 430
 431         /*
 432          * We add a devfreq driver to our parent since it has a device tree node
 433          * with operating points.
 434          */
 435         if (dev_pm_opp_of_add_table(dev)) {
 436                 dev_err(dev, "Invalid operating-points in device tree.\n");
 437                 rcu_read_unlock();
 438                 return -EINVAL;
 439         }
 440
 441         if (of_get_opp_table(dev, devp))
 442                 return -EFAULT;
 443
 444         of_property_read_u32(np, "upthreshold",
 445                              &data->ondemand_data.upthreshold);
 446         of_property_read_u32(np, "downdifferential",
 447                              &data->ondemand_data.downdifferential);
 448
 449         data->rate = clk_get_rate(data->dmc_clk);
 450
 451         rcu_read_lock();
 452         opp = devfreq_recommended_opp(dev, &data->rate, 0);
 453         if (IS_ERR(opp)) {
 454                 rcu_read_unlock();
 455                 return PTR_ERR(opp);
 456         }
 457         rcu_read_unlock();
 458
 459         data->curr_opp = opp;
 460         devp->initial_freq = data->rate;
 461         data->devfreq = devfreq_add_device(dev, devp,
 462                                            "simple_ondemand",
 463                                            &data->ondemand_data);
 464         if (IS_ERR(data->devfreq))
 465                 return PTR_ERR(data->devfreq);
 466         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 467
 468         data->dev = dev;
 469         platform_set_drvdata(pdev, data);
 470
 471         if (vop_register_dmc())
 472                 dev_err(dev, "fail to register notify to vop.\n");
 473
 474         return 0;
 475 }
 476
 477 static int rk3399_dmcfreq_remove(struct platform_device *pdev)
 478 {
 479         struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);
 480
 481         regulator_put(dmcfreq->vdd_center);
 482
 483         return 0;
 484 }
 485
 486 static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
 487         { .compatible = "rockchip,rk3399-dmc" },
 488         { },
 489 };
 490
 491 static struct platform_driver rk3399_dmcfreq_driver = {
 492         .probe  = rk3399_dmcfreq_probe,
 493         .remove = rk3399_dmcfreq_remove,
 494         .driver = {
 495                 .name   = "rk3399-dmc-freq",
 496                 .pm     = &rk3399_dmcfreq_pm,
 497                 .of_match_table = rk3399dmc_devfreq_of_match,
 498         },
 499 };
 500 module_platform_driver(rk3399_dmcfreq_driver);
 501
 502 MODULE_LICENSE("GPL v2");
 503 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 504 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");