drivers/devfreq/rk3399_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/arm-smccc.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/devfreq.h>
  19 #include <linux/devfreq-event.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_opp.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/rwsem.h>
  27 #include <linux/slab.h>
  28 #include <linux/suspend.h>
  29
  30 #include <soc/rockchip/rkfb_dmc.h>
  31 #include <soc/rockchip/rockchip_sip.h>
  32
  33 struct dram_timing {
  34         unsigned int ddr3_speed_bin;
  35         unsigned int pd_idle;
  36         unsigned int sr_idle;
  37         unsigned int sr_mc_gate_idle;
  38         unsigned int srpd_lite_idle;
  39         unsigned int standby_idle;
  40         unsigned int dram_dll_dis_freq;
  41         unsigned int phy_dll_dis_freq;
  42         unsigned int ddr3_odt_dis_freq;
  43         unsigned int ddr3_drv;
  44         unsigned int ddr3_odt;
  45         unsigned int phy_ddr3_ca_drv;
  46         unsigned int phy_ddr3_dq_drv;
  47         unsigned int phy_ddr3_odt;
  48         unsigned int lpddr3_odt_dis_freq;
  49         unsigned int lpddr3_drv;
  50         unsigned int lpddr3_odt;
  51         unsigned int phy_lpddr3_ca_drv;
  52         unsigned int phy_lpddr3_dq_drv;
  53         unsigned int phy_lpddr3_odt;
  54         unsigned int lpddr4_odt_dis_freq;
  55         unsigned int lpddr4_drv;
  56         unsigned int lpddr4_dq_odt;
  57         unsigned int lpddr4_ca_odt;
  58         unsigned int phy_lpddr4_ca_drv;
  59         unsigned int phy_lpddr4_ck_cs_drv;
  60         unsigned int phy_lpddr4_dq_drv;
  61         unsigned int phy_lpddr4_odt;
  62 };
  63
  64 struct rk3399_dmcfreq {
  65         struct device *dev;
  66         struct devfreq *devfreq;
  67         struct devfreq_simple_ondemand_data ondemand_data;
  68         struct clk *dmc_clk;
  69         struct devfreq_event_dev *edev;
  70         struct mutex lock;
  71         struct dram_timing *timing;
  72         struct regulator *vdd_center;
  73         unsigned long rate, target_rate;
  74         unsigned long volt, target_volt;
  75 };
  76
  77 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
  78                                  u32 flags)
  79 {
  80         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  81         struct dev_pm_opp *opp;
  82         unsigned long old_clk_rate = dmcfreq->rate;
  83         unsigned long temp_rate, target_volt, target_rate;
  84         int err;
  85
  86         rcu_read_lock();
  87         opp = devfreq_recommended_opp(dev, freq, flags);
  88         if (IS_ERR(opp)) {
  89                 rcu_read_unlock();
  90                 return PTR_ERR(opp);
  91         }
  92
  93         temp_rate = dev_pm_opp_get_freq(opp);
  94         target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
  95         if ((long)target_rate <= 0)
  96                 target_rate = temp_rate;
  97         target_volt = dev_pm_opp_get_voltage(opp);
  98
  99         rcu_read_unlock();
 100
 101         if (dmcfreq->rate == target_rate) {
 102                 if (dmcfreq->volt == target_volt)
 103                         return 0;
 104                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 105                                             INT_MAX);
 106                 if (err) {
 107                         dev_err(dev, "Cannot set voltage %lu uV\n",
 108                                 target_volt);
 109                         goto out;
 110                 }
 111         }
 112
 113         mutex_lock(&dmcfreq->lock);
 114
 115         /*
 116          * If frequency scaling from low to high, adjust voltage first.
 117          * If frequency scaling from high to low, adjust frequency first.
 118          */
 119         if (old_clk_rate < target_rate) {
 120                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 121                                             INT_MAX);
 122                 if (err) {
 123                         dev_err(dev, "Cannot set voltage %lu uV\n",
 124                                 target_volt);
 125                         goto out;
 126                 }
 127         }
 128
 129         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 130         if (err) {
 131                 dev_err(dev, "Cannot set frequency %lu (%d)\n",
 132                         target_rate, err);
 133                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 134                                       INT_MAX);
 135                 goto out;
 136         }
 137
 138         /*
 139          * Check the dpll rate,
 140          * There only two result we will get,
 141          * 1. Ddr frequency scaling fail, we still get the old rate.
 142          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 143          */
 144         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 145
 146         /* If get the incorrect rate, set voltage to old value. */
 147         if (dmcfreq->rate != target_rate) {
 148                 dev_err(dev, "Get wrong frequency, Request %lu, Current %lu\n",
 149                         target_rate, dmcfreq->rate);
 150                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 151                                       INT_MAX);
 152                 goto out;
 153         } else if (old_clk_rate > target_rate) {
 154                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 155                                             INT_MAX);
 156                 if (err) {
 157                         dev_err(dev, "Cannot set vol %lu uV\n", target_volt);
 158                         goto out;
 159                 }
 160         }
 161
 162         dmcfreq->volt = target_volt;
 163 out:
 164         mutex_unlock(&dmcfreq->lock);
 165         return err;
 166 }
 167
 168 static int rk3399_dmcfreq_get_dev_status(struct device *dev,
 169                                          struct devfreq_dev_status *stat)
 170 {
 171         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 172         struct devfreq_event_data edata;
 173         int ret = 0;
 174
 175         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 176         if (ret < 0)
 177                 return ret;
 178
 179         stat->current_frequency = dmcfreq->rate;
 180         stat->busy_time = edata.load_count;
 181         stat->total_time = edata.total_count;
 182
 183         return ret;
 184 }
 185
 186 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
 187 {
 188         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 189
 190         *freq = dmcfreq->rate;
 191
 192         return 0;
 193 }
 194
 195 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
 196         .polling_ms     = 200,
 197         .target         = rk3399_dmcfreq_target,
 198         .get_dev_status = rk3399_dmcfreq_get_dev_status,
 199         .get_cur_freq   = rk3399_dmcfreq_get_cur_freq,
 200 };
 201
 202 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
 203 {
 204         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 205         int ret = 0;
 206
 207         ret = devfreq_event_disable_edev(dmcfreq->edev);
 208         if (ret < 0) {
 209                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 210                 return ret;
 211         }
 212
 213         ret = devfreq_suspend_device(dmcfreq->devfreq);
 214         if (ret < 0) {
 215                 dev_err(dev, "failed to suspend the devfreq devices\n");
 216                 return ret;
 217         }
 218
 219         return 0;
 220 }
 221
 222 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
 223 {
 224         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 225         int ret = 0;
 226
 227         ret = devfreq_event_enable_edev(dmcfreq->edev);
 228         if (ret < 0) {
 229                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 230                 return ret;
 231         }
 232
 233         ret = devfreq_resume_device(dmcfreq->devfreq);
 234         if (ret < 0) {
 235                 dev_err(dev, "failed to resume the devfreq devices\n");
 236                 return ret;
 237         }
 238         return ret;
 239 }
 240
 241 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
 242                          rk3399_dmcfreq_resume);
 243
 244 static struct dram_timing *of_get_ddr_timings(struct device *dev,
 245                                               struct device_node *np)
 246 {
 247         struct dram_timing      *timing = NULL;
 248         struct device_node      *np_tim;
 249         int ret;
 250
 251         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 252         if (np_tim) {
 253                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 254                 if (!timing)
 255                         goto err;
 256
 257                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 258                                            &timing->ddr3_speed_bin);
 259                 ret |= of_property_read_u32(np_tim, "pd_idle",
 260                                             &timing->pd_idle);
 261                 ret |= of_property_read_u32(np_tim, "sr_idle",
 262                                             &timing->sr_idle);
 263                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 264                                             &timing->sr_mc_gate_idle);
 265                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 266                                             &timing->srpd_lite_idle);
 267                 ret |= of_property_read_u32(np_tim, "standby_idle",
 268                                             &timing->standby_idle);
 269                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 270                                             &timing->dram_dll_dis_freq);
 271                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 272                                             &timing->phy_dll_dis_freq);
 273                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 274                                             &timing->ddr3_odt_dis_freq);
 275                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 276                                             &timing->ddr3_drv);
 277                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 278                                             &timing->ddr3_odt);
 279                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 280                                             &timing->phy_ddr3_ca_drv);
 281                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 282                                             &timing->phy_ddr3_dq_drv);
 283                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 284                                             &timing->phy_ddr3_odt);
 285                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 286                                             &timing->lpddr3_odt_dis_freq);
 287                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 288                                             &timing->lpddr3_drv);
 289                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 290                                             &timing->lpddr3_odt);
 291                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 292                                             &timing->phy_lpddr3_ca_drv);
 293                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 294                                             &timing->phy_lpddr3_dq_drv);
 295                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 296                                             &timing->phy_lpddr3_odt);
 297                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 298                                             &timing->lpddr4_odt_dis_freq);
 299                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 300                                             &timing->lpddr4_drv);
 301                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 302                                             &timing->lpddr4_dq_odt);
 303                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 304                                             &timing->lpddr4_ca_odt);
 305                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 306                                             &timing->phy_lpddr4_ca_drv);
 307                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 308                                             &timing->phy_lpddr4_ck_cs_drv);
 309                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 310                                             &timing->phy_lpddr4_dq_drv);
 311                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 312                                             &timing->phy_lpddr4_odt);
 313                 if (ret) {
 314                         devm_kfree(dev, timing);
 315                         goto err;
 316                 }
 317                 of_node_put(np_tim);
 318                 return timing;
 319         }
 320
 321 err:
 322         if (timing) {
 323                 devm_kfree(dev, timing);
 324                 timing = NULL;
 325         }
 326         of_node_put(np_tim);
 327         return timing;
 328 }
 329
 330 static int rk3399_dmcfreq_init_freq_table(struct device *dev,
 331                                           struct devfreq_dev_profile *devp)
 332 {
 333         int count;
 334         int i = 0;
 335         unsigned long freq = 0;
 336         struct dev_pm_opp *opp;
 337
 338         rcu_read_lock();
 339         count = dev_pm_opp_get_opp_count(dev);
 340         if (count < 0) {
 341                 rcu_read_unlock();
 342                 return count;
 343         }
 344         rcu_read_unlock();
 345
 346         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 347                                 GFP_KERNEL);
 348         if (!devp->freq_table)
 349                 return -ENOMEM;
 350
 351         rcu_read_lock();
 352         for (i = 0; i < count; i++, freq++) {
 353                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 354                 if (IS_ERR(opp))
 355                         break;
 356
 357                 devp->freq_table[i] = freq;
 358         }
 359         rcu_read_unlock();
 360
 361         if (count != i)
 362                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 363                          count, i);
 364
 365         devp->max_state = i;
 366         return 0;
 367 }
 368
 369 static int rk3399_dmcfreq_probe(struct platform_device *pdev)
 370 {
 371         struct arm_smccc_res res;
 372         struct device *dev = &pdev->dev;
 373         struct device_node *np = pdev->dev.of_node;
 374         struct rk3399_dmcfreq *data;
 375         int ret, index, size;
 376         uint32_t *timing;
 377         struct devfreq_dev_profile *devp = &rk3399_devfreq_dmc_profile;
 378
 379         data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
 380         if (!data)
 381                 return -ENOMEM;
 382
 383         mutex_init(&data->lock);
 384
 385         data->vdd_center = devm_regulator_get(dev, "center");
 386         if (IS_ERR(data->vdd_center)) {
 387                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 388                 return PTR_ERR(data->vdd_center);
 389         }
 390
 391         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 392         if (IS_ERR(data->dmc_clk)) {
 393                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 394                 return PTR_ERR(data->dmc_clk);
 395         };
 396
 397         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 398         if (IS_ERR(data->edev))
 399                 return -EPROBE_DEFER;
 400
 401         ret = devfreq_event_enable_edev(data->edev);
 402         if (ret < 0) {
 403                 dev_err(dev, "failed to enable devfreq-event devices\n");
 404                 return ret;
 405         }
 406
 407         /*
 408          * Get dram timing and pass it to arm trust firmware,
 409          * the dram drvier in arm trust firmware will get these
 410          * timing and to do dram initial.
 411          */
 412         data->timing = of_get_ddr_timings(dev, np);
 413         if (data->timing) {
 414                 timing = (uint32_t *)data->timing;
 415                 size = sizeof(struct dram_timing) / 4;
 416                 for (index = 0; index < size; index++) {
 417                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 418                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 419                                       0, 0, 0, 0, &res);
 420                         if (res.a0) {
 421                                 dev_err(dev, "Failed to set dram param: %ld\n",
 422                                         res.a0);
 423                                 return -EINVAL;
 424                         }
 425                 }
 426         }
 427
 428         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 429                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 430                       0, 0, 0, 0, &res);
 431
 432         /*
 433          * We add a devfreq driver to our parent since it has a device tree node
 434          * with operating points.
 435          */
 436         if (dev_pm_opp_of_add_table(dev)) {
 437                 dev_err(dev, "Invalid operating-points in device tree.\n");
 438                 return -EINVAL;
 439         }
 440
 441         if (rk3399_dmcfreq_init_freq_table(dev, devp))
 442                 return -EFAULT;
 443
 444         of_property_read_u32(np, "upthreshold",
 445                              &data->ondemand_data.upthreshold);
 446         of_property_read_u32(np, "downdifferential",
 447                              &data->ondemand_data.downdifferential);
 448
 449         data->rate = clk_get_rate(data->dmc_clk);
 450         data->volt = regulator_get_voltage(data->vdd_center);
 451
 452         devp->initial_freq = data->rate;
 453         data->devfreq = devm_devfreq_add_device(dev, devp,
 454                                            "simple_ondemand",
 455                                            &data->ondemand_data);
 456         if (IS_ERR(data->devfreq))
 457                 return PTR_ERR(data->devfreq);
 458         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 459
 460         data->devfreq->min_freq = devp->freq_table[0];
 461         data->devfreq->max_freq =
 462                 devp->freq_table[devp->max_state ? devp->max_state - 1 : 0];
 463
 464         data->dev = dev;
 465         platform_set_drvdata(pdev, data);
 466
 467         if (vop_register_dmc())
 468                 dev_err(dev, "fail to register notify to vop.\n");
 469
 470         return 0;
 471 }
 472
 473 static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
 474         { .compatible = "rockchip,rk3399-dmc" },
 475         { },
 476 };
 477 MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
 478
 479 static struct platform_driver rk3399_dmcfreq_driver = {
 480         .probe  = rk3399_dmcfreq_probe,
 481         .driver = {
 482                 .name   = "rk3399-dmc-freq",
 483                 .pm     = &rk3399_dmcfreq_pm,
 484                 .of_match_table = rk3399dmc_devfreq_of_match,
 485         },
 486 };
 487 module_platform_driver(rk3399_dmcfreq_driver);
 488
 489 MODULE_LICENSE("GPL v2");
 490 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 491 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");