drivers/devfreq/ddr_rk3368.c

   1 /*
   2  * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, you can access it online at
  15  * http://www.gnu.org/licenses/gpl-2.0.html.
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <linux/kernel.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31
  32 #include <asm/cacheflush.h>
  33 #include <asm/tlbflush.h>
  34 #include <linux/cpu.h>
  35 #include <dt-bindings/clock/ddr.h>
  36 #include <linux/rockchip/common.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39 #include <linux/rockchip/dvfs.h>
  40 #include <linux/rockchip/grf.h>
  41 #include <linux/rockchip/iomap.h>
  42 #include <linux/rockchip/pmu.h>
  43 #include <linux/rk_fb.h>
  44 #include <linux/scpi_protocol.h>
  45
  46 #define GRF_DDRC0_CON0    0x600
  47 #define GRF_SOC_STATUS5  0x494
  48 #define DDR_PCTL_TOGCNT_1U  0xc0
  49
  50 enum ddr_bandwidth_id {
  51         ddrbw_wr_num = 0,
  52         ddrbw_rd_num,
  53         ddrbw_act_num,
  54         ddrbw_time_num,
  55         ddrbw_eff,
  56         ddrbw_id_end
  57 };
  58
  59 struct rockchip_ddr {
  60         struct regmap *ddrpctl_regs;
  61         struct regmap *msch_regs;
  62         struct regmap *grf_regs;
  63 };
  64
  65 static struct rockchip_ddr *ddr_data = NULL;
  66
  67 static int _ddr_recalc_rate(void)
  68 {
  69         int ddr_freq;
  70
  71         regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
  72                     &ddr_freq);
  73         ddr_freq = ddr_freq * 2 * 1000000;
  74         return ddr_freq;
  75 }
  76
  77 static int _ddr_change_freq(u32 n_mhz)
  78 {
  79         u32 ret;
  80
  81         printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
  82         if (scpi_ddr_set_clk_rate(n_mhz))
  83                 pr_info("set ddr freq timeout\n");
  84         ret = _ddr_recalc_rate() / 1000000;
  85         printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
  86         return ret;
  87 }
  88
  89 static long _ddr_round_rate(u32 n_mhz)
  90 {
  91         return (n_mhz / 12) * 12;
  92 }
  93
  94 static void _ddr_set_auto_self_refresh(bool en)
  95 {
  96         if (scpi_ddr_set_auto_self_refresh(en))
  97                 printk(KERN_DEBUG pr_fmt("ddr set auto selfrefresh error\n"));
  98 }
  99
 100 static void ddr_monitor_start(void)
 101 {
 102         u32 i;
 103
 104         /* cpum, gpu probe */
 105         for (i = 1; i < 3; i++) {
 106                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x8,
 107                              0x8);
 108                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0xc,
 109                              0x1);
 110                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x138,
 111                              0x6);
 112                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x14c,
 113                              0x10);
 114                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x160,
 115                              0x8);
 116                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x174,
 117                              0x10);
 118         }
 119         /* video, vio0, vio1 probe */
 120         for (i = 0; i < 3; i++) {
 121                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x8,
 122                              0x8);
 123                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0xc,
 124                              0x1);
 125                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x138,
 126                              0x6);
 127                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x14c,
 128                              0x10);
 129                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x160,
 130                              0x8);
 131                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x174,
 132                              0x10);
 133         }
 134         /* dfi eff start */
 135         regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
 136                      ((0x3 << 5) << 16) | 0x3 << 5);
 137         /*flash data */
 138         wmb();
 139         /* trigger statistic */
 140         for (i = 1; i < 3; i++)
 141                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x28,
 142                              0x1);
 143         for (i = 0; i < 3; i++)
 144                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x28,
 145                              0x1);
 146 }
 147
 148 static void ddr_monitor_stop(void)
 149 {
 150         /* dfi eff stop */
 151         regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
 152                      ((0x3 << 5) << 16) | 0x0 << 5);
 153 }
 154
 155 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
 156                                struct ddr_bw_info *ddr_bw_ch1)
 157 {
 158         u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq, dfi_freq;
 159         u64 temp64;
 160         int i, j;
 161         u32 tmp32;
 162
 163         if (!ddr_data)
 164                 return;
 165
 166         ddr_monitor_stop();
 167         /* read dfi eff */
 168         for (j = 0; j < 2; j++) {
 169                 for (i = 0; i < ddrbw_eff; i++) {
 170                         regmap_read(ddr_data->grf_regs,
 171                                     GRF_SOC_STATUS5 + 4 * i + j * 16,
 172                                     &ddr_bw_val[j][i]);
 173                 }
 174         }
 175         if (!ddr_bw_val[0][ddrbw_time_num])
 176                 goto end;
 177         if (ddr_bw_ch0) {
 178                 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
 179                             &ddr_freq);
 180                 ddr_freq *= 2;
 181                 dfi_freq = ddr_freq / 2;
 182                 /* dfi eff */
 183                 temp64 = ((u64) ddr_bw_val[0][0] + ddr_bw_val[0][1]
 184                           + ddr_bw_val[1][0] + ddr_bw_val[1][1]) * 2 * 100;
 185                 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
 186                 ddr_bw_val[0][ddrbw_eff] = temp64;
 187                 ddr_bw_ch0->ddr_percent = temp64;
 188                 ddr_bw_ch0->ddr_time =
 189                     ddr_bw_val[0][ddrbw_time_num] / (dfi_freq * 1000);
 190                 /*unit:MB/s */
 191                 ddr_bw_ch0->ddr_wr = (((u64)
 192                                        (ddr_bw_val[0][ddrbw_wr_num] +
 193                                         ddr_bw_val[1][ddrbw_wr_num]) * 8 * 4) *
 194                                       dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
 195                 ddr_bw_ch0->ddr_rd = (((u64)
 196                                        (ddr_bw_val[0][ddrbw_rd_num] +
 197                                         ddr_bw_val[1][ddrbw_rd_num]) * 8 * 4) *
 198                                       dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
 199                 ddr_bw_ch0->ddr_act = ddr_bw_val[0][ddrbw_act_num];
 200                 ddr_bw_ch0->ddr_total = ddr_freq * 2 * 4;
 201                 /* noc unit:bype */
 202                 regmap_read(ddr_data->msch_regs, 0x1400 + 0x178, &tmp32);
 203                 regmap_read(ddr_data->msch_regs, 0x1400 + 0x164,
 204                             &ddr_bw_ch0->cpum);
 205                 ddr_bw_ch0->cpum += (tmp32 << 16);
 206                 regmap_read(ddr_data->msch_regs, 0x1800 + 0x178, &tmp32);
 207                 regmap_read(ddr_data->msch_regs, 0x1800 + 0x164,
 208                             &ddr_bw_ch0->gpu);
 209                 ddr_bw_ch0->gpu += (tmp32 << 16);
 210                 ddr_bw_ch0->peri = 0;
 211                 regmap_read(ddr_data->msch_regs, 0x2000 + 0x178, &tmp32);
 212                 regmap_read(ddr_data->msch_regs, 0x2000 + 0x164,
 213                             &ddr_bw_ch0->video);
 214                 ddr_bw_ch0->video += (tmp32 << 16);
 215                 regmap_read(ddr_data->msch_regs, 0x2400 + 0x178, &tmp32);
 216                 regmap_read(ddr_data->msch_regs, 0x2400 + 0x164,
 217                             &ddr_bw_ch0->vio0);
 218                 ddr_bw_ch0->vio0 += (tmp32 << 16);
 219                 regmap_read(ddr_data->msch_regs, 0x2800 + 0x178, &tmp32);
 220                 regmap_read(ddr_data->msch_regs, 0x2800 + 0x164,
 221                             &ddr_bw_ch0->vio1);
 222                 ddr_bw_ch0->vio1 += (tmp32 << 16);
 223                 ddr_bw_ch0->vio2 = 0;
 224
 225                 /* B/s => MB/s */
 226                 ddr_bw_ch0->cpum =
 227                     (u64) ddr_bw_ch0->cpum * dfi_freq /
 228                     ddr_bw_val[0][ddrbw_time_num];
 229                 ddr_bw_ch0->gpu =
 230                     (u64) ddr_bw_ch0->gpu * dfi_freq /
 231                     ddr_bw_val[0][ddrbw_time_num];
 232                 ddr_bw_ch0->peri =
 233                     (u64) ddr_bw_ch0->peri * dfi_freq /
 234                     ddr_bw_val[0][ddrbw_time_num];
 235                 ddr_bw_ch0->video =
 236                     (u64) ddr_bw_ch0->video * dfi_freq /
 237                     ddr_bw_val[0][ddrbw_time_num];
 238                 ddr_bw_ch0->vio0 =
 239                     (u64) ddr_bw_ch0->vio0 * dfi_freq /
 240                     ddr_bw_val[0][ddrbw_time_num];
 241                 ddr_bw_ch0->vio1 =
 242                     (u64) ddr_bw_ch0->vio1 * dfi_freq /
 243                     ddr_bw_val[0][ddrbw_time_num];
 244                 ddr_bw_ch0->vio2 =
 245                     (u64) ddr_bw_ch0->vio2 * dfi_freq /
 246                     ddr_bw_val[0][ddrbw_time_num];
 247         }
 248 end:
 249         ddr_monitor_start();
 250 }
 251
 252 static void ddr_init(u32 dram_speed_bin, u32 freq)
 253 {
 254         int lcdc_type;
 255
 256         lcdc_type = rockchip_get_screen_type();
 257         printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
 258                __func__, dram_speed_bin, freq, lcdc_type);
 259         if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type))
 260                 pr_info("ddr init error\n");
 261         else
 262                 printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
 263 }
 264
 265 static int ddr_init_resume(struct platform_device *pdev)
 266 {
 267         ddr_init(DDR3_DEFAULT, 0);
 268         return 0;
 269 }
 270
 271 static int __init rockchip_ddr_probe(struct platform_device *pdev)
 272 {
 273         struct device_node *np;
 274
 275         np = pdev->dev.of_node;
 276         ddr_data =
 277             devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
 278         if (!ddr_data) {
 279                 dev_err(&pdev->dev, "no memory for state\n");
 280                 return -ENOMEM;
 281         }
 282         /* ddrpctl */
 283         ddr_data->ddrpctl_regs =
 284             syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
 285         if (IS_ERR(ddr_data->ddrpctl_regs)) {
 286                 dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
 287                         __func__);
 288                 return -ENXIO;
 289         }
 290
 291         /* grf */
 292         ddr_data->grf_regs =
 293             syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 294         if (IS_ERR(ddr_data->grf_regs)) {
 295                 dev_err(&pdev->dev, "%s: could not find grf dt node\n",
 296                         __func__);
 297                 return -ENXIO;
 298         }
 299         /* msch */
 300         ddr_data->msch_regs =
 301             syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
 302         if (IS_ERR(ddr_data->msch_regs)) {
 303                 dev_err(&pdev->dev, "%s: could not find msch dt node\n",
 304                         __func__);
 305                 return -ENXIO;
 306         }
 307
 308         platform_set_drvdata(pdev, ddr_data);
 309         ddr_change_freq = _ddr_change_freq;
 310         ddr_round_rate = _ddr_round_rate;
 311         ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 312         ddr_bandwidth_get = _ddr_bandwidth_get;
 313         ddr_recalc_rate = _ddr_recalc_rate;
 314         ddr_init(DDR3_DEFAULT, 0);
 315         pr_info("%s: success\n", __func__);
 316         return 0;
 317 }
 318
 319 static const struct of_device_id rockchip_ddr_of_match[] __refdata = {
 320         {.compatible = "rockchip,rk3368-ddr", .data = NULL,},
 321         {},
 322 };
 323
 324 static struct platform_driver rockchip_ddr_driver = {
 325 #ifdef CONFIG_PM
 326         .resume = ddr_init_resume,
 327 #endif /* CONFIG_PM */
 328         .driver = {
 329                    .name = "rockchip_ddr",
 330                    .of_match_table = rockchip_ddr_of_match,
 331         },
 332 };
 333
 334 static int __init rockchip_ddr_init(void)
 335 {
 336         pr_info("rockchip_ddr_init\n");
 337         return platform_driver_probe(&rockchip_ddr_driver, rockchip_ddr_probe);
 338 }
 339
 340 device_initcall(rockchip_ddr_init);