drivers/devfreq/ddr_rk3368.c

   1 /*
   2  * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, you can access it online at
  15  * http://www.gnu.org/licenses/gpl-2.0.html.
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <asm/compiler.h>
  21 #include <dt-bindings/clock/ddr.h>
  22 #include <linux/delay.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regmap.h>
  27 #include <linux/rk_fb.h>
  28 #include <linux/rockchip/common.h>
  29 #include <linux/rockchip/psci.h>
  30 #include <linux/scpi_protocol.h>
  31
  32 #define GRF_DDRC0_CON0    0x600
  33 #define GRF_SOC_STATUS5  0x494
  34 #define DDR_PCTL_TOGCNT_1U  0xc0
  35
  36 #define FIQ_CPU_TGT_BOOT                0x0 /* to booting cpu */
  37 #define FIQ_NUM_FOR_DCF         (143)  /*NA irq map to fiq for dcf*/
  38
  39
  40 #define DDR_VERSION                     "V1.02 20150907"
  41
  42 enum ddr_bandwidth_id {
  43         ddrbw_wr_num = 0,
  44         ddrbw_rd_num,
  45         ddrbw_act_num,
  46         ddrbw_time_num,
  47         ddrbw_eff,
  48         ddrbw_id_end
  49 };
  50
  51 struct rockchip_ddr {
  52         struct regmap *ddrpctl_regs;
  53         struct regmap *msch_regs;
  54         struct regmap *grf_regs;
  55 };
  56
  57 static struct rockchip_ddr *ddr_data = NULL;
  58
  59 static int _ddr_recalc_rate(void)
  60 {
  61         int ddr_freq;
  62
  63         regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
  64                     &ddr_freq);
  65         ddr_freq = ddr_freq * 2 * 1000000;
  66         return ddr_freq;
  67 }
  68
  69 static int _ddr_change_freq(u32 n_mhz)
  70 {
  71         u32 ret;
  72         u32 lcdc_type;
  73         struct rk_lcdc_driver *lcdc_dev = NULL;
  74
  75         printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
  76         lcdc_dev = rk_get_lcdc_drv("lcdc0");
  77         lcdc_type = lcdc_dev ? (u32)lcdc_dev->cur_screen->type : 0;
  78         printk(KERN_DEBUG pr_fmt("lcdc type:%d\n"), lcdc_type);
  79         if (scpi_ddr_set_clk_rate(n_mhz, lcdc_type))
  80                 pr_info("set ddr freq timeout\n");
  81         ret = _ddr_recalc_rate() / 1000000;
  82         printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
  83         return ret;
  84 }
  85
  86 static long _ddr_round_rate(u32 n_mhz)
  87 {
  88         return (n_mhz / 12) * 12;
  89 }
  90
  91 static void _ddr_set_auto_self_refresh(bool en)
  92 {
  93         if (scpi_ddr_set_auto_self_refresh(en))
  94                 printk(KERN_DEBUG pr_fmt("ddr set auto selfrefresh error\n"));
  95 }
  96
  97 static void ddr_monitor_start(void)
  98 {
  99         u32 i;
 100
 101         /* cpum, gpu probe */
 102         for (i = 1; i < 3; i++) {
 103                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x8,
 104                              0x8);
 105                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0xc,
 106                              0x1);
 107                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x138,
 108                              0x6);
 109                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x14c,
 110                              0x10);
 111                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x160,
 112                              0x8);
 113                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x174,
 114                              0x10);
 115         }
 116         /* video, vio0, vio1 probe */
 117         for (i = 0; i < 3; i++) {
 118                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x8,
 119                              0x8);
 120                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0xc,
 121                              0x1);
 122                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x138,
 123                              0x6);
 124                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x14c,
 125                              0x10);
 126                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x160,
 127                              0x8);
 128                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x174,
 129                              0x10);
 130         }
 131         /* dfi eff start */
 132         regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
 133                      ((0x3 << 5) << 16) | 0x3 << 5);
 134         /*flash data */
 135         wmb();
 136         /* trigger statistic */
 137         for (i = 1; i < 3; i++)
 138                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x28,
 139                              0x1);
 140         for (i = 0; i < 3; i++)
 141                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x28,
 142                              0x1);
 143 }
 144
 145 static void ddr_monitor_stop(void)
 146 {
 147         /* dfi eff stop */
 148         regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
 149                      ((0x3 << 5) << 16) | 0x0 << 5);
 150 }
 151
 152 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
 153                                struct ddr_bw_info *ddr_bw_ch1)
 154 {
 155         u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq, dfi_freq;
 156         u64 temp64;
 157         int i, j;
 158         u32 tmp32;
 159
 160         if (!ddr_data)
 161                 return;
 162
 163         ddr_monitor_stop();
 164         /* read dfi eff */
 165         for (j = 0; j < 2; j++) {
 166                 for (i = 0; i < ddrbw_eff; i++) {
 167                         regmap_read(ddr_data->grf_regs,
 168                                     GRF_SOC_STATUS5 + 4 * i + j * 16,
 169                                     &ddr_bw_val[j][i]);
 170                 }
 171         }
 172         if (!ddr_bw_val[0][ddrbw_time_num])
 173                 goto end;
 174         if (ddr_bw_ch0) {
 175                 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
 176                             &ddr_freq);
 177                 ddr_freq *= 2;
 178                 dfi_freq = ddr_freq / 2;
 179                 /* dfi eff */
 180                 temp64 = ((u64) ddr_bw_val[0][0] + ddr_bw_val[0][1]
 181                           + ddr_bw_val[1][0] + ddr_bw_val[1][1]) * 2 * 100;
 182                 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
 183                 ddr_bw_val[0][ddrbw_eff] = temp64;
 184                 ddr_bw_ch0->ddr_percent = temp64;
 185                 ddr_bw_ch0->ddr_time =
 186                     ddr_bw_val[0][ddrbw_time_num] / (dfi_freq * 1000);
 187                 /*unit:MB/s */
 188                 ddr_bw_ch0->ddr_wr = (((u64)
 189                                        (ddr_bw_val[0][ddrbw_wr_num] +
 190                                         ddr_bw_val[1][ddrbw_wr_num]) * 8 * 4) *
 191                                       dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
 192                 ddr_bw_ch0->ddr_rd = (((u64)
 193                                        (ddr_bw_val[0][ddrbw_rd_num] +
 194                                         ddr_bw_val[1][ddrbw_rd_num]) * 8 * 4) *
 195                                       dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
 196                 ddr_bw_ch0->ddr_act = ddr_bw_val[0][ddrbw_act_num];
 197                 ddr_bw_ch0->ddr_total = ddr_freq * 2 * 4;
 198                 /* noc unit:bype */
 199                 regmap_read(ddr_data->msch_regs, 0x1400 + 0x178, &tmp32);
 200                 regmap_read(ddr_data->msch_regs, 0x1400 + 0x164,
 201                             &ddr_bw_ch0->cpum);
 202                 ddr_bw_ch0->cpum += (tmp32 << 16);
 203                 regmap_read(ddr_data->msch_regs, 0x1800 + 0x178, &tmp32);
 204                 regmap_read(ddr_data->msch_regs, 0x1800 + 0x164,
 205                             &ddr_bw_ch0->gpu);
 206                 ddr_bw_ch0->gpu += (tmp32 << 16);
 207                 ddr_bw_ch0->peri = 0;
 208                 regmap_read(ddr_data->msch_regs, 0x2000 + 0x178, &tmp32);
 209                 regmap_read(ddr_data->msch_regs, 0x2000 + 0x164,
 210                             &ddr_bw_ch0->video);
 211                 ddr_bw_ch0->video += (tmp32 << 16);
 212                 regmap_read(ddr_data->msch_regs, 0x2400 + 0x178, &tmp32);
 213                 regmap_read(ddr_data->msch_regs, 0x2400 + 0x164,
 214                             &ddr_bw_ch0->vio0);
 215                 ddr_bw_ch0->vio0 += (tmp32 << 16);
 216                 regmap_read(ddr_data->msch_regs, 0x2800 + 0x178, &tmp32);
 217                 regmap_read(ddr_data->msch_regs, 0x2800 + 0x164,
 218                             &ddr_bw_ch0->vio1);
 219                 ddr_bw_ch0->vio1 += (tmp32 << 16);
 220                 ddr_bw_ch0->vio2 = 0;
 221
 222                 /* B/s => MB/s */
 223                 ddr_bw_ch0->cpum =
 224                     (u64) ddr_bw_ch0->cpum * dfi_freq /
 225                     ddr_bw_val[0][ddrbw_time_num];
 226                 ddr_bw_ch0->gpu =
 227                     (u64) ddr_bw_ch0->gpu * dfi_freq /
 228                     ddr_bw_val[0][ddrbw_time_num];
 229                 ddr_bw_ch0->peri =
 230                     (u64) ddr_bw_ch0->peri * dfi_freq /
 231                     ddr_bw_val[0][ddrbw_time_num];
 232                 ddr_bw_ch0->video =
 233                     (u64) ddr_bw_ch0->video * dfi_freq /
 234                     ddr_bw_val[0][ddrbw_time_num];
 235                 ddr_bw_ch0->vio0 =
 236                     (u64) ddr_bw_ch0->vio0 * dfi_freq /
 237                     ddr_bw_val[0][ddrbw_time_num];
 238                 ddr_bw_ch0->vio1 =
 239                     (u64) ddr_bw_ch0->vio1 * dfi_freq /
 240                     ddr_bw_val[0][ddrbw_time_num];
 241                 ddr_bw_ch0->vio2 =
 242                     (u64) ddr_bw_ch0->vio2 * dfi_freq /
 243                     ddr_bw_val[0][ddrbw_time_num];
 244         }
 245 end:
 246         ddr_monitor_start();
 247 }
 248
 249 static void ddr_init(u32 dram_speed_bin, u32 freq, u32 addr_mcu_el3)
 250 {
 251         int lcdc_type;
 252         static u32 addr = 0;
 253
 254         struct rk_lcdc_driver *lcdc_dev = NULL;
 255
 256         if (addr == 0)
 257                 addr = addr_mcu_el3;
 258
 259         lcdc_dev = rk_get_lcdc_drv("lcdc0");
 260         if (lcdc_dev == NULL)
 261                 lcdc_type = 0;
 262         else
 263                 lcdc_type = (u32)lcdc_dev->cur_screen->type;
 264         printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
 265                __func__, dram_speed_bin, freq, lcdc_type);
 266         if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type, addr))
 267                 pr_info("ddr init error\n");
 268         else
 269                 printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
 270 }
 271
 272 static int ddr_init_resume(struct platform_device *pdev)
 273 {
 274         ddr_init(DDR3_DEFAULT, 0, 0);
 275         return 0;
 276 }
 277 #define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
 278 #define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
 279 /* valid ver */
 280 #define RKTF_VLDVER_MAJOR (1)
 281 #define RKTF_VLDVER_MINOR (5)
 282
 283 static int __init rockchip_tf_ver_check(void)
 284 {
 285         u32 version;
 286
 287         version = rockchip_psci_smc_get_tf_ver();
 288         if (((RKTF_VER_MAJOR(version) == RKTF_VLDVER_MAJOR) &&
 289              (RKTF_VER_MINOR(version) >= RKTF_VLDVER_MINOR)) ||
 290             (RKTF_VER_MAJOR(version) > RKTF_VLDVER_MAJOR))
 291                 return 0;
 292
 293         pr_err("read tf version 0x%x!\n", version);
 294
 295         do {
 296                 mdelay(1000);
 297                 pr_err("trusted firmware need to update to(%d.%d) or is invaild!\n",
 298                        RKTF_VLDVER_MAJOR, RKTF_VLDVER_MINOR);
 299         } while (1);
 300
 301         return 0;
 302 }
 303
 304
 305 static int __init rockchip_ddr_probe(struct platform_device *pdev)
 306 {
 307         u32 addr_mcu_el3;
 308         struct device_node *np;
 309
 310         pr_info("Rockchip DDR Initialize, verision: "DDR_VERSION"\n");
 311         np = pdev->dev.of_node;
 312         ddr_data =
 313             devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
 314         if (!ddr_data) {
 315                 dev_err(&pdev->dev, "no memory for state\n");
 316                 return -ENOMEM;
 317         }
 318         /* ddrpctl */
 319         ddr_data->ddrpctl_regs =
 320             syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
 321         if (IS_ERR(ddr_data->ddrpctl_regs)) {
 322                 dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
 323                         __func__);
 324                 return -ENXIO;
 325         }
 326
 327         /* grf */
 328         ddr_data->grf_regs =
 329             syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 330         if (IS_ERR(ddr_data->grf_regs)) {
 331                 dev_err(&pdev->dev, "%s: could not find grf dt node\n",
 332                         __func__);
 333                 return -ENXIO;
 334         }
 335         /* msch */
 336         ddr_data->msch_regs =
 337             syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
 338         if (IS_ERR(ddr_data->msch_regs)) {
 339                 dev_err(&pdev->dev, "%s: could not find msch dt node\n",
 340                         __func__);
 341                 return -ENXIO;
 342         }
 343
 344         platform_set_drvdata(pdev, ddr_data);
 345         ddr_change_freq = _ddr_change_freq;
 346         ddr_round_rate = _ddr_round_rate;
 347         ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 348         ddr_bandwidth_get = _ddr_bandwidth_get;
 349         ddr_recalc_rate = _ddr_recalc_rate;
 350         rockchip_tf_ver_check();
 351         addr_mcu_el3 = rockchip_psci_smc_write(PSCI_SIP_EL3FIQ_CFG,
 352                                                FIQ_NUM_FOR_DCF,
 353                                                FIQ_CPU_TGT_BOOT, 0);
 354         if ((addr_mcu_el3 == 0) || (addr_mcu_el3 > 0x80000))
 355                 pr_info("Trust version error, pls check trust version\n");
 356         ddr_init(DDR3_DEFAULT, 0, addr_mcu_el3);
 357         pr_info("%s: success\n", __func__);
 358         return 0;
 359 }
 360
 361 static const struct of_device_id rockchip_ddr_of_match[] __refdata = {
 362         {.compatible = "rockchip,rk3368-ddr", .data = NULL,},
 363         {},
 364 };
 365
 366 static struct platform_driver rockchip_ddr_driver = {
 367 #ifdef CONFIG_PM
 368         .resume = ddr_init_resume,
 369 #endif /* CONFIG_PM */
 370         .driver = {
 371                    .name = "rockchip_ddr",
 372                    .of_match_table = rockchip_ddr_of_match,
 373         },
 374 };
 375
 376 static int __init rockchip_ddr_init(void)
 377 {
 378         pr_info("rockchip_ddr_init\n");
 379         return platform_driver_probe(&rockchip_ddr_driver, rockchip_ddr_probe);
 380 }
 381
 382 device_initcall(rockchip_ddr_init);