drivers/devfreq/ddr_rk3368.c

   1 /*
   2  * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, you can access it online at
  15  * http://www.gnu.org/licenses/gpl-2.0.html.
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <dt-bindings/clock/ddr.h>
  21 #include <linux/delay.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26 #include <linux/rk_fb.h>
  27 #include <linux/rockchip/common.h>
  28 #include <linux/rockchip/psci.h>
  29 #include <linux/scpi_protocol.h>
  30 #include <asm/compiler.h>
  31
  32 #define GRF_DDRC0_CON0    0x600
  33 #define GRF_SOC_STATUS5  0x494
  34 #define DDR_PCTL_TOGCNT_1U  0xc0
  35
  36 #define FIQ_CPU_TGT_BOOT                0x0 /* to booting cpu */
  37 #define FIQ_NUM_FOR_DCF         (143)  /*NA irq map to fiq for dcf*/
  38
  39
  40 #define DDR_VERSION                     "V1.03 20150910"
  41
  42 enum ddr_bandwidth_id {
  43         ddrbw_wr_num = 0,
  44         ddrbw_rd_num,
  45         ddrbw_act_num,
  46         ddrbw_time_num,
  47         ddrbw_eff,
  48         ddrbw_id_end
  49 };
  50
  51 struct ddr_timing {
  52         u32 dram_spd_bin;
  53         u32 sr_idle;
  54         u32 pd_idle;
  55         u32 dram_dll_dis_freq;
  56         u32 phy_dll_dis_freq;
  57         u32 dram_odt_dis_freq;
  58         u32 phy_odt_dis_freq;
  59         u32 ddr3_drv;
  60         u32 ddr3_odt;
  61         u32 lpddr3_drv;
  62         u32 lpddr3_odt;
  63         u32 lpddr2_drv;
  64         u32 phy_clk_drv;
  65         u32 phy_cmd_drv;
  66         u32 phy_dqs_drv;
  67         u32 phy_odt;
  68 };
  69
  70 struct rockchip_ddr {
  71         struct regmap *ddrpctl_regs;
  72         struct regmap *msch_regs;
  73         struct regmap *grf_regs;
  74         struct ddr_timing dram_timing;
  75 };
  76
  77 static struct rockchip_ddr *ddr_data = NULL;
  78
  79 static int of_do_get_timings(struct device_node *np, struct ddr_timing *tim)
  80 {
  81         struct device_node *np_tim;
  82         int ret;
  83
  84         ret = 0;
  85
  86         np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
  87         if (!np_tim)
  88                 return 1;
  89
  90         ret |= of_property_read_u32(np_tim, "dram_spd_bin",
  91                                     &tim->dram_spd_bin);
  92         ret |= of_property_read_u32(np_tim, "sr_idle", &tim->sr_idle);
  93         ret |= of_property_read_u32(np_tim, "pd_idle", &tim->pd_idle);
  94         ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
  95                                     &tim->dram_dll_dis_freq);
  96         ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
  97                                     &tim->phy_dll_dis_freq);
  98         ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
  99                                     &tim->dram_odt_dis_freq);
 100         ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
 101                                     &tim->phy_odt_dis_freq);
 102         ret |= of_property_read_u32(np_tim, "ddr3_drv", &tim->ddr3_drv);
 103         ret |= of_property_read_u32(np_tim, "ddr3_odt", &tim->ddr3_odt);
 104         ret |= of_property_read_u32(np_tim, "lpddr3_drv", &tim->lpddr3_drv);
 105         ret |= of_property_read_u32(np_tim, "lpddr3_odt", &tim->lpddr3_odt);
 106         ret |= of_property_read_u32(np_tim, "lpddr2_drv", &tim->lpddr2_drv);
 107         ret |= of_property_read_u32(np_tim, "phy_clk_drv", &tim->phy_clk_drv);
 108         ret |= of_property_read_u32(np_tim, "phy_cmd_drv", &tim->phy_cmd_drv);
 109         ret |= of_property_read_u32(np_tim, "phy_dqs_drv", &tim->phy_dqs_drv);
 110         ret |= of_property_read_u32(np_tim, "phy_odt", &tim->phy_odt);
 111
 112         return ret;
 113 }
 114
 115 static int _ddr_recalc_rate(void)
 116 {
 117         int ddr_freq;
 118
 119         regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
 120                     &ddr_freq);
 121         ddr_freq = ddr_freq * 2 * 1000000;
 122         return ddr_freq;
 123 }
 124
 125 static int _ddr_change_freq(u32 n_mhz)
 126 {
 127         u32 ret;
 128         u32 lcdc_type;
 129         struct rk_lcdc_driver *lcdc_dev = NULL;
 130
 131         printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
 132         lcdc_dev = rk_get_lcdc_drv("lcdc0");
 133         lcdc_type = lcdc_dev ? (u32)lcdc_dev->cur_screen->type : 0;
 134         printk(KERN_DEBUG pr_fmt("lcdc type:%d\n"), lcdc_type);
 135         if (scpi_ddr_set_clk_rate(n_mhz, lcdc_type))
 136                 pr_info("set ddr freq timeout\n");
 137         ret = _ddr_recalc_rate() / 1000000;
 138         printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
 139         return ret;
 140 }
 141
 142 static long _ddr_round_rate(u32 n_mhz)
 143 {
 144         return (n_mhz / 12) * 12;
 145 }
 146
 147 static void _ddr_set_auto_self_refresh(bool en)
 148 {
 149         if (scpi_ddr_set_auto_self_refresh(en))
 150                 printk(KERN_DEBUG pr_fmt("ddr set auto selfrefresh error\n"));
 151 }
 152
 153 static void ddr_monitor_start(void)
 154 {
 155         u32 i;
 156
 157         /* cpum, gpu probe */
 158         for (i = 1; i < 3; i++) {
 159                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x8,
 160                              0x8);
 161                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0xc,
 162                              0x1);
 163                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x138,
 164                              0x6);
 165                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x14c,
 166                              0x10);
 167                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x160,
 168                              0x8);
 169                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x174,
 170                              0x10);
 171         }
 172         /* video, vio0, vio1 probe */
 173         for (i = 0; i < 3; i++) {
 174                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x8,
 175                              0x8);
 176                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0xc,
 177                              0x1);
 178                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x138,
 179                              0x6);
 180                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x14c,
 181                              0x10);
 182                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x160,
 183                              0x8);
 184                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x174,
 185                              0x10);
 186         }
 187         /* dfi eff start */
 188         regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
 189                      ((0x3 << 5) << 16) | 0x3 << 5);
 190         /*flash data */
 191         wmb();
 192         /* trigger statistic */
 193         for (i = 1; i < 3; i++)
 194                 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x28,
 195                              0x1);
 196         for (i = 0; i < 3; i++)
 197                 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x28,
 198                              0x1);
 199 }
 200
 201 static void ddr_monitor_stop(void)
 202 {
 203         /* dfi eff stop */
 204         regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
 205                      ((0x3 << 5) << 16) | 0x0 << 5);
 206 }
 207
 208 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
 209                                struct ddr_bw_info *ddr_bw_ch1)
 210 {
 211         u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq, dfi_freq;
 212         u64 temp64;
 213         int i, j;
 214         u32 tmp32;
 215
 216         if (!ddr_data)
 217                 return;
 218
 219         ddr_monitor_stop();
 220         /* read dfi eff */
 221         for (j = 0; j < 2; j++) {
 222                 for (i = 0; i < ddrbw_eff; i++) {
 223                         regmap_read(ddr_data->grf_regs,
 224                                     GRF_SOC_STATUS5 + 4 * i + j * 16,
 225                                     &ddr_bw_val[j][i]);
 226                 }
 227         }
 228         if (!ddr_bw_val[0][ddrbw_time_num])
 229                 goto end;
 230         if (ddr_bw_ch0) {
 231                 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
 232                             &ddr_freq);
 233                 ddr_freq *= 2;
 234                 dfi_freq = ddr_freq / 2;
 235                 /* dfi eff */
 236                 temp64 = ((u64) ddr_bw_val[0][0] + ddr_bw_val[0][1]
 237                           + ddr_bw_val[1][0] + ddr_bw_val[1][1]) * 2 * 100;
 238                 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
 239                 ddr_bw_val[0][ddrbw_eff] = temp64;
 240                 ddr_bw_ch0->ddr_percent = temp64;
 241                 ddr_bw_ch0->ddr_time =
 242                     ddr_bw_val[0][ddrbw_time_num] / (dfi_freq * 1000);
 243                 /*unit:MB/s */
 244                 ddr_bw_ch0->ddr_wr = (((u64)
 245                                        (ddr_bw_val[0][ddrbw_wr_num] +
 246                                         ddr_bw_val[1][ddrbw_wr_num]) * 8 * 4) *
 247                                       dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
 248                 ddr_bw_ch0->ddr_rd = (((u64)
 249                                        (ddr_bw_val[0][ddrbw_rd_num] +
 250                                         ddr_bw_val[1][ddrbw_rd_num]) * 8 * 4) *
 251                                       dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
 252                 ddr_bw_ch0->ddr_act = ddr_bw_val[0][ddrbw_act_num];
 253                 ddr_bw_ch0->ddr_total = ddr_freq * 2 * 4;
 254                 /* noc unit:bype */
 255                 regmap_read(ddr_data->msch_regs, 0x1400 + 0x178, &tmp32);
 256                 regmap_read(ddr_data->msch_regs, 0x1400 + 0x164,
 257                             &ddr_bw_ch0->cpum);
 258                 ddr_bw_ch0->cpum += (tmp32 << 16);
 259                 regmap_read(ddr_data->msch_regs, 0x1800 + 0x178, &tmp32);
 260                 regmap_read(ddr_data->msch_regs, 0x1800 + 0x164,
 261                             &ddr_bw_ch0->gpu);
 262                 ddr_bw_ch0->gpu += (tmp32 << 16);
 263                 ddr_bw_ch0->peri = 0;
 264                 regmap_read(ddr_data->msch_regs, 0x2000 + 0x178, &tmp32);
 265                 regmap_read(ddr_data->msch_regs, 0x2000 + 0x164,
 266                             &ddr_bw_ch0->video);
 267                 ddr_bw_ch0->video += (tmp32 << 16);
 268                 regmap_read(ddr_data->msch_regs, 0x2400 + 0x178, &tmp32);
 269                 regmap_read(ddr_data->msch_regs, 0x2400 + 0x164,
 270                             &ddr_bw_ch0->vio0);
 271                 ddr_bw_ch0->vio0 += (tmp32 << 16);
 272                 regmap_read(ddr_data->msch_regs, 0x2800 + 0x178, &tmp32);
 273                 regmap_read(ddr_data->msch_regs, 0x2800 + 0x164,
 274                             &ddr_bw_ch0->vio1);
 275                 ddr_bw_ch0->vio1 += (tmp32 << 16);
 276                 ddr_bw_ch0->vio2 = 0;
 277
 278                 /* B/s => MB/s */
 279                 ddr_bw_ch0->cpum =
 280                     (u64) ddr_bw_ch0->cpum * dfi_freq /
 281                     ddr_bw_val[0][ddrbw_time_num];
 282                 ddr_bw_ch0->gpu =
 283                     (u64) ddr_bw_ch0->gpu * dfi_freq /
 284                     ddr_bw_val[0][ddrbw_time_num];
 285                 ddr_bw_ch0->peri =
 286                     (u64) ddr_bw_ch0->peri * dfi_freq /
 287                     ddr_bw_val[0][ddrbw_time_num];
 288                 ddr_bw_ch0->video =
 289                     (u64) ddr_bw_ch0->video * dfi_freq /
 290                     ddr_bw_val[0][ddrbw_time_num];
 291                 ddr_bw_ch0->vio0 =
 292                     (u64) ddr_bw_ch0->vio0 * dfi_freq /
 293                     ddr_bw_val[0][ddrbw_time_num];
 294                 ddr_bw_ch0->vio1 =
 295                     (u64) ddr_bw_ch0->vio1 * dfi_freq /
 296                     ddr_bw_val[0][ddrbw_time_num];
 297                 ddr_bw_ch0->vio2 =
 298                     (u64) ddr_bw_ch0->vio2 * dfi_freq /
 299                     ddr_bw_val[0][ddrbw_time_num];
 300         }
 301 end:
 302         ddr_monitor_start();
 303 }
 304
 305 static void ddr_init(u32 dram_speed_bin, u32 freq, u32 addr_mcu_el3)
 306 {
 307         int lcdc_type;
 308         static u32 addr = 0;
 309
 310         struct rk_lcdc_driver *lcdc_dev = NULL;
 311
 312         if (addr == 0)
 313                 addr = addr_mcu_el3;
 314
 315         lcdc_dev = rk_get_lcdc_drv("lcdc0");
 316         if (lcdc_dev == NULL)
 317                 lcdc_type = 0;
 318         else
 319                 lcdc_type = (u32)lcdc_dev->cur_screen->type;
 320         printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
 321                __func__, dram_speed_bin, freq, lcdc_type);
 322         if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type, addr))
 323                 pr_info("ddr init error\n");
 324         else
 325                 printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
 326 }
 327
 328 static int ddr_init_resume(struct platform_device *pdev)
 329 {
 330         ddr_init(DDR3_DEFAULT, 0, 0);
 331         return 0;
 332 }
 333 #define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
 334 #define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
 335 /* valid ver */
 336 #define RKTF_VLDVER_MAJOR (1)
 337 #define RKTF_VLDVER_MINOR (5)
 338
 339 static int __init rockchip_tf_ver_check(void)
 340 {
 341         u32 version;
 342
 343         version = rockchip_psci_smc_get_tf_ver();
 344         if (((RKTF_VER_MAJOR(version) == RKTF_VLDVER_MAJOR) &&
 345              (RKTF_VER_MINOR(version) >= RKTF_VLDVER_MINOR)) ||
 346             (RKTF_VER_MAJOR(version) > RKTF_VLDVER_MAJOR))
 347                 return 0;
 348
 349         pr_err("read tf version 0x%x!\n", version);
 350
 351         do {
 352                 mdelay(1000);
 353                 pr_err("trusted firmware need to update to(%d.%d) or is invaild!\n",
 354                        RKTF_VLDVER_MAJOR, RKTF_VLDVER_MINOR);
 355         } while (1);
 356
 357         return 0;
 358 }
 359
 360
 361 static int __init rockchip_ddr_probe(struct platform_device *pdev)
 362 {
 363         u32 addr_mcu_el3;
 364         struct device_node *np;
 365
 366         pr_info("Rockchip DDR Initialize, verision: "DDR_VERSION"\n");
 367         np = pdev->dev.of_node;
 368         ddr_data =
 369             devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
 370         if (!ddr_data) {
 371                 dev_err(&pdev->dev, "no memory for state\n");
 372                 return -ENOMEM;
 373         }
 374         /* ddrpctl */
 375         ddr_data->ddrpctl_regs =
 376             syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
 377         if (IS_ERR(ddr_data->ddrpctl_regs)) {
 378                 dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
 379                         __func__);
 380                 return -ENXIO;
 381         }
 382
 383         /* grf */
 384         ddr_data->grf_regs =
 385             syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 386         if (IS_ERR(ddr_data->grf_regs)) {
 387                 dev_err(&pdev->dev, "%s: could not find grf dt node\n",
 388                         __func__);
 389                 return -ENXIO;
 390         }
 391         /* msch */
 392         ddr_data->msch_regs =
 393             syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
 394         if (IS_ERR(ddr_data->msch_regs)) {
 395                 dev_err(&pdev->dev, "%s: could not find msch dt node\n",
 396                         __func__);
 397                 return -ENXIO;
 398         }
 399
 400         platform_set_drvdata(pdev, ddr_data);
 401         ddr_change_freq = _ddr_change_freq;
 402         ddr_round_rate = _ddr_round_rate;
 403         ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 404         ddr_bandwidth_get = _ddr_bandwidth_get;
 405         ddr_recalc_rate = _ddr_recalc_rate;
 406         rockchip_tf_ver_check();
 407         if (!of_do_get_timings(np, (struct ddr_timing *)&ddr_data->dram_timing)) {
 408                 if (scpi_ddr_send_timing((u32 *)&ddr_data->dram_timing,
 409                                          sizeof(struct ddr_timing)))
 410                         pr_info("send ddr timing timeout\n");
 411         } else {
 412                 pr_err("get ddr timing from dts error\n");
 413                 ddr_data->dram_timing.dram_spd_bin = DDR3_DEFAULT;
 414         }
 415         addr_mcu_el3 = rockchip_psci_smc_write(PSCI_SIP_EL3FIQ_CFG,
 416                                                FIQ_NUM_FOR_DCF,
 417                                                FIQ_CPU_TGT_BOOT, 0);
 418         if ((addr_mcu_el3 == 0) || (addr_mcu_el3 > 0x80000))
 419                 pr_info("Trust version error, pls check trust version\n");
 420         ddr_init(ddr_data->dram_timing.dram_spd_bin, 0, addr_mcu_el3);
 421         pr_info("%s: success\n", __func__);
 422         return 0;
 423 }
 424
 425 static const struct of_device_id rockchip_ddr_of_match[] __refdata = {
 426         {.compatible = "rockchip,rk3368-ddr", .data = NULL,},
 427         {},
 428 };
 429
 430 static struct platform_driver rockchip_ddr_driver = {
 431 #ifdef CONFIG_PM
 432         .resume = ddr_init_resume,
 433 #endif /* CONFIG_PM */
 434         .driver = {
 435                    .name = "rockchip_ddr",
 436                    .of_match_table = rockchip_ddr_of_match,
 437         },
 438 };
 439
 440 static int __init rockchip_ddr_init(void)
 441 {
 442         return platform_driver_probe(&rockchip_ddr_driver, rockchip_ddr_probe);
 443 }
 444
 445 device_initcall(rockchip_ddr_init);