drivers/clocksource/rockchip_timer.c

   1 /*
   2  * Rockchip timer support
   3  *
   4  * Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/clk.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17
  18 #define TIMER_NAME "rk_timer"
  19
  20 #define TIMER_LOAD_COUNT0       0x00
  21 #define TIMER_LOAD_COUNT1       0x04
  22 #define TIMER_CONTROL_REG       0x10
  23 #define TIMER_INT_STATUS        0x18
  24
  25 #define TIMER_DISABLE           0x0
  26 #define TIMER_ENABLE            0x1
  27 #define TIMER_MODE_FREE_RUNNING                 (0 << 1)
  28 #define TIMER_MODE_USER_DEFINED_COUNT           (1 << 1)
  29 #define TIMER_INT_UNMASK                        (1 << 2)
  30
  31 struct bc_timer {
  32         struct clock_event_device ce;
  33         void __iomem *base;
  34         u32 freq;
  35 };
  36
  37 static struct bc_timer bc_timer;
  38
  39 static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
  40 {
  41         return container_of(ce, struct bc_timer, ce);
  42 }
  43
  44 static inline void __iomem *rk_base(struct clock_event_device *ce)
  45 {
  46         return rk_timer(ce)->base;
  47 }
  48
  49 static inline void rk_timer_disable(struct clock_event_device *ce)
  50 {
  51         writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG);
  52 }
  53
  54 static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
  55 {
  56         writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
  57                        rk_base(ce) + TIMER_CONTROL_REG);
  58 }
  59
  60 static void rk_timer_update_counter(unsigned long cycles,
  61                                     struct clock_event_device *ce)
  62 {
  63         writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
  64         writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
  65 }
  66
  67 static void rk_timer_interrupt_clear(struct clock_event_device *ce)
  68 {
  69         writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
  70 }
  71
  72 static inline int rk_timer_set_next_event(unsigned long cycles,
  73                                           struct clock_event_device *ce)
  74 {
  75         rk_timer_disable(ce);
  76         rk_timer_update_counter(cycles, ce);
  77         rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
  78         return 0;
  79 }
  80
  81 static int rk_timer_shutdown(struct clock_event_device *ce)
  82 {
  83         rk_timer_disable(ce);
  84         return 0;
  85 }
  86
  87 static int rk_timer_set_periodic(struct clock_event_device *ce)
  88 {
  89         rk_timer_disable(ce);
  90         rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
  91         rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
  92         return 0;
  93 }
  94
  95 static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
  96 {
  97         struct clock_event_device *ce = dev_id;
  98
  99         rk_timer_interrupt_clear(ce);
 100
 101         if (clockevent_state_oneshot(ce))
 102                 rk_timer_disable(ce);
 103
 104         ce->event_handler(ce);
 105
 106         return IRQ_HANDLED;
 107 }
 108
 109 static void __init rk_timer_init(struct device_node *np)
 110 {
 111         struct clock_event_device *ce = &bc_timer.ce;
 112         struct clk *timer_clk;
 113         struct clk *pclk;
 114         int ret, irq;
 115
 116         bc_timer.base = of_iomap(np, 0);
 117         if (!bc_timer.base) {
 118                 pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
 119                 return;
 120         }
 121
 122         pclk = of_clk_get_by_name(np, "pclk");
 123         if (IS_ERR(pclk)) {
 124                 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
 125                 return;
 126         }
 127
 128         if (clk_prepare_enable(pclk)) {
 129                 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
 130                 return;
 131         }
 132
 133         timer_clk = of_clk_get_by_name(np, "timer");
 134         if (IS_ERR(timer_clk)) {
 135                 pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
 136                 return;
 137         }
 138
 139         if (clk_prepare_enable(timer_clk)) {
 140                 pr_err("Failed to enable timer clock\n");
 141                 return;
 142         }
 143
 144         bc_timer.freq = clk_get_rate(timer_clk);
 145
 146         irq = irq_of_parse_and_map(np, 0);
 147         if (!irq) {
 148                 pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
 149                 return;
 150         }
 151
 152         ce->name = TIMER_NAME;
 153         ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 154         ce->set_next_event = rk_timer_set_next_event;
 155         ce->set_state_shutdown = rk_timer_shutdown;
 156         ce->set_state_periodic = rk_timer_set_periodic;
 157         ce->irq = irq;
 158         ce->cpumask = cpumask_of(0);
 159         ce->rating = 250;
 160
 161         rk_timer_interrupt_clear(ce);
 162         rk_timer_disable(ce);
 163
 164         ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
 165         if (ret) {
 166                 pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
 167                 return;
 168         }
 169
 170         clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
 171 }
 172
 173 CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init);