drivers/clk/tegra/clk-tegra30.c

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/delay.h>
  19 #include <linux/clk.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/clkdev.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/clk/tegra.h>
  25
  26 #include <mach/powergate.h>
  27
  28 #include "clk.h"
  29
  30 #define RST_DEVICES_L 0x004
  31 #define RST_DEVICES_H 0x008
  32 #define RST_DEVICES_U 0x00c
  33 #define RST_DEVICES_V 0x358
  34 #define RST_DEVICES_W 0x35c
  35 #define RST_DEVICES_SET_L 0x300
  36 #define RST_DEVICES_CLR_L 0x304
  37 #define RST_DEVICES_SET_H 0x308
  38 #define RST_DEVICES_CLR_H 0x30c
  39 #define RST_DEVICES_SET_U 0x310
  40 #define RST_DEVICES_CLR_U 0x314
  41 #define RST_DEVICES_SET_V 0x430
  42 #define RST_DEVICES_CLR_V 0x434
  43 #define RST_DEVICES_SET_W 0x438
  44 #define RST_DEVICES_CLR_W 0x43c
  45 #define RST_DEVICES_NUM 5
  46
  47 #define CLK_OUT_ENB_L 0x010
  48 #define CLK_OUT_ENB_H 0x014
  49 #define CLK_OUT_ENB_U 0x018
  50 #define CLK_OUT_ENB_V 0x360
  51 #define CLK_OUT_ENB_W 0x364
  52 #define CLK_OUT_ENB_SET_L 0x320
  53 #define CLK_OUT_ENB_CLR_L 0x324
  54 #define CLK_OUT_ENB_SET_H 0x328
  55 #define CLK_OUT_ENB_CLR_H 0x32c
  56 #define CLK_OUT_ENB_SET_U 0x330
  57 #define CLK_OUT_ENB_CLR_U 0x334
  58 #define CLK_OUT_ENB_SET_V 0x440
  59 #define CLK_OUT_ENB_CLR_V 0x444
  60 #define CLK_OUT_ENB_SET_W 0x448
  61 #define CLK_OUT_ENB_CLR_W 0x44c
  62 #define CLK_OUT_ENB_NUM 5
  63
  64 #define OSC_CTRL                        0x50
  65 #define OSC_CTRL_OSC_FREQ_MASK          (0xF<<28)
  66 #define OSC_CTRL_OSC_FREQ_13MHZ         (0X0<<28)
  67 #define OSC_CTRL_OSC_FREQ_19_2MHZ       (0X4<<28)
  68 #define OSC_CTRL_OSC_FREQ_12MHZ         (0X8<<28)
  69 #define OSC_CTRL_OSC_FREQ_26MHZ         (0XC<<28)
  70 #define OSC_CTRL_OSC_FREQ_16_8MHZ       (0X1<<28)
  71 #define OSC_CTRL_OSC_FREQ_38_4MHZ       (0X5<<28)
  72 #define OSC_CTRL_OSC_FREQ_48MHZ         (0X9<<28)
  73 #define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
  74
  75 #define OSC_CTRL_PLL_REF_DIV_MASK       (3<<26)
  76 #define OSC_CTRL_PLL_REF_DIV_1          (0<<26)
  77 #define OSC_CTRL_PLL_REF_DIV_2          (1<<26)
  78 #define OSC_CTRL_PLL_REF_DIV_4          (2<<26)
  79
  80 #define OSC_FREQ_DET                    0x58
  81 #define OSC_FREQ_DET_TRIG               BIT(31)
  82
  83 #define OSC_FREQ_DET_STATUS             0x5c
  84 #define OSC_FREQ_DET_BUSY               BIT(31)
  85 #define OSC_FREQ_DET_CNT_MASK           0xffff
  86
  87 #define CCLKG_BURST_POLICY 0x368
  88 #define SUPER_CCLKG_DIVIDER 0x36c
  89 #define CCLKLP_BURST_POLICY 0x370
  90 #define SUPER_CCLKLP_DIVIDER 0x374
  91 #define SCLK_BURST_POLICY 0x028
  92 #define SUPER_SCLK_DIVIDER 0x02c
  93
  94 #define SYSTEM_CLK_RATE 0x030
  95
  96 #define PLLC_BASE 0x80
  97 #define PLLC_MISC 0x8c
  98 #define PLLM_BASE 0x90
  99 #define PLLM_MISC 0x9c
 100 #define PLLP_BASE 0xa0
 101 #define PLLP_MISC 0xac
 102 #define PLLX_BASE 0xe0
 103 #define PLLX_MISC 0xe4
 104 #define PLLD_BASE 0xd0
 105 #define PLLD_MISC 0xdc
 106 #define PLLD2_BASE 0x4b8
 107 #define PLLD2_MISC 0x4bc
 108 #define PLLE_BASE 0xe8
 109 #define PLLE_MISC 0xec
 110 #define PLLA_BASE 0xb0
 111 #define PLLA_MISC 0xbc
 112 #define PLLU_BASE 0xc0
 113 #define PLLU_MISC 0xcc
 114
 115 #define PLL_MISC_LOCK_ENABLE 18
 116 #define PLLDU_MISC_LOCK_ENABLE 22
 117 #define PLLE_MISC_LOCK_ENABLE 9
 118
 119 #define PLL_BASE_LOCK 27
 120 #define PLLE_MISC_LOCK 11
 121
 122 #define PLLE_AUX 0x48c
 123 #define PLLC_OUT 0x84
 124 #define PLLM_OUT 0x94
 125 #define PLLP_OUTA 0xa4
 126 #define PLLP_OUTB 0xa8
 127 #define PLLA_OUT 0xb4
 128
 129 #define AUDIO_SYNC_CLK_I2S0 0x4a0
 130 #define AUDIO_SYNC_CLK_I2S1 0x4a4
 131 #define AUDIO_SYNC_CLK_I2S2 0x4a8
 132 #define AUDIO_SYNC_CLK_I2S3 0x4ac
 133 #define AUDIO_SYNC_CLK_I2S4 0x4b0
 134 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
 135
 136 #define PMC_CLK_OUT_CNTRL 0x1a8
 137
 138 #define CLK_SOURCE_I2S0 0x1d8
 139 #define CLK_SOURCE_I2S1 0x100
 140 #define CLK_SOURCE_I2S2 0x104
 141 #define CLK_SOURCE_I2S3 0x3bc
 142 #define CLK_SOURCE_I2S4 0x3c0
 143 #define CLK_SOURCE_SPDIF_OUT 0x108
 144 #define CLK_SOURCE_SPDIF_IN 0x10c
 145 #define CLK_SOURCE_PWM 0x110
 146 #define CLK_SOURCE_D_AUDIO 0x3d0
 147 #define CLK_SOURCE_DAM0 0x3d8
 148 #define CLK_SOURCE_DAM1 0x3dc
 149 #define CLK_SOURCE_DAM2 0x3e0
 150 #define CLK_SOURCE_HDA 0x428
 151 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
 152 #define CLK_SOURCE_SBC1 0x134
 153 #define CLK_SOURCE_SBC2 0x118
 154 #define CLK_SOURCE_SBC3 0x11c
 155 #define CLK_SOURCE_SBC4 0x1b4
 156 #define CLK_SOURCE_SBC5 0x3c8
 157 #define CLK_SOURCE_SBC6 0x3cc
 158 #define CLK_SOURCE_SATA_OOB 0x420
 159 #define CLK_SOURCE_SATA 0x424
 160 #define CLK_SOURCE_NDFLASH 0x160
 161 #define CLK_SOURCE_NDSPEED 0x3f8
 162 #define CLK_SOURCE_VFIR 0x168
 163 #define CLK_SOURCE_SDMMC1 0x150
 164 #define CLK_SOURCE_SDMMC2 0x154
 165 #define CLK_SOURCE_SDMMC3 0x1bc
 166 #define CLK_SOURCE_SDMMC4 0x164
 167 #define CLK_SOURCE_VDE 0x1c8
 168 #define CLK_SOURCE_CSITE 0x1d4
 169 #define CLK_SOURCE_LA 0x1f8
 170 #define CLK_SOURCE_OWR 0x1cc
 171 #define CLK_SOURCE_NOR 0x1d0
 172 #define CLK_SOURCE_MIPI 0x174
 173 #define CLK_SOURCE_I2C1 0x124
 174 #define CLK_SOURCE_I2C2 0x198
 175 #define CLK_SOURCE_I2C3 0x1b8
 176 #define CLK_SOURCE_I2C4 0x3c4
 177 #define CLK_SOURCE_I2C5 0x128
 178 #define CLK_SOURCE_UARTA 0x178
 179 #define CLK_SOURCE_UARTB 0x17c
 180 #define CLK_SOURCE_UARTC 0x1a0
 181 #define CLK_SOURCE_UARTD 0x1c0
 182 #define CLK_SOURCE_UARTE 0x1c4
 183 #define CLK_SOURCE_VI 0x148
 184 #define CLK_SOURCE_VI_SENSOR 0x1a8
 185 #define CLK_SOURCE_3D 0x158
 186 #define CLK_SOURCE_3D2 0x3b0
 187 #define CLK_SOURCE_2D 0x15c
 188 #define CLK_SOURCE_EPP 0x16c
 189 #define CLK_SOURCE_MPE 0x170
 190 #define CLK_SOURCE_HOST1X 0x180
 191 #define CLK_SOURCE_CVE 0x140
 192 #define CLK_SOURCE_TVO 0x188
 193 #define CLK_SOURCE_DTV 0x1dc
 194 #define CLK_SOURCE_HDMI 0x18c
 195 #define CLK_SOURCE_TVDAC 0x194
 196 #define CLK_SOURCE_DISP1 0x138
 197 #define CLK_SOURCE_DISP2 0x13c
 198 #define CLK_SOURCE_DSIB 0xd0
 199 #define CLK_SOURCE_TSENSOR 0x3b8
 200 #define CLK_SOURCE_ACTMON 0x3e8
 201 #define CLK_SOURCE_EXTERN1 0x3ec
 202 #define CLK_SOURCE_EXTERN2 0x3f0
 203 #define CLK_SOURCE_EXTERN3 0x3f4
 204 #define CLK_SOURCE_I2CSLOW 0x3fc
 205 #define CLK_SOURCE_SE 0x42c
 206 #define CLK_SOURCE_MSELECT 0x3b4
 207 #define CLK_SOURCE_EMC 0x19c
 208
 209 #define AUDIO_SYNC_DOUBLER 0x49c
 210
 211 #define PMC_CTRL 0
 212 #define PMC_CTRL_BLINK_ENB 7
 213
 214 #define PMC_DPD_PADS_ORIDE 0x1c
 215 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
 216 #define PMC_BLINK_TIMER 0x40
 217
 218 #define UTMIP_PLL_CFG2 0x488
 219 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 220 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 221 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 222 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 223 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 224
 225 #define UTMIP_PLL_CFG1 0x484
 226 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
 227 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 228 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 229 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 230 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 231
 232 /* Tegra CPU clock and reset control regs */
 233 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
 234 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
 235 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
 236 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
 237 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
 238
 239 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
 240 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
 241
 242 #define CLK_RESET_CCLK_BURST    0x20
 243 #define CLK_RESET_CCLK_DIVIDER  0x24
 244 #define CLK_RESET_PLLX_BASE     0xe0
 245 #define CLK_RESET_PLLX_MISC     0xe4
 246
 247 #define CLK_RESET_SOURCE_CSITE  0x1d4
 248
 249 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT       28
 250 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT         4
 251 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT        0
 252 #define CLK_RESET_CCLK_IDLE_POLICY              1
 253 #define CLK_RESET_CCLK_RUN_POLICY               2
 254 #define CLK_RESET_CCLK_BURST_POLICY_PLLX        8
 255
 256 #ifdef CONFIG_PM_SLEEP
 257 static struct cpu_clk_suspend_context {
 258         u32 pllx_misc;
 259         u32 pllx_base;
 260
 261         u32 cpu_burst;
 262         u32 clk_csite_src;
 263         u32 cclk_divider;
 264 } tegra30_cpu_clk_sctx;
 265 #endif
 266
 267 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 268
 269 static void __iomem *clk_base;
 270 static void __iomem *pmc_base;
 271 static unsigned long input_freq;
 272
 273 static DEFINE_SPINLOCK(clk_doubler_lock);
 274 static DEFINE_SPINLOCK(clk_out_lock);
 275 static DEFINE_SPINLOCK(pll_div_lock);
 276 static DEFINE_SPINLOCK(cml_lock);
 277 static DEFINE_SPINLOCK(pll_d_lock);
 278 static DEFINE_SPINLOCK(sysrate_lock);
 279
 280 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
 281                             _clk_num, _regs, _gate_flags, _clk_id)      \
 282         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 283                         30, 2, 0, 0, 8, 1, 0, _regs, _clk_num,          \
 284                         periph_clk_enb_refcnt, _gate_flags, _clk_id)
 285
 286 #define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
 287                             _clk_num, _regs, _gate_flags, _clk_id)      \
 288         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 289                         30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,     \
 290                         _regs, _clk_num, periph_clk_enb_refcnt,         \
 291                         _gate_flags, _clk_id)
 292
 293 #define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
 294                              _clk_num, _regs, _gate_flags, _clk_id)     \
 295         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 296                         29, 3, 0, 0, 8, 1, 0, _regs, _clk_num,          \
 297                         periph_clk_enb_refcnt, _gate_flags, _clk_id)
 298
 299 #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
 300                             _clk_num, _regs, _gate_flags, _clk_id)      \
 301         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 302                         30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,    \
 303                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 304                         _clk_id)
 305
 306 #define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
 307                              _clk_num, _regs, _clk_id)                  \
 308         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 309                         30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,  \
 310                         _clk_num, periph_clk_enb_refcnt, 0, _clk_id)
 311
 312 #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
 313                               _mux_shift, _mux_width, _clk_num, _regs,  \
 314                               _gate_flags, _clk_id)                     \
 315         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 316                         _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs,   \
 317                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 318                         _clk_id)
 319
 320 /*
 321  * IDs assigned here must be in sync with DT bindings definition
 322  * for Tegra30 clocks.
 323  */
 324 enum tegra30_clk {
 325         cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
 326         sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
 327         disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
 328         kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
 329         i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
 330         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
 331         pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
 332         dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
 333         cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
 334         i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
 335         atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
 336         spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
 337         se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
 338         vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
 339         clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
 340         pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
 341         pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
 342         spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
 343         vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
 344         clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
 345         hclk, pclk, clk_out_1_mux = 300, clk_max
 346 };
 347
 348 static struct clk *clks[clk_max];
 349 static struct clk_onecell_data clk_data;
 350
 351 /*
 352  * Structure defining the fields for USB UTMI clocks Parameters.
 353  */
 354 struct utmi_clk_param {
 355         /* Oscillator Frequency in KHz */
 356         u32 osc_frequency;
 357         /* UTMIP PLL Enable Delay Count  */
 358         u8 enable_delay_count;
 359         /* UTMIP PLL Stable count */
 360         u8 stable_count;
 361         /*  UTMIP PLL Active delay count */
 362         u8 active_delay_count;
 363         /* UTMIP PLL Xtal frequency count */
 364         u8 xtal_freq_count;
 365 };
 366
 367 static const struct utmi_clk_param utmi_parameters[] = {
 368 /*      OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
 369         {13000000,     0x02,       0x33,       0x05,       0x7F},
 370         {19200000,     0x03,       0x4B,       0x06,       0xBB},
 371         {12000000,     0x02,       0x2F,       0x04,       0x76},
 372         {26000000,     0x04,       0x66,       0x09,       0xFE},
 373         {16800000,     0x03,       0x41,       0x0A,       0xA4},
 374 };
 375
 376 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
 377         { 12000000, 1040000000, 520,  6, 1, 8},
 378         { 13000000, 1040000000, 480,  6, 1, 8},
 379         { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
 380         { 19200000, 1040000000, 325,  6, 1, 6},
 381         { 26000000, 1040000000, 520, 13, 1, 8},
 382
 383         { 12000000, 832000000, 416,  6, 1, 8},
 384         { 13000000, 832000000, 832, 13, 1, 8},
 385         { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
 386         { 19200000, 832000000, 260,  6, 1, 8},
 387         { 26000000, 832000000, 416, 13, 1, 8},
 388
 389         { 12000000, 624000000, 624, 12, 1, 8},
 390         { 13000000, 624000000, 624, 13, 1, 8},
 391         { 16800000, 600000000, 520, 14, 1, 8},
 392         { 19200000, 624000000, 520, 16, 1, 8},
 393         { 26000000, 624000000, 624, 26, 1, 8},
 394
 395         { 12000000, 600000000, 600, 12, 1, 8},
 396         { 13000000, 600000000, 600, 13, 1, 8},
 397         { 16800000, 600000000, 500, 14, 1, 8},
 398         { 19200000, 600000000, 375, 12, 1, 6},
 399         { 26000000, 600000000, 600, 26, 1, 8},
 400
 401         { 12000000, 520000000, 520, 12, 1, 8},
 402         { 13000000, 520000000, 520, 13, 1, 8},
 403         { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
 404         { 19200000, 520000000, 325, 12, 1, 6},
 405         { 26000000, 520000000, 520, 26, 1, 8},
 406
 407         { 12000000, 416000000, 416, 12, 1, 8},
 408         { 13000000, 416000000, 416, 13, 1, 8},
 409         { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
 410         { 19200000, 416000000, 260, 12, 1, 6},
 411         { 26000000, 416000000, 416, 26, 1, 8},
 412         { 0, 0, 0, 0, 0, 0 },
 413 };
 414
 415 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
 416         { 12000000, 666000000, 666, 12, 1, 8},
 417         { 13000000, 666000000, 666, 13, 1, 8},
 418         { 16800000, 666000000, 555, 14, 1, 8},
 419         { 19200000, 666000000, 555, 16, 1, 8},
 420         { 26000000, 666000000, 666, 26, 1, 8},
 421         { 12000000, 600000000, 600, 12, 1, 8},
 422         { 13000000, 600000000, 600, 13, 1, 8},
 423         { 16800000, 600000000, 500, 14, 1, 8},
 424         { 19200000, 600000000, 375, 12, 1, 6},
 425         { 26000000, 600000000, 600, 26, 1, 8},
 426         { 0, 0, 0, 0, 0, 0 },
 427 };
 428
 429 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
 430         { 12000000, 216000000, 432, 12, 2, 8},
 431         { 13000000, 216000000, 432, 13, 2, 8},
 432         { 16800000, 216000000, 360, 14, 2, 8},
 433         { 19200000, 216000000, 360, 16, 2, 8},
 434         { 26000000, 216000000, 432, 26, 2, 8},
 435         { 0, 0, 0, 0, 0, 0 },
 436 };
 437
 438 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
 439         { 9600000, 564480000, 294, 5, 1, 4},
 440         { 9600000, 552960000, 288, 5, 1, 4},
 441         { 9600000, 24000000,  5,   2, 1, 1},
 442
 443         { 28800000, 56448000, 49, 25, 1, 1},
 444         { 28800000, 73728000, 64, 25, 1, 1},
 445         { 28800000, 24000000,  5,  6, 1, 1},
 446         { 0, 0, 0, 0, 0, 0 },
 447 };
 448
 449 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
 450         { 12000000, 216000000, 216, 12, 1, 4},
 451         { 13000000, 216000000, 216, 13, 1, 4},
 452         { 16800000, 216000000, 180, 14, 1, 4},
 453         { 19200000, 216000000, 180, 16, 1, 4},
 454         { 26000000, 216000000, 216, 26, 1, 4},
 455
 456         { 12000000, 594000000, 594, 12, 1, 8},
 457         { 13000000, 594000000, 594, 13, 1, 8},
 458         { 16800000, 594000000, 495, 14, 1, 8},
 459         { 19200000, 594000000, 495, 16, 1, 8},
 460         { 26000000, 594000000, 594, 26, 1, 8},
 461
 462         { 12000000, 1000000000, 1000, 12, 1, 12},
 463         { 13000000, 1000000000, 1000, 13, 1, 12},
 464         { 19200000, 1000000000, 625,  12, 1, 8},
 465         { 26000000, 1000000000, 1000, 26, 1, 12},
 466
 467         { 0, 0, 0, 0, 0, 0 },
 468 };
 469
 470 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
 471         { 12000000, 480000000, 960, 12, 2, 12},
 472         { 13000000, 480000000, 960, 13, 2, 12},
 473         { 16800000, 480000000, 400, 7,  2, 5},
 474         { 19200000, 480000000, 200, 4,  2, 3},
 475         { 26000000, 480000000, 960, 26, 2, 12},
 476         { 0, 0, 0, 0, 0, 0 },
 477 };
 478
 479 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 480         /* 1.7 GHz */
 481         { 12000000, 1700000000, 850,  6,  1, 8},
 482         { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
 483         { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
 484         { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
 485         { 26000000, 1700000000, 850,  13, 1, 8},
 486
 487         /* 1.6 GHz */
 488         { 12000000, 1600000000, 800,  6,  1, 8},
 489         { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
 490         { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
 491         { 19200000, 1600000000, 500,  6,  1, 8},
 492         { 26000000, 1600000000, 800,  13, 1, 8},
 493
 494         /* 1.5 GHz */
 495         { 12000000, 1500000000, 750,  6,  1, 8},
 496         { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
 497         { 16800000, 1500000000, 625,  7,  1, 8},
 498         { 19200000, 1500000000, 625,  8,  1, 8},
 499         { 26000000, 1500000000, 750,  13, 1, 8},
 500
 501         /* 1.4 GHz */
 502         { 12000000, 1400000000, 700,  6,  1, 8},
 503         { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
 504         { 16800000, 1400000000, 1000, 12, 1, 8},
 505         { 19200000, 1400000000, 875,  12, 1, 8},
 506         { 26000000, 1400000000, 700,  13, 1, 8},
 507
 508         /* 1.3 GHz */
 509         { 12000000, 1300000000, 975,  9,  1, 8},
 510         { 13000000, 1300000000, 1000, 10, 1, 8},
 511         { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
 512         { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
 513         { 26000000, 1300000000, 650,  13, 1, 8},
 514
 515         /* 1.2 GHz */
 516         { 12000000, 1200000000, 1000, 10, 1, 8},
 517         { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
 518         { 16800000, 1200000000, 1000, 14, 1, 8},
 519         { 19200000, 1200000000, 1000, 16, 1, 8},
 520         { 26000000, 1200000000, 600,  13, 1, 8},
 521
 522         /* 1.1 GHz */
 523         { 12000000, 1100000000, 825,  9,  1, 8},
 524         { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
 525         { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
 526         { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
 527         { 26000000, 1100000000, 550,  13, 1, 8},
 528
 529         /* 1 GHz */
 530         { 12000000, 1000000000, 1000, 12, 1, 8},
 531         { 13000000, 1000000000, 1000, 13, 1, 8},
 532         { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
 533         { 19200000, 1000000000, 625,  12, 1, 8},
 534         { 26000000, 1000000000, 1000, 26, 1, 8},
 535
 536         { 0, 0, 0, 0, 0, 0 },
 537 };
 538
 539 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 540         /* PLLE special case: use cpcon field to store cml divider value */
 541         { 12000000,  100000000, 150, 1,  18, 11},
 542         { 216000000, 100000000, 200, 18, 24, 13},
 543         { 0, 0, 0, 0, 0, 0 },
 544 };
 545
 546 /* PLL parameters */
 547 static struct tegra_clk_pll_params pll_c_params = {
 548         .input_min = 2000000,
 549         .input_max = 31000000,
 550         .cf_min = 1000000,
 551         .cf_max = 6000000,
 552         .vco_min = 20000000,
 553         .vco_max = 1400000000,
 554         .base_reg = PLLC_BASE,
 555         .misc_reg = PLLC_MISC,
 556         .lock_bit_idx = PLL_BASE_LOCK,
 557         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 558         .lock_delay = 300,
 559 };
 560
 561 static struct tegra_clk_pll_params pll_m_params = {
 562         .input_min = 2000000,
 563         .input_max = 31000000,
 564         .cf_min = 1000000,
 565         .cf_max = 6000000,
 566         .vco_min = 20000000,
 567         .vco_max = 1200000000,
 568         .base_reg = PLLM_BASE,
 569         .misc_reg = PLLM_MISC,
 570         .lock_bit_idx = PLL_BASE_LOCK,
 571         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 572         .lock_delay = 300,
 573 };
 574
 575 static struct tegra_clk_pll_params pll_p_params = {
 576         .input_min = 2000000,
 577         .input_max = 31000000,
 578         .cf_min = 1000000,
 579         .cf_max = 6000000,
 580         .vco_min = 20000000,
 581         .vco_max = 1400000000,
 582         .base_reg = PLLP_BASE,
 583         .misc_reg = PLLP_MISC,
 584         .lock_bit_idx = PLL_BASE_LOCK,
 585         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 586         .lock_delay = 300,
 587 };
 588
 589 static struct tegra_clk_pll_params pll_a_params = {
 590         .input_min = 2000000,
 591         .input_max = 31000000,
 592         .cf_min = 1000000,
 593         .cf_max = 6000000,
 594         .vco_min = 20000000,
 595         .vco_max = 1400000000,
 596         .base_reg = PLLA_BASE,
 597         .misc_reg = PLLA_MISC,
 598         .lock_bit_idx = PLL_BASE_LOCK,
 599         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 600         .lock_delay = 300,
 601 };
 602
 603 static struct tegra_clk_pll_params pll_d_params = {
 604         .input_min = 2000000,
 605         .input_max = 40000000,
 606         .cf_min = 1000000,
 607         .cf_max = 6000000,
 608         .vco_min = 40000000,
 609         .vco_max = 1000000000,
 610         .base_reg = PLLD_BASE,
 611         .misc_reg = PLLD_MISC,
 612         .lock_bit_idx = PLL_BASE_LOCK,
 613         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 614         .lock_delay = 1000,
 615 };
 616
 617 static struct tegra_clk_pll_params pll_d2_params = {
 618         .input_min = 2000000,
 619         .input_max = 40000000,
 620         .cf_min = 1000000,
 621         .cf_max = 6000000,
 622         .vco_min = 40000000,
 623         .vco_max = 1000000000,
 624         .base_reg = PLLD2_BASE,
 625         .misc_reg = PLLD2_MISC,
 626         .lock_bit_idx = PLL_BASE_LOCK,
 627         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 628         .lock_delay = 1000,
 629 };
 630
 631 static struct tegra_clk_pll_params pll_u_params = {
 632         .input_min = 2000000,
 633         .input_max = 40000000,
 634         .cf_min = 1000000,
 635         .cf_max = 6000000,
 636         .vco_min = 48000000,
 637         .vco_max = 960000000,
 638         .base_reg = PLLU_BASE,
 639         .misc_reg = PLLU_MISC,
 640         .lock_bit_idx = PLL_BASE_LOCK,
 641         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 642         .lock_delay = 1000,
 643 };
 644
 645 static struct tegra_clk_pll_params pll_x_params = {
 646         .input_min = 2000000,
 647         .input_max = 31000000,
 648         .cf_min = 1000000,
 649         .cf_max = 6000000,
 650         .vco_min = 20000000,
 651         .vco_max = 1700000000,
 652         .base_reg = PLLX_BASE,
 653         .misc_reg = PLLX_MISC,
 654         .lock_bit_idx = PLL_BASE_LOCK,
 655         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 656         .lock_delay = 300,
 657 };
 658
 659 static struct tegra_clk_pll_params pll_e_params = {
 660         .input_min = 12000000,
 661         .input_max = 216000000,
 662         .cf_min = 12000000,
 663         .cf_max = 12000000,
 664         .vco_min = 1200000000,
 665         .vco_max = 2400000000U,
 666         .base_reg = PLLE_BASE,
 667         .misc_reg = PLLE_MISC,
 668         .lock_bit_idx = PLLE_MISC_LOCK,
 669         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 670         .lock_delay = 300,
 671 };
 672
 673 /* Peripheral clock registers */
 674 static struct tegra_clk_periph_regs periph_l_regs = {
 675         .enb_reg = CLK_OUT_ENB_L,
 676         .enb_set_reg = CLK_OUT_ENB_SET_L,
 677         .enb_clr_reg = CLK_OUT_ENB_CLR_L,
 678         .rst_reg = RST_DEVICES_L,
 679         .rst_set_reg = RST_DEVICES_SET_L,
 680         .rst_clr_reg = RST_DEVICES_CLR_L,
 681 };
 682
 683 static struct tegra_clk_periph_regs periph_h_regs = {
 684         .enb_reg = CLK_OUT_ENB_H,
 685         .enb_set_reg = CLK_OUT_ENB_SET_H,
 686         .enb_clr_reg = CLK_OUT_ENB_CLR_H,
 687         .rst_reg = RST_DEVICES_H,
 688         .rst_set_reg = RST_DEVICES_SET_H,
 689         .rst_clr_reg = RST_DEVICES_CLR_H,
 690 };
 691
 692 static struct tegra_clk_periph_regs periph_u_regs = {
 693         .enb_reg = CLK_OUT_ENB_U,
 694         .enb_set_reg = CLK_OUT_ENB_SET_U,
 695         .enb_clr_reg = CLK_OUT_ENB_CLR_U,
 696         .rst_reg = RST_DEVICES_U,
 697         .rst_set_reg = RST_DEVICES_SET_U,
 698         .rst_clr_reg = RST_DEVICES_CLR_U,
 699 };
 700
 701 static struct tegra_clk_periph_regs periph_v_regs = {
 702         .enb_reg = CLK_OUT_ENB_V,
 703         .enb_set_reg = CLK_OUT_ENB_SET_V,
 704         .enb_clr_reg = CLK_OUT_ENB_CLR_V,
 705         .rst_reg = RST_DEVICES_V,
 706         .rst_set_reg = RST_DEVICES_SET_V,
 707         .rst_clr_reg = RST_DEVICES_CLR_V,
 708 };
 709
 710 static struct tegra_clk_periph_regs periph_w_regs = {
 711         .enb_reg = CLK_OUT_ENB_W,
 712         .enb_set_reg = CLK_OUT_ENB_SET_W,
 713         .enb_clr_reg = CLK_OUT_ENB_CLR_W,
 714         .rst_reg = RST_DEVICES_W,
 715         .rst_set_reg = RST_DEVICES_SET_W,
 716         .rst_clr_reg = RST_DEVICES_CLR_W,
 717 };
 718
 719 static void tegra30_clk_measure_input_freq(void)
 720 {
 721         u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
 722         u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
 723         u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
 724
 725         switch (auto_clk_control) {
 726         case OSC_CTRL_OSC_FREQ_12MHZ:
 727                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 728                 input_freq = 12000000;
 729                 break;
 730         case OSC_CTRL_OSC_FREQ_13MHZ:
 731                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 732                 input_freq = 13000000;
 733                 break;
 734         case OSC_CTRL_OSC_FREQ_19_2MHZ:
 735                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 736                 input_freq = 19200000;
 737                 break;
 738         case OSC_CTRL_OSC_FREQ_26MHZ:
 739                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 740                 input_freq = 26000000;
 741                 break;
 742         case OSC_CTRL_OSC_FREQ_16_8MHZ:
 743                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 744                 input_freq = 16800000;
 745                 break;
 746         case OSC_CTRL_OSC_FREQ_38_4MHZ:
 747                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
 748                 input_freq = 38400000;
 749                 break;
 750         case OSC_CTRL_OSC_FREQ_48MHZ:
 751                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
 752                 input_freq = 48000000;
 753                 break;
 754         default:
 755                 pr_err("Unexpected auto clock control value %d",
 756                         auto_clk_control);
 757                 BUG();
 758                 return;
 759         }
 760 }
 761
 762 static unsigned int tegra30_get_pll_ref_div(void)
 763 {
 764         u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
 765                                         OSC_CTRL_PLL_REF_DIV_MASK;
 766
 767         switch (pll_ref_div) {
 768         case OSC_CTRL_PLL_REF_DIV_1:
 769                 return 1;
 770         case OSC_CTRL_PLL_REF_DIV_2:
 771                 return 2;
 772         case OSC_CTRL_PLL_REF_DIV_4:
 773                 return 4;
 774         default:
 775                 pr_err("Invalid pll ref divider %d", pll_ref_div);
 776                 BUG();
 777         }
 778         return 0;
 779 }
 780
 781 static void tegra30_utmi_param_configure(void)
 782 {
 783         u32 reg;
 784         int i;
 785
 786         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
 787                 if (input_freq == utmi_parameters[i].osc_frequency)
 788                         break;
 789         }
 790
 791         if (i >= ARRAY_SIZE(utmi_parameters)) {
 792                 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
 793                 return;
 794         }
 795
 796         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
 797
 798         /* Program UTMIP PLL stable and active counts */
 799         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
 800         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
 801                         utmi_parameters[i].stable_count);
 802
 803         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
 804
 805         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
 806                         utmi_parameters[i].active_delay_count);
 807
 808         /* Remove power downs from UTMIP PLL control bits */
 809         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
 810         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
 811         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
 812
 813         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
 814
 815         /* Program UTMIP PLL delay and oscillator frequency counts */
 816         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
 817         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
 818
 819         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
 820                 utmi_parameters[i].enable_delay_count);
 821
 822         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
 823         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
 824                 utmi_parameters[i].xtal_freq_count);
 825
 826         /* Remove power downs from UTMIP PLL control bits */
 827         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
 828         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
 829         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
 830
 831         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
 832 }
 833
 834 static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
 835
 836 static void __init tegra30_pll_init(void)
 837 {
 838         struct clk *clk;
 839
 840         /* PLLC */
 841         clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
 842                             0, &pll_c_params,
 843                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
 844                             pll_c_freq_table, NULL);
 845         clk_register_clkdev(clk, "pll_c", NULL);
 846         clks[pll_c] = clk;
 847
 848         /* PLLC_OUT1 */
 849         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
 850                                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 851                                 8, 8, 1, NULL);
 852         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
 853                                 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
 854                                 0, NULL);
 855         clk_register_clkdev(clk, "pll_c_out1", NULL);
 856         clks[pll_c_out1] = clk;
 857
 858         /* PLLP */
 859         clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
 860                             408000000, &pll_p_params,
 861                             TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
 862                             TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL);
 863         clk_register_clkdev(clk, "pll_p", NULL);
 864         clks[pll_p] = clk;
 865
 866         /* PLLP_OUT1 */
 867         clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
 868                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
 869                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
 870                                 &pll_div_lock);
 871         clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
 872                                 clk_base + PLLP_OUTA, 1, 0,
 873                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 874                                 &pll_div_lock);
 875         clk_register_clkdev(clk, "pll_p_out1", NULL);
 876         clks[pll_p_out1] = clk;
 877
 878         /* PLLP_OUT2 */
 879         clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
 880                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
 881                                 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
 882                                 &pll_div_lock);
 883         clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
 884                                 clk_base + PLLP_OUTA, 17, 16,
 885                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 886                                 &pll_div_lock);
 887         clk_register_clkdev(clk, "pll_p_out2", NULL);
 888         clks[pll_p_out2] = clk;
 889
 890         /* PLLP_OUT3 */
 891         clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
 892                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
 893                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
 894                                 &pll_div_lock);
 895         clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
 896                                 clk_base + PLLP_OUTB, 1, 0,
 897                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 898                                 &pll_div_lock);
 899         clk_register_clkdev(clk, "pll_p_out3", NULL);
 900         clks[pll_p_out3] = clk;
 901
 902         /* PLLP_OUT4 */
 903         clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
 904                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
 905                                 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
 906                                 &pll_div_lock);
 907         clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
 908                                 clk_base + PLLP_OUTB, 17, 16,
 909                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 910                                 &pll_div_lock);
 911         clk_register_clkdev(clk, "pll_p_out4", NULL);
 912         clks[pll_p_out4] = clk;
 913
 914         /* PLLM */
 915         clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
 916                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
 917                             &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
 918                             TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
 919                             pll_m_freq_table, NULL);
 920         clk_register_clkdev(clk, "pll_m", NULL);
 921         clks[pll_m] = clk;
 922
 923         /* PLLM_OUT1 */
 924         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
 925                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 926                                 8, 8, 1, NULL);
 927         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
 928                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
 929                                 CLK_SET_RATE_PARENT, 0, NULL);
 930         clk_register_clkdev(clk, "pll_m_out1", NULL);
 931         clks[pll_m_out1] = clk;
 932
 933         /* PLLX */
 934         clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
 935                             0, &pll_x_params, TEGRA_PLL_HAS_CPCON |
 936                             TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
 937                             pll_x_freq_table, NULL);
 938         clk_register_clkdev(clk, "pll_x", NULL);
 939         clks[pll_x] = clk;
 940
 941         /* PLLX_OUT0 */
 942         clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
 943                                         CLK_SET_RATE_PARENT, 1, 2);
 944         clk_register_clkdev(clk, "pll_x_out0", NULL);
 945         clks[pll_x_out0] = clk;
 946
 947         /* PLLU */
 948         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
 949                             0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
 950                             TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
 951                             pll_u_freq_table,
 952                             NULL);
 953         clk_register_clkdev(clk, "pll_u", NULL);
 954         clks[pll_u] = clk;
 955
 956         tegra30_utmi_param_configure();
 957
 958         /* PLLD */
 959         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
 960                             0, &pll_d_params, TEGRA_PLL_HAS_CPCON |
 961                             TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
 962                             pll_d_freq_table, &pll_d_lock);
 963         clk_register_clkdev(clk, "pll_d", NULL);
 964         clks[pll_d] = clk;
 965
 966         /* PLLD_OUT0 */
 967         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
 968                                         CLK_SET_RATE_PARENT, 1, 2);
 969         clk_register_clkdev(clk, "pll_d_out0", NULL);
 970         clks[pll_d_out0] = clk;
 971
 972         /* PLLD2 */
 973         clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
 974                             0, &pll_d2_params, TEGRA_PLL_HAS_CPCON |
 975                             TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
 976                             pll_d_freq_table, NULL);
 977         clk_register_clkdev(clk, "pll_d2", NULL);
 978         clks[pll_d2] = clk;
 979
 980         /* PLLD2_OUT0 */
 981         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
 982                                         CLK_SET_RATE_PARENT, 1, 2);
 983         clk_register_clkdev(clk, "pll_d2_out0", NULL);
 984         clks[pll_d2_out0] = clk;
 985
 986         /* PLLA */
 987         clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
 988                             0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
 989                             TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
 990         clk_register_clkdev(clk, "pll_a", NULL);
 991         clks[pll_a] = clk;
 992
 993         /* PLLA_OUT0 */
 994         clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
 995                                 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 996                                 8, 8, 1, NULL);
 997         clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
 998                                 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
 999                                 CLK_SET_RATE_PARENT, 0, NULL);
1000         clk_register_clkdev(clk, "pll_a_out0", NULL);
1001         clks[pll_a_out0] = clk;
1002
1003         /* PLLE */
1004         clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1005                                ARRAY_SIZE(pll_e_parents), 0,
1006                                clk_base + PLLE_AUX, 2, 1, 0, NULL);
1007         clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1008                              CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
1009                              TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL);
1010         clk_register_clkdev(clk, "pll_e", NULL);
1011         clks[pll_e] = clk;
1012 }
1013
1014 static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1015         "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
1016 static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1017                                           "clk_m_div4", "extern1", };
1018 static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1019                                           "clk_m_div4", "extern2", };
1020 static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1021                                           "clk_m_div4", "extern3", };
1022
1023 static void __init tegra30_audio_clk_init(void)
1024 {
1025         struct clk *clk;
1026
1027         /* spdif_in_sync */
1028         clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1029                                              24000000);
1030         clk_register_clkdev(clk, "spdif_in_sync", NULL);
1031         clks[spdif_in_sync] = clk;
1032
1033         /* i2s0_sync */
1034         clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1035         clk_register_clkdev(clk, "i2s0_sync", NULL);
1036         clks[i2s0_sync] = clk;
1037
1038         /* i2s1_sync */
1039         clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1040         clk_register_clkdev(clk, "i2s1_sync", NULL);
1041         clks[i2s1_sync] = clk;
1042
1043         /* i2s2_sync */
1044         clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1045         clk_register_clkdev(clk, "i2s2_sync", NULL);
1046         clks[i2s2_sync] = clk;
1047
1048         /* i2s3_sync */
1049         clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1050         clk_register_clkdev(clk, "i2s3_sync", NULL);
1051         clks[i2s3_sync] = clk;
1052
1053         /* i2s4_sync */
1054         clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1055         clk_register_clkdev(clk, "i2s4_sync", NULL);
1056         clks[i2s4_sync] = clk;
1057
1058         /* vimclk_sync */
1059         clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1060         clk_register_clkdev(clk, "vimclk_sync", NULL);
1061         clks[vimclk_sync] = clk;
1062
1063         /* audio0 */
1064         clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1065                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1066                                 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1067         clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1068                                 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1069                                 CLK_GATE_SET_TO_DISABLE, NULL);
1070         clk_register_clkdev(clk, "audio0", NULL);
1071         clks[audio0] = clk;
1072
1073         /* audio1 */
1074         clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1075                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1076                                 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1077         clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1078                                 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1079                                 CLK_GATE_SET_TO_DISABLE, NULL);
1080         clk_register_clkdev(clk, "audio1", NULL);
1081         clks[audio1] = clk;
1082
1083         /* audio2 */
1084         clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1085                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1086                                 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1087         clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1088                                 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1089                                 CLK_GATE_SET_TO_DISABLE, NULL);
1090         clk_register_clkdev(clk, "audio2", NULL);
1091         clks[audio2] = clk;
1092
1093         /* audio3 */
1094         clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1095                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1096                                 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1097         clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1098                                 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1099                                 CLK_GATE_SET_TO_DISABLE, NULL);
1100         clk_register_clkdev(clk, "audio3", NULL);
1101         clks[audio3] = clk;
1102
1103         /* audio4 */
1104         clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1105                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1106                                 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1107         clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1108                                 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1109                                 CLK_GATE_SET_TO_DISABLE, NULL);
1110         clk_register_clkdev(clk, "audio4", NULL);
1111         clks[audio4] = clk;
1112
1113         /* spdif */
1114         clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1115                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1116                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1117         clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1118                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1119                                 CLK_GATE_SET_TO_DISABLE, NULL);
1120         clk_register_clkdev(clk, "spdif", NULL);
1121         clks[spdif] = clk;
1122
1123         /* audio0_2x */
1124         clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1125                                         CLK_SET_RATE_PARENT, 2, 1);
1126         clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1127                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1128                                 &clk_doubler_lock);
1129         clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1130                                     TEGRA_PERIPH_NO_RESET, clk_base,
1131                                     CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1132                                     periph_clk_enb_refcnt);
1133         clk_register_clkdev(clk, "audio0_2x", NULL);
1134         clks[audio0_2x] = clk;
1135
1136         /* audio1_2x */
1137         clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1138                                         CLK_SET_RATE_PARENT, 2, 1);
1139         clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1140                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1141                                 &clk_doubler_lock);
1142         clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1143                                     TEGRA_PERIPH_NO_RESET, clk_base,
1144                                     CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1145                                     periph_clk_enb_refcnt);
1146         clk_register_clkdev(clk, "audio1_2x", NULL);
1147         clks[audio1_2x] = clk;
1148
1149         /* audio2_2x */
1150         clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1151                                         CLK_SET_RATE_PARENT, 2, 1);
1152         clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1153                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1154                                 &clk_doubler_lock);
1155         clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1156                                     TEGRA_PERIPH_NO_RESET, clk_base,
1157                                     CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1158                                     periph_clk_enb_refcnt);
1159         clk_register_clkdev(clk, "audio2_2x", NULL);
1160         clks[audio2_2x] = clk;
1161
1162         /* audio3_2x */
1163         clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1164                                         CLK_SET_RATE_PARENT, 2, 1);
1165         clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1166                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1167                                 &clk_doubler_lock);
1168         clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1169                                     TEGRA_PERIPH_NO_RESET, clk_base,
1170                                     CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1171                                     periph_clk_enb_refcnt);
1172         clk_register_clkdev(clk, "audio3_2x", NULL);
1173         clks[audio3_2x] = clk;
1174
1175         /* audio4_2x */
1176         clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1177                                         CLK_SET_RATE_PARENT, 2, 1);
1178         clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1179                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1180                                 &clk_doubler_lock);
1181         clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1182                                     TEGRA_PERIPH_NO_RESET, clk_base,
1183                                     CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1184                                     periph_clk_enb_refcnt);
1185         clk_register_clkdev(clk, "audio4_2x", NULL);
1186         clks[audio4_2x] = clk;
1187
1188         /* spdif_2x */
1189         clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1190                                         CLK_SET_RATE_PARENT, 2, 1);
1191         clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1192                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1193                                 &clk_doubler_lock);
1194         clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1195                                     TEGRA_PERIPH_NO_RESET, clk_base,
1196                                     CLK_SET_RATE_PARENT, 118, &periph_v_regs,
1197                                     periph_clk_enb_refcnt);
1198         clk_register_clkdev(clk, "spdif_2x", NULL);
1199         clks[spdif_2x] = clk;
1200 }
1201
1202 static void __init tegra30_pmc_clk_init(void)
1203 {
1204         struct clk *clk;
1205
1206         /* clk_out_1 */
1207         clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1208                                ARRAY_SIZE(clk_out1_parents), 0,
1209                                pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1210                                &clk_out_lock);
1211         clks[clk_out_1_mux] = clk;
1212         clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1213                                 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1214                                 &clk_out_lock);
1215         clk_register_clkdev(clk, "extern1", "clk_out_1");
1216         clks[clk_out_1] = clk;
1217
1218         /* clk_out_2 */
1219         clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1220                                ARRAY_SIZE(clk_out1_parents), 0,
1221                                pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1222                                &clk_out_lock);
1223         clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1224                                 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1225                                 &clk_out_lock);
1226         clk_register_clkdev(clk, "extern2", "clk_out_2");
1227         clks[clk_out_2] = clk;
1228
1229         /* clk_out_3 */
1230         clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1231                                ARRAY_SIZE(clk_out1_parents), 0,
1232                                pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1233                                &clk_out_lock);
1234         clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1235                                 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1236                                 &clk_out_lock);
1237         clk_register_clkdev(clk, "extern3", "clk_out_3");
1238         clks[clk_out_3] = clk;
1239
1240         /* blink */
1241         writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1242         clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1243                                 pmc_base + PMC_DPD_PADS_ORIDE,
1244                                 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1245         clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1246                                 pmc_base + PMC_CTRL,
1247                                 PMC_CTRL_BLINK_ENB, 0, NULL);
1248         clk_register_clkdev(clk, "blink", NULL);
1249         clks[blink] = clk;
1250
1251 }
1252
1253 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1254                                         "pll_p_cclkg", "pll_p_out4_cclkg",
1255                                         "pll_p_out3_cclkg", "unused", "pll_x" };
1256 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1257                                          "pll_p_cclklp", "pll_p_out4_cclklp",
1258                                          "pll_p_out3_cclklp", "unused", "pll_x",
1259                                          "pll_x_out0" };
1260 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1261                                       "pll_p_out3", "pll_p_out2", "unused",
1262                                       "clk_32k", "pll_m_out1" };
1263
1264 static void __init tegra30_super_clk_init(void)
1265 {
1266         struct clk *clk;
1267
1268         /*
1269          * Clock input to cclk_g divided from pll_p using
1270          * U71 divider of cclk_g.
1271          */
1272         clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1273                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1274                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1275         clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1276
1277         /*
1278          * Clock input to cclk_g divided from pll_p_out3 using
1279          * U71 divider of cclk_g.
1280          */
1281         clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1282                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1283                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1284         clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1285
1286         /*
1287          * Clock input to cclk_g divided from pll_p_out4 using
1288          * U71 divider of cclk_g.
1289          */
1290         clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1291                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1292                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1293         clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1294
1295         /* CCLKG */
1296         clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1297                                   ARRAY_SIZE(cclk_g_parents),
1298                                   CLK_SET_RATE_PARENT,
1299                                   clk_base + CCLKG_BURST_POLICY,
1300                                   0, 4, 0, 0, NULL);
1301         clk_register_clkdev(clk, "cclk_g", NULL);
1302         clks[cclk_g] = clk;
1303
1304         /*
1305          * Clock input to cclk_lp divided from pll_p using
1306          * U71 divider of cclk_lp.
1307          */
1308         clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1309                                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1310                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1311         clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1312
1313         /*
1314          * Clock input to cclk_lp divided from pll_p_out3 using
1315          * U71 divider of cclk_lp.
1316          */
1317         clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1318                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1319                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1320         clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1321
1322         /*
1323          * Clock input to cclk_lp divided from pll_p_out4 using
1324          * U71 divider of cclk_lp.
1325          */
1326         clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1327                                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1328                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1329         clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1330
1331         /* CCLKLP */
1332         clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1333                                   ARRAY_SIZE(cclk_lp_parents),
1334                                   CLK_SET_RATE_PARENT,
1335                                   clk_base + CCLKLP_BURST_POLICY,
1336                                   TEGRA_DIVIDER_2, 4, 8, 9,
1337                               NULL);
1338         clk_register_clkdev(clk, "cclk_lp", NULL);
1339         clks[cclk_lp] = clk;
1340
1341         /* SCLK */
1342         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1343                                   ARRAY_SIZE(sclk_parents),
1344                                   CLK_SET_RATE_PARENT,
1345                                   clk_base + SCLK_BURST_POLICY,
1346                                   0, 4, 0, 0, NULL);
1347         clk_register_clkdev(clk, "sclk", NULL);
1348         clks[sclk] = clk;
1349
1350         /* HCLK */
1351         clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1352                                    clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1353                                    &sysrate_lock);
1354         clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1355                                 clk_base + SYSTEM_CLK_RATE, 7,
1356                                 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1357         clk_register_clkdev(clk, "hclk", NULL);
1358         clks[hclk] = clk;
1359
1360         /* PCLK */
1361         clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1362                                    clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1363                                    &sysrate_lock);
1364         clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1365                                 clk_base + SYSTEM_CLK_RATE, 3,
1366                                 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1367         clk_register_clkdev(clk, "pclk", NULL);
1368         clks[pclk] = clk;
1369
1370         /* twd */
1371         clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1372                                         CLK_SET_RATE_PARENT, 1, 2);
1373         clk_register_clkdev(clk, "twd", NULL);
1374         clks[twd] = clk;
1375 }
1376
1377 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1378                                          "clk_m" };
1379 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1380 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1381 static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1382                                       "clk_m" };
1383 static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1384                                       "clk_m" };
1385 static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1386                                       "clk_m" };
1387 static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1388                                       "clk_m" };
1389 static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1390                                       "clk_m" };
1391 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1392                                            "clk_m" };
1393 static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1394 static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1395                                                "clk_m" };
1396 static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1397                                                "clk_32k" };
1398 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1399 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1400                                          "clk_m" };
1401 static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1402 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1403                                              "pll_a_out0", "pll_c",
1404                                              "pll_d2_out0", "clk_m" };
1405 static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1406                                                         "clk_32k", "pll_p",
1407                                                         "clk_m", "pll_e" };
1408 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1409                                                   "pll_d2_out0" };
1410
1411 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1412         TEGRA_INIT_DATA_MUX("i2s0",     NULL,           "tegra30-i2s.0",        i2s0_parents,           CLK_SOURCE_I2S0,        30,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1413         TEGRA_INIT_DATA_MUX("i2s1",     NULL,           "tegra30-i2s.1",        i2s1_parents,           CLK_SOURCE_I2S1,        11,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1414         TEGRA_INIT_DATA_MUX("i2s2",     NULL,           "tegra30-i2s.2",        i2s2_parents,           CLK_SOURCE_I2S2,        18,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1415         TEGRA_INIT_DATA_MUX("i2s3",     NULL,           "tegra30-i2s.3",        i2s3_parents,           CLK_SOURCE_I2S3,        101,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1416         TEGRA_INIT_DATA_MUX("i2s4",     NULL,           "tegra30-i2s.4",        i2s4_parents,           CLK_SOURCE_I2S4,        102,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1417         TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out",   "tegra30-spdif",        spdif_out_parents,      CLK_SOURCE_SPDIF_OUT,   10,     &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1418         TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in",     "tegra30-spdif",        spdif_in_parents,       CLK_SOURCE_SPDIF_IN,    10,     &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1419         TEGRA_INIT_DATA_MUX("d_audio",  "d_audio",      "tegra30-ahub",         mux_pllacp_clkm,        CLK_SOURCE_D_AUDIO,     106,    &periph_v_regs, 0, d_audio),
1420         TEGRA_INIT_DATA_MUX("dam0",     NULL,           "tegra30-dam.0",        mux_pllacp_clkm,        CLK_SOURCE_DAM0,        108,    &periph_v_regs, 0, dam0),
1421         TEGRA_INIT_DATA_MUX("dam1",     NULL,           "tegra30-dam.1",        mux_pllacp_clkm,        CLK_SOURCE_DAM1,        109,    &periph_v_regs, 0, dam1),
1422         TEGRA_INIT_DATA_MUX("dam2",     NULL,           "tegra30-dam.2",        mux_pllacp_clkm,        CLK_SOURCE_DAM2,        110,    &periph_v_regs, 0, dam2),
1423         TEGRA_INIT_DATA_MUX("hda",      "hda",          "tegra30-hda",          mux_pllpcm_clkm,        CLK_SOURCE_HDA,         125,    &periph_v_regs, 0, hda),
1424         TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda",         mux_pllpcm_clkm,        CLK_SOURCE_HDA2CODEC_2X, 111,   &periph_v_regs, 0, hda2codec_2x),
1425         TEGRA_INIT_DATA_MUX("sbc1",     NULL,           "spi_tegra.0",          mux_pllpcm_clkm,        CLK_SOURCE_SBC1,        41,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1426         TEGRA_INIT_DATA_MUX("sbc2",     NULL,           "spi_tegra.1",          mux_pllpcm_clkm,        CLK_SOURCE_SBC2,        44,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1427         TEGRA_INIT_DATA_MUX("sbc3",     NULL,           "spi_tegra.2",          mux_pllpcm_clkm,        CLK_SOURCE_SBC3,        46,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1428         TEGRA_INIT_DATA_MUX("sbc4",     NULL,           "spi_tegra.3",          mux_pllpcm_clkm,        CLK_SOURCE_SBC4,        68,     &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1429         TEGRA_INIT_DATA_MUX("sbc5",     NULL,           "spi_tegra.4",          mux_pllpcm_clkm,        CLK_SOURCE_SBC5,        104,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1430         TEGRA_INIT_DATA_MUX("sbc6",     NULL,           "spi_tegra.5",          mux_pllpcm_clkm,        CLK_SOURCE_SBC6,        105,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1431         TEGRA_INIT_DATA_MUX("sata_oob", NULL,           "tegra_sata_oob",       mux_pllpcm_clkm,        CLK_SOURCE_SATA_OOB,    123,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob),
1432         TEGRA_INIT_DATA_MUX("sata",     NULL,           "tegra_sata",           mux_pllpcm_clkm,        CLK_SOURCE_SATA,        124,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sata),
1433         TEGRA_INIT_DATA_MUX("ndflash",  NULL,           "tegra_nand",           mux_pllpcm_clkm,        CLK_SOURCE_NDFLASH,     13,     &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash),
1434         TEGRA_INIT_DATA_MUX("ndspeed",  NULL,           "tegra_nand_speed",     mux_pllpcm_clkm,        CLK_SOURCE_NDSPEED,     80,     &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1435         TEGRA_INIT_DATA_MUX("vfir",     NULL,           "vfir",                 mux_pllpcm_clkm,        CLK_SOURCE_VFIR,        7,      &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1436         TEGRA_INIT_DATA_MUX("csite",    NULL,           "csite",                mux_pllpcm_clkm,        CLK_SOURCE_CSITE,       73,     &periph_u_regs, TEGRA_PERIPH_ON_APB, csite),
1437         TEGRA_INIT_DATA_MUX("la",       NULL,           "la",                   mux_pllpcm_clkm,        CLK_SOURCE_LA,          76,     &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1438         TEGRA_INIT_DATA_MUX("owr",      NULL,           "tegra_w1",             mux_pllpcm_clkm,        CLK_SOURCE_OWR,         71,     &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1439         TEGRA_INIT_DATA_MUX("mipi",     NULL,           "mipi",                 mux_pllpcm_clkm,        CLK_SOURCE_MIPI,        50,     &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1440         TEGRA_INIT_DATA_MUX("tsensor",  NULL,           "tegra-tsensor",        mux_pllpc_clkm_clk32k,  CLK_SOURCE_TSENSOR,     100,    &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1441         TEGRA_INIT_DATA_MUX("i2cslow",  NULL,           "i2cslow",              mux_pllpc_clk32k_clkm,  CLK_SOURCE_I2CSLOW,     81,     &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1442         TEGRA_INIT_DATA_INT("vde",      NULL,           "vde",                  mux_pllpcm_clkm,        CLK_SOURCE_VDE,         61,     &periph_h_regs, 0, vde),
1443         TEGRA_INIT_DATA_INT("vi",       "vi",           "tegra_camera",         mux_pllmcpa,            CLK_SOURCE_VI,          20,     &periph_l_regs, 0, vi),
1444         TEGRA_INIT_DATA_INT("epp",      NULL,           "epp",                  mux_pllmcpa,            CLK_SOURCE_EPP,         19,     &periph_l_regs, 0, epp),
1445         TEGRA_INIT_DATA_INT("mpe",      NULL,           "mpe",                  mux_pllmcpa,            CLK_SOURCE_MPE,         60,     &periph_h_regs, 0, mpe),
1446         TEGRA_INIT_DATA_INT("host1x",   NULL,           "host1x",               mux_pllmcpa,            CLK_SOURCE_HOST1X,      28,     &periph_l_regs, 0, host1x),
1447         TEGRA_INIT_DATA_INT("3d",       NULL,           "3d",                   mux_pllmcpa,            CLK_SOURCE_3D,          24,     &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1448         TEGRA_INIT_DATA_INT("3d2",      NULL,           "3d2",                  mux_pllmcpa,            CLK_SOURCE_3D2,         98,     &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1449         TEGRA_INIT_DATA_INT("2d",       NULL,           "2d",                   mux_pllmcpa,            CLK_SOURCE_2D,          21,     &periph_l_regs, 0, gr2d),
1450         TEGRA_INIT_DATA_INT("se",       NULL,           "se",                   mux_pllpcm_clkm,        CLK_SOURCE_SE,          127,    &periph_v_regs, 0, se),
1451         TEGRA_INIT_DATA_MUX("mselect",  NULL,           "mselect",              mux_pllp_clkm,          CLK_SOURCE_MSELECT,     99,     &periph_v_regs, 0, mselect),
1452         TEGRA_INIT_DATA_MUX("nor",      NULL,           "tegra-nor",            mux_pllpcm_clkm,        CLK_SOURCE_NOR,         42,     &periph_h_regs, 0, nor),
1453         TEGRA_INIT_DATA_MUX("sdmmc1",   NULL,           "sdhci-tegra.0",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC1,      14,     &periph_l_regs, 0, sdmmc1),
1454         TEGRA_INIT_DATA_MUX("sdmmc2",   NULL,           "sdhci-tegra.1",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC2,      9,      &periph_l_regs, 0, sdmmc2),
1455         TEGRA_INIT_DATA_MUX("sdmmc3",   NULL,           "sdhci-tegra.2",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC3,      69,     &periph_u_regs, 0, sdmmc3),
1456         TEGRA_INIT_DATA_MUX("sdmmc4",   NULL,           "sdhci-tegra.3",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC4,      15,     &periph_l_regs, 0, sdmmc4),
1457         TEGRA_INIT_DATA_MUX("cve",      NULL,           "cve",                  mux_pllpdc_clkm,        CLK_SOURCE_CVE,         49,     &periph_h_regs, 0, cve),
1458         TEGRA_INIT_DATA_MUX("tvo",      NULL,           "tvo",                  mux_pllpdc_clkm,        CLK_SOURCE_TVO,         49,     &periph_h_regs, 0, tvo),
1459         TEGRA_INIT_DATA_MUX("tvdac",    NULL,           "tvdac",                mux_pllpdc_clkm,        CLK_SOURCE_TVDAC,       53,     &periph_h_regs, 0, tvdac),
1460         TEGRA_INIT_DATA_MUX("actmon",   NULL,           "actmon",               mux_pllpc_clk32k_clkm,  CLK_SOURCE_ACTMON,      119,    &periph_v_regs, 0, actmon),
1461         TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor",   "tegra_camera",         mux_pllmcpa,            CLK_SOURCE_VI_SENSOR,   20,     &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1462         TEGRA_INIT_DATA_DIV16("i2c1",   "div-clk",      "tegra-i2c.0",          mux_pllp_clkm,          CLK_SOURCE_I2C1,        12,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
1463         TEGRA_INIT_DATA_DIV16("i2c2",   "div-clk",      "tegra-i2c.1",          mux_pllp_clkm,          CLK_SOURCE_I2C2,        54,     &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
1464         TEGRA_INIT_DATA_DIV16("i2c3",   "div-clk",      "tegra-i2c.2",          mux_pllp_clkm,          CLK_SOURCE_I2C3,        67,     &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
1465         TEGRA_INIT_DATA_DIV16("i2c4",   "div-clk",      "tegra-i2c.3",          mux_pllp_clkm,          CLK_SOURCE_I2C4,        103,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4),
1466         TEGRA_INIT_DATA_DIV16("i2c5",   "div-clk",      "tegra-i2c.4",          mux_pllp_clkm,          CLK_SOURCE_I2C5,        47,     &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5),
1467         TEGRA_INIT_DATA_UART("uarta",   NULL,           "tegra_uart.0",         mux_pllpcm_clkm,        CLK_SOURCE_UARTA,       6,      &periph_l_regs, uarta),
1468         TEGRA_INIT_DATA_UART("uartb",   NULL,           "tegra_uart.1",         mux_pllpcm_clkm,        CLK_SOURCE_UARTB,       7,      &periph_l_regs, uartb),
1469         TEGRA_INIT_DATA_UART("uartc",   NULL,           "tegra_uart.2",         mux_pllpcm_clkm,        CLK_SOURCE_UARTC,       55,     &periph_h_regs, uartc),
1470         TEGRA_INIT_DATA_UART("uartd",   NULL,           "tegra_uart.3",         mux_pllpcm_clkm,        CLK_SOURCE_UARTD,       65,     &periph_u_regs, uartd),
1471         TEGRA_INIT_DATA_UART("uarte",   NULL,           "tegra_uart.4",         mux_pllpcm_clkm,        CLK_SOURCE_UARTE,       66,     &periph_u_regs, uarte),
1472         TEGRA_INIT_DATA_MUX8("hdmi",    NULL,           "hdmi",                 mux_pllpmdacd2_clkm,    CLK_SOURCE_HDMI,        51,     &periph_h_regs, 0, hdmi),
1473         TEGRA_INIT_DATA_MUX8("extern1", NULL,           "extern1",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1,     120,    &periph_v_regs, 0, extern1),
1474         TEGRA_INIT_DATA_MUX8("extern2", NULL,           "extern2",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2,     121,    &periph_v_regs, 0, extern2),
1475         TEGRA_INIT_DATA_MUX8("extern3", NULL,           "extern3",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3,     122,    &periph_v_regs, 0, extern3),
1476         TEGRA_INIT_DATA("pwm",          NULL,           "pwm",                  mux_pllpc_clk32k_clkm,  CLK_SOURCE_PWM,         28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm),
1477 };
1478
1479 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1480         TEGRA_INIT_DATA_NODIV("disp1",  NULL, "tegradc.0", mux_pllpmdacd2_clkm,      CLK_SOURCE_DISP1,  29, 3, 27, &periph_l_regs, 0, disp1),
1481         TEGRA_INIT_DATA_NODIV("disp2",  NULL, "tegradc.1", mux_pllpmdacd2_clkm,      CLK_SOURCE_DISP2,  29, 3, 26, &periph_l_regs, 0, disp2),
1482         TEGRA_INIT_DATA_NODIV("dsib",   NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB,   25, 1, 82, &periph_u_regs, 0, dsib),
1483 };
1484
1485 static void __init tegra30_periph_clk_init(void)
1486 {
1487         struct tegra_periph_init_data *data;
1488         struct clk *clk;
1489         int i;
1490
1491         /* apbdma */
1492         clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1493                                     &periph_h_regs, periph_clk_enb_refcnt);
1494         clk_register_clkdev(clk, NULL, "tegra-apbdma");
1495         clks[apbdma] = clk;
1496
1497         /* rtc */
1498         clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1499                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1500                                     clk_base, 0, 4, &periph_l_regs,
1501                                     periph_clk_enb_refcnt);
1502         clk_register_clkdev(clk, NULL, "rtc-tegra");
1503         clks[rtc] = clk;
1504
1505         /* timer */
1506         clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1507                                     5, &periph_l_regs, periph_clk_enb_refcnt);
1508         clk_register_clkdev(clk, NULL, "timer");
1509         clks[timer] = clk;
1510
1511         /* kbc */
1512         clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1513                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1514                                     clk_base, 0, 36, &periph_h_regs,
1515                                     periph_clk_enb_refcnt);
1516         clk_register_clkdev(clk, NULL, "tegra-kbc");
1517         clks[kbc] = clk;
1518
1519         /* csus */
1520         clk = tegra_clk_register_periph_gate("csus", "clk_m",
1521                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1522                                     clk_base, 0, 92, &periph_u_regs,
1523                                     periph_clk_enb_refcnt);
1524         clk_register_clkdev(clk, "csus", "tengra_camera");
1525         clks[csus] = clk;
1526
1527         /* vcp */
1528         clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1529                                     &periph_l_regs, periph_clk_enb_refcnt);
1530         clk_register_clkdev(clk, "vcp", "tegra-avp");
1531         clks[vcp] = clk;
1532
1533         /* bsea */
1534         clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1535                                     62, &periph_h_regs, periph_clk_enb_refcnt);
1536         clk_register_clkdev(clk, "bsea", "tegra-avp");
1537         clks[bsea] = clk;
1538
1539         /* bsev */
1540         clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1541                                     63, &periph_h_regs, periph_clk_enb_refcnt);
1542         clk_register_clkdev(clk, "bsev", "tegra-aes");
1543         clks[bsev] = clk;
1544
1545         /* usbd */
1546         clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1547                                     22, &periph_l_regs, periph_clk_enb_refcnt);
1548         clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1549         clks[usbd] = clk;
1550
1551         /* usb2 */
1552         clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1553                                     58, &periph_h_regs, periph_clk_enb_refcnt);
1554         clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1555         clks[usb2] = clk;
1556
1557         /* usb3 */
1558         clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1559                                     59, &periph_h_regs, periph_clk_enb_refcnt);
1560         clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1561         clks[usb3] = clk;
1562
1563         /* dsia */
1564         clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1565                                     0, 48, &periph_h_regs,
1566                                     periph_clk_enb_refcnt);
1567         clk_register_clkdev(clk, "dsia", "tegradc.0");
1568         clks[dsia] = clk;
1569
1570         /* csi */
1571         clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1572                                     0, 52, &periph_h_regs,
1573                                     periph_clk_enb_refcnt);
1574         clk_register_clkdev(clk, "csi", "tegra_camera");
1575         clks[csi] = clk;
1576
1577         /* isp */
1578         clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1579                                     &periph_l_regs, periph_clk_enb_refcnt);
1580         clk_register_clkdev(clk, "isp", "tegra_camera");
1581         clks[isp] = clk;
1582
1583         /* pcie */
1584         clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1585                                     70, &periph_u_regs, periph_clk_enb_refcnt);
1586         clk_register_clkdev(clk, "pcie", "tegra-pcie");
1587         clks[pcie] = clk;
1588
1589         /* afi */
1590         clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1591                                     &periph_u_regs, periph_clk_enb_refcnt);
1592         clk_register_clkdev(clk, "afi", "tegra-pcie");
1593         clks[afi] = clk;
1594
1595         /* kfuse */
1596         clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1597                                     TEGRA_PERIPH_ON_APB,
1598                                     clk_base, 0, 40, &periph_h_regs,
1599                                     periph_clk_enb_refcnt);
1600         clk_register_clkdev(clk, NULL, "kfuse-tegra");
1601         clks[kfuse] = clk;
1602
1603         /* fuse */
1604         clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1605                                     TEGRA_PERIPH_ON_APB,
1606                                     clk_base, 0, 39, &periph_h_regs,
1607                                     periph_clk_enb_refcnt);
1608         clk_register_clkdev(clk, "fuse", "fuse-tegra");
1609         clks[fuse] = clk;
1610
1611         /* fuse_burn */
1612         clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1613                                     TEGRA_PERIPH_ON_APB,
1614                                     clk_base, 0, 39, &periph_h_regs,
1615                                     periph_clk_enb_refcnt);
1616         clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1617         clks[fuse_burn] = clk;
1618
1619         /* apbif */
1620         clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1621                                     clk_base, 0, 107, &periph_v_regs,
1622                                     periph_clk_enb_refcnt);
1623         clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1624         clks[apbif] = clk;
1625
1626         /* hda2hdmi */
1627         clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1628                                     TEGRA_PERIPH_ON_APB,
1629                                     clk_base, 0, 128, &periph_w_regs,
1630                                     periph_clk_enb_refcnt);
1631         clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1632         clks[hda2hdmi] = clk;
1633
1634         /* sata_cold */
1635         clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1636                                     TEGRA_PERIPH_ON_APB,
1637                                     clk_base, 0, 129, &periph_w_regs,
1638                                     periph_clk_enb_refcnt);
1639         clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1640         clks[sata_cold] = clk;
1641
1642         /* dtv */
1643         clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1644                                     TEGRA_PERIPH_ON_APB,
1645                                     clk_base, 0, 79, &periph_u_regs,
1646                                     periph_clk_enb_refcnt);
1647         clk_register_clkdev(clk, NULL, "dtv");
1648         clks[dtv] = clk;
1649
1650         /* emc */
1651         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1652                                ARRAY_SIZE(mux_pllmcp_clkm), 0,
1653                                clk_base + CLK_SOURCE_EMC,
1654                                30, 2, 0, NULL);
1655         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1656                                     57, &periph_h_regs, periph_clk_enb_refcnt);
1657         clk_register_clkdev(clk, "emc", NULL);
1658         clks[emc] = clk;
1659
1660         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1661                 data = &tegra_periph_clk_list[i];
1662                 clk = tegra_clk_register_periph(data->name, data->parent_names,
1663                                 data->num_parents, &data->periph,
1664                                 clk_base, data->offset);
1665                 clk_register_clkdev(clk, data->con_id, data->dev_id);
1666                 clks[data->clk_id] = clk;
1667         }
1668
1669         for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1670                 data = &tegra_periph_nodiv_clk_list[i];
1671                 clk = tegra_clk_register_periph_nodiv(data->name,
1672                                         data->parent_names,
1673                                         data->num_parents, &data->periph,
1674                                         clk_base, data->offset);
1675                 clk_register_clkdev(clk, data->con_id, data->dev_id);
1676                 clks[data->clk_id] = clk;
1677         }
1678 }
1679
1680 static void __init tegra30_fixed_clk_init(void)
1681 {
1682         struct clk *clk;
1683
1684         /* clk_32k */
1685         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1686                                 32768);
1687         clk_register_clkdev(clk, "clk_32k", NULL);
1688         clks[clk_32k] = clk;
1689
1690         /* clk_m_div2 */
1691         clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1692                                 CLK_SET_RATE_PARENT, 1, 2);
1693         clk_register_clkdev(clk, "clk_m_div2", NULL);
1694         clks[clk_m_div2] = clk;
1695
1696         /* clk_m_div4 */
1697         clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1698                                 CLK_SET_RATE_PARENT, 1, 4);
1699         clk_register_clkdev(clk, "clk_m_div4", NULL);
1700         clks[clk_m_div4] = clk;
1701
1702         /* cml0 */
1703         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1704                                 0, 0, &cml_lock);
1705         clk_register_clkdev(clk, "cml0", NULL);
1706         clks[cml0] = clk;
1707
1708         /* cml1 */
1709         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1710                                 1, 0, &cml_lock);
1711         clk_register_clkdev(clk, "cml1", NULL);
1712         clks[cml1] = clk;
1713
1714         /* pciex */
1715         clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
1716         clk_register_clkdev(clk, "pciex", NULL);
1717         clks[pciex] = clk;
1718 }
1719
1720 static void __init tegra30_osc_clk_init(void)
1721 {
1722         struct clk *clk;
1723         unsigned int pll_ref_div;
1724
1725         tegra30_clk_measure_input_freq();
1726
1727         /* clk_m */
1728         clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1729                                 input_freq);
1730         clk_register_clkdev(clk, "clk_m", NULL);
1731         clks[clk_m] = clk;
1732
1733         /* pll_ref */
1734         pll_ref_div = tegra30_get_pll_ref_div();
1735         clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1736                                 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1737         clk_register_clkdev(clk, "pll_ref", NULL);
1738         clks[pll_ref] = clk;
1739 }
1740
1741 /* Tegra30 CPU clock and reset control functions */
1742 static void tegra30_wait_cpu_in_reset(u32 cpu)
1743 {
1744         unsigned int reg;
1745
1746         do {
1747                 reg = readl(clk_base +
1748                             TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1749                 cpu_relax();
1750         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1751
1752         return;
1753 }
1754
1755 static void tegra30_put_cpu_in_reset(u32 cpu)
1756 {
1757         writel(CPU_RESET(cpu),
1758                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1759         dmb();
1760 }
1761
1762 static void tegra30_cpu_out_of_reset(u32 cpu)
1763 {
1764         writel(CPU_RESET(cpu),
1765                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1766         wmb();
1767 }
1768
1769
1770 static void tegra30_enable_cpu_clock(u32 cpu)
1771 {
1772         unsigned int reg;
1773
1774         writel(CPU_CLOCK(cpu),
1775                clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1776         reg = readl(clk_base +
1777                     TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1778 }
1779
1780 static void tegra30_disable_cpu_clock(u32 cpu)
1781 {
1782
1783         unsigned int reg;
1784
1785         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1786         writel(reg | CPU_CLOCK(cpu),
1787                clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1788 }
1789
1790 #ifdef CONFIG_PM_SLEEP
1791 static bool tegra30_cpu_rail_off_ready(void)
1792 {
1793         unsigned int cpu_rst_status;
1794         int cpu_pwr_status;
1795
1796         cpu_rst_status = readl(clk_base +
1797                                 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1798         cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1799                          tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1800                          tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1801
1802         if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1803                 return false;
1804
1805         return true;
1806 }
1807
1808 static void tegra30_cpu_clock_suspend(void)
1809 {
1810         /* switch coresite to clk_m, save off original source */
1811         tegra30_cpu_clk_sctx.clk_csite_src =
1812                                 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1813         writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1814
1815         tegra30_cpu_clk_sctx.cpu_burst =
1816                                 readl(clk_base + CLK_RESET_CCLK_BURST);
1817         tegra30_cpu_clk_sctx.pllx_base =
1818                                 readl(clk_base + CLK_RESET_PLLX_BASE);
1819         tegra30_cpu_clk_sctx.pllx_misc =
1820                                 readl(clk_base + CLK_RESET_PLLX_MISC);
1821         tegra30_cpu_clk_sctx.cclk_divider =
1822                                 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1823 }
1824
1825 static void tegra30_cpu_clock_resume(void)
1826 {
1827         unsigned int reg, policy;
1828
1829         /* Is CPU complex already running on PLLX? */
1830         reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1831         policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1832
1833         if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1834                 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1835         else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1836                 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1837         else
1838                 BUG();
1839
1840         if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1841                 /* restore PLLX settings if CPU is on different PLL */
1842                 writel(tegra30_cpu_clk_sctx.pllx_misc,
1843                                         clk_base + CLK_RESET_PLLX_MISC);
1844                 writel(tegra30_cpu_clk_sctx.pllx_base,
1845                                         clk_base + CLK_RESET_PLLX_BASE);
1846
1847                 /* wait for PLL stabilization if PLLX was enabled */
1848                 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1849                         udelay(300);
1850         }
1851
1852         /*
1853          * Restore original burst policy setting for calls resulting from CPU
1854          * LP2 in idle or system suspend.
1855          */
1856         writel(tegra30_cpu_clk_sctx.cclk_divider,
1857                                         clk_base + CLK_RESET_CCLK_DIVIDER);
1858         writel(tegra30_cpu_clk_sctx.cpu_burst,
1859                                         clk_base + CLK_RESET_CCLK_BURST);
1860
1861         writel(tegra30_cpu_clk_sctx.clk_csite_src,
1862                                         clk_base + CLK_RESET_SOURCE_CSITE);
1863 }
1864 #endif
1865
1866 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1867         .wait_for_reset = tegra30_wait_cpu_in_reset,
1868         .put_in_reset   = tegra30_put_cpu_in_reset,
1869         .out_of_reset   = tegra30_cpu_out_of_reset,
1870         .enable_clock   = tegra30_enable_cpu_clock,
1871         .disable_clock  = tegra30_disable_cpu_clock,
1872 #ifdef CONFIG_PM_SLEEP
1873         .rail_off_ready = tegra30_cpu_rail_off_ready,
1874         .suspend        = tegra30_cpu_clock_suspend,
1875         .resume         = tegra30_cpu_clock_resume,
1876 #endif
1877 };
1878
1879 static __initdata struct tegra_clk_init_table init_table[] = {
1880         {uarta, pll_p, 408000000, 0},
1881         {uartb, pll_p, 408000000, 0},
1882         {uartc, pll_p, 408000000, 0},
1883         {uartd, pll_p, 408000000, 0},
1884         {uarte, pll_p, 408000000, 0},
1885         {pll_a, clk_max, 564480000, 1},
1886         {pll_a_out0, clk_max, 11289600, 1},
1887         {extern1, pll_a_out0, 0, 1},
1888         {clk_out_1_mux, extern1, 0, 0},
1889         {clk_out_1, clk_max, 0, 1},
1890         {blink, clk_max, 0, 1},
1891         {i2s0, pll_a_out0, 11289600, 0},
1892         {i2s1, pll_a_out0, 11289600, 0},
1893         {i2s2, pll_a_out0, 11289600, 0},
1894         {i2s3, pll_a_out0, 11289600, 0},
1895         {i2s4, pll_a_out0, 11289600, 0},
1896         {sdmmc1, pll_p, 48000000, 0},
1897         {sdmmc2, pll_p, 48000000, 0},
1898         {sdmmc3, pll_p, 48000000, 0},
1899         {pll_m, clk_max, 0, 1},
1900         {pclk, clk_max, 0, 1},
1901         {csite, clk_max, 0, 1},
1902         {emc, clk_max, 0, 1},
1903         {mselect, clk_max, 0, 1},
1904         {sbc1, pll_p, 100000000, 0},
1905         {sbc2, pll_p, 100000000, 0},
1906         {sbc3, pll_p, 100000000, 0},
1907         {sbc4, pll_p, 100000000, 0},
1908         {sbc5, pll_p, 100000000, 0},
1909         {sbc6, pll_p, 100000000, 0},
1910         {host1x, pll_c, 150000000, 0},
1911         {disp1, pll_p, 600000000, 0},
1912         {disp2, pll_p, 600000000, 0},
1913         {twd, clk_max, 0, 1},
1914         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1915 };
1916
1917 /*
1918  * Some clocks may be used by different drivers depending on the board
1919  * configuration.  List those here to register them twice in the clock lookup
1920  * table under two names.
1921  */
1922 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1923         TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
1924         TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
1925         TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
1926         TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"),
1927         TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"),
1928         TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"),
1929         TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"),
1930         TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"),
1931         TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
1932         TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
1933         TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),
1934         TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"),
1935         TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
1936 };
1937
1938 static const struct of_device_id pmc_match[] __initconst = {
1939         { .compatible = "nvidia,tegra30-pmc" },
1940         {},
1941 };
1942
1943 void __init tegra30_clock_init(struct device_node *np)
1944 {
1945         struct device_node *node;
1946         int i;
1947
1948         clk_base = of_iomap(np, 0);
1949         if (!clk_base) {
1950                 pr_err("ioremap tegra30 CAR failed\n");
1951                 return;
1952         }
1953
1954         node = of_find_matching_node(NULL, pmc_match);
1955         if (!node) {
1956                 pr_err("Failed to find pmc node\n");
1957                 BUG();
1958         }
1959
1960         pmc_base = of_iomap(node, 0);
1961         if (!pmc_base) {
1962                 pr_err("Can't map pmc registers\n");
1963                 BUG();
1964         }
1965
1966         tegra30_osc_clk_init();
1967         tegra30_fixed_clk_init();
1968         tegra30_pll_init();
1969         tegra30_super_clk_init();
1970         tegra30_periph_clk_init();
1971         tegra30_audio_clk_init();
1972         tegra30_pmc_clk_init();
1973
1974         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1975                 if (IS_ERR(clks[i])) {
1976                         pr_err("Tegra30 clk %d: register failed with %ld\n",
1977                                i, PTR_ERR(clks[i]));
1978                         BUG();
1979                 }
1980                 if (!clks[i])
1981                         clks[i] = ERR_PTR(-EINVAL);
1982         }
1983
1984         tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1985
1986         clk_data.clks = clks;
1987         clk_data.clk_num = ARRAY_SIZE(clks);
1988         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1989
1990         tegra_init_from_table(init_table, clks, clk_max);
1991
1992         tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1993 }