drivers/clk/samsung/clk-exynos5433.c

   1 /*
   2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3  * Author: Chanwoo Choi <cw00.choi@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Exynos5443 SoC.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/of.h>
  16
  17 #include <dt-bindings/clock/exynos5433.h>
  18
  19 #include "clk.h"
  20 #include "clk-pll.h"
  21
  22 /*
  23  * Register offset definitions for CMU_TOP
  24  */
  25 #define ISP_PLL_LOCK                    0x0000
  26 #define AUD_PLL_LOCK                    0x0004
  27 #define ISP_PLL_CON0                    0x0100
  28 #define ISP_PLL_CON1                    0x0104
  29 #define ISP_PLL_FREQ_DET                0x0108
  30 #define AUD_PLL_CON0                    0x0110
  31 #define AUD_PLL_CON1                    0x0114
  32 #define AUD_PLL_CON2                    0x0118
  33 #define AUD_PLL_FREQ_DET                0x011c
  34 #define MUX_SEL_TOP0                    0x0200
  35 #define MUX_SEL_TOP1                    0x0204
  36 #define MUX_SEL_TOP2                    0x0208
  37 #define MUX_SEL_TOP3                    0x020c
  38 #define MUX_SEL_TOP4                    0x0210
  39 #define MUX_SEL_TOP_MSCL                0x0220
  40 #define MUX_SEL_TOP_CAM1                0x0224
  41 #define MUX_SEL_TOP_DISP                0x0228
  42 #define MUX_SEL_TOP_FSYS0               0x0230
  43 #define MUX_SEL_TOP_FSYS1               0x0234
  44 #define MUX_SEL_TOP_PERIC0              0x0238
  45 #define MUX_SEL_TOP_PERIC1              0x023c
  46 #define MUX_ENABLE_TOP0                 0x0300
  47 #define MUX_ENABLE_TOP1                 0x0304
  48 #define MUX_ENABLE_TOP2                 0x0308
  49 #define MUX_ENABLE_TOP3                 0x030c
  50 #define MUX_ENABLE_TOP4                 0x0310
  51 #define MUX_ENABLE_TOP_MSCL             0x0320
  52 #define MUX_ENABLE_TOP_CAM1             0x0324
  53 #define MUX_ENABLE_TOP_DISP             0x0328
  54 #define MUX_ENABLE_TOP_FSYS0            0x0330
  55 #define MUX_ENABLE_TOP_FSYS1            0x0334
  56 #define MUX_ENABLE_TOP_PERIC0           0x0338
  57 #define MUX_ENABLE_TOP_PERIC1           0x033c
  58 #define MUX_STAT_TOP0                   0x0400
  59 #define MUX_STAT_TOP1                   0x0404
  60 #define MUX_STAT_TOP2                   0x0408
  61 #define MUX_STAT_TOP3                   0x040c
  62 #define MUX_STAT_TOP4                   0x0410
  63 #define MUX_STAT_TOP_MSCL               0x0420
  64 #define MUX_STAT_TOP_CAM1               0x0424
  65 #define MUX_STAT_TOP_FSYS0              0x0430
  66 #define MUX_STAT_TOP_FSYS1              0x0434
  67 #define MUX_STAT_TOP_PERIC0             0x0438
  68 #define MUX_STAT_TOP_PERIC1             0x043c
  69 #define DIV_TOP0                        0x0600
  70 #define DIV_TOP1                        0x0604
  71 #define DIV_TOP2                        0x0608
  72 #define DIV_TOP3                        0x060c
  73 #define DIV_TOP4                        0x0610
  74 #define DIV_TOP_MSCL                    0x0618
  75 #define DIV_TOP_CAM10                   0x061c
  76 #define DIV_TOP_CAM11                   0x0620
  77 #define DIV_TOP_FSYS0                   0x062c
  78 #define DIV_TOP_FSYS1                   0x0630
  79 #define DIV_TOP_FSYS2                   0x0634
  80 #define DIV_TOP_PERIC0                  0x0638
  81 #define DIV_TOP_PERIC1                  0x063c
  82 #define DIV_TOP_PERIC2                  0x0640
  83 #define DIV_TOP_PERIC3                  0x0644
  84 #define DIV_TOP_PERIC4                  0x0648
  85 #define DIV_TOP_PLL_FREQ_DET            0x064c
  86 #define DIV_STAT_TOP0                   0x0700
  87 #define DIV_STAT_TOP1                   0x0704
  88 #define DIV_STAT_TOP2                   0x0708
  89 #define DIV_STAT_TOP3                   0x070c
  90 #define DIV_STAT_TOP4                   0x0710
  91 #define DIV_STAT_TOP_MSCL               0x0718
  92 #define DIV_STAT_TOP_CAM10              0x071c
  93 #define DIV_STAT_TOP_CAM11              0x0720
  94 #define DIV_STAT_TOP_FSYS0              0x072c
  95 #define DIV_STAT_TOP_FSYS1              0x0730
  96 #define DIV_STAT_TOP_FSYS2              0x0734
  97 #define DIV_STAT_TOP_PERIC0             0x0738
  98 #define DIV_STAT_TOP_PERIC1             0x073c
  99 #define DIV_STAT_TOP_PERIC2             0x0740
 100 #define DIV_STAT_TOP_PERIC3             0x0744
 101 #define DIV_STAT_TOP_PLL_FREQ_DET       0x074c
 102 #define ENABLE_ACLK_TOP                 0x0800
 103 #define ENABLE_SCLK_TOP                 0x0a00
 104 #define ENABLE_SCLK_TOP_MSCL            0x0a04
 105 #define ENABLE_SCLK_TOP_CAM1            0x0a08
 106 #define ENABLE_SCLK_TOP_DISP            0x0a0c
 107 #define ENABLE_SCLK_TOP_FSYS            0x0a10
 108 #define ENABLE_SCLK_TOP_PERIC           0x0a14
 109 #define ENABLE_IP_TOP                   0x0b00
 110 #define ENABLE_CMU_TOP                  0x0c00
 111 #define ENABLE_CMU_TOP_DIV_STAT         0x0c04
 112
 113 static unsigned long top_clk_regs[] __initdata = {
 114         ISP_PLL_LOCK,
 115         AUD_PLL_LOCK,
 116         ISP_PLL_CON0,
 117         ISP_PLL_CON1,
 118         ISP_PLL_FREQ_DET,
 119         AUD_PLL_CON0,
 120         AUD_PLL_CON1,
 121         AUD_PLL_CON2,
 122         AUD_PLL_FREQ_DET,
 123         MUX_SEL_TOP0,
 124         MUX_SEL_TOP1,
 125         MUX_SEL_TOP2,
 126         MUX_SEL_TOP3,
 127         MUX_SEL_TOP4,
 128         MUX_SEL_TOP_MSCL,
 129         MUX_SEL_TOP_CAM1,
 130         MUX_SEL_TOP_DISP,
 131         MUX_SEL_TOP_FSYS0,
 132         MUX_SEL_TOP_FSYS1,
 133         MUX_SEL_TOP_PERIC0,
 134         MUX_SEL_TOP_PERIC1,
 135         MUX_ENABLE_TOP0,
 136         MUX_ENABLE_TOP1,
 137         MUX_ENABLE_TOP2,
 138         MUX_ENABLE_TOP3,
 139         MUX_ENABLE_TOP4,
 140         MUX_ENABLE_TOP_MSCL,
 141         MUX_ENABLE_TOP_CAM1,
 142         MUX_ENABLE_TOP_DISP,
 143         MUX_ENABLE_TOP_FSYS0,
 144         MUX_ENABLE_TOP_FSYS1,
 145         MUX_ENABLE_TOP_PERIC0,
 146         MUX_ENABLE_TOP_PERIC1,
 147         MUX_STAT_TOP0,
 148         MUX_STAT_TOP1,
 149         MUX_STAT_TOP2,
 150         MUX_STAT_TOP3,
 151         MUX_STAT_TOP4,
 152         MUX_STAT_TOP_MSCL,
 153         MUX_STAT_TOP_CAM1,
 154         MUX_STAT_TOP_FSYS0,
 155         MUX_STAT_TOP_FSYS1,
 156         MUX_STAT_TOP_PERIC0,
 157         MUX_STAT_TOP_PERIC1,
 158         DIV_TOP0,
 159         DIV_TOP1,
 160         DIV_TOP2,
 161         DIV_TOP3,
 162         DIV_TOP4,
 163         DIV_TOP_MSCL,
 164         DIV_TOP_CAM10,
 165         DIV_TOP_CAM11,
 166         DIV_TOP_FSYS0,
 167         DIV_TOP_FSYS1,
 168         DIV_TOP_FSYS2,
 169         DIV_TOP_PERIC0,
 170         DIV_TOP_PERIC1,
 171         DIV_TOP_PERIC2,
 172         DIV_TOP_PERIC3,
 173         DIV_TOP_PERIC4,
 174         DIV_TOP_PLL_FREQ_DET,
 175         DIV_STAT_TOP0,
 176         DIV_STAT_TOP1,
 177         DIV_STAT_TOP2,
 178         DIV_STAT_TOP3,
 179         DIV_STAT_TOP4,
 180         DIV_STAT_TOP_MSCL,
 181         DIV_STAT_TOP_CAM10,
 182         DIV_STAT_TOP_CAM11,
 183         DIV_STAT_TOP_FSYS0,
 184         DIV_STAT_TOP_FSYS1,
 185         DIV_STAT_TOP_FSYS2,
 186         DIV_STAT_TOP_PERIC0,
 187         DIV_STAT_TOP_PERIC1,
 188         DIV_STAT_TOP_PERIC2,
 189         DIV_STAT_TOP_PERIC3,
 190         DIV_STAT_TOP_PLL_FREQ_DET,
 191         ENABLE_ACLK_TOP,
 192         ENABLE_SCLK_TOP,
 193         ENABLE_SCLK_TOP_MSCL,
 194         ENABLE_SCLK_TOP_CAM1,
 195         ENABLE_SCLK_TOP_DISP,
 196         ENABLE_SCLK_TOP_FSYS,
 197         ENABLE_SCLK_TOP_PERIC,
 198         ENABLE_IP_TOP,
 199         ENABLE_CMU_TOP,
 200         ENABLE_CMU_TOP_DIV_STAT,
 201 };
 202
 203 /* list of all parent clock list */
 204 PNAME(mout_aud_pll_p)           = { "oscclk", "fout_aud_pll", };
 205 PNAME(mout_isp_pll_p)           = { "oscclk", "fout_isp_pll", };
 206 PNAME(mout_aud_pll_user_p)      = { "oscclk", "mout_aud_pll", };
 207 PNAME(mout_mphy_pll_user_p)     = { "oscclk", "sclk_mphy_pll", };
 208 PNAME(mout_mfc_pll_user_p)      = { "oscclk", "sclk_mfc_pll", };
 209 PNAME(mout_bus_pll_user_p)      = { "oscclk", "sclk_bus_pll", };
 210 PNAME(mout_bus_pll_user_t_p)    = { "oscclk", "mout_bus_pll_user", };
 211 PNAME(mout_mphy_pll_user_t_p)   = { "oscclk", "mout_mphy_pll_user", };
 212
 213 PNAME(mout_bus_mfc_pll_user_p)  = { "mout_bus_pll_user", "mout_mfc_pll_user",};
 214 PNAME(mout_mfc_bus_pll_user_p)  = { "mout_mfc_pll_user", "mout_bus_pll_user",};
 215 PNAME(mout_aclk_cam1_552_b_p)   = { "mout_aclk_cam1_552_a",
 216                                     "mout_mfc_pll_user", };
 217 PNAME(mout_aclk_cam1_552_a_p)   = { "mout_isp_pll", "mout_bus_pll_user", };
 218
 219 PNAME(mout_aclk_mfc_400_c_p)    = { "mout_aclk_mfc_400_b",
 220                                     "mout_mphy_pll_user", };
 221 PNAME(mout_aclk_mfc_400_b_p)    = { "mout_aclk_mfc_400_a",
 222                                     "mout_bus_pll_user", };
 223 PNAME(mout_aclk_mfc_400_a_p)    = { "mout_mfc_pll_user", "mout_isp_pll", };
 224
 225 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
 226                                     "mout_mphy_pll_user", };
 227 PNAME(mout_aclk_mscl_b_p)       = { "mout_aclk_mscl_400_a",
 228                                     "mout_mphy_pll_user", };
 229 PNAME(mout_aclk_g2d_400_b_p)    = { "mout_aclk_g2d_400_a",
 230                                     "mout_mphy_pll_user", };
 231
 232 PNAME(mout_sclk_jpeg_c_p)       = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
 233 PNAME(mout_sclk_jpeg_b_p)       = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
 234
 235 PNAME(mout_sclk_mmc2_b_p)       = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
 236 PNAME(mout_sclk_mmc1_b_p)       = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
 237 PNAME(mout_sclk_mmc0_d_p)       = { "mout_sclk_mmc0_c", "mout_isp_pll", };
 238 PNAME(mout_sclk_mmc0_c_p)       = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
 239 PNAME(mout_sclk_mmc0_b_p)       = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
 240
 241 PNAME(mout_sclk_spdif_p)        = { "sclk_audio0", "sclk_audio1",
 242                                     "oscclk", "ioclk_spdif_extclk", };
 243 PNAME(mout_sclk_audio1_p)       = { "ioclk_audiocdclk1", "oscclk",
 244                                     "mout_aud_pll_user_t",};
 245 PNAME(mout_sclk_audio0_p)       = { "ioclk_audiocdclk0", "oscclk",
 246                                     "mout_aud_pll_user_t",};
 247
 248 PNAME(mout_sclk_hdmi_spdif_p)   = { "sclk_audio1", "ioclk_spdif_extclk", };
 249
 250 static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
 251         FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
 252 };
 253
 254 static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
 255         /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
 256         FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
 257         FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
 258         /* Xi2s1SDI input clock for SPDIF */
 259         FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
 260         /* XspiCLK[4:0] input clock for SPI */
 261         FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
 262         FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
 263         FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
 264         FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
 265         FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
 266         /* Xi2s1SCLK input clock for I2S1_BCLK */
 267         FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
 268 };
 269
 270 static struct samsung_mux_clock top_mux_clks[] __initdata = {
 271         /* MUX_SEL_TOP0 */
 272         MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
 273                         4, 1),
 274         MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
 275                         0, 1),
 276
 277         /* MUX_SEL_TOP1 */
 278         MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
 279                         mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
 280         MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
 281                         MUX_SEL_TOP1, 8, 1),
 282         MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
 283                         MUX_SEL_TOP1, 4, 1),
 284         MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
 285                         MUX_SEL_TOP1, 0, 1),
 286
 287         /* MUX_SEL_TOP2 */
 288         MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
 289                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
 290         MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
 291                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
 292         MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
 293                         mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
 294         MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
 295                         mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
 296         MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
 297                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
 298         MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
 299                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
 300
 301         /* MUX_SEL_TOP3 */
 302         MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
 303                         mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
 304         MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
 305                         mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
 306         MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
 307                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
 308         MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
 309                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
 310         MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
 311                         mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
 312         MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
 313                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
 314
 315         /* MUX_SEL_TOP4 */
 316         MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
 317                         mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
 318         MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
 319                         mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
 320         MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
 321                         mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
 322
 323         /* MUX_SEL_TOP_MSCL */
 324         MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
 325                         MUX_SEL_TOP_MSCL, 8, 1),
 326         MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
 327                         MUX_SEL_TOP_MSCL, 4, 1),
 328         MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
 329                         MUX_SEL_TOP_MSCL, 0, 1),
 330
 331         /* MUX_SEL_TOP_CAM1 */
 332         MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
 333                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
 334         MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
 335                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
 336         MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
 337                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
 338         MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
 339                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
 340         MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
 341                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
 342         MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
 343                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
 344
 345         /* MUX_SEL_TOP_FSYS0 */
 346         MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
 347                         MUX_SEL_TOP_FSYS0, 28, 1),
 348         MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
 349                         MUX_SEL_TOP_FSYS0, 24, 1),
 350         MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
 351                         MUX_SEL_TOP_FSYS0, 20, 1),
 352         MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
 353                         MUX_SEL_TOP_FSYS0, 16, 1),
 354         MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
 355                         MUX_SEL_TOP_FSYS0, 12, 1),
 356         MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
 357                         MUX_SEL_TOP_FSYS0, 8, 1),
 358         MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
 359                         MUX_SEL_TOP_FSYS0, 4, 1),
 360         MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
 361                         MUX_SEL_TOP_FSYS0, 0, 1),
 362
 363         /* MUX_SEL_TOP_FSYS1 */
 364         MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
 365                         MUX_SEL_TOP_FSYS1, 12, 1),
 366         MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
 367                         mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
 368         MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
 369                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
 370         MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
 371                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
 372
 373         /* MUX_SEL_TOP_PERIC0 */
 374         MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
 375                         MUX_SEL_TOP_PERIC0, 28, 1),
 376         MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
 377                         MUX_SEL_TOP_PERIC0, 24, 1),
 378         MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
 379                         MUX_SEL_TOP_PERIC0, 20, 1),
 380         MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
 381                         MUX_SEL_TOP_PERIC0, 16, 1),
 382         MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
 383                         MUX_SEL_TOP_PERIC0, 12, 1),
 384         MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
 385                         MUX_SEL_TOP_PERIC0, 8, 1),
 386         MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
 387                         MUX_SEL_TOP_PERIC0, 4, 1),
 388         MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
 389                         MUX_SEL_TOP_PERIC0, 0, 1),
 390
 391         /* MUX_SEL_TOP_PERIC1 */
 392         MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
 393                         MUX_SEL_TOP_PERIC1, 16, 1),
 394         MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
 395                         MUX_SEL_TOP_PERIC1, 12, 2),
 396         MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
 397                         MUX_SEL_TOP_PERIC1, 4, 2),
 398         MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
 399                         MUX_SEL_TOP_PERIC1, 0, 2),
 400
 401         /* MUX_SEL_TOP_DISP */
 402         MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
 403                         mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
 404 };
 405
 406 static struct samsung_div_clock top_div_clks[] __initdata = {
 407         /* DIV_TOP0 */
 408         DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
 409                         "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
 410         DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
 411                         "mout_aclk_isp_400", DIV_TOP0, 0, 4),
 412
 413         /* DIV_TOP1 */
 414         DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
 415                         DIV_TOP1, 28, 3),
 416         DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
 417                         DIV_TOP1, 24, 3),
 418         DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
 419                         DIV_TOP1, 20, 3),
 420         DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
 421                         DIV_TOP1, 12, 3),
 422         DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
 423                         DIV_TOP1, 8, 3),
 424         DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
 425                         DIV_TOP1, 0, 3),
 426
 427         /* DIV_TOP2 */
 428         DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
 429                         DIV_TOP2, 4, 3),
 430         DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
 431                         DIV_TOP2, 0, 3),
 432
 433         /* DIV_TOP3 */
 434         DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
 435                         "mout_bus_pll_user", DIV_TOP3, 24, 3),
 436         DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
 437                         "mout_bus_pll_user", DIV_TOP3, 20, 3),
 438         DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
 439                         "mout_bus_pll_user", DIV_TOP3, 16, 3),
 440         DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
 441                         "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
 442         DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
 443                         "mout_bus_pll_user", DIV_TOP3, 8, 3),
 444         DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
 445                         "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
 446         DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
 447                         "mout_bus_pll_user", DIV_TOP3, 0, 3),
 448
 449         /* DIV_TOP4 */
 450         DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
 451                         DIV_TOP4, 8, 3),
 452         DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
 453                         DIV_TOP4, 4, 3),
 454         DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
 455                         DIV_TOP4, 0, 3),
 456
 457         /* DIV_TOP_MSCL */
 458         DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
 459                         DIV_TOP_MSCL, 0, 4),
 460
 461         /* DIV_TOP_FSYS0 */
 462         DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
 463                         DIV_TOP_FSYS0, 16, 8),
 464         DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
 465                         DIV_TOP_FSYS0, 12, 4),
 466         DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
 467                         DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
 468         DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
 469                         DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
 470
 471         /* DIV_TOP_FSYS1 */
 472         DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
 473                         DIV_TOP_FSYS1, 4, 8),
 474         DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
 475                         DIV_TOP_FSYS1, 0, 4),
 476
 477         /* DIV_TOP_FSYS2 */
 478         DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
 479                         DIV_TOP_FSYS2, 12, 3),
 480         DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
 481                         "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
 482         DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
 483                         "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
 484         DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
 485                         DIV_TOP_FSYS2, 0, 4),
 486
 487         /* DIV_TOP_PERIC0 */
 488         DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
 489                         DIV_TOP_PERIC0, 16, 8),
 490         DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
 491                         DIV_TOP_PERIC0, 12, 4),
 492         DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
 493                         DIV_TOP_PERIC0, 4, 8),
 494         DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
 495                         DIV_TOP_PERIC0, 0, 4),
 496
 497         /* DIV_TOP_PERIC1 */
 498         DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
 499                         DIV_TOP_PERIC1, 4, 8),
 500         DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
 501                         DIV_TOP_PERIC1, 0, 4),
 502
 503         /* DIV_TOP_PERIC2 */
 504         DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
 505                         DIV_TOP_PERIC2, 8, 4),
 506         DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
 507                         DIV_TOP_PERIC2, 4, 4),
 508         DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
 509                         DIV_TOP_PERIC2, 0, 4),
 510
 511         /* DIV_TOP_PERIC3 */
 512         DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
 513                         DIV_TOP_PERIC3, 16, 6),
 514         DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
 515                         DIV_TOP_PERIC3, 8, 8),
 516         DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
 517                         DIV_TOP_PERIC3, 4, 4),
 518         DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
 519                         DIV_TOP_PERIC3, 0, 4),
 520
 521         /* DIV_TOP_PERIC4 */
 522         DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
 523                         DIV_TOP_PERIC4, 16, 8),
 524         DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
 525                         DIV_TOP_PERIC4, 12, 4),
 526         DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
 527                         DIV_TOP_PERIC4, 4, 8),
 528         DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
 529                         DIV_TOP_PERIC4, 0, 4),
 530 };
 531
 532 static struct samsung_gate_clock top_gate_clks[] __initdata = {
 533         /* ENABLE_ACLK_TOP */
 534         GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
 535                         ENABLE_ACLK_TOP, 30, 0, 0),
 536         GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
 537                         "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
 538                         29, CLK_IGNORE_UNUSED, 0),
 539         GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
 540                         ENABLE_ACLK_TOP, 26,
 541                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 542         GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
 543                         ENABLE_ACLK_TOP, 25,
 544                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 545         GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
 546                         ENABLE_ACLK_TOP, 24,
 547                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 548         GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
 549                         ENABLE_ACLK_TOP, 23,
 550                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 551         GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
 552                         ENABLE_ACLK_TOP, 22,
 553                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 554         GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
 555                         ENABLE_ACLK_TOP, 21,
 556                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 557         GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
 558                         ENABLE_ACLK_TOP, 19,
 559                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 560         GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
 561                         ENABLE_ACLK_TOP, 18,
 562                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 563         GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
 564                         ENABLE_ACLK_TOP, 15,
 565                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 566         GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
 567                         ENABLE_ACLK_TOP, 14,
 568                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 569         GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
 570                         ENABLE_ACLK_TOP, 7,
 571                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 572         GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
 573                         ENABLE_ACLK_TOP, 6,
 574                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 575         GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
 576                         ENABLE_ACLK_TOP, 5,
 577                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 578         GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
 579                         ENABLE_ACLK_TOP, 3,
 580                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 581         GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
 582                         ENABLE_ACLK_TOP, 2,
 583                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 584         GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
 585                         ENABLE_ACLK_TOP, 0,
 586                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 587
 588         /* ENABLE_SCLK_TOP_MSCL */
 589         GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
 590                         ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
 591
 592         /* ENABLE_SCLK_TOP_FSYS */
 593         GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
 594                         ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
 595         GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
 596                         ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
 597         GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
 598                         ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
 599         GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
 600                         ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
 601         GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
 602                         "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
 603                         3, CLK_SET_RATE_PARENT, 0),
 604         GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
 605                         "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
 606                         1, CLK_SET_RATE_PARENT, 0),
 607         GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
 608                         "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
 609                         0, CLK_SET_RATE_PARENT, 0),
 610
 611         /* ENABLE_SCLK_TOP_PERIC */
 612         GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
 613                         ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
 614         GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
 615                         ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 616         GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
 617                         ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 618         GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
 619                         ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 620         GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
 621                         ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 622         GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
 623                         ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
 624         GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
 625                         ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
 626         GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
 627                         ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
 628         GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
 629                         ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 630         GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
 631                         ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 632         GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
 633                         ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 634
 635         /* MUX_ENABLE_TOP_PERIC1 */
 636         GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
 637                         MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
 638         GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
 639                         MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
 640         GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
 641                         MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
 642 };
 643
 644 /*
 645  * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
 646  * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
 647  */
 648 static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
 649         PLL_35XX_RATE(2500000000U, 625, 6,  0),
 650         PLL_35XX_RATE(2400000000U, 500, 5,  0),
 651         PLL_35XX_RATE(2300000000U, 575, 6,  0),
 652         PLL_35XX_RATE(2200000000U, 550, 6,  0),
 653         PLL_35XX_RATE(2100000000U, 350, 4,  0),
 654         PLL_35XX_RATE(2000000000U, 500, 6,  0),
 655         PLL_35XX_RATE(1900000000U, 475, 6,  0),
 656         PLL_35XX_RATE(1800000000U, 375, 5,  0),
 657         PLL_35XX_RATE(1700000000U, 425, 6,  0),
 658         PLL_35XX_RATE(1600000000U, 400, 6,  0),
 659         PLL_35XX_RATE(1500000000U, 250, 4,  0),
 660         PLL_35XX_RATE(1400000000U, 350, 6,  0),
 661         PLL_35XX_RATE(1332000000U, 222, 4,  0),
 662         PLL_35XX_RATE(1300000000U, 325, 6,  0),
 663         PLL_35XX_RATE(1200000000U, 500, 5,  1),
 664         PLL_35XX_RATE(1100000000U, 550, 6,  1),
 665         PLL_35XX_RATE(1086000000U, 362, 4,  1),
 666         PLL_35XX_RATE(1066000000U, 533, 6,  1),
 667         PLL_35XX_RATE(1000000000U, 500, 6,  1),
 668         PLL_35XX_RATE(933000000U,  311, 4,  1),
 669         PLL_35XX_RATE(921000000U,  307, 4,  1),
 670         PLL_35XX_RATE(900000000U,  375, 5,  1),
 671         PLL_35XX_RATE(825000000U,  275, 4,  1),
 672         PLL_35XX_RATE(800000000U,  400, 6,  1),
 673         PLL_35XX_RATE(733000000U,  733, 12, 1),
 674         PLL_35XX_RATE(700000000U,  360, 6,  1),
 675         PLL_35XX_RATE(667000000U,  222, 4,  1),
 676         PLL_35XX_RATE(633000000U,  211, 4,  1),
 677         PLL_35XX_RATE(600000000U,  500, 5,  2),
 678         PLL_35XX_RATE(552000000U,  460, 5,  2),
 679         PLL_35XX_RATE(550000000U,  550, 6,  2),
 680         PLL_35XX_RATE(543000000U,  362, 4,  2),
 681         PLL_35XX_RATE(533000000U,  533, 6,  2),
 682         PLL_35XX_RATE(500000000U,  500, 6,  2),
 683         PLL_35XX_RATE(444000000U,  370, 5,  2),
 684         PLL_35XX_RATE(420000000U,  350, 5,  2),
 685         PLL_35XX_RATE(400000000U,  400, 6,  2),
 686         PLL_35XX_RATE(350000000U,  360, 6,  2),
 687         PLL_35XX_RATE(333000000U,  222, 4,  2),
 688         PLL_35XX_RATE(300000000U,  500, 5,  3),
 689         PLL_35XX_RATE(266000000U,  532, 6,  3),
 690         PLL_35XX_RATE(200000000U,  400, 6,  3),
 691         PLL_35XX_RATE(166000000U,  332, 6,  3),
 692         PLL_35XX_RATE(160000000U,  320, 6,  3),
 693         PLL_35XX_RATE(133000000U,  552, 6,  4),
 694         PLL_35XX_RATE(100000000U,  400, 6,  4),
 695         { /* sentinel */ }
 696 };
 697
 698 /* AUD_PLL */
 699 static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
 700         PLL_36XX_RATE(400000000U, 200, 3, 2,      0),
 701         PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
 702         PLL_36XX_RATE(384000000U, 128, 2, 2,      0),
 703         PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
 704         PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
 705         PLL_36XX_RATE(338688000U, 113, 2, 2,  -6816),
 706         PLL_36XX_RATE(294912000U,  98, 1, 3,  19923),
 707         PLL_36XX_RATE(288000000U,  96, 1, 3,      0),
 708         PLL_36XX_RATE(252000000U,  84, 1, 3,      0),
 709         { /* sentinel */ }
 710 };
 711
 712 static struct samsung_pll_clock top_pll_clks[] __initdata = {
 713         PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
 714                 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
 715         PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
 716                 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
 717 };
 718
 719 static struct samsung_cmu_info top_cmu_info __initdata = {
 720         .pll_clks               = top_pll_clks,
 721         .nr_pll_clks            = ARRAY_SIZE(top_pll_clks),
 722         .mux_clks               = top_mux_clks,
 723         .nr_mux_clks            = ARRAY_SIZE(top_mux_clks),
 724         .div_clks               = top_div_clks,
 725         .nr_div_clks            = ARRAY_SIZE(top_div_clks),
 726         .gate_clks              = top_gate_clks,
 727         .nr_gate_clks           = ARRAY_SIZE(top_gate_clks),
 728         .fixed_clks             = top_fixed_clks,
 729         .nr_fixed_clks          = ARRAY_SIZE(top_fixed_clks),
 730         .fixed_factor_clks      = top_fixed_factor_clks,
 731         .nr_fixed_factor_clks   = ARRAY_SIZE(top_fixed_factor_clks),
 732         .nr_clk_ids             = TOP_NR_CLK,
 733         .clk_regs               = top_clk_regs,
 734         .nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
 735 };
 736
 737 static void __init exynos5433_cmu_top_init(struct device_node *np)
 738 {
 739         samsung_cmu_register_one(np, &top_cmu_info);
 740 }
 741 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
 742                 exynos5433_cmu_top_init);
 743
 744 /*
 745  * Register offset definitions for CMU_CPIF
 746  */
 747 #define MPHY_PLL_LOCK           0x0000
 748 #define MPHY_PLL_CON0           0x0100
 749 #define MPHY_PLL_CON1           0x0104
 750 #define MPHY_PLL_FREQ_DET       0x010c
 751 #define MUX_SEL_CPIF0           0x0200
 752 #define DIV_CPIF                0x0600
 753 #define ENABLE_SCLK_CPIF        0x0a00
 754
 755 static unsigned long cpif_clk_regs[] __initdata = {
 756         MPHY_PLL_LOCK,
 757         MPHY_PLL_CON0,
 758         MPHY_PLL_CON1,
 759         MPHY_PLL_FREQ_DET,
 760         MUX_SEL_CPIF0,
 761         ENABLE_SCLK_CPIF,
 762 };
 763
 764 /* list of all parent clock list */
 765 PNAME(mout_mphy_pll_p)          = { "oscclk", "fout_mphy_pll", };
 766
 767 static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
 768         PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
 769                 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
 770 };
 771
 772 static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
 773         /* MUX_SEL_CPIF0 */
 774         MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
 775                         0, 1),
 776 };
 777
 778 static struct samsung_div_clock cpif_div_clks[] __initdata = {
 779         /* DIV_CPIF */
 780         DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
 781                         0, 6),
 782 };
 783
 784 static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
 785         /* ENABLE_SCLK_CPIF */
 786         GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
 787                         ENABLE_SCLK_CPIF, 9, 0, 0),
 788         GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
 789                         ENABLE_SCLK_CPIF, 4, 0, 0),
 790 };
 791
 792 static struct samsung_cmu_info cpif_cmu_info __initdata = {
 793         .pll_clks               = cpif_pll_clks,
 794         .nr_pll_clks            = ARRAY_SIZE(cpif_pll_clks),
 795         .mux_clks               = cpif_mux_clks,
 796         .nr_mux_clks            = ARRAY_SIZE(cpif_mux_clks),
 797         .div_clks               = cpif_div_clks,
 798         .nr_div_clks            = ARRAY_SIZE(cpif_div_clks),
 799         .gate_clks              = cpif_gate_clks,
 800         .nr_gate_clks           = ARRAY_SIZE(cpif_gate_clks),
 801         .nr_clk_ids             = CPIF_NR_CLK,
 802         .clk_regs               = cpif_clk_regs,
 803         .nr_clk_regs            = ARRAY_SIZE(cpif_clk_regs),
 804 };
 805
 806 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
 807 {
 808         samsung_cmu_register_one(np, &cpif_cmu_info);
 809 }
 810 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
 811                 exynos5433_cmu_cpif_init);
 812
 813 /*
 814  * Register offset definitions for CMU_MIF
 815  */
 816 #define MEM0_PLL_LOCK                   0x0000
 817 #define MEM1_PLL_LOCK                   0x0004
 818 #define BUS_PLL_LOCK                    0x0008
 819 #define MFC_PLL_LOCK                    0x000c
 820 #define MEM0_PLL_CON0                   0x0100
 821 #define MEM0_PLL_CON1                   0x0104
 822 #define MEM0_PLL_FREQ_DET               0x010c
 823 #define MEM1_PLL_CON0                   0x0110
 824 #define MEM1_PLL_CON1                   0x0114
 825 #define MEM1_PLL_FREQ_DET               0x011c
 826 #define BUS_PLL_CON0                    0x0120
 827 #define BUS_PLL_CON1                    0x0124
 828 #define BUS_PLL_FREQ_DET                0x012c
 829 #define MFC_PLL_CON0                    0x0130
 830 #define MFC_PLL_CON1                    0x0134
 831 #define MFC_PLL_FREQ_DET                0x013c
 832 #define MUX_SEL_MIF0                    0x0200
 833 #define MUX_SEL_MIF1                    0x0204
 834 #define MUX_SEL_MIF2                    0x0208
 835 #define MUX_SEL_MIF3                    0x020c
 836 #define MUX_SEL_MIF4                    0x0210
 837 #define MUX_SEL_MIF5                    0x0214
 838 #define MUX_SEL_MIF6                    0x0218
 839 #define MUX_SEL_MIF7                    0x021c
 840 #define MUX_ENABLE_MIF0                 0x0300
 841 #define MUX_ENABLE_MIF1                 0x0304
 842 #define MUX_ENABLE_MIF2                 0x0308
 843 #define MUX_ENABLE_MIF3                 0x030c
 844 #define MUX_ENABLE_MIF4                 0x0310
 845 #define MUX_ENABLE_MIF5                 0x0314
 846 #define MUX_ENABLE_MIF6                 0x0318
 847 #define MUX_ENABLE_MIF7                 0x031c
 848 #define MUX_STAT_MIF0                   0x0400
 849 #define MUX_STAT_MIF1                   0x0404
 850 #define MUX_STAT_MIF2                   0x0408
 851 #define MUX_STAT_MIF3                   0x040c
 852 #define MUX_STAT_MIF4                   0x0410
 853 #define MUX_STAT_MIF5                   0x0414
 854 #define MUX_STAT_MIF6                   0x0418
 855 #define MUX_STAT_MIF7                   0x041c
 856 #define DIV_MIF1                        0x0604
 857 #define DIV_MIF2                        0x0608
 858 #define DIV_MIF3                        0x060c
 859 #define DIV_MIF4                        0x0610
 860 #define DIV_MIF5                        0x0614
 861 #define DIV_MIF_PLL_FREQ_DET            0x0618
 862 #define DIV_STAT_MIF1                   0x0704
 863 #define DIV_STAT_MIF2                   0x0708
 864 #define DIV_STAT_MIF3                   0x070c
 865 #define DIV_STAT_MIF4                   0x0710
 866 #define DIV_STAT_MIF5                   0x0714
 867 #define DIV_STAT_MIF_PLL_FREQ_DET       0x0718
 868 #define ENABLE_ACLK_MIF0                0x0800
 869 #define ENABLE_ACLK_MIF1                0x0804
 870 #define ENABLE_ACLK_MIF2                0x0808
 871 #define ENABLE_ACLK_MIF3                0x080c
 872 #define ENABLE_PCLK_MIF                 0x0900
 873 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
 874 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
 875 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT    0x090c
 876 #define ENABLE_PCLK_MIF_SECURE_RTC      0x0910
 877 #define ENABLE_SCLK_MIF                 0x0a00
 878 #define ENABLE_IP_MIF0                  0x0b00
 879 #define ENABLE_IP_MIF1                  0x0b04
 880 #define ENABLE_IP_MIF2                  0x0b08
 881 #define ENABLE_IP_MIF3                  0x0b0c
 882 #define ENABLE_IP_MIF_SECURE_DREX0_TZ   0x0b10
 883 #define ENABLE_IP_MIF_SECURE_DREX1_TZ   0x0b14
 884 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT      0x0b18
 885 #define ENABLE_IP_MIF_SECURE_RTC        0x0b1c
 886 #define CLKOUT_CMU_MIF                  0x0c00
 887 #define CLKOUT_CMU_MIF_DIV_STAT         0x0c04
 888 #define DREX_FREQ_CTRL0                 0x1000
 889 #define DREX_FREQ_CTRL1                 0x1004
 890 #define PAUSE                           0x1008
 891 #define DDRPHY_LOCK_CTRL                0x100c
 892
 893 static unsigned long mif_clk_regs[] __initdata = {
 894         MEM0_PLL_LOCK,
 895         MEM1_PLL_LOCK,
 896         BUS_PLL_LOCK,
 897         MFC_PLL_LOCK,
 898         MEM0_PLL_CON0,
 899         MEM0_PLL_CON1,
 900         MEM0_PLL_FREQ_DET,
 901         MEM1_PLL_CON0,
 902         MEM1_PLL_CON1,
 903         MEM1_PLL_FREQ_DET,
 904         BUS_PLL_CON0,
 905         BUS_PLL_CON1,
 906         BUS_PLL_FREQ_DET,
 907         MFC_PLL_CON0,
 908         MFC_PLL_CON1,
 909         MFC_PLL_FREQ_DET,
 910         MUX_SEL_MIF0,
 911         MUX_SEL_MIF1,
 912         MUX_SEL_MIF2,
 913         MUX_SEL_MIF3,
 914         MUX_SEL_MIF4,
 915         MUX_SEL_MIF5,
 916         MUX_SEL_MIF6,
 917         MUX_SEL_MIF7,
 918         MUX_ENABLE_MIF0,
 919         MUX_ENABLE_MIF1,
 920         MUX_ENABLE_MIF2,
 921         MUX_ENABLE_MIF3,
 922         MUX_ENABLE_MIF4,
 923         MUX_ENABLE_MIF5,
 924         MUX_ENABLE_MIF6,
 925         MUX_ENABLE_MIF7,
 926         MUX_STAT_MIF0,
 927         MUX_STAT_MIF1,
 928         MUX_STAT_MIF2,
 929         MUX_STAT_MIF3,
 930         MUX_STAT_MIF4,
 931         MUX_STAT_MIF5,
 932         MUX_STAT_MIF6,
 933         MUX_STAT_MIF7,
 934         DIV_MIF1,
 935         DIV_MIF2,
 936         DIV_MIF3,
 937         DIV_MIF4,
 938         DIV_MIF5,
 939         DIV_MIF_PLL_FREQ_DET,
 940         DIV_STAT_MIF1,
 941         DIV_STAT_MIF2,
 942         DIV_STAT_MIF3,
 943         DIV_STAT_MIF4,
 944         DIV_STAT_MIF5,
 945         DIV_STAT_MIF_PLL_FREQ_DET,
 946         ENABLE_ACLK_MIF0,
 947         ENABLE_ACLK_MIF1,
 948         ENABLE_ACLK_MIF2,
 949         ENABLE_ACLK_MIF3,
 950         ENABLE_PCLK_MIF,
 951         ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
 952         ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
 953         ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
 954         ENABLE_PCLK_MIF_SECURE_RTC,
 955         ENABLE_SCLK_MIF,
 956         ENABLE_IP_MIF0,
 957         ENABLE_IP_MIF1,
 958         ENABLE_IP_MIF2,
 959         ENABLE_IP_MIF3,
 960         ENABLE_IP_MIF_SECURE_DREX0_TZ,
 961         ENABLE_IP_MIF_SECURE_DREX1_TZ,
 962         ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
 963         ENABLE_IP_MIF_SECURE_RTC,
 964         CLKOUT_CMU_MIF,
 965         CLKOUT_CMU_MIF_DIV_STAT,
 966         DREX_FREQ_CTRL0,
 967         DREX_FREQ_CTRL1,
 968         PAUSE,
 969         DDRPHY_LOCK_CTRL,
 970 };
 971
 972 static struct samsung_pll_clock mif_pll_clks[] __initdata = {
 973         PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
 974                 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
 975         PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
 976                 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
 977         PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
 978                 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
 979         PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
 980                 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
 981 };
 982
 983 /* list of all parent clock list */
 984 PNAME(mout_mfc_pll_div2_p)      = { "mout_mfc_pll", "dout_mfc_pll", };
 985 PNAME(mout_bus_pll_div2_p)      = { "mout_bus_pll", "dout_bus_pll", };
 986 PNAME(mout_mem1_pll_div2_p)     = { "mout_mem1_pll", "dout_mem1_pll", };
 987 PNAME(mout_mem0_pll_div2_p)     = { "mout_mem0_pll", "dout_mem0_pll", };
 988 PNAME(mout_mfc_pll_p)           = { "oscclk", "fout_mfc_pll", };
 989 PNAME(mout_bus_pll_p)           = { "oscclk", "fout_bus_pll", };
 990 PNAME(mout_mem1_pll_p)          = { "oscclk", "fout_mem1_pll", };
 991 PNAME(mout_mem0_pll_p)          = { "oscclk", "fout_mem0_pll", };
 992
 993 PNAME(mout_clk2x_phy_c_p)       = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
 994 PNAME(mout_clk2x_phy_b_p)       = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
 995 PNAME(mout_clk2x_phy_a_p)       = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
 996 PNAME(mout_clkm_phy_b_p)        = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
 997
 998 PNAME(mout_aclk_mifnm_200_p)    = { "mout_mem0_pll_div2", "div_mif_pre", };
 999 PNAME(mout_aclk_mifnm_400_p)    = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1000
1001 PNAME(mout_aclk_disp_333_b_p)   = { "mout_aclk_disp_333_a",
1002                                     "mout_bus_pll_div2", };
1003 PNAME(mout_aclk_disp_333_a_p)   = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1004
1005 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1006                                     "sclk_mphy_pll", };
1007 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1008                                     "mout_mfc_pll_div2", };
1009 PNAME(mout_sclk_decon_p)        = { "oscclk", "mout_bus_pll_div2", };
1010 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1011                                     "sclk_mphy_pll", };
1012 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1013                                     "mout_mfc_pll_div2", };
1014
1015 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1016                                        "sclk_mphy_pll", };
1017 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1018                                        "mout_mfc_pll_div2", };
1019 PNAME(mout_sclk_dsd_c_p)        = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1020 PNAME(mout_sclk_dsd_b_p)        = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1021 PNAME(mout_sclk_dsd_a_p)        = { "oscclk", "mout_mfc_pll_div2", };
1022
1023 PNAME(mout_sclk_dsim0_c_p)      = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1024 PNAME(mout_sclk_dsim0_b_p)      = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1025
1026 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1027                                        "sclk_mphy_pll", };
1028 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1029                                        "mout_mfc_pll_div2", };
1030 PNAME(mout_sclk_dsim1_c_p)      = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1031 PNAME(mout_sclk_dsim1_b_p)      = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1032
1033 static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1034         /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1035         FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1036         FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1037         FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1038         FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1039 };
1040
1041 static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1042         /* MUX_SEL_MIF0 */
1043         MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1044                         MUX_SEL_MIF0, 28, 1),
1045         MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1046                         MUX_SEL_MIF0, 24, 1),
1047         MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1048                         MUX_SEL_MIF0, 20, 1),
1049         MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1050                         MUX_SEL_MIF0, 16, 1),
1051         MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1052                         12, 1),
1053         MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1054                         8, 1),
1055         MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1056                         4, 1),
1057         MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1058                         0, 1),
1059
1060         /* MUX_SEL_MIF1 */
1061         MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1062                         MUX_SEL_MIF1, 24, 1),
1063         MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1064                         MUX_SEL_MIF1, 20, 1),
1065         MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1066                         MUX_SEL_MIF1, 16, 1),
1067         MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1068                         MUX_SEL_MIF1, 12, 1),
1069         MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1070                         MUX_SEL_MIF1, 8, 1),
1071         MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1072                         MUX_SEL_MIF1, 4, 1),
1073
1074         /* MUX_SEL_MIF2 */
1075         MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1076                         mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1077         MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1078                         mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1079
1080         /* MUX_SEL_MIF3 */
1081         MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1082                         mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1083         MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1084                         mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1085
1086         /* MUX_SEL_MIF4 */
1087         MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1088                         mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1089         MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1090                         mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1091         MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1092                         mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1093         MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1094                         mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1095         MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1096                         mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1097         MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1098                         mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1099
1100         /* MUX_SEL_MIF5 */
1101         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1102                         mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1103         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1104                         mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1105         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1106                         mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1107         MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1108                         MUX_SEL_MIF5, 8, 1),
1109         MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1110                         MUX_SEL_MIF5, 4, 1),
1111         MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1112                         MUX_SEL_MIF5, 0, 1),
1113
1114         /* MUX_SEL_MIF6 */
1115         MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1116                         MUX_SEL_MIF6, 8, 1),
1117         MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1118                         MUX_SEL_MIF6, 4, 1),
1119         MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1120                         MUX_SEL_MIF6, 0, 1),
1121
1122         /* MUX_SEL_MIF7 */
1123         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1124                         mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1125         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1126                         mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1127         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1128                         mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1129         MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1130                         MUX_SEL_MIF7, 8, 1),
1131         MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1132                         MUX_SEL_MIF7, 4, 1),
1133         MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1134                         MUX_SEL_MIF7, 0, 1),
1135 };
1136
1137 static struct samsung_div_clock mif_div_clks[] __initdata = {
1138         /* DIV_MIF1 */
1139         DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1140                         DIV_MIF1, 16, 2),
1141         DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1142                         12, 2),
1143         DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1144                         8, 2),
1145         DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1146                         4, 4),
1147
1148         /* DIV_MIF2 */
1149         DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1150                         DIV_MIF2, 20, 3),
1151         DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1152                         DIV_MIF2, 16, 4),
1153         DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1154                         DIV_MIF2, 12, 4),
1155         DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1156                         "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1157         DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1158                         DIV_MIF2, 4, 2),
1159         DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1160                         DIV_MIF2, 0, 3),
1161
1162         /* DIV_MIF3 */
1163         DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1164                         DIV_MIF3, 16, 4),
1165         DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1166                         DIV_MIF3, 4, 3),
1167         DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1168                         DIV_MIF3, 0, 3),
1169
1170         /* DIV_MIF4 */
1171         DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1172                         DIV_MIF4, 24, 4),
1173         DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1174                         "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1175         DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1176                         DIV_MIF4, 16, 4),
1177         DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1178                         DIV_MIF4, 12, 4),
1179         DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1180                         "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1181         DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1182                         "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1183         DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1184                         "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1185
1186         /* DIV_MIF5 */
1187         DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1188                         0, 3),
1189 };
1190
1191 static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1192         /* ENABLE_ACLK_MIF0 */
1193         GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1194                         19, CLK_IGNORE_UNUSED, 0),
1195         GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1196                         18, CLK_IGNORE_UNUSED, 0),
1197         GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1198                         17, CLK_IGNORE_UNUSED, 0),
1199         GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1200                         16, CLK_IGNORE_UNUSED, 0),
1201         GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1202                         15, CLK_IGNORE_UNUSED, 0),
1203         GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1204                         14, CLK_IGNORE_UNUSED, 0),
1205         GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1206                         ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1207         GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1208                         ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1209         GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1210                         ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1211         GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1212                         ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1213         GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1214                         ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1215         GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1216                         ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1217         GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1218                         ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1219         GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1220                         ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1221         GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1222                         ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1223         GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1224                         ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1225         GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1226                         ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1227         GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1228                         ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1229         GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1230                         ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1231         GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1232                         ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1233
1234         /* ENABLE_ACLK_MIF1 */
1235         GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1236                         "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1237                         CLK_IGNORE_UNUSED, 0),
1238         GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1239                         "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1240                         27, CLK_IGNORE_UNUSED, 0),
1241         GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1242                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1243                         26, CLK_IGNORE_UNUSED, 0),
1244         GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1245                         "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1246                         25, CLK_IGNORE_UNUSED, 0),
1247         GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1248                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1249                         24, CLK_IGNORE_UNUSED, 0),
1250         GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1251                         "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1252                         23, CLK_IGNORE_UNUSED, 0),
1253         GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1254                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1255                         22, CLK_IGNORE_UNUSED, 0),
1256         GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1257                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1258                         21, CLK_IGNORE_UNUSED, 0),
1259         GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1260                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1261                         20, CLK_IGNORE_UNUSED, 0),
1262         GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1263                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1264                         19, CLK_IGNORE_UNUSED, 0),
1265         GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1266                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1267                         18, CLK_IGNORE_UNUSED, 0),
1268         GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1269                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1270                         17, CLK_IGNORE_UNUSED, 0),
1271         GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1272                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1273                         16, CLK_IGNORE_UNUSED, 0),
1274         GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1275                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1276                         15, CLK_IGNORE_UNUSED, 0),
1277         GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1278                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1279                         14, CLK_IGNORE_UNUSED, 0),
1280         GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1281                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1282                         13, CLK_IGNORE_UNUSED, 0),
1283         GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1284                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1285                         12, CLK_IGNORE_UNUSED, 0),
1286         GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1287                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1288                         11, CLK_IGNORE_UNUSED, 0),
1289         GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1290                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1291                         10, CLK_IGNORE_UNUSED, 0),
1292         GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1293                         ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1294         GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1295                         ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1296         GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1297                         ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1298         GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1299                         ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1300         GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1301                         ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1302         GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1303                         ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1304         GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1305                         ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1306         GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1307                         ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1308         GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1309                         ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1310         GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1311                         0, CLK_IGNORE_UNUSED, 0),
1312
1313         /* ENABLE_ACLK_MIF2 */
1314         GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1315                         ENABLE_ACLK_MIF2, 20, 0, 0),
1316         GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1317                         ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1318         GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1319                         ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1320         GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1321                         ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1322         GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1323                         ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1324         GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1325                         ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1326         GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1327                         ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1328         GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1329                         "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1330                         CLK_IGNORE_UNUSED, 0),
1331         GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1332                         "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1333                         5, CLK_IGNORE_UNUSED, 0),
1334         GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1335                         ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1336         GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1337                         "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1338                         3, CLK_IGNORE_UNUSED, 0),
1339         GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1340                         "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1341
1342         /* ENABLE_ACLK_MIF3 */
1343         GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1344                         ENABLE_ACLK_MIF3, 4,
1345                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1346         GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1347                         ENABLE_ACLK_MIF3, 1,
1348                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1349         GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1350                         ENABLE_ACLK_MIF3, 0,
1351                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1352
1353         /* ENABLE_PCLK_MIF */
1354         GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1355                         ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1356         GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1357                         ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1358         GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1359                         ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1360         GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1361                         ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1362         GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1363                         ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1364         GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1365                         ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1366         GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1367                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1368                         CLK_IGNORE_UNUSED, 0),
1369         GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1370                         ENABLE_PCLK_MIF, 19, 0, 0),
1371         GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1372                         ENABLE_PCLK_MIF, 18, 0, 0),
1373         GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1374                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1375         GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1376                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1377         GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1378                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1379         GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1380                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1381         GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1382                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1383         GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1384                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1385         GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1386                         ENABLE_PCLK_MIF, 11, 0, 0),
1387         GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1388                         ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1389         GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1390                         ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1391         GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1392                         ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1393         GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1394                         ENABLE_PCLK_MIF, 7, 0, 0),
1395         GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1396                         ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1397         GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1398                         ENABLE_PCLK_MIF, 5, 0, 0),
1399         GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1400                         ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1401         GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1402                         ENABLE_PCLK_MIF, 2, 0, 0),
1403         GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1404                         ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1405
1406         /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1407         GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1408                         ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1409
1410         /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1411         GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1412                         ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1413
1414         /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1415         GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1416                         ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1417
1418         /* ENABLE_PCLK_MIF_SECURE_RTC */
1419         GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1420                         ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1421
1422         /* ENABLE_SCLK_MIF */
1423         GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1424                         ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1425         GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1426                         "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1427                         14, CLK_IGNORE_UNUSED, 0),
1428         GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1429                         ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1430         GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1431                         ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1432         GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1433                         "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1434                         7, CLK_IGNORE_UNUSED, 0),
1435         GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1436                         "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1437                         6, CLK_IGNORE_UNUSED, 0),
1438         GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1439                         "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1440                         5, CLK_IGNORE_UNUSED, 0),
1441         GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1442                         ENABLE_SCLK_MIF, 4,
1443                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1444         GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1445                         ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1446         GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1447                         ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1448         GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1449                         ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1450         GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1451                         ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1452
1453         /* ENABLE_SCLK_TOP_DISP */
1454         GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
1455                         "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
1456                         CLK_IGNORE_UNUSED, 0),
1457 };
1458
1459 static struct samsung_cmu_info mif_cmu_info __initdata = {
1460         .pll_clks               = mif_pll_clks,
1461         .nr_pll_clks            = ARRAY_SIZE(mif_pll_clks),
1462         .mux_clks               = mif_mux_clks,
1463         .nr_mux_clks            = ARRAY_SIZE(mif_mux_clks),
1464         .div_clks               = mif_div_clks,
1465         .nr_div_clks            = ARRAY_SIZE(mif_div_clks),
1466         .gate_clks              = mif_gate_clks,
1467         .nr_gate_clks           = ARRAY_SIZE(mif_gate_clks),
1468         .fixed_factor_clks      = mif_fixed_factor_clks,
1469         .nr_fixed_factor_clks   = ARRAY_SIZE(mif_fixed_factor_clks),
1470         .nr_clk_ids             = MIF_NR_CLK,
1471         .clk_regs               = mif_clk_regs,
1472         .nr_clk_regs            = ARRAY_SIZE(mif_clk_regs),
1473 };
1474
1475 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1476 {
1477         samsung_cmu_register_one(np, &mif_cmu_info);
1478 }
1479 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1480                 exynos5433_cmu_mif_init);
1481
1482 /*
1483  * Register offset definitions for CMU_PERIC
1484  */
1485 #define DIV_PERIC                       0x0600
1486 #define DIV_STAT_PERIC                  0x0700
1487 #define ENABLE_ACLK_PERIC               0x0800
1488 #define ENABLE_PCLK_PERIC0              0x0900
1489 #define ENABLE_PCLK_PERIC1              0x0904
1490 #define ENABLE_SCLK_PERIC               0x0A00
1491 #define ENABLE_IP_PERIC0                0x0B00
1492 #define ENABLE_IP_PERIC1                0x0B04
1493 #define ENABLE_IP_PERIC2                0x0B08
1494
1495 static unsigned long peric_clk_regs[] __initdata = {
1496         DIV_PERIC,
1497         DIV_STAT_PERIC,
1498         ENABLE_ACLK_PERIC,
1499         ENABLE_PCLK_PERIC0,
1500         ENABLE_PCLK_PERIC1,
1501         ENABLE_SCLK_PERIC,
1502         ENABLE_IP_PERIC0,
1503         ENABLE_IP_PERIC1,
1504         ENABLE_IP_PERIC2,
1505 };
1506
1507 static struct samsung_div_clock peric_div_clks[] __initdata = {
1508         /* DIV_PERIC */
1509         DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1510         DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1511 };
1512
1513 static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1514         /* ENABLE_ACLK_PERIC */
1515         GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1516                         ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1517         GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1518                         ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1519         GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1520                         ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1521         GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1522                         ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1523
1524         /* ENABLE_PCLK_PERIC0 */
1525         GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1526                         31, CLK_SET_RATE_PARENT, 0),
1527         GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1528                         ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1529         GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1530                         ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1531         GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1532                         28, CLK_SET_RATE_PARENT, 0),
1533         GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1534                         26, CLK_SET_RATE_PARENT, 0),
1535         GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1536                         25, CLK_SET_RATE_PARENT, 0),
1537         GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1538                         24, CLK_SET_RATE_PARENT, 0),
1539         GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1540                         23, CLK_SET_RATE_PARENT, 0),
1541         GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1542                         22, CLK_SET_RATE_PARENT, 0),
1543         GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1544                         21, CLK_SET_RATE_PARENT, 0),
1545         GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1546                         20, CLK_SET_RATE_PARENT, 0),
1547         GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1548                         ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1549         GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1550                         ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1551         GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1552                         ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1553         GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1554                         ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1555         GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1556                         ENABLE_PCLK_PERIC0, 15,
1557                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1558         GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1559                         14, CLK_SET_RATE_PARENT, 0),
1560         GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1561                         13, CLK_SET_RATE_PARENT, 0),
1562         GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1563                         12, CLK_SET_RATE_PARENT, 0),
1564         GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1565                         ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1566         GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1567                         ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1568         GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1569                         ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1570         GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1571                         ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1572         GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1573                         7, CLK_SET_RATE_PARENT, 0),
1574         GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1575                         6, CLK_SET_RATE_PARENT, 0),
1576         GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1577                         5, CLK_SET_RATE_PARENT, 0),
1578         GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1579                         4, CLK_SET_RATE_PARENT, 0),
1580         GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1581                         3, CLK_SET_RATE_PARENT, 0),
1582         GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1583                         2, CLK_SET_RATE_PARENT, 0),
1584         GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1585                         1, CLK_SET_RATE_PARENT, 0),
1586         GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1587                         0, CLK_SET_RATE_PARENT, 0),
1588
1589         /* ENABLE_PCLK_PERIC1 */
1590         GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1591                         9, CLK_SET_RATE_PARENT, 0),
1592         GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1593                         8, CLK_SET_RATE_PARENT, 0),
1594         GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1595                         ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1596         GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1597                         ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1598         GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1599                         ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1600         GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1601                         ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1602         GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1603                         ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1604         GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1605                         ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1606         GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1607                         ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1608         GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1609                         ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1610
1611         /* ENABLE_SCLK_PERIC */
1612         GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1613                         ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1614         GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1615                         ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1616         GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1617                         19, CLK_SET_RATE_PARENT, 0),
1618         GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1619                         18, CLK_SET_RATE_PARENT, 0),
1620         GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1621                         17, 0, 0),
1622         GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1623                         16, 0, 0),
1624         GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1625         GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1626                         ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1627         GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1628                         ENABLE_SCLK_PERIC, 12,
1629                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1630         GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1631                         ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1632         GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1633                         "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1634                         CLK_SET_RATE_PARENT, 0),
1635         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1636                         ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1637         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1638                         ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1639         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1640                         ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1641         GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1642                         5, CLK_SET_RATE_PARENT, 0),
1643         GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1644                         4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1645         GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1646                         3, CLK_SET_RATE_PARENT, 0),
1647         GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1648                         ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1649         GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1650                         ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1651         GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1652                         ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1653 };
1654
1655 static struct samsung_cmu_info peric_cmu_info __initdata = {
1656         .div_clks               = peric_div_clks,
1657         .nr_div_clks            = ARRAY_SIZE(peric_div_clks),
1658         .gate_clks              = peric_gate_clks,
1659         .nr_gate_clks           = ARRAY_SIZE(peric_gate_clks),
1660         .nr_clk_ids             = PERIC_NR_CLK,
1661         .clk_regs               = peric_clk_regs,
1662         .nr_clk_regs            = ARRAY_SIZE(peric_clk_regs),
1663 };
1664
1665 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1666 {
1667         samsung_cmu_register_one(np, &peric_cmu_info);
1668 }
1669
1670 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1671                 exynos5433_cmu_peric_init);
1672
1673 /*
1674  * Register offset definitions for CMU_PERIS
1675  */
1676 #define ENABLE_ACLK_PERIS                               0x0800
1677 #define ENABLE_PCLK_PERIS                               0x0900
1678 #define ENABLE_PCLK_PERIS_SECURE_TZPC                   0x0904
1679 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF           0x0908
1680 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF           0x090c
1681 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC                 0x0910
1682 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF     0x0914
1683 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF      0x0918
1684 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF          0x091c
1685 #define ENABLE_SCLK_PERIS                               0x0a00
1686 #define ENABLE_SCLK_PERIS_SECURE_SECKEY                 0x0a04
1687 #define ENABLE_SCLK_PERIS_SECURE_CHIPID                 0x0a08
1688 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC                 0x0a0c
1689 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE           0x0a10
1690 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT            0x0a14
1691 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON                0x0a18
1692 #define ENABLE_IP_PERIS0                                0x0b00
1693 #define ENABLE_IP_PERIS1                                0x0b04
1694 #define ENABLE_IP_PERIS_SECURE_TZPC                     0x0b08
1695 #define ENABLE_IP_PERIS_SECURE_SECKEY                   0x0b0c
1696 #define ENABLE_IP_PERIS_SECURE_CHIPID                   0x0b10
1697 #define ENABLE_IP_PERIS_SECURE_TOPRTC                   0x0b14
1698 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE             0x0b18
1699 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT              0x0b1c
1700 #define ENABLE_IP_PERIS_SECURE_OTP_CON                  0x0b20
1701
1702 static unsigned long peris_clk_regs[] __initdata = {
1703         ENABLE_ACLK_PERIS,
1704         ENABLE_PCLK_PERIS,
1705         ENABLE_PCLK_PERIS_SECURE_TZPC,
1706         ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1707         ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1708         ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1709         ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1710         ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1711         ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1712         ENABLE_SCLK_PERIS,
1713         ENABLE_SCLK_PERIS_SECURE_SECKEY,
1714         ENABLE_SCLK_PERIS_SECURE_CHIPID,
1715         ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1716         ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1717         ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1718         ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1719         ENABLE_IP_PERIS0,
1720         ENABLE_IP_PERIS1,
1721         ENABLE_IP_PERIS_SECURE_TZPC,
1722         ENABLE_IP_PERIS_SECURE_SECKEY,
1723         ENABLE_IP_PERIS_SECURE_CHIPID,
1724         ENABLE_IP_PERIS_SECURE_TOPRTC,
1725         ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1726         ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1727         ENABLE_IP_PERIS_SECURE_OTP_CON,
1728 };
1729
1730 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1731         /* ENABLE_ACLK_PERIS */
1732         GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1733                         ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1734         GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1735                         ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1736         GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1737                         ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1738
1739         /* ENABLE_PCLK_PERIS */
1740         GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1741                         ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1742         GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1743                         ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1744         GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1745                         ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1746         GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1747                         ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1748         GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1749                         ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1750         GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1751                         ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1752         GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1753                         ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1754         GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1755                         ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1756         GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1757                         ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1758         GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1759                         ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1760
1761         /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1762         GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1763                         ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
1764         GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1765                         ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
1766         GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1767                         ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
1768         GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1769                         ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
1770         GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1771                         ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
1772         GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1773                         ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
1774         GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1775                         ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
1776         GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1777                         ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
1778         GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1779                         ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
1780         GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1781                         ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
1782         GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1783                         ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
1784         GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1785                         ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
1786         GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1787                         ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
1788
1789         /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1790         GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1791                         ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
1792
1793         /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1794         GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1795                         ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
1796
1797         /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1798         GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1799                         ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1800
1801         /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1802         GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1803                         "aclk_peris_66",
1804                         ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1805
1806         /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1807         GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1808                         "aclk_peris_66",
1809                         ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1810
1811         /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1812         GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1813                         "aclk_peris_66",
1814                         ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1815
1816         /* ENABLE_SCLK_PERIS */
1817         GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1818                         ENABLE_SCLK_PERIS, 10, 0, 0),
1819         GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1820                         ENABLE_SCLK_PERIS, 4, 0, 0),
1821         GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1822                         ENABLE_SCLK_PERIS, 3, 0, 0),
1823
1824         /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1825         GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1826                         ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
1827
1828         /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1829         GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1830                         ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
1831
1832         /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1833         GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1834                         ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1835
1836         /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1837         GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1838                         ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1839
1840         /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1841         GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1842                         ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1843
1844         /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1845         GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1846                         ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1847 };
1848
1849 static struct samsung_cmu_info peris_cmu_info __initdata = {
1850         .gate_clks              = peris_gate_clks,
1851         .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
1852         .nr_clk_ids             = PERIS_NR_CLK,
1853         .clk_regs               = peris_clk_regs,
1854         .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
1855 };
1856
1857 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1858 {
1859         samsung_cmu_register_one(np, &peris_cmu_info);
1860 }
1861
1862 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1863                 exynos5433_cmu_peris_init);
1864
1865 /*
1866  * Register offset definitions for CMU_FSYS
1867  */
1868 #define MUX_SEL_FSYS0                   0x0200
1869 #define MUX_SEL_FSYS1                   0x0204
1870 #define MUX_SEL_FSYS2                   0x0208
1871 #define MUX_SEL_FSYS3                   0x020c
1872 #define MUX_SEL_FSYS4                   0x0210
1873 #define MUX_ENABLE_FSYS0                0x0300
1874 #define MUX_ENABLE_FSYS1                0x0304
1875 #define MUX_ENABLE_FSYS2                0x0308
1876 #define MUX_ENABLE_FSYS3                0x030c
1877 #define MUX_ENABLE_FSYS4                0x0310
1878 #define MUX_STAT_FSYS0                  0x0400
1879 #define MUX_STAT_FSYS1                  0x0404
1880 #define MUX_STAT_FSYS2                  0x0408
1881 #define MUX_STAT_FSYS3                  0x040c
1882 #define MUX_STAT_FSYS4                  0x0410
1883 #define MUX_IGNORE_FSYS2                0x0508
1884 #define MUX_IGNORE_FSYS3                0x050c
1885 #define ENABLE_ACLK_FSYS0               0x0800
1886 #define ENABLE_ACLK_FSYS1               0x0804
1887 #define ENABLE_PCLK_FSYS                0x0900
1888 #define ENABLE_SCLK_FSYS                0x0a00
1889 #define ENABLE_IP_FSYS0                 0x0b00
1890 #define ENABLE_IP_FSYS1                 0x0b04
1891
1892 /* list of all parent clock list */
1893 PNAME(mout_sclk_ufs_mphy_user_p)        = { "oscclk", "sclk_ufs_mphy", };
1894 PNAME(mout_aclk_fsys_200_user_p)        = { "oscclk", "div_aclk_fsys_200", };
1895 PNAME(mout_sclk_pcie_100_user_p)        = { "oscclk", "sclk_pcie_100_fsys",};
1896 PNAME(mout_sclk_ufsunipro_user_p)       = { "oscclk", "sclk_ufsunipro_fsys",};
1897 PNAME(mout_sclk_mmc2_user_p)            = { "oscclk", "sclk_mmc2_fsys", };
1898 PNAME(mout_sclk_mmc1_user_p)            = { "oscclk", "sclk_mmc1_fsys", };
1899 PNAME(mout_sclk_mmc0_user_p)            = { "oscclk", "sclk_mmc0_fsys", };
1900 PNAME(mout_sclk_usbhost30_user_p)       = { "oscclk", "sclk_usbhost30_fsys",};
1901 PNAME(mout_sclk_usbdrd30_user_p)        = { "oscclk", "sclk_usbdrd30_fsys", };
1902
1903 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1904                 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1905 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1906                 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1907 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1908                 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1909 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1910                 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1911 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1912                 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1913 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1914                 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1915 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1916                 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1917 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1918                 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1919 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1920                 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1921 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1922                 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1923 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1924                 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1925 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1926                 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1927 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1928                 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
1929 PNAME(mout_sclk_mphy_p)
1930                 = { "mout_sclk_ufs_mphy_user",
1931                             "mout_phyclk_lli_mphy_to_ufs_user", };
1932
1933 static unsigned long fsys_clk_regs[] __initdata = {
1934         MUX_SEL_FSYS0,
1935         MUX_SEL_FSYS1,
1936         MUX_SEL_FSYS2,
1937         MUX_SEL_FSYS3,
1938         MUX_SEL_FSYS4,
1939         MUX_ENABLE_FSYS0,
1940         MUX_ENABLE_FSYS1,
1941         MUX_ENABLE_FSYS2,
1942         MUX_ENABLE_FSYS3,
1943         MUX_ENABLE_FSYS4,
1944         MUX_STAT_FSYS0,
1945         MUX_STAT_FSYS1,
1946         MUX_STAT_FSYS2,
1947         MUX_STAT_FSYS3,
1948         MUX_STAT_FSYS4,
1949         MUX_IGNORE_FSYS2,
1950         MUX_IGNORE_FSYS3,
1951         ENABLE_ACLK_FSYS0,
1952         ENABLE_ACLK_FSYS1,
1953         ENABLE_PCLK_FSYS,
1954         ENABLE_SCLK_FSYS,
1955         ENABLE_IP_FSYS0,
1956         ENABLE_IP_FSYS1,
1957 };
1958
1959 static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
1960         /* PHY clocks from USBDRD30_PHY */
1961         FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
1962                         "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
1963                         CLK_IS_ROOT, 60000000),
1964         FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
1965                         "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
1966                         CLK_IS_ROOT, 125000000),
1967         /* PHY clocks from USBHOST30_PHY */
1968         FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
1969                         "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
1970                         CLK_IS_ROOT, 60000000),
1971         FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
1972                         "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
1973                         CLK_IS_ROOT, 125000000),
1974         /* PHY clocks from USBHOST20_PHY */
1975         FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
1976                         "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
1977                         60000000),
1978         FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
1979                         "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
1980                         60000000),
1981         FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
1982                         "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
1983                         CLK_IS_ROOT, 48000000),
1984         FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
1985                         "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
1986                         60000000),
1987         /* PHY clocks from UFS_PHY */
1988         FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
1989                         NULL, CLK_IS_ROOT, 300000000),
1990         FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
1991                         NULL, CLK_IS_ROOT, 300000000),
1992         FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
1993                         NULL, CLK_IS_ROOT, 300000000),
1994         FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
1995                         NULL, CLK_IS_ROOT, 300000000),
1996         /* PHY clocks from LLI_PHY */
1997         FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
1998                         NULL, CLK_IS_ROOT, 26000000),
1999 };
2000
2001 static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
2002         /* MUX_SEL_FSYS0 */
2003         MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2004                         mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2005         MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2006                         mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2007
2008         /* MUX_SEL_FSYS1 */
2009         MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2010                         mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2011         MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2012                         mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2013         MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2014                         mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2015         MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2016                         mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2017         MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2018                         mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2019         MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2020                         mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2021         MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2022                         mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2023
2024         /* MUX_SEL_FSYS2 */
2025         MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2026                         "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2027                         mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2028                         MUX_SEL_FSYS2, 28, 1),
2029         MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2030                         "mout_phyclk_usbhost30_uhost30_phyclock_user",
2031                         mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2032                         MUX_SEL_FSYS2, 24, 1),
2033         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2034                         "mout_phyclk_usbhost20_phy_hsic1",
2035                         mout_phyclk_usbhost20_phy_hsic1_p,
2036                         MUX_SEL_FSYS2, 20, 1),
2037         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2038                         "mout_phyclk_usbhost20_phy_clk48mohci_user",
2039                         mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2040                         MUX_SEL_FSYS2, 16, 1),
2041         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2042                         "mout_phyclk_usbhost20_phy_phyclock_user",
2043                         mout_phyclk_usbhost20_phy_phyclock_user_p,
2044                         MUX_SEL_FSYS2, 12, 1),
2045         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2046                         "mout_phyclk_usbhost20_phy_freeclk_user",
2047                         mout_phyclk_usbhost20_phy_freeclk_user_p,
2048                         MUX_SEL_FSYS2, 8, 1),
2049         MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2050                         "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2051                         mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2052                         MUX_SEL_FSYS2, 4, 1),
2053         MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2054                         "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2055                         mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2056                         MUX_SEL_FSYS2, 0, 1),
2057
2058         /* MUX_SEL_FSYS3 */
2059         MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2060                         "mout_phyclk_ufs_rx1_symbol_user",
2061                         mout_phyclk_ufs_rx1_symbol_user_p,
2062                         MUX_SEL_FSYS3, 16, 1),
2063         MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2064                         "mout_phyclk_ufs_rx0_symbol_user",
2065                         mout_phyclk_ufs_rx0_symbol_user_p,
2066                         MUX_SEL_FSYS3, 12, 1),
2067         MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2068                         "mout_phyclk_ufs_tx1_symbol_user",
2069                         mout_phyclk_ufs_tx1_symbol_user_p,
2070                         MUX_SEL_FSYS3, 8, 1),
2071         MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2072                         "mout_phyclk_ufs_tx0_symbol_user",
2073                         mout_phyclk_ufs_tx0_symbol_user_p,
2074                         MUX_SEL_FSYS3, 4, 1),
2075         MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2076                         "mout_phyclk_lli_mphy_to_ufs_user",
2077                         mout_phyclk_lli_mphy_to_ufs_user_p,
2078                         MUX_SEL_FSYS3, 0, 1),
2079
2080         /* MUX_SEL_FSYS4 */
2081         MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2082                         MUX_SEL_FSYS4, 0, 1),
2083 };
2084
2085 static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2086         /* ENABLE_ACLK_FSYS0 */
2087         GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2088                         ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2089         GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2090                         ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2091         GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2092                         ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2093         GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2094                         ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2095         GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2096                         ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2097         GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2098                         ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2099         GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2100                         ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2101         GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2102                         ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2103         GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2104                         ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2105         GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2106                         ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2107         GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2108                         ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2109
2110         /* ENABLE_ACLK_FSYS1 */
2111         GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2112                         ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2113         GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2114                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2115                         26, CLK_IGNORE_UNUSED, 0),
2116         GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2117                         ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2118         GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2119                         ENABLE_ACLK_FSYS1, 24, 0, 0),
2120         GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2121                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2122                         22, CLK_IGNORE_UNUSED, 0),
2123         GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2124                         ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2125         GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2126                         ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2127         GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2128                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2129                         13, 0, 0),
2130         GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2131                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2132                         12, 0, 0),
2133         GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2134                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2135                         11, CLK_IGNORE_UNUSED, 0),
2136         GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2137                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2138                         10, CLK_IGNORE_UNUSED, 0),
2139         GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2140                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2141                         9, CLK_IGNORE_UNUSED, 0),
2142         GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2143                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2144                         8, CLK_IGNORE_UNUSED, 0),
2145         GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2146                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2147                         7, CLK_IGNORE_UNUSED, 0),
2148         GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2149                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2150                         6, CLK_IGNORE_UNUSED, 0),
2151         GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2152                         ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2153         GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2154                         ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2155         GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2156                         ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2157         GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2158                         ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2159         GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2160                         ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2161         GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2162                         ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2163
2164         /* ENABLE_PCLK_FSYS */
2165         GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2166                         ENABLE_PCLK_FSYS, 17, 0, 0),
2167         GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2168                         ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2169         GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2170                         ENABLE_PCLK_FSYS, 14, 0, 0),
2171         GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2172                         ENABLE_PCLK_FSYS, 13, 0, 0),
2173         GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2174                         ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2175         GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2176                         ENABLE_PCLK_FSYS, 5, 0, 0),
2177         GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2178                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2179         GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2180                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2181         GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2182                         ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2183         GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2184                         ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2185         GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2186                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2187                         0, CLK_IGNORE_UNUSED, 0),
2188
2189         /* ENABLE_SCLK_FSYS */
2190         GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2191                         ENABLE_SCLK_FSYS, 21, 0, 0),
2192         GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2193                         "phyclk_usbhost30_uhost30_pipe_pclk",
2194                         "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2195                         ENABLE_SCLK_FSYS, 18, 0, 0),
2196         GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2197                         "phyclk_usbhost30_uhost30_phyclock",
2198                         "mout_phyclk_usbhost30_uhost30_phyclock_user",
2199                         ENABLE_SCLK_FSYS, 17, 0, 0),
2200         GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2201                         "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2202                         16, 0, 0),
2203         GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2204                         "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2205                         15, 0, 0),
2206         GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2207                         "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2208                         14, 0, 0),
2209         GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2210                         "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2211                         13, 0, 0),
2212         GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2213                         "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2214                         12, 0, 0),
2215         GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2216                         "phyclk_usbhost20_phy_clk48mohci",
2217                         "mout_phyclk_usbhost20_phy_clk48mohci_user",
2218                         ENABLE_SCLK_FSYS, 11, 0, 0),
2219         GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2220                         "phyclk_usbhost20_phy_phyclock",
2221                         "mout_phyclk_usbhost20_phy_phyclock_user",
2222                         ENABLE_SCLK_FSYS, 10, 0, 0),
2223         GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2224                         "phyclk_usbhost20_phy_freeclk",
2225                         "mout_phyclk_usbhost20_phy_freeclk_user",
2226                         ENABLE_SCLK_FSYS, 9, 0, 0),
2227         GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2228                         "phyclk_usbdrd30_udrd30_pipe_pclk",
2229                         "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2230                         ENABLE_SCLK_FSYS, 8, 0, 0),
2231         GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2232                         "phyclk_usbdrd30_udrd30_phyclock",
2233                         "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2234                         ENABLE_SCLK_FSYS, 7, 0, 0),
2235         GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2236                         ENABLE_SCLK_FSYS, 6, 0, 0),
2237         GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2238                         ENABLE_SCLK_FSYS, 5, 0, 0),
2239         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2240                         ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2241         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2242                         ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2243         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2244                         ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2245         GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2246                         ENABLE_SCLK_FSYS, 1, 0, 0),
2247         GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2248                         ENABLE_SCLK_FSYS, 0, 0, 0),
2249
2250         /* ENABLE_IP_FSYS0 */
2251         GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2252         GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2253 };
2254
2255 static struct samsung_cmu_info fsys_cmu_info __initdata = {
2256         .mux_clks               = fsys_mux_clks,
2257         .nr_mux_clks            = ARRAY_SIZE(fsys_mux_clks),
2258         .gate_clks              = fsys_gate_clks,
2259         .nr_gate_clks           = ARRAY_SIZE(fsys_gate_clks),
2260         .fixed_clks             = fsys_fixed_clks,
2261         .nr_fixed_clks          = ARRAY_SIZE(fsys_fixed_clks),
2262         .nr_clk_ids             = FSYS_NR_CLK,
2263         .clk_regs               = fsys_clk_regs,
2264         .nr_clk_regs            = ARRAY_SIZE(fsys_clk_regs),
2265 };
2266
2267 static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2268 {
2269         samsung_cmu_register_one(np, &fsys_cmu_info);
2270 }
2271
2272 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2273                 exynos5433_cmu_fsys_init);
2274
2275 /*
2276  * Register offset definitions for CMU_G2D
2277  */
2278 #define MUX_SEL_G2D0                            0x0200
2279 #define MUX_SEL_ENABLE_G2D0                     0x0300
2280 #define MUX_SEL_STAT_G2D0                       0x0400
2281 #define DIV_G2D                                 0x0600
2282 #define DIV_STAT_G2D                            0x0700
2283 #define DIV_ENABLE_ACLK_G2D                     0x0800
2284 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D     0x0804
2285 #define DIV_ENABLE_PCLK_G2D                     0x0900
2286 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D     0x0904
2287 #define DIV_ENABLE_IP_G2D0                      0x0b00
2288 #define DIV_ENABLE_IP_G2D1                      0x0b04
2289 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D       0x0b08
2290
2291 static unsigned long g2d_clk_regs[] __initdata = {
2292         MUX_SEL_G2D0,
2293         MUX_SEL_ENABLE_G2D0,
2294         MUX_SEL_STAT_G2D0,
2295         DIV_G2D,
2296         DIV_STAT_G2D,
2297         DIV_ENABLE_ACLK_G2D,
2298         DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2299         DIV_ENABLE_PCLK_G2D,
2300         DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2301         DIV_ENABLE_IP_G2D0,
2302         DIV_ENABLE_IP_G2D1,
2303         DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2304 };
2305
2306 /* list of all parent clock list */
2307 PNAME(mout_aclk_g2d_266_user_p)         = { "oscclk", "aclk_g2d_266", };
2308 PNAME(mout_aclk_g2d_400_user_p)         = { "oscclk", "aclk_g2d_400", };
2309
2310 static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2311         /* MUX_SEL_G2D0 */
2312         MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2313                         mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2314         MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2315                         mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2316 };
2317
2318 static struct samsung_div_clock g2d_div_clks[] __initdata = {
2319         /* DIV_G2D */
2320         DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2321                         DIV_G2D, 0, 2),
2322 };
2323
2324 static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2325         /* DIV_ENABLE_ACLK_G2D */
2326         GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2327                         DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2328         GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2329                         DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2330         GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2331                         DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2332         GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2333                         DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2334         GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2335                         DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2336         GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2337                         "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2338                         7, 0, 0),
2339         GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2340                         DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2341         GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2342                         DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2343         GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2344                         DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2345         GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2346                         DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2347         GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2348                         DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2349         GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2350                         DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2351         GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2352                         DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2353
2354         /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2355         GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2356                 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2357
2358         /* DIV_ENABLE_PCLK_G2D */
2359         GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2360                         DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2361         GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2362                         DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2363         GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2364                         DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2365         GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2366                         DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2367         GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2368                         DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2369         GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2370                         DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2371         GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2372                         DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2373         GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2374                         0, 0, 0),
2375
2376         /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2377         GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2378                 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2379 };
2380
2381 static struct samsung_cmu_info g2d_cmu_info __initdata = {
2382         .mux_clks               = g2d_mux_clks,
2383         .nr_mux_clks            = ARRAY_SIZE(g2d_mux_clks),
2384         .div_clks               = g2d_div_clks,
2385         .nr_div_clks            = ARRAY_SIZE(g2d_div_clks),
2386         .gate_clks              = g2d_gate_clks,
2387         .nr_gate_clks           = ARRAY_SIZE(g2d_gate_clks),
2388         .nr_clk_ids             = G2D_NR_CLK,
2389         .clk_regs               = g2d_clk_regs,
2390         .nr_clk_regs            = ARRAY_SIZE(g2d_clk_regs),
2391 };
2392
2393 static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2394 {
2395         samsung_cmu_register_one(np, &g2d_cmu_info);
2396 }
2397
2398 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2399                 exynos5433_cmu_g2d_init);
2400
2401 /*
2402  * Register offset definitions for CMU_DISP
2403  */
2404 #define DISP_PLL_LOCK                   0x0000
2405 #define DISP_PLL_CON0                   0x0100
2406 #define DISP_PLL_CON1                   0x0104
2407 #define DISP_PLL_FREQ_DET               0x0108
2408 #define MUX_SEL_DISP0                   0x0200
2409 #define MUX_SEL_DISP1                   0x0204
2410 #define MUX_SEL_DISP2                   0x0208
2411 #define MUX_SEL_DISP3                   0x020c
2412 #define MUX_SEL_DISP4                   0x0210
2413 #define MUX_ENABLE_DISP0                0x0300
2414 #define MUX_ENABLE_DISP1                0x0304
2415 #define MUX_ENABLE_DISP2                0x0308
2416 #define MUX_ENABLE_DISP3                0x030c
2417 #define MUX_ENABLE_DISP4                0x0310
2418 #define MUX_STAT_DISP0                  0x0400
2419 #define MUX_STAT_DISP1                  0x0404
2420 #define MUX_STAT_DISP2                  0x0408
2421 #define MUX_STAT_DISP3                  0x040c
2422 #define MUX_STAT_DISP4                  0x0410
2423 #define MUX_IGNORE_DISP2                0x0508
2424 #define DIV_DISP                        0x0600
2425 #define DIV_DISP_PLL_FREQ_DET           0x0604
2426 #define DIV_STAT_DISP                   0x0700
2427 #define DIV_STAT_DISP_PLL_FREQ_DET      0x0704
2428 #define ENABLE_ACLK_DISP0               0x0800
2429 #define ENABLE_ACLK_DISP1               0x0804
2430 #define ENABLE_PCLK_DISP                0x0900
2431 #define ENABLE_SCLK_DISP                0x0a00
2432 #define ENABLE_IP_DISP0                 0x0b00
2433 #define ENABLE_IP_DISP1                 0x0b04
2434 #define CLKOUT_CMU_DISP                 0x0c00
2435 #define CLKOUT_CMU_DISP_DIV_STAT        0x0c04
2436
2437 static unsigned long disp_clk_regs[] __initdata = {
2438         DISP_PLL_LOCK,
2439         DISP_PLL_CON0,
2440         DISP_PLL_CON1,
2441         DISP_PLL_FREQ_DET,
2442         MUX_SEL_DISP0,
2443         MUX_SEL_DISP1,
2444         MUX_SEL_DISP2,
2445         MUX_SEL_DISP3,
2446         MUX_SEL_DISP4,
2447         MUX_ENABLE_DISP0,
2448         MUX_ENABLE_DISP1,
2449         MUX_ENABLE_DISP2,
2450         MUX_ENABLE_DISP3,
2451         MUX_ENABLE_DISP4,
2452         MUX_STAT_DISP0,
2453         MUX_STAT_DISP1,
2454         MUX_STAT_DISP2,
2455         MUX_STAT_DISP3,
2456         MUX_STAT_DISP4,
2457         MUX_IGNORE_DISP2,
2458         DIV_DISP,
2459         DIV_DISP_PLL_FREQ_DET,
2460         DIV_STAT_DISP,
2461         DIV_STAT_DISP_PLL_FREQ_DET,
2462         ENABLE_ACLK_DISP0,
2463         ENABLE_ACLK_DISP1,
2464         ENABLE_PCLK_DISP,
2465         ENABLE_SCLK_DISP,
2466         ENABLE_IP_DISP0,
2467         ENABLE_IP_DISP1,
2468         CLKOUT_CMU_DISP,
2469         CLKOUT_CMU_DISP_DIV_STAT,
2470 };
2471
2472 /* list of all parent clock list */
2473 PNAME(mout_disp_pll_p)                  = { "oscclk", "fout_disp_pll", };
2474 PNAME(mout_sclk_dsim1_user_p)           = { "oscclk", "sclk_dsim1_disp", };
2475 PNAME(mout_sclk_dsim0_user_p)           = { "oscclk", "sclk_dsim0_disp", };
2476 PNAME(mout_sclk_dsd_user_p)             = { "oscclk", "sclk_dsd_disp", };
2477 PNAME(mout_sclk_decon_tv_eclk_user_p)   = { "oscclk",
2478                                             "sclk_decon_tv_eclk_disp", };
2479 PNAME(mout_sclk_decon_vclk_user_p)      = { "oscclk",
2480                                             "sclk_decon_vclk_disp", };
2481 PNAME(mout_sclk_decon_eclk_user_p)      = { "oscclk",
2482                                             "sclk_decon_eclk_disp", };
2483 PNAME(mout_sclk_decon_tv_vlkc_user_p)   = { "oscclk",
2484                                             "sclk_decon_tv_vclk_disp", };
2485 PNAME(mout_aclk_disp_333_user_p)        = { "oscclk", "aclk_disp_333", };
2486
2487 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p)  = { "oscclk",
2488                                         "phyclk_mipidphy1_bitclkdiv8_phy", };
2489 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p)   = { "oscclk",
2490                                         "phyclk_mipidphy1_rxclkesc0_phy", };
2491 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p)  = { "oscclk",
2492                                         "phyclk_mipidphy0_bitclkdiv8_phy", };
2493 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p)   = { "oscclk",
2494                                         "phyclk_mipidphy0_rxclkesc0_phy", };
2495 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p)     = { "oscclk",
2496                                         "phyclk_hdmiphy_tmds_clko_phy", };
2497 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p)    = { "oscclk",
2498                                         "phyclk_hdmiphy_pixel_clko_phy", };
2499
2500 PNAME(mout_sclk_dsim0_p)                = { "mout_disp_pll",
2501                                             "mout_sclk_dsim0_user", };
2502 PNAME(mout_sclk_decon_tv_eclk_p)        = { "mout_disp_pll",
2503                                             "mout_sclk_decon_tv_eclk_user", };
2504 PNAME(mout_sclk_decon_vclk_p)           = { "mout_disp_pll",
2505                                             "mout_sclk_decon_vclk_user", };
2506 PNAME(mout_sclk_decon_eclk_p)           = { "mout_disp_pll",
2507                                             "mout_sclk_decon_eclk_user", };
2508
2509 PNAME(mout_sclk_dsim1_b_disp_p)         = { "mout_sclk_dsim1_a_disp",
2510                                             "mout_sclk_dsim1_user", };
2511 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2512                                 "mout_phyclk_hdmiphy_pixel_clko_user",
2513                                 "mout_sclk_decon_tv_vclk_b_disp", };
2514 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2515                                             "mout_sclk_decon_tv_vclk_user", };
2516
2517 static struct samsung_pll_clock disp_pll_clks[] __initdata = {
2518         PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2519                 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2520 };
2521
2522 static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2523         /*
2524          * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2525          * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2526          * and sclk_decon_{vclk|tv_vclk}.
2527          */
2528         FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2529                         1, 2, 0),
2530         FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2531                         1, 2, 0),
2532 };
2533
2534 static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2535         /* PHY clocks from MIPI_DPHY1 */
2536         FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2537                         188000000),
2538         FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2539                         100000000),
2540         /* PHY clocks from MIPI_DPHY0 */
2541         FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2542                         188000000),
2543         FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2544                         100000000),
2545         /* PHY clocks from HDMI_PHY */
2546         FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
2547         FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
2548 };
2549
2550 static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2551         /* MUX_SEL_DISP0 */
2552         MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2553                         0, 1),
2554
2555         /* MUX_SEL_DISP1 */
2556         MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2557                         mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2558         MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2559                         mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2560         MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2561                         MUX_SEL_DISP1, 20, 1),
2562         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2563                         mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2564         MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2565                         mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2566         MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2567                         mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2568         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2569                         mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2570         MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2571                         mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2572
2573         /* MUX_SEL_DISP2 */
2574         MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2575                         "mout_phyclk_mipidphy1_bitclkdiv8_user",
2576                         mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2577                         20, 1),
2578         MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2579                         "mout_phyclk_mipidphy1_rxclkesc0_user",
2580                         mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2581                         16, 1),
2582         MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2583                         "mout_phyclk_mipidphy0_bitclkdiv8_user",
2584                         mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2585                         12, 1),
2586         MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2587                         "mout_phyclk_mipidphy0_rxclkesc0_user",
2588                         mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2589                         8, 1),
2590         MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2591                         "mout_phyclk_hdmiphy_tmds_clko_user",
2592                         mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2593                         4, 1),
2594         MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2595                         "mout_phyclk_hdmiphy_pixel_clko_user",
2596                         mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2597                         0, 1),
2598
2599         /* MUX_SEL_DISP3 */
2600         MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2601                         MUX_SEL_DISP3, 12, 1),
2602         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2603                         mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2604         MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2605                         mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2606         MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2607                         mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2608
2609         /* MUX_SEL_DISP4 */
2610         MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2611                         mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2612         MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2613                         mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2614         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2615                         "mout_sclk_decon_tv_vclk_c_disp",
2616                         mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2617         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2618                         "mout_sclk_decon_tv_vclk_b_disp",
2619                         mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2620         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2621                         "mout_sclk_decon_tv_vclk_a_disp",
2622                         mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2623 };
2624
2625 static struct samsung_div_clock disp_div_clks[] __initdata = {
2626         /* DIV_DISP */
2627         DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2628                         "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2629         DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2630                         "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2631         DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2632                         DIV_DISP, 16, 3),
2633         DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2634                         "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2635         DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2636                         "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2637         DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2638                         "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2639         DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2640                         DIV_DISP, 0, 2),
2641 };
2642
2643 static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2644         /* ENABLE_ACLK_DISP0 */
2645         GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2646                         ENABLE_ACLK_DISP0, 2, 0, 0),
2647         GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2648                         ENABLE_ACLK_DISP0, 0, 0, 0),
2649
2650         /* ENABLE_ACLK_DISP1 */
2651         GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2652                         ENABLE_ACLK_DISP1, 25, 0, 0),
2653         GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2654                         ENABLE_ACLK_DISP1, 24, 0, 0),
2655         GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2656                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2657         GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2658                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2659         GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2660                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2661         GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2662                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2663         GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2664                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2665         GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2666                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2667         GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2668                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2669         GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2670                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2671         GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2672                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2673         GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2674                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2675         GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2676                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2677         GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2678                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2679                         12, CLK_IGNORE_UNUSED, 0),
2680         GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2681                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2682                         11, CLK_IGNORE_UNUSED, 0),
2683         GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2684                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2685                         10, CLK_IGNORE_UNUSED, 0),
2686         GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2687                         ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2688         GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2689                         ENABLE_ACLK_DISP1, 7, 0, 0),
2690         GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2691                         ENABLE_ACLK_DISP1, 6, 0, 0),
2692         GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2693                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2694         GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2695                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2696         GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2697                         ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2698         GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2699                         ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2700         GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2701                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2702                         CLK_IGNORE_UNUSED, 0),
2703         GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2704                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2705                         0, CLK_IGNORE_UNUSED, 0),
2706
2707         /* ENABLE_PCLK_DISP */
2708         GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2709                         ENABLE_PCLK_DISP, 23, 0, 0),
2710         GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2711                         ENABLE_PCLK_DISP, 22, 0, 0),
2712         GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2713                         ENABLE_PCLK_DISP, 21, 0, 0),
2714         GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2715                         ENABLE_PCLK_DISP, 20, 0, 0),
2716         GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2717                         ENABLE_PCLK_DISP, 19, 0, 0),
2718         GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2719                         ENABLE_PCLK_DISP, 18, 0, 0),
2720         GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2721                         ENABLE_PCLK_DISP, 17, 0, 0),
2722         GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2723                         ENABLE_PCLK_DISP, 16, 0, 0),
2724         GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2725                         ENABLE_PCLK_DISP, 15, 0, 0),
2726         GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2727                         ENABLE_PCLK_DISP, 14, 0, 0),
2728         GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2729                         ENABLE_PCLK_DISP, 13, 0, 0),
2730         GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2731                         ENABLE_PCLK_DISP, 12, 0, 0),
2732         GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2733                         ENABLE_PCLK_DISP, 11, 0, 0),
2734         GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2735                         ENABLE_PCLK_DISP, 10, 0, 0),
2736         GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2737                         ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2738         GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2739                         ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2740         GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2741                         ENABLE_PCLK_DISP, 7, 0, 0),
2742         GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2743                         ENABLE_PCLK_DISP, 6, 0, 0),
2744         GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2745                         ENABLE_PCLK_DISP, 5, 0, 0),
2746         GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2747                         ENABLE_PCLK_DISP, 3, 0, 0),
2748         GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2749                         ENABLE_PCLK_DISP, 2, 0, 0),
2750         GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2751                         ENABLE_PCLK_DISP, 1, 0, 0),
2752
2753         /* ENABLE_SCLK_DISP */
2754         GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2755                         "mout_phyclk_mipidphy1_bitclkdiv8_user",
2756                         ENABLE_SCLK_DISP, 26, 0, 0),
2757         GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2758                         "mout_phyclk_mipidphy1_rxclkesc0_user",
2759                         ENABLE_SCLK_DISP, 25, 0, 0),
2760         GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2761                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2762         GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2763                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2764         GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2765                         ENABLE_SCLK_DISP, 22, 0, 0),
2766         GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2767                         "div_sclk_decon_tv_vclk_disp",
2768                         ENABLE_SCLK_DISP, 21, 0, 0),
2769         GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2770                         "mout_phyclk_mipidphy0_bitclkdiv8_user",
2771                         ENABLE_SCLK_DISP, 15, 0, 0),
2772         GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2773                         "mout_phyclk_mipidphy0_rxclkesc0_user",
2774                         ENABLE_SCLK_DISP, 14, 0, 0),
2775         GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2776                         "mout_phyclk_hdmiphy_tmds_clko_user",
2777                         ENABLE_SCLK_DISP, 13, 0, 0),
2778         GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2779                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2780         GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2781                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2782         GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2783                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2784         GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2785                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2786         GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2787                         ENABLE_SCLK_DISP, 7, 0, 0),
2788         GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2789                         ENABLE_SCLK_DISP, 6, 0, 0),
2790         GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2791                         ENABLE_SCLK_DISP, 5, 0, 0),
2792         GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2793                         "div_sclk_decon_tv_eclk_disp",
2794                         ENABLE_SCLK_DISP, 4, 0, 0),
2795         GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2796                         "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2797         GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2798                         "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2799 };
2800
2801 static struct samsung_cmu_info disp_cmu_info __initdata = {
2802         .pll_clks               = disp_pll_clks,
2803         .nr_pll_clks            = ARRAY_SIZE(disp_pll_clks),
2804         .mux_clks               = disp_mux_clks,
2805         .nr_mux_clks            = ARRAY_SIZE(disp_mux_clks),
2806         .div_clks               = disp_div_clks,
2807         .nr_div_clks            = ARRAY_SIZE(disp_div_clks),
2808         .gate_clks              = disp_gate_clks,
2809         .nr_gate_clks           = ARRAY_SIZE(disp_gate_clks),
2810         .fixed_clks             = disp_fixed_clks,
2811         .nr_fixed_clks          = ARRAY_SIZE(disp_fixed_clks),
2812         .fixed_factor_clks      = disp_fixed_factor_clks,
2813         .nr_fixed_factor_clks   = ARRAY_SIZE(disp_fixed_factor_clks),
2814         .nr_clk_ids             = DISP_NR_CLK,
2815         .clk_regs               = disp_clk_regs,
2816         .nr_clk_regs            = ARRAY_SIZE(disp_clk_regs),
2817 };
2818
2819 static void __init exynos5433_cmu_disp_init(struct device_node *np)
2820 {
2821         samsung_cmu_register_one(np, &disp_cmu_info);
2822 }
2823
2824 CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2825                 exynos5433_cmu_disp_init);
2826
2827 /*
2828  * Register offset definitions for CMU_AUD
2829  */
2830 #define MUX_SEL_AUD0                    0x0200
2831 #define MUX_SEL_AUD1                    0x0204
2832 #define MUX_ENABLE_AUD0                 0x0300
2833 #define MUX_ENABLE_AUD1                 0x0304
2834 #define MUX_STAT_AUD0                   0x0400
2835 #define DIV_AUD0                        0x0600
2836 #define DIV_AUD1                        0x0604
2837 #define DIV_STAT_AUD0                   0x0700
2838 #define DIV_STAT_AUD1                   0x0704
2839 #define ENABLE_ACLK_AUD                 0x0800
2840 #define ENABLE_PCLK_AUD                 0x0900
2841 #define ENABLE_SCLK_AUD0                0x0a00
2842 #define ENABLE_SCLK_AUD1                0x0a04
2843 #define ENABLE_IP_AUD0                  0x0b00
2844 #define ENABLE_IP_AUD1                  0x0b04
2845
2846 static unsigned long aud_clk_regs[] __initdata = {
2847         MUX_SEL_AUD0,
2848         MUX_SEL_AUD1,
2849         MUX_ENABLE_AUD0,
2850         MUX_ENABLE_AUD1,
2851         MUX_STAT_AUD0,
2852         DIV_AUD0,
2853         DIV_AUD1,
2854         DIV_STAT_AUD0,
2855         DIV_STAT_AUD1,
2856         ENABLE_ACLK_AUD,
2857         ENABLE_PCLK_AUD,
2858         ENABLE_SCLK_AUD0,
2859         ENABLE_SCLK_AUD1,
2860         ENABLE_IP_AUD0,
2861         ENABLE_IP_AUD1,
2862 };
2863
2864 /* list of all parent clock list */
2865 PNAME(mout_aud_pll_user_aud_p)  = { "oscclk", "fout_aud_pll", };
2866 PNAME(mout_sclk_aud_pcm_p)      = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2867
2868 static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
2869         FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
2870         FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
2871         FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
2872 };
2873
2874 static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2875         /* MUX_SEL_AUD0 */
2876         MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2877                         mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2878
2879         /* MUX_SEL_AUD1 */
2880         MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2881                         MUX_SEL_AUD1, 8, 1),
2882         MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2883                         MUX_SEL_AUD1, 0, 1),
2884 };
2885
2886 static struct samsung_div_clock aud_div_clks[] __initdata = {
2887         /* DIV_AUD0 */
2888         DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2889                         12, 4),
2890         DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2891                         8, 4),
2892         DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2893                         4, 4),
2894         DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2895                         0, 4),
2896
2897         /* DIV_AUD1 */
2898         DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2899                         "mout_aud_pll_user", DIV_AUD1, 16, 5),
2900         DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2901                         DIV_AUD1, 12, 4),
2902         DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2903                         DIV_AUD1, 4, 8),
2904         DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s",  "mout_sclk_aud_i2s",
2905                         DIV_AUD1, 0, 4),
2906 };
2907
2908 static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2909         /* ENABLE_ACLK_AUD */
2910         GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2911                         ENABLE_ACLK_AUD, 12, 0, 0),
2912         GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2913                         ENABLE_ACLK_AUD, 7, 0, 0),
2914         GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2915                         ENABLE_ACLK_AUD, 0, 4, 0),
2916         GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2917                         ENABLE_ACLK_AUD, 0, 3, 0),
2918         GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2919                         ENABLE_ACLK_AUD, 0, 2, 0),
2920         GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2921                         0, 1, 0),
2922         GATE(CLK_ACLK_DMAC, "aclk_dmac",  "div_aclk_aud", ENABLE_ACLK_AUD,
2923                         0, CLK_IGNORE_UNUSED, 0),
2924
2925         /* ENABLE_PCLK_AUD */
2926         GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2927                         13, 0, 0),
2928         GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
2929                         12, 0, 0),
2930         GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
2931                         11, 0, 0),
2932         GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
2933                         ENABLE_PCLK_AUD, 10, 0, 0),
2934         GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
2935                         ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
2936         GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
2937                         ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
2938         GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
2939                         ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
2940         GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
2941                         ENABLE_PCLK_AUD, 6, 0, 0),
2942         GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
2943                         ENABLE_PCLK_AUD, 5, 0, 0),
2944         GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
2945                         ENABLE_PCLK_AUD, 4, 0, 0),
2946         GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
2947                         ENABLE_PCLK_AUD, 3, 0, 0),
2948         GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2949                         2, 0, 0),
2950         GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
2951                         ENABLE_PCLK_AUD, 0, 0, 0),
2952
2953         /* ENABLE_SCLK_AUD0 */
2954         GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2955                         2, 0, 0),
2956         GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
2957                         ENABLE_SCLK_AUD0, 1, 0, 0),
2958         GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
2959                         0, 0, 0),
2960
2961         /* ENABLE_SCLK_AUD1 */
2962         GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
2963                         ENABLE_SCLK_AUD1, 6, 0, 0),
2964         GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
2965                         ENABLE_SCLK_AUD1, 5, 0, 0),
2966         GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
2967                         ENABLE_SCLK_AUD1, 4, 0, 0),
2968         GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
2969                         ENABLE_SCLK_AUD1, 3, 0, 0),
2970         GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
2971                         ENABLE_SCLK_AUD1, 2, 0, 0),
2972         GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
2973                         ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
2974         GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
2975                         ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
2976 };
2977
2978 static struct samsung_cmu_info aud_cmu_info __initdata = {
2979         .mux_clks               = aud_mux_clks,
2980         .nr_mux_clks            = ARRAY_SIZE(aud_mux_clks),
2981         .div_clks               = aud_div_clks,
2982         .nr_div_clks            = ARRAY_SIZE(aud_div_clks),
2983         .gate_clks              = aud_gate_clks,
2984         .nr_gate_clks           = ARRAY_SIZE(aud_gate_clks),
2985         .fixed_clks             = aud_fixed_clks,
2986         .nr_fixed_clks          = ARRAY_SIZE(aud_fixed_clks),
2987         .nr_clk_ids             = AUD_NR_CLK,
2988         .clk_regs               = aud_clk_regs,
2989         .nr_clk_regs            = ARRAY_SIZE(aud_clk_regs),
2990 };
2991
2992 static void __init exynos5433_cmu_aud_init(struct device_node *np)
2993 {
2994         samsung_cmu_register_one(np, &aud_cmu_info);
2995 }
2996 CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
2997                 exynos5433_cmu_aud_init);
2998
2999
3000 /*
3001  * Register offset definitions for CMU_BUS{0|1|2}
3002  */
3003 #define DIV_BUS                         0x0600
3004 #define DIV_STAT_BUS                    0x0700
3005 #define ENABLE_ACLK_BUS                 0x0800
3006 #define ENABLE_PCLK_BUS                 0x0900
3007 #define ENABLE_IP_BUS0                  0x0b00
3008 #define ENABLE_IP_BUS1                  0x0b04
3009
3010 #define MUX_SEL_BUS2                    0x0200  /* Only for CMU_BUS2 */
3011 #define MUX_ENABLE_BUS2                 0x0300  /* Only for CMU_BUS2 */
3012 #define MUX_STAT_BUS2                   0x0400  /* Only for CMU_BUS2 */
3013
3014 /* list of all parent clock list */
3015 PNAME(mout_aclk_bus2_400_p)     = { "oscclk", "aclk_bus2_400", };
3016
3017 #define CMU_BUS_COMMON_CLK_REGS \
3018         DIV_BUS,                \
3019         DIV_STAT_BUS,           \
3020         ENABLE_ACLK_BUS,        \
3021         ENABLE_PCLK_BUS,        \
3022         ENABLE_IP_BUS0,         \
3023         ENABLE_IP_BUS1
3024
3025 static unsigned long bus01_clk_regs[] __initdata = {
3026         CMU_BUS_COMMON_CLK_REGS,
3027 };
3028
3029 static unsigned long bus2_clk_regs[] __initdata = {
3030         MUX_SEL_BUS2,
3031         MUX_ENABLE_BUS2,
3032         MUX_STAT_BUS2,
3033         CMU_BUS_COMMON_CLK_REGS,
3034 };
3035
3036 static struct samsung_div_clock bus0_div_clks[] __initdata = {
3037         /* DIV_BUS0 */
3038         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3039                         DIV_BUS, 0, 3),
3040 };
3041
3042 /* CMU_BUS0 clocks */
3043 static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3044         /* ENABLE_ACLK_BUS0 */
3045         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3046                         ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3047         GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3048                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3049         GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3050                         ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3051
3052         /* ENABLE_PCLK_BUS0 */
3053         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3054                         ENABLE_PCLK_BUS, 2, 0, 0),
3055         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3056                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3057         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3058                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3059 };
3060
3061 /* CMU_BUS1 clocks */
3062 static struct samsung_div_clock bus1_div_clks[] __initdata = {
3063         /* DIV_BUS1 */
3064         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3065                         DIV_BUS, 0, 3),
3066 };
3067
3068 static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3069         /* ENABLE_ACLK_BUS1 */
3070         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3071                         ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3072         GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3073                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3074         GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3075                         ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3076
3077         /* ENABLE_PCLK_BUS1 */
3078         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3079                         ENABLE_PCLK_BUS, 2, 0, 0),
3080         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3081                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3082         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3083                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3084 };
3085
3086 /* CMU_BUS2 clocks */
3087 static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
3088         /* MUX_SEL_BUS2 */
3089         MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3090                         mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3091 };
3092
3093 static struct samsung_div_clock bus2_div_clks[] __initdata = {
3094         /* DIV_BUS2 */
3095         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3096                         "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3097 };
3098
3099 static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3100         /* ENABLE_ACLK_BUS2 */
3101         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3102                         ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3103         GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3104                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3105         GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3106                         "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3107                         1, CLK_IGNORE_UNUSED, 0),
3108         GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3109                         "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3110                         0, CLK_IGNORE_UNUSED, 0),
3111
3112         /* ENABLE_PCLK_BUS2 */
3113         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3114                         ENABLE_PCLK_BUS, 2, 0, 0),
3115         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3116                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3117         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3118                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3119 };
3120
3121 #define CMU_BUS_INFO_CLKS(id)                                           \
3122         .div_clks               = bus##id##_div_clks,                   \
3123         .nr_div_clks            = ARRAY_SIZE(bus##id##_div_clks),       \
3124         .gate_clks              = bus##id##_gate_clks,                  \
3125         .nr_gate_clks           = ARRAY_SIZE(bus##id##_gate_clks),      \
3126         .nr_clk_ids             = BUSx_NR_CLK
3127
3128 static struct samsung_cmu_info bus0_cmu_info __initdata = {
3129         CMU_BUS_INFO_CLKS(0),
3130         .clk_regs               = bus01_clk_regs,
3131         .nr_clk_regs            = ARRAY_SIZE(bus01_clk_regs),
3132 };
3133
3134 static struct samsung_cmu_info bus1_cmu_info __initdata = {
3135         CMU_BUS_INFO_CLKS(1),
3136         .clk_regs               = bus01_clk_regs,
3137         .nr_clk_regs            = ARRAY_SIZE(bus01_clk_regs),
3138 };
3139
3140 static struct samsung_cmu_info bus2_cmu_info __initdata = {
3141         CMU_BUS_INFO_CLKS(2),
3142         .mux_clks               = bus2_mux_clks,
3143         .nr_mux_clks            = ARRAY_SIZE(bus2_mux_clks),
3144         .clk_regs               = bus2_clk_regs,
3145         .nr_clk_regs            = ARRAY_SIZE(bus2_clk_regs),
3146 };
3147
3148 #define exynos5433_cmu_bus_init(id)                                     \
3149 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3150 {                                                                       \
3151         samsung_cmu_register_one(np, &bus##id##_cmu_info);              \
3152 }                                                                       \
3153 CLK_OF_DECLARE(exynos5433_cmu_bus##id,                                  \
3154                 "samsung,exynos5433-cmu-bus"#id,                        \
3155                 exynos5433_cmu_bus##id##_init)
3156
3157 exynos5433_cmu_bus_init(0);
3158 exynos5433_cmu_bus_init(1);
3159 exynos5433_cmu_bus_init(2);
3160
3161 /*
3162  * Register offset definitions for CMU_G3D
3163  */
3164 #define G3D_PLL_LOCK                    0x0000
3165 #define G3D_PLL_CON0                    0x0100
3166 #define G3D_PLL_CON1                    0x0104
3167 #define G3D_PLL_FREQ_DET                0x010c
3168 #define MUX_SEL_G3D                     0x0200
3169 #define MUX_ENABLE_G3D                  0x0300
3170 #define MUX_STAT_G3D                    0x0400
3171 #define DIV_G3D                         0x0600
3172 #define DIV_G3D_PLL_FREQ_DET            0x0604
3173 #define DIV_STAT_G3D                    0x0700
3174 #define DIV_STAT_G3D_PLL_FREQ_DET       0x0704
3175 #define ENABLE_ACLK_G3D                 0x0800
3176 #define ENABLE_PCLK_G3D                 0x0900
3177 #define ENABLE_SCLK_G3D                 0x0a00
3178 #define ENABLE_IP_G3D0                  0x0b00
3179 #define ENABLE_IP_G3D1                  0x0b04
3180 #define CLKOUT_CMU_G3D                  0x0c00
3181 #define CLKOUT_CMU_G3D_DIV_STAT         0x0c04
3182 #define CLK_STOPCTRL                    0x1000
3183
3184 static unsigned long g3d_clk_regs[] __initdata = {
3185         G3D_PLL_LOCK,
3186         G3D_PLL_CON0,
3187         G3D_PLL_CON1,
3188         G3D_PLL_FREQ_DET,
3189         MUX_SEL_G3D,
3190         MUX_ENABLE_G3D,
3191         MUX_STAT_G3D,
3192         DIV_G3D,
3193         DIV_G3D_PLL_FREQ_DET,
3194         DIV_STAT_G3D,
3195         DIV_STAT_G3D_PLL_FREQ_DET,
3196         ENABLE_ACLK_G3D,
3197         ENABLE_PCLK_G3D,
3198         ENABLE_SCLK_G3D,
3199         ENABLE_IP_G3D0,
3200         ENABLE_IP_G3D1,
3201         CLKOUT_CMU_G3D,
3202         CLKOUT_CMU_G3D_DIV_STAT,
3203         CLK_STOPCTRL,
3204 };
3205
3206 /* list of all parent clock list */
3207 PNAME(mout_aclk_g3d_400_p)      = { "mout_g3d_pll", "aclk_g3d_400", };
3208 PNAME(mout_g3d_pll_p)           = { "oscclk", "fout_g3d_pll", };
3209
3210 static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
3211         PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3212                 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3213 };
3214
3215 static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3216         /* MUX_SEL_G3D */
3217         MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3218                         MUX_SEL_G3D, 8, 1),
3219         MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3220                         MUX_SEL_G3D, 0, 1),
3221 };
3222
3223 static struct samsung_div_clock g3d_div_clks[] __initdata = {
3224         /* DIV_G3D */
3225         DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3226                         8, 2),
3227         DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3228                         4, 3),
3229         DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3230                         0, 3),
3231 };
3232
3233 static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3234         /* ENABLE_ACLK_G3D */
3235         GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3236                         ENABLE_ACLK_G3D, 7, 0, 0),
3237         GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3238                         ENABLE_ACLK_G3D, 6, 0, 0),
3239         GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3240                         ENABLE_ACLK_G3D, 5, 0, 0),
3241         GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3242                         ENABLE_ACLK_G3D, 4, 0, 0),
3243         GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3244                         ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3245         GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3246                         ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3247         GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3248                         ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3249         GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3250                         ENABLE_ACLK_G3D, 0, 0, 0),
3251
3252         /* ENABLE_PCLK_G3D */
3253         GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3254                         ENABLE_PCLK_G3D, 3, 0, 0),
3255         GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3256                         ENABLE_PCLK_G3D, 2, 0, 0),
3257         GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3258                         ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3259         GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3260                         ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3261
3262         /* ENABLE_SCLK_G3D */
3263         GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3264                         ENABLE_SCLK_G3D, 0, 0, 0),
3265 };
3266
3267 static struct samsung_cmu_info g3d_cmu_info __initdata = {
3268         .pll_clks               = g3d_pll_clks,
3269         .nr_pll_clks            = ARRAY_SIZE(g3d_pll_clks),
3270         .mux_clks               = g3d_mux_clks,
3271         .nr_mux_clks            = ARRAY_SIZE(g3d_mux_clks),
3272         .div_clks               = g3d_div_clks,
3273         .nr_div_clks            = ARRAY_SIZE(g3d_div_clks),
3274         .gate_clks              = g3d_gate_clks,
3275         .nr_gate_clks           = ARRAY_SIZE(g3d_gate_clks),
3276         .nr_clk_ids             = G3D_NR_CLK,
3277         .clk_regs               = g3d_clk_regs,
3278         .nr_clk_regs            = ARRAY_SIZE(g3d_clk_regs),
3279 };
3280
3281 static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3282 {
3283         samsung_cmu_register_one(np, &g3d_cmu_info);
3284 }
3285 CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3286                 exynos5433_cmu_g3d_init);
3287
3288 /*
3289  * Register offset definitions for CMU_GSCL
3290  */
3291 #define MUX_SEL_GSCL                            0x0200
3292 #define MUX_ENABLE_GSCL                         0x0300
3293 #define MUX_STAT_GSCL                           0x0400
3294 #define ENABLE_ACLK_GSCL                        0x0800
3295 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0      0x0804
3296 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1      0x0808
3297 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2      0x080c
3298 #define ENABLE_PCLK_GSCL                        0x0900
3299 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0      0x0904
3300 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1      0x0908
3301 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2      0x090c
3302 #define ENABLE_IP_GSCL0                         0x0b00
3303 #define ENABLE_IP_GSCL1                         0x0b04
3304 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0        0x0b08
3305 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1        0x0b0c
3306 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2        0x0b10
3307
3308 static unsigned long gscl_clk_regs[] __initdata = {
3309         MUX_SEL_GSCL,
3310         MUX_ENABLE_GSCL,
3311         MUX_STAT_GSCL,
3312         ENABLE_ACLK_GSCL,
3313         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3314         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3315         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3316         ENABLE_PCLK_GSCL,
3317         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3318         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3319         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3320         ENABLE_IP_GSCL0,
3321         ENABLE_IP_GSCL1,
3322         ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3323         ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3324         ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3325 };
3326
3327 /* list of all parent clock list */
3328 PNAME(aclk_gscl_111_user_p)     = { "oscclk", "aclk_gscl_111", };
3329 PNAME(aclk_gscl_333_user_p)     = { "oscclk", "aclk_gscl_333", };
3330
3331 static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3332         /* MUX_SEL_GSCL */
3333         MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3334                         aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3335         MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3336                         aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3337 };
3338
3339 static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3340         /* ENABLE_ACLK_GSCL */
3341         GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3342                         ENABLE_ACLK_GSCL, 11, 0, 0),
3343         GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3344                         ENABLE_ACLK_GSCL, 10, 0, 0),
3345         GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3346                         ENABLE_ACLK_GSCL, 9, 0, 0),
3347         GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3348                         "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3349                         8, CLK_IGNORE_UNUSED, 0),
3350         GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3351                         ENABLE_ACLK_GSCL, 7, 0, 0),
3352         GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3353                         ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3354         GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3355                         "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
3356         GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3357                         "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
3358         GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3359                         ENABLE_ACLK_GSCL, 3, 0, 0),
3360         GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3361                         ENABLE_ACLK_GSCL, 2, 0, 0),
3362         GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3363                         ENABLE_ACLK_GSCL, 1, 0, 0),
3364         GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3365                         ENABLE_ACLK_GSCL, 0, 0, 0),
3366
3367         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3368         GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3369                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3370
3371         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3372         GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3373                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3374
3375         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3376         GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3377                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3378
3379         /* ENABLE_PCLK_GSCL */
3380         GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3381                         ENABLE_PCLK_GSCL, 7, 0, 0),
3382         GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3383                         ENABLE_PCLK_GSCL, 6, 0, 0),
3384         GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3385                         ENABLE_PCLK_GSCL, 5, 0, 0),
3386         GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3387                         ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3388         GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3389                         "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3390                         3, CLK_IGNORE_UNUSED, 0),
3391         GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3392                         ENABLE_PCLK_GSCL, 2, 0, 0),
3393         GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3394                         ENABLE_PCLK_GSCL, 1, 0, 0),
3395         GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3396                         ENABLE_PCLK_GSCL, 0, 0, 0),
3397
3398         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3399         GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3400                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3401
3402         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3403         GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3404                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3405
3406         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3407         GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3408                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3409 };
3410
3411 static struct samsung_cmu_info gscl_cmu_info __initdata = {
3412         .mux_clks               = gscl_mux_clks,
3413         .nr_mux_clks            = ARRAY_SIZE(gscl_mux_clks),
3414         .gate_clks              = gscl_gate_clks,
3415         .nr_gate_clks           = ARRAY_SIZE(gscl_gate_clks),
3416         .nr_clk_ids             = GSCL_NR_CLK,
3417         .clk_regs               = gscl_clk_regs,
3418         .nr_clk_regs            = ARRAY_SIZE(gscl_clk_regs),
3419 };
3420
3421 static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3422 {
3423         samsung_cmu_register_one(np, &gscl_cmu_info);
3424 }
3425 CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3426                 exynos5433_cmu_gscl_init);
3427
3428 /*
3429  * Register offset definitions for CMU_APOLLO
3430  */
3431 #define APOLLO_PLL_LOCK                         0x0000
3432 #define APOLLO_PLL_CON0                         0x0100
3433 #define APOLLO_PLL_CON1                         0x0104
3434 #define APOLLO_PLL_FREQ_DET                     0x010c
3435 #define MUX_SEL_APOLLO0                         0x0200
3436 #define MUX_SEL_APOLLO1                         0x0204
3437 #define MUX_SEL_APOLLO2                         0x0208
3438 #define MUX_ENABLE_APOLLO0                      0x0300
3439 #define MUX_ENABLE_APOLLO1                      0x0304
3440 #define MUX_ENABLE_APOLLO2                      0x0308
3441 #define MUX_STAT_APOLLO0                        0x0400
3442 #define MUX_STAT_APOLLO1                        0x0404
3443 #define MUX_STAT_APOLLO2                        0x0408
3444 #define DIV_APOLLO0                             0x0600
3445 #define DIV_APOLLO1                             0x0604
3446 #define DIV_APOLLO_PLL_FREQ_DET                 0x0608
3447 #define DIV_STAT_APOLLO0                        0x0700
3448 #define DIV_STAT_APOLLO1                        0x0704
3449 #define DIV_STAT_APOLLO_PLL_FREQ_DET            0x0708
3450 #define ENABLE_ACLK_APOLLO                      0x0800
3451 #define ENABLE_PCLK_APOLLO                      0x0900
3452 #define ENABLE_SCLK_APOLLO                      0x0a00
3453 #define ENABLE_IP_APOLLO0                       0x0b00
3454 #define ENABLE_IP_APOLLO1                       0x0b04
3455 #define CLKOUT_CMU_APOLLO                       0x0c00
3456 #define CLKOUT_CMU_APOLLO_DIV_STAT              0x0c04
3457 #define ARMCLK_STOPCTRL                         0x1000
3458 #define APOLLO_PWR_CTRL                         0x1020
3459 #define APOLLO_PWR_CTRL2                        0x1024
3460 #define APOLLO_INTR_SPREAD_ENABLE               0x1080
3461 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI       0x1084
3462 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION    0x1088
3463
3464 static unsigned long apollo_clk_regs[] __initdata = {
3465         APOLLO_PLL_LOCK,
3466         APOLLO_PLL_CON0,
3467         APOLLO_PLL_CON1,
3468         APOLLO_PLL_FREQ_DET,
3469         MUX_SEL_APOLLO0,
3470         MUX_SEL_APOLLO1,
3471         MUX_SEL_APOLLO2,
3472         MUX_ENABLE_APOLLO0,
3473         MUX_ENABLE_APOLLO1,
3474         MUX_ENABLE_APOLLO2,
3475         MUX_STAT_APOLLO0,
3476         MUX_STAT_APOLLO1,
3477         MUX_STAT_APOLLO2,
3478         DIV_APOLLO0,
3479         DIV_APOLLO1,
3480         DIV_APOLLO_PLL_FREQ_DET,
3481         DIV_STAT_APOLLO0,
3482         DIV_STAT_APOLLO1,
3483         DIV_STAT_APOLLO_PLL_FREQ_DET,
3484         ENABLE_ACLK_APOLLO,
3485         ENABLE_PCLK_APOLLO,
3486         ENABLE_SCLK_APOLLO,
3487         ENABLE_IP_APOLLO0,
3488         ENABLE_IP_APOLLO1,
3489         CLKOUT_CMU_APOLLO,
3490         CLKOUT_CMU_APOLLO_DIV_STAT,
3491         ARMCLK_STOPCTRL,
3492         APOLLO_PWR_CTRL,
3493         APOLLO_PWR_CTRL2,
3494         APOLLO_INTR_SPREAD_ENABLE,
3495         APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3496         APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3497 };
3498
3499 /* list of all parent clock list */
3500 PNAME(mout_apollo_pll_p)                = { "oscclk", "fout_apollo_pll", };
3501 PNAME(mout_bus_pll_apollo_user_p)       = { "oscclk", "sclk_bus_pll_apollo", };
3502 PNAME(mout_apollo_p)                    = { "mout_apollo_pll",
3503                                             "mout_bus_pll_apollo_user", };
3504
3505 static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
3506         PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3507                 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3508 };
3509
3510 static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3511         /* MUX_SEL_APOLLO0 */
3512         MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3513                         MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY),
3514
3515         /* MUX_SEL_APOLLO1 */
3516         MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3517                         mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3518
3519         /* MUX_SEL_APOLLO2 */
3520         MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3521                         0, 1, 0, CLK_MUX_READ_ONLY),
3522 };
3523
3524 static struct samsung_div_clock apollo_div_clks[] __initdata = {
3525         /* DIV_APOLLO0 */
3526         DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3527                         DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3528                         CLK_DIVIDER_READ_ONLY),
3529         DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3530                         DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3531                         CLK_DIVIDER_READ_ONLY),
3532         DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3533                         DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3534                         CLK_DIVIDER_READ_ONLY),
3535         DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3536                         DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3537                         CLK_DIVIDER_READ_ONLY),
3538         DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3539                         DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3540                         CLK_DIVIDER_READ_ONLY),
3541         DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3542                         DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE,
3543                         CLK_DIVIDER_READ_ONLY),
3544         DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3545                         DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE,
3546                         CLK_DIVIDER_READ_ONLY),
3547
3548         /* DIV_APOLLO1 */
3549         DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3550                         DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3551                         CLK_DIVIDER_READ_ONLY),
3552         DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3553                         DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3554                         CLK_DIVIDER_READ_ONLY),
3555 };
3556
3557 static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3558         /* ENABLE_ACLK_APOLLO */
3559         GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3560                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3561                         6, CLK_IGNORE_UNUSED, 0),
3562         GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3563                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3564                         5, CLK_IGNORE_UNUSED, 0),
3565         GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3566                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3567                         4, CLK_IGNORE_UNUSED, 0),
3568         GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3569                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3570                         3, CLK_IGNORE_UNUSED, 0),
3571         GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3572                         "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3573                         2, CLK_IGNORE_UNUSED, 0),
3574         GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3575                         "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3576                         1, CLK_IGNORE_UNUSED, 0),
3577         GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3578                         "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3579                         0, CLK_IGNORE_UNUSED, 0),
3580
3581         /* ENABLE_PCLK_APOLLO */
3582         GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3583                         "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3584                         2, CLK_IGNORE_UNUSED, 0),
3585         GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3586                         ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3587         GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3588                         "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3589                         0, CLK_IGNORE_UNUSED, 0),
3590
3591         /* ENABLE_SCLK_APOLLO */
3592         GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3593                         ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3594         GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3595                         ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3596         GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll",
3597                         ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0),
3598 };
3599
3600 static struct samsung_cmu_info apollo_cmu_info __initdata = {
3601         .pll_clks               = apollo_pll_clks,
3602         .nr_pll_clks            = ARRAY_SIZE(apollo_pll_clks),
3603         .mux_clks               = apollo_mux_clks,
3604         .nr_mux_clks            = ARRAY_SIZE(apollo_mux_clks),
3605         .div_clks               = apollo_div_clks,
3606         .nr_div_clks            = ARRAY_SIZE(apollo_div_clks),
3607         .gate_clks              = apollo_gate_clks,
3608         .nr_gate_clks           = ARRAY_SIZE(apollo_gate_clks),
3609         .nr_clk_ids             = APOLLO_NR_CLK,
3610         .clk_regs               = apollo_clk_regs,
3611         .nr_clk_regs            = ARRAY_SIZE(apollo_clk_regs),
3612 };
3613
3614 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3615 {
3616         samsung_cmu_register_one(np, &apollo_cmu_info);
3617 }
3618 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3619                 exynos5433_cmu_apollo_init);
3620
3621 /*
3622  * Register offset definitions for CMU_ATLAS
3623  */
3624 #define ATLAS_PLL_LOCK                          0x0000
3625 #define ATLAS_PLL_CON0                          0x0100
3626 #define ATLAS_PLL_CON1                          0x0104
3627 #define ATLAS_PLL_FREQ_DET                      0x010c
3628 #define MUX_SEL_ATLAS0                          0x0200
3629 #define MUX_SEL_ATLAS1                          0x0204
3630 #define MUX_SEL_ATLAS2                          0x0208
3631 #define MUX_ENABLE_ATLAS0                       0x0300
3632 #define MUX_ENABLE_ATLAS1                       0x0304
3633 #define MUX_ENABLE_ATLAS2                       0x0308
3634 #define MUX_STAT_ATLAS0                         0x0400
3635 #define MUX_STAT_ATLAS1                         0x0404
3636 #define MUX_STAT_ATLAS2                         0x0408
3637 #define DIV_ATLAS0                              0x0600
3638 #define DIV_ATLAS1                              0x0604
3639 #define DIV_ATLAS_PLL_FREQ_DET                  0x0608
3640 #define DIV_STAT_ATLAS0                         0x0700
3641 #define DIV_STAT_ATLAS1                         0x0704
3642 #define DIV_STAT_ATLAS_PLL_FREQ_DET             0x0708
3643 #define ENABLE_ACLK_ATLAS                       0x0800
3644 #define ENABLE_PCLK_ATLAS                       0x0900
3645 #define ENABLE_SCLK_ATLAS                       0x0a00
3646 #define ENABLE_IP_ATLAS0                        0x0b00
3647 #define ENABLE_IP_ATLAS1                        0x0b04
3648 #define CLKOUT_CMU_ATLAS                        0x0c00
3649 #define CLKOUT_CMU_ATLAS_DIV_STAT               0x0c04
3650 #define ARMCLK_STOPCTRL                         0x1000
3651 #define ATLAS_PWR_CTRL                          0x1020
3652 #define ATLAS_PWR_CTRL2                         0x1024
3653 #define ATLAS_INTR_SPREAD_ENABLE                0x1080
3654 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI        0x1084
3655 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION     0x1088
3656
3657 static unsigned long atlas_clk_regs[] __initdata = {
3658         ATLAS_PLL_LOCK,
3659         ATLAS_PLL_CON0,
3660         ATLAS_PLL_CON1,
3661         ATLAS_PLL_FREQ_DET,
3662         MUX_SEL_ATLAS0,
3663         MUX_SEL_ATLAS1,
3664         MUX_SEL_ATLAS2,
3665         MUX_ENABLE_ATLAS0,
3666         MUX_ENABLE_ATLAS1,
3667         MUX_ENABLE_ATLAS2,
3668         MUX_STAT_ATLAS0,
3669         MUX_STAT_ATLAS1,
3670         MUX_STAT_ATLAS2,
3671         DIV_ATLAS0,
3672         DIV_ATLAS1,
3673         DIV_ATLAS_PLL_FREQ_DET,
3674         DIV_STAT_ATLAS0,
3675         DIV_STAT_ATLAS1,
3676         DIV_STAT_ATLAS_PLL_FREQ_DET,
3677         ENABLE_ACLK_ATLAS,
3678         ENABLE_PCLK_ATLAS,
3679         ENABLE_SCLK_ATLAS,
3680         ENABLE_IP_ATLAS0,
3681         ENABLE_IP_ATLAS1,
3682         CLKOUT_CMU_ATLAS,
3683         CLKOUT_CMU_ATLAS_DIV_STAT,
3684         ARMCLK_STOPCTRL,
3685         ATLAS_PWR_CTRL,
3686         ATLAS_PWR_CTRL2,
3687         ATLAS_INTR_SPREAD_ENABLE,
3688         ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3689         ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3690 };
3691
3692 /* list of all parent clock list */
3693 PNAME(mout_atlas_pll_p)                 = { "oscclk", "fout_atlas_pll", };
3694 PNAME(mout_bus_pll_atlas_user_p)        = { "oscclk", "sclk_bus_pll_atlas", };
3695 PNAME(mout_atlas_p)                     = { "mout_atlas_pll",
3696                                             "mout_bus_pll_atlas_user", };
3697
3698 static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
3699         PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3700                 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3701 };
3702
3703 static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3704         /* MUX_SEL_ATLAS0 */
3705         MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3706                         MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY),
3707
3708         /* MUX_SEL_ATLAS1 */
3709         MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3710                         mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3711
3712         /* MUX_SEL_ATLAS2 */
3713         MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3714                         0, 1, 0, CLK_MUX_READ_ONLY),
3715 };
3716
3717 static struct samsung_div_clock atlas_div_clks[] __initdata = {
3718         /* DIV_ATLAS0 */
3719         DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3720                         DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3721                         CLK_DIVIDER_READ_ONLY),
3722         DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3723                         DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3724                         CLK_DIVIDER_READ_ONLY),
3725         DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3726                         DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3727                         CLK_DIVIDER_READ_ONLY),
3728         DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3729                         DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3730                         CLK_DIVIDER_READ_ONLY),
3731         DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3732                         DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3733                         CLK_DIVIDER_READ_ONLY),
3734         DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3735                         DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE,
3736                         CLK_DIVIDER_READ_ONLY),
3737         DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3738                         DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE,
3739                         CLK_DIVIDER_READ_ONLY),
3740
3741         /* DIV_ATLAS1 */
3742         DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3743                         DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3744                         CLK_DIVIDER_READ_ONLY),
3745         DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3746                         DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3747                         CLK_DIVIDER_READ_ONLY),
3748 };
3749
3750 static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3751         /* ENABLE_ACLK_ATLAS */
3752         GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3753                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3754                         9, CLK_IGNORE_UNUSED, 0),
3755         GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3756                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3757                         8, CLK_IGNORE_UNUSED, 0),
3758         GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3759                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3760                         7, CLK_IGNORE_UNUSED, 0),
3761         GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3762                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3763                         6, CLK_IGNORE_UNUSED, 0),
3764         GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3765                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3766                         5, CLK_IGNORE_UNUSED, 0),
3767         GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3768                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3769                         4, CLK_IGNORE_UNUSED, 0),
3770         GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3771                         "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3772                         3, CLK_IGNORE_UNUSED, 0),
3773         GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3774                         "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3775                         2, CLK_IGNORE_UNUSED, 0),
3776         GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3777                         ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3778         GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3779                         ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3780
3781         /* ENABLE_PCLK_ATLAS */
3782         GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3783                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3784                         5, CLK_IGNORE_UNUSED, 0),
3785         GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3786                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3787                         4, CLK_IGNORE_UNUSED, 0),
3788         GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3789                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3790                         3, CLK_IGNORE_UNUSED, 0),
3791         GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3792                         ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3793         GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3794                         ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3795         GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3796                         ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3797
3798         /* ENABLE_SCLK_ATLAS */
3799         GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3800                         ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3801         GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3802                         ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3803         GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3804                         ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3805         GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3806                         ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3807         GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3808                         ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3809         GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3810                         ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3811         GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3812                         ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3813         GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3814                         ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3815         GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3816                         ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3817 };
3818
3819 static struct samsung_cmu_info atlas_cmu_info __initdata = {
3820         .pll_clks               = atlas_pll_clks,
3821         .nr_pll_clks            = ARRAY_SIZE(atlas_pll_clks),
3822         .mux_clks               = atlas_mux_clks,
3823         .nr_mux_clks            = ARRAY_SIZE(atlas_mux_clks),
3824         .div_clks               = atlas_div_clks,
3825         .nr_div_clks            = ARRAY_SIZE(atlas_div_clks),
3826         .gate_clks              = atlas_gate_clks,
3827         .nr_gate_clks           = ARRAY_SIZE(atlas_gate_clks),
3828         .nr_clk_ids             = ATLAS_NR_CLK,
3829         .clk_regs               = atlas_clk_regs,
3830         .nr_clk_regs            = ARRAY_SIZE(atlas_clk_regs),
3831 };
3832
3833 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3834 {
3835         samsung_cmu_register_one(np, &atlas_cmu_info);
3836 }
3837 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3838                 exynos5433_cmu_atlas_init);
3839
3840 /*
3841  * Register offset definitions for CMU_MSCL
3842  */
3843 #define MUX_SEL_MSCL0                                   0x0200
3844 #define MUX_SEL_MSCL1                                   0x0204
3845 #define MUX_ENABLE_MSCL0                                0x0300
3846 #define MUX_ENABLE_MSCL1                                0x0304
3847 #define MUX_STAT_MSCL0                                  0x0400
3848 #define MUX_STAT_MSCL1                                  0x0404
3849 #define DIV_MSCL                                        0x0600
3850 #define DIV_STAT_MSCL                                   0x0700
3851 #define ENABLE_ACLK_MSCL                                0x0800
3852 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0804
3853 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0808
3854 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG               0x080c
3855 #define ENABLE_PCLK_MSCL                                0x0900
3856 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0904
3857 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0908
3858 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG               0x000c
3859 #define ENABLE_SCLK_MSCL                                0x0a00
3860 #define ENABLE_IP_MSCL0                                 0x0b00
3861 #define ENABLE_IP_MSCL1                                 0x0b04
3862 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0           0x0b08
3863 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1           0x0b0c
3864 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG                 0x0b10
3865
3866 static unsigned long mscl_clk_regs[] __initdata = {
3867         MUX_SEL_MSCL0,
3868         MUX_SEL_MSCL1,
3869         MUX_ENABLE_MSCL0,
3870         MUX_ENABLE_MSCL1,
3871         MUX_STAT_MSCL0,
3872         MUX_STAT_MSCL1,
3873         DIV_MSCL,
3874         DIV_STAT_MSCL,
3875         ENABLE_ACLK_MSCL,
3876         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3877         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3878         ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3879         ENABLE_PCLK_MSCL,
3880         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3881         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3882         ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3883         ENABLE_SCLK_MSCL,
3884         ENABLE_IP_MSCL0,
3885         ENABLE_IP_MSCL1,
3886         ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3887         ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3888         ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3889 };
3890
3891 /* list of all parent clock list */
3892 PNAME(mout_sclk_jpeg_user_p)            = { "oscclk", "sclk_jpeg_mscl", };
3893 PNAME(mout_aclk_mscl_400_user_p)        = { "oscclk", "aclk_mscl_400", };
3894 PNAME(mout_sclk_jpeg_p)                 = { "mout_sclk_jpeg_user",
3895                                         "mout_aclk_mscl_400_user", };
3896
3897 static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
3898         /* MUX_SEL_MSCL0 */
3899         MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3900                         mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
3901         MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
3902                         mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
3903
3904         /* MUX_SEL_MSCL1 */
3905         MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
3906                         MUX_SEL_MSCL1, 0, 1),
3907 };
3908
3909 static struct samsung_div_clock mscl_div_clks[] __initdata = {
3910         /* DIV_MSCL */
3911         DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3912                         DIV_MSCL, 0, 3),
3913 };
3914
3915 static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
3916         /* ENABLE_ACLK_MSCL */
3917         GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3918                         ENABLE_ACLK_MSCL, 9, 0, 0),
3919         GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
3920                         "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
3921         GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
3922                         "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
3923         GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
3924                         ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
3925         GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
3926                         ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
3927         GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
3928                         ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3929         GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
3930                         ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
3931         GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
3932                         ENABLE_ACLK_MSCL, 2, 0, 0),
3933         GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
3934                         ENABLE_ACLK_MSCL, 1, 0, 0),
3935         GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
3936                         ENABLE_ACLK_MSCL, 0, 0, 0),
3937
3938         /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
3939         GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
3940                         "mout_aclk_mscl_400_user",
3941                         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3942                         0, CLK_IGNORE_UNUSED, 0),
3943
3944         /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
3945         GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
3946                         "mout_aclk_mscl_400_user",
3947                         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3948                         0, CLK_IGNORE_UNUSED, 0),
3949
3950         /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
3951         GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
3952                         ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3953                         0, CLK_IGNORE_UNUSED, 0),
3954
3955         /* ENABLE_PCLK_MSCL */
3956         GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
3957                         ENABLE_PCLK_MSCL, 7, 0, 0),
3958         GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
3959                         ENABLE_PCLK_MSCL, 6, 0, 0),
3960         GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
3961                         ENABLE_PCLK_MSCL, 5, 0, 0),
3962         GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
3963                         ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3964         GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
3965                         ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
3966         GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
3967                         ENABLE_PCLK_MSCL, 2, 0, 0),
3968         GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
3969                         ENABLE_PCLK_MSCL, 1, 0, 0),
3970         GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
3971                         ENABLE_PCLK_MSCL, 0, 0, 0),
3972
3973         /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
3974         GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
3975                         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3976                         0, CLK_IGNORE_UNUSED, 0),
3977
3978         /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
3979         GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
3980                         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3981                         0, CLK_IGNORE_UNUSED, 0),
3982
3983         /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
3984         GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
3985                         ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3986                         0, CLK_IGNORE_UNUSED, 0),
3987
3988         /* ENABLE_SCLK_MSCL */
3989         GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
3990                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3991 };
3992
3993 static struct samsung_cmu_info mscl_cmu_info __initdata = {
3994         .mux_clks               = mscl_mux_clks,
3995         .nr_mux_clks            = ARRAY_SIZE(mscl_mux_clks),
3996         .div_clks               = mscl_div_clks,
3997         .nr_div_clks            = ARRAY_SIZE(mscl_div_clks),
3998         .gate_clks              = mscl_gate_clks,
3999         .nr_gate_clks           = ARRAY_SIZE(mscl_gate_clks),
4000         .nr_clk_ids             = MSCL_NR_CLK,
4001         .clk_regs               = mscl_clk_regs,
4002         .nr_clk_regs            = ARRAY_SIZE(mscl_clk_regs),
4003 };
4004
4005 static void __init exynos5433_cmu_mscl_init(struct device_node *np)
4006 {
4007         samsung_cmu_register_one(np, &mscl_cmu_info);
4008 }
4009 CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4010                 exynos5433_cmu_mscl_init);
4011
4012 /*
4013  * Register offset definitions for CMU_MFC
4014  */
4015 #define MUX_SEL_MFC                             0x0200
4016 #define MUX_ENABLE_MFC                          0x0300
4017 #define MUX_STAT_MFC                            0x0400
4018 #define DIV_MFC                                 0x0600
4019 #define DIV_STAT_MFC                            0x0700
4020 #define ENABLE_ACLK_MFC                         0x0800
4021 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC         0x0804
4022 #define ENABLE_PCLK_MFC                         0x0900
4023 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC         0x0904
4024 #define ENABLE_IP_MFC0                          0x0b00
4025 #define ENABLE_IP_MFC1                          0x0b04
4026 #define ENABLE_IP_MFC_SECURE_SMMU_MFC           0x0b08
4027
4028 static unsigned long mfc_clk_regs[] __initdata = {
4029         MUX_SEL_MFC,
4030         MUX_ENABLE_MFC,
4031         MUX_STAT_MFC,
4032         DIV_MFC,
4033         DIV_STAT_MFC,
4034         ENABLE_ACLK_MFC,
4035         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4036         ENABLE_PCLK_MFC,
4037         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4038         ENABLE_IP_MFC0,
4039         ENABLE_IP_MFC1,
4040         ENABLE_IP_MFC_SECURE_SMMU_MFC,
4041 };
4042
4043 PNAME(mout_aclk_mfc_400_user_p)         = { "oscclk", "aclk_mfc_400", };
4044
4045 static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
4046         /* MUX_SEL_MFC */
4047         MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4048                         mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4049 };
4050
4051 static struct samsung_div_clock mfc_div_clks[] __initdata = {
4052         /* DIV_MFC */
4053         DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4054                         DIV_MFC, 0, 2),
4055 };
4056
4057 static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4058         /* ENABLE_ACLK_MFC */
4059         GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4060                         ENABLE_ACLK_MFC, 6, 0, 0),
4061         GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4062                         ENABLE_ACLK_MFC, 5, 0, 0),
4063         GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4064                         ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4065         GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4066                         ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4067         GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4068                         ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4069         GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4070                         ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4071         GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4072                         ENABLE_ACLK_MFC, 0, 0, 0),
4073
4074         /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4075         GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4076                         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4077                         1, CLK_IGNORE_UNUSED, 0),
4078         GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4079                         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4080                         0, CLK_IGNORE_UNUSED, 0),
4081
4082         /* ENABLE_PCLK_MFC */
4083         GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4084                         ENABLE_PCLK_MFC, 4, 0, 0),
4085         GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4086                         ENABLE_PCLK_MFC, 3, 0, 0),
4087         GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4088                         ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4089         GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4090                         ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4091         GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4092                         ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4093
4094         /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4095         GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4096                         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4097                         1, CLK_IGNORE_UNUSED, 0),
4098         GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4099                         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4100                         0, CLK_IGNORE_UNUSED, 0),
4101 };
4102
4103 static struct samsung_cmu_info mfc_cmu_info __initdata = {
4104         .mux_clks               = mfc_mux_clks,
4105         .nr_mux_clks            = ARRAY_SIZE(mfc_mux_clks),
4106         .div_clks               = mfc_div_clks,
4107         .nr_div_clks            = ARRAY_SIZE(mfc_div_clks),
4108         .gate_clks              = mfc_gate_clks,
4109         .nr_gate_clks           = ARRAY_SIZE(mfc_gate_clks),
4110         .nr_clk_ids             = MFC_NR_CLK,
4111         .clk_regs               = mfc_clk_regs,
4112         .nr_clk_regs            = ARRAY_SIZE(mfc_clk_regs),
4113 };
4114
4115 static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4116 {
4117         samsung_cmu_register_one(np, &mfc_cmu_info);
4118 }
4119 CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4120                 exynos5433_cmu_mfc_init);
4121
4122 /*
4123  * Register offset definitions for CMU_HEVC
4124  */
4125 #define MUX_SEL_HEVC                            0x0200
4126 #define MUX_ENABLE_HEVC                         0x0300
4127 #define MUX_STAT_HEVC                           0x0400
4128 #define DIV_HEVC                                0x0600
4129 #define DIV_STAT_HEVC                           0x0700
4130 #define ENABLE_ACLK_HEVC                        0x0800
4131 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC       0x0804
4132 #define ENABLE_PCLK_HEVC                        0x0900
4133 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC       0x0904
4134 #define ENABLE_IP_HEVC0                         0x0b00
4135 #define ENABLE_IP_HEVC1                         0x0b04
4136 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC         0x0b08
4137
4138 static unsigned long hevc_clk_regs[] __initdata = {
4139         MUX_SEL_HEVC,
4140         MUX_ENABLE_HEVC,
4141         MUX_STAT_HEVC,
4142         DIV_HEVC,
4143         DIV_STAT_HEVC,
4144         ENABLE_ACLK_HEVC,
4145         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4146         ENABLE_PCLK_HEVC,
4147         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4148         ENABLE_IP_HEVC0,
4149         ENABLE_IP_HEVC1,
4150         ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4151 };
4152
4153 PNAME(mout_aclk_hevc_400_user_p)        = { "oscclk", "aclk_hevc_400", };
4154
4155 static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
4156         /* MUX_SEL_HEVC */
4157         MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4158                         mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4159 };
4160
4161 static struct samsung_div_clock hevc_div_clks[] __initdata = {
4162         /* DIV_HEVC */
4163         DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4164                         DIV_HEVC, 0, 2),
4165 };
4166
4167 static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
4168         /* ENABLE_ACLK_HEVC */
4169         GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4170                         ENABLE_ACLK_HEVC, 6, 0, 0),
4171         GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4172                         ENABLE_ACLK_HEVC, 5, 0, 0),
4173         GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4174                         ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4175         GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4176                         ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4177         GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4178                         ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4179         GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4180                         ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4181         GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4182                         ENABLE_ACLK_HEVC, 0, 0, 0),
4183
4184         /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4185         GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4186                         "mout_aclk_hevc_400_user",
4187                         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4188                         1, CLK_IGNORE_UNUSED, 0),
4189         GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4190                         "mout_aclk_hevc_400_user",
4191                         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4192                         0, CLK_IGNORE_UNUSED, 0),
4193
4194         /* ENABLE_PCLK_HEVC */
4195         GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4196                         ENABLE_PCLK_HEVC, 4, 0, 0),
4197         GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4198                         ENABLE_PCLK_HEVC, 3, 0, 0),
4199         GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4200                         ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4201         GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4202                         ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4203         GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4204                         ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4205
4206         /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4207         GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4208                         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4209                         1, CLK_IGNORE_UNUSED, 0),
4210         GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4211                         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4212                         0, CLK_IGNORE_UNUSED, 0),
4213 };
4214
4215 static struct samsung_cmu_info hevc_cmu_info __initdata = {
4216         .mux_clks               = hevc_mux_clks,
4217         .nr_mux_clks            = ARRAY_SIZE(hevc_mux_clks),
4218         .div_clks               = hevc_div_clks,
4219         .nr_div_clks            = ARRAY_SIZE(hevc_div_clks),
4220         .gate_clks              = hevc_gate_clks,
4221         .nr_gate_clks           = ARRAY_SIZE(hevc_gate_clks),
4222         .nr_clk_ids             = HEVC_NR_CLK,
4223         .clk_regs               = hevc_clk_regs,
4224         .nr_clk_regs            = ARRAY_SIZE(hevc_clk_regs),
4225 };
4226
4227 static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4228 {
4229         samsung_cmu_register_one(np, &hevc_cmu_info);
4230 }
4231 CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4232                 exynos5433_cmu_hevc_init);
4233
4234 /*
4235  * Register offset definitions for CMU_ISP
4236  */
4237 #define MUX_SEL_ISP                     0x0200
4238 #define MUX_ENABLE_ISP                  0x0300
4239 #define MUX_STAT_ISP                    0x0400
4240 #define DIV_ISP                         0x0600
4241 #define DIV_STAT_ISP                    0x0700
4242 #define ENABLE_ACLK_ISP0                0x0800
4243 #define ENABLE_ACLK_ISP1                0x0804
4244 #define ENABLE_ACLK_ISP2                0x0808
4245 #define ENABLE_PCLK_ISP                 0x0900
4246 #define ENABLE_SCLK_ISP                 0x0a00
4247 #define ENABLE_IP_ISP0                  0x0b00
4248 #define ENABLE_IP_ISP1                  0x0b04
4249 #define ENABLE_IP_ISP2                  0x0b08
4250 #define ENABLE_IP_ISP3                  0x0b0c
4251
4252 static unsigned long isp_clk_regs[] __initdata = {
4253         MUX_SEL_ISP,
4254         MUX_ENABLE_ISP,
4255         MUX_STAT_ISP,
4256         DIV_ISP,
4257         DIV_STAT_ISP,
4258         ENABLE_ACLK_ISP0,
4259         ENABLE_ACLK_ISP1,
4260         ENABLE_ACLK_ISP2,
4261         ENABLE_PCLK_ISP,
4262         ENABLE_SCLK_ISP,
4263         ENABLE_IP_ISP0,
4264         ENABLE_IP_ISP1,
4265         ENABLE_IP_ISP2,
4266         ENABLE_IP_ISP3,
4267 };
4268
4269 PNAME(mout_aclk_isp_dis_400_user_p)     = { "oscclk", "aclk_isp_dis_400", };
4270 PNAME(mout_aclk_isp_400_user_p)         = { "oscclk", "aclk_isp_400", };
4271
4272 static struct samsung_mux_clock isp_mux_clks[] __initdata = {
4273         /* MUX_SEL_ISP */
4274         MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4275                         mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4276         MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4277                         mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4278 };
4279
4280 static struct samsung_div_clock isp_div_clks[] __initdata = {
4281         /* DIV_ISP */
4282         DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4283                         "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4284         DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4285                         DIV_ISP, 8, 3),
4286         DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4287                         "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4288         DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4289                         "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4290 };
4291
4292 static struct samsung_gate_clock isp_gate_clks[] __initdata = {
4293         /* ENABLE_ACLK_ISP0 */
4294         GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4295                         ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4296         GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4297                         ENABLE_ACLK_ISP0, 5, 0, 0),
4298         GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4299                         ENABLE_ACLK_ISP0, 4, 0, 0),
4300         GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4301                         ENABLE_ACLK_ISP0, 3, 0, 0),
4302         GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4303                         ENABLE_ACLK_ISP0, 2, 0, 0),
4304         GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4305                         ENABLE_ACLK_ISP0, 1, 0, 0),
4306         GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4307                         ENABLE_ACLK_ISP0, 0, 0, 0),
4308
4309         /* ENABLE_ACLK_ISP1 */
4310         GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4311                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4312                         17, CLK_IGNORE_UNUSED, 0),
4313         GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4314                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4315                         16, CLK_IGNORE_UNUSED, 0),
4316         GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4317                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4318                         15, CLK_IGNORE_UNUSED, 0),
4319         GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4320                         "div_pclk_isp", ENABLE_ACLK_ISP1,
4321                         14, CLK_IGNORE_UNUSED, 0),
4322         GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4323                         "div_pclk_isp", ENABLE_ACLK_ISP1,
4324                         13, CLK_IGNORE_UNUSED, 0),
4325         GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4326                         "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4327                         12, CLK_IGNORE_UNUSED, 0),
4328         GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4329                         "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4330                         11, CLK_IGNORE_UNUSED, 0),
4331         GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4332                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4333                         10, CLK_IGNORE_UNUSED, 0),
4334         GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4335                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4336                         9, CLK_IGNORE_UNUSED, 0),
4337         GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4338                         "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4339                         8, CLK_IGNORE_UNUSED, 0),
4340         GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4341                         "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4342                         7, CLK_IGNORE_UNUSED, 0),
4343         GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4344                         ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4345         GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4346                         ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4347         GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4348                         "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4349                         4, CLK_IGNORE_UNUSED, 0),
4350         GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4351                         "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4352                         3, CLK_IGNORE_UNUSED, 0),
4353         GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4354                         ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4355         GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4356                         ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4357         GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4358                         ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4359
4360         /* ENABLE_ACLK_ISP2 */
4361         GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4362                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4363                         13, CLK_IGNORE_UNUSED, 0),
4364         GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4365                         ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4366         GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4367                         ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4368         GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4369                         ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4370         GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4371                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4372                         9, CLK_IGNORE_UNUSED, 0),
4373         GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4374                         ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4375         GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4376                         ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4377         GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4378                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4379                         6, CLK_IGNORE_UNUSED, 0),
4380         GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4381                         ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4382         GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4383                         ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4384         GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4385                         ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4386         GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4387                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4388                         2, CLK_IGNORE_UNUSED, 0),
4389         GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4390                         ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4391         GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4392                         ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4393
4394         /* ENABLE_PCLK_ISP */
4395         GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4396                         ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4397         GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4398                         ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4399         GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4400                         ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4401         GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4402                         ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4403         GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4404                         ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4405         GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4406                         ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4407         GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4408                         ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4409         GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4410                         ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4411         GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4412                         ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4413         GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4414                         ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4415         GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4416                         ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4417         GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4418                         ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4419         GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4420                         ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4421         GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4422                         ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4423         GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4424                         ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4425         GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4426                         ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4427         GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4428                         ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4429         GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4430                         ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4431         GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4432                         "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4433                         7, CLK_IGNORE_UNUSED, 0),
4434         GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4435                         ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4436         GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4437                         ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4438         GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4439                         ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4440         GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4441                         ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4442         GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4443                         ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4444         GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4445                         ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4446         GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4447                         ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4448
4449         /* ENABLE_SCLK_ISP */
4450         GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4451                         "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4452                         5, CLK_IGNORE_UNUSED, 0),
4453         GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4454                         "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4455                         4, CLK_IGNORE_UNUSED, 0),
4456         GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4457                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4458                         3, CLK_IGNORE_UNUSED, 0),
4459         GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4460                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4461                         2, CLK_IGNORE_UNUSED, 0),
4462         GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4463                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4464                         1, CLK_IGNORE_UNUSED, 0),
4465         GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4466                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4467                         0, CLK_IGNORE_UNUSED, 0),
4468 };
4469
4470 static struct samsung_cmu_info isp_cmu_info __initdata = {
4471         .mux_clks               = isp_mux_clks,
4472         .nr_mux_clks            = ARRAY_SIZE(isp_mux_clks),
4473         .div_clks               = isp_div_clks,
4474         .nr_div_clks            = ARRAY_SIZE(isp_div_clks),
4475         .gate_clks              = isp_gate_clks,
4476         .nr_gate_clks           = ARRAY_SIZE(isp_gate_clks),
4477         .nr_clk_ids             = ISP_NR_CLK,
4478         .clk_regs               = isp_clk_regs,
4479         .nr_clk_regs            = ARRAY_SIZE(isp_clk_regs),
4480 };
4481
4482 static void __init exynos5433_cmu_isp_init(struct device_node *np)
4483 {
4484         samsung_cmu_register_one(np, &isp_cmu_info);
4485 }
4486 CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4487                 exynos5433_cmu_isp_init);