drivers/clk/rockchip/clk.h

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * based on
   9  *
  10  * samsung/clk.h
  11  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  12  * Copyright (c) 2013 Linaro Ltd.
  13  * Author: Thomas Abraham <thomas.ab@samsung.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #ifndef CLK_ROCKCHIP_CLK_H
  27 #define CLK_ROCKCHIP_CLK_H
  28
  29 #include <linux/io.h>
  30 #include <linux/clk-provider.h>
  31
  32 struct clk;
  33
  34 #define HIWORD_UPDATE(val, mask, shift) \
  35                 ((val) << (shift) | (mask) << ((shift) + 16))
  36
  37 /* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
  38 #define RK2928_PLL_CON(x)               ((x) * 0x4)
  39 #define RK2928_MODE_CON         0x40
  40 #define RK2928_CLKSEL_CON(x)    ((x) * 0x4 + 0x44)
  41 #define RK2928_CLKGATE_CON(x)   ((x) * 0x4 + 0xd0)
  42 #define RK2928_GLB_SRST_FST             0x100
  43 #define RK2928_GLB_SRST_SND             0x104
  44 #define RK2928_SOFTRST_CON(x)   ((x) * 0x4 + 0x110)
  45 #define RK2928_MISC_CON         0x134
  46
  47 #define RK3036_SDMMC_CON0               0x144
  48 #define RK3036_SDMMC_CON1               0x148
  49 #define RK3036_SDIO_CON0                0x14c
  50 #define RK3036_SDIO_CON1                0x150
  51 #define RK3036_EMMC_CON0                0x154
  52 #define RK3036_EMMC_CON1                0x158
  53
  54 #define RK3228_GLB_SRST_FST             0x1f0
  55 #define RK3228_GLB_SRST_SND             0x1f4
  56 #define RK3228_SDMMC_CON0               0x1c0
  57 #define RK3228_SDMMC_CON1               0x1c4
  58 #define RK3228_SDIO_CON0                0x1c8
  59 #define RK3228_SDIO_CON1                0x1cc
  60 #define RK3228_EMMC_CON0                0x1d8
  61 #define RK3228_EMMC_CON1                0x1dc
  62
  63 #define RK3288_PLL_CON(x)               RK2928_PLL_CON(x)
  64 #define RK3288_MODE_CON                 0x50
  65 #define RK3288_CLKSEL_CON(x)            ((x) * 0x4 + 0x60)
  66 #define RK3288_CLKGATE_CON(x)           ((x) * 0x4 + 0x160)
  67 #define RK3288_GLB_SRST_FST             0x1b0
  68 #define RK3288_GLB_SRST_SND             0x1b4
  69 #define RK3288_SOFTRST_CON(x)           ((x) * 0x4 + 0x1b8)
  70 #define RK3288_MISC_CON                 0x1e8
  71 #define RK3288_SDMMC_CON0               0x200
  72 #define RK3288_SDMMC_CON1               0x204
  73 #define RK3288_SDIO0_CON0               0x208
  74 #define RK3288_SDIO0_CON1               0x20c
  75 #define RK3288_SDIO1_CON0               0x210
  76 #define RK3288_SDIO1_CON1               0x214
  77 #define RK3288_EMMC_CON0                0x218
  78 #define RK3288_EMMC_CON1                0x21c
  79
  80 #define RK3368_PLL_CON(x)               RK2928_PLL_CON(x)
  81 #define RK3368_CLKSEL_CON(x)            ((x) * 0x4 + 0x100)
  82 #define RK3368_CLKGATE_CON(x)           ((x) * 0x4 + 0x200)
  83 #define RK3368_GLB_SRST_FST             0x280
  84 #define RK3368_GLB_SRST_SND             0x284
  85 #define RK3368_SOFTRST_CON(x)           ((x) * 0x4 + 0x300)
  86 #define RK3368_MISC_CON                 0x380
  87 #define RK3368_SDMMC_CON0               0x400
  88 #define RK3368_SDMMC_CON1               0x404
  89 #define RK3368_SDIO0_CON0               0x408
  90 #define RK3368_SDIO0_CON1               0x40c
  91 #define RK3368_SDIO1_CON0               0x410
  92 #define RK3368_SDIO1_CON1               0x414
  93 #define RK3368_EMMC_CON0                0x418
  94 #define RK3368_EMMC_CON1                0x41c
  95
  96 #define RK3399_PLL_CON(x)               RK2928_PLL_CON(x)
  97 #define RK3399_CLKSEL_CON(x)            ((x) * 0x4 + 0x100)
  98 #define RK3399_CLKGATE_CON(x)           ((x) * 0x4 + 0x300)
  99 #define RK3399_SOFTRST_CON(x)           ((x) * 0x4 + 0x400)
 100 #define RK3399_GLB_SRST_FST             0x500
 101 #define RK3399_GLB_SRST_SND             0x504
 102 #define RK3399_GLB_CNT_TH               0x508
 103 #define RK3399_MISC_CON                 0x50c
 104 #define RK3399_RST_CON                  0x510
 105 #define RK3399_RST_ST                   0x514
 106 #define RK3399_SDMMC_CON0               0x580
 107 #define RK3399_SDMMC_CON1               0x584
 108 #define RK3399_SDIO_CON0                0x588
 109 #define RK3399_SDIO_CON1                0x58c
 110
 111 #define RK3399_PMU_PLL_CON(x)           RK2928_PLL_CON(x)
 112 #define RK3399_PMU_CLKSEL_CON(x)        ((x) * 0x4 + 0x80)
 113 #define RK3399_PMU_CLKGATE_CON(x)       ((x) * 0x4 + 0x100)
 114 #define RK3399_PMU_SOFTRST_CON(x)       ((x) * 0x4 + 0x110)
 115 #define RK3399_PMU_RSTNHOLD_CON(x)      ((x) * 0x4 + 0x120)
 116 #define RK3399_PMU_GATEDIS_CON(x)       ((x) * 0x4 + 0x130)
 117
 118 enum rockchip_pll_type {
 119         pll_rk3036,
 120         pll_rk3066,
 121         pll_rk3366,
 122         pll_rk3399,
 123 };
 124
 125 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
 126                         _postdiv2, _dsmpd, _frac)               \
 127 {                                                               \
 128         .rate   = _rate##U,                                     \
 129         .fbdiv = _fbdiv,                                        \
 130         .postdiv1 = _postdiv1,                                  \
 131         .refdiv = _refdiv,                                      \
 132         .postdiv2 = _postdiv2,                                  \
 133         .dsmpd = _dsmpd,                                        \
 134         .frac = _frac,                                          \
 135 }
 136
 137 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)   \
 138 {                                               \
 139         .rate   = _rate##U,                     \
 140         .nr = _nr,                              \
 141         .nf = _nf,                              \
 142         .no = _no,                              \
 143         .nb = ((_nf) < 2) ? 1 : (_nf) >> 1,     \
 144 }
 145
 146 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb)           \
 147 {                                                               \
 148         .rate   = _rate##U,                                     \
 149         .nr = _nr,                                              \
 150         .nf = _nf,                                              \
 151         .no = _no,                                              \
 152         .nb = _nb,                                              \
 153 }
 154
 155 /**
 156  * struct rockchip_clk_provider - information about clock provider
 157  * @reg_base: virtual address for the register base.
 158  * @clk_data: holds clock related data like clk* and number of clocks.
 159  * @cru_node: device-node of the clock-provider
 160  * @grf: regmap of the general-register-files syscon
 161  * @lock: maintains exclusion between callbacks for a given clock-provider.
 162  */
 163 struct rockchip_clk_provider {
 164         void __iomem *reg_base;
 165         struct clk_onecell_data clk_data;
 166         struct device_node *cru_node;
 167         struct regmap *grf;
 168         spinlock_t lock;
 169 };
 170
 171 struct rockchip_pll_rate_table {
 172         unsigned long rate;
 173         unsigned int nr;
 174         unsigned int nf;
 175         unsigned int no;
 176         unsigned int nb;
 177         /* for RK3036/RK3399 */
 178         unsigned int fbdiv;
 179         unsigned int postdiv1;
 180         unsigned int refdiv;
 181         unsigned int postdiv2;
 182         unsigned int dsmpd;
 183         unsigned int frac;
 184 };
 185
 186 /**
 187  * struct rockchip_pll_clock - information about pll clock
 188  * @id: platform specific id of the clock.
 189  * @name: name of this pll clock.
 190  * @parent_names: name of the parent clock.
 191  * @num_parents: number of parents
 192  * @flags: optional flags for basic clock.
 193  * @con_offset: offset of the register for configuring the PLL.
 194  * @mode_offset: offset of the register for configuring the PLL-mode.
 195  * @mode_shift: offset inside the mode-register for the mode of this pll.
 196  * @lock_shift: offset inside the lock register for the lock status.
 197  * @type: Type of PLL to be registered.
 198  * @pll_flags: hardware-specific flags
 199  * @rate_table: Table of usable pll rates
 200  *
 201  * Flags:
 202  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
 203  *      rate_table parameters and ajust them if necessary.
 204  */
 205 struct rockchip_pll_clock {
 206         unsigned int            id;
 207         const char              *name;
 208         const char              *const *parent_names;
 209         u8                      num_parents;
 210         unsigned long           flags;
 211         int                     con_offset;
 212         int                     mode_offset;
 213         int                     mode_shift;
 214         int                     lock_shift;
 215         enum rockchip_pll_type  type;
 216         u8                      pll_flags;
 217         struct rockchip_pll_rate_table *rate_table;
 218 };
 219
 220 #define ROCKCHIP_PLL_SYNC_RATE          BIT(0)
 221
 222 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,   \
 223                 _lshift, _pflags, _rtable)                              \
 224         {                                                               \
 225                 .id             = _id,                                  \
 226                 .type           = _type,                                \
 227                 .name           = _name,                                \
 228                 .parent_names   = _pnames,                              \
 229                 .num_parents    = ARRAY_SIZE(_pnames),                  \
 230                 .flags          = CLK_GET_RATE_NOCACHE | _flags,        \
 231                 .con_offset     = _con,                                 \
 232                 .mode_offset    = _mode,                                \
 233                 .mode_shift     = _mshift,                              \
 234                 .lock_shift     = _lshift,                              \
 235                 .pll_flags      = _pflags,                              \
 236                 .rate_table     = _rtable,                              \
 237         }
 238
 239 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 240                 enum rockchip_pll_type pll_type,
 241                 const char *name, const char *const *parent_names,
 242                 u8 num_parents, int con_offset, int grf_lock_offset,
 243                 int lock_shift, int mode_offset, int mode_shift,
 244                 struct rockchip_pll_rate_table *rate_table,
 245                 unsigned long flags, u8 clk_pll_flags);
 246
 247 struct rockchip_cpuclk_clksel {
 248         int reg;
 249         u32 val;
 250 };
 251
 252 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS    2
 253 struct rockchip_cpuclk_rate_table {
 254         unsigned long prate;
 255         struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
 256 };
 257
 258 /**
 259  * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock
 260  * @core_reg:           register offset of the core settings register
 261  * @div_core_shift:     core divider offset used to divide the pll value
 262  * @div_core_mask:      core divider mask
 263  * @mux_core_alt:       mux value to select alternate parent
 264  * @mux_core_main:      mux value to select main parent of core
 265  * @mux_core_shift:     offset of the core multiplexer
 266  * @mux_core_mask:      core multiplexer mask
 267  */
 268 struct rockchip_cpuclk_reg_data {
 269         int             core_reg;
 270         u8              div_core_shift;
 271         u32             div_core_mask;
 272         u8              mux_core_alt;
 273         u8              mux_core_main;
 274         u8              mux_core_shift;
 275         u32             mux_core_mask;
 276 };
 277
 278 struct clk *rockchip_clk_register_cpuclk(const char *name,
 279                         const char *const *parent_names, u8 num_parents,
 280                         const struct rockchip_cpuclk_reg_data *reg_data,
 281                         const struct rockchip_cpuclk_rate_table *rates,
 282                         int nrates, void __iomem *reg_base, spinlock_t *lock);
 283
 284 struct clk *rockchip_clk_register_mmc(const char *name,
 285                                 const char *const *parent_names, u8 num_parents,
 286                                 void __iomem *reg, int shift);
 287
 288 /*
 289  * for COMPOSITE_DDRCLK div_flag,
 290  * there may have serval ways to set ddr clock, use
 291  * this flag to distinguish them.
 292  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
 293  */
 294 #define ROCKCHIP_DDRCLK_SIP             0x01
 295
 296 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
 297                                          const char *const *parent_names,
 298                                          u8 num_parents, int mux_offset,
 299                                          int mux_shift, int mux_width,
 300                                          int div_shift, int div_width,
 301                                          int ddr_flags, void __iomem *reg_base,
 302                                          spinlock_t *lock);
 303
 304 #define ROCKCHIP_INVERTER_HIWORD_MASK   BIT(0)
 305
 306 struct clk *rockchip_clk_register_inverter(const char *name,
 307                                 const char *const *parent_names, u8 num_parents,
 308                                 void __iomem *reg, int shift, int flags,
 309                                 spinlock_t *lock);
 310
 311 #define PNAME(x) static const char *const x[] __initconst
 312
 313 enum rockchip_clk_branch_type {
 314         branch_composite,
 315         branch_mux,
 316         branch_divider,
 317         branch_fraction_divider,
 318         branch_gate,
 319         branch_mmc,
 320         branch_inverter,
 321         branch_factor,
 322         branch_ddrc,
 323 };
 324
 325 struct rockchip_clk_branch {
 326         unsigned int                    id;
 327         enum rockchip_clk_branch_type   branch_type;
 328         const char                      *name;
 329         const char                      *const *parent_names;
 330         u8                              num_parents;
 331         unsigned long                   flags;
 332         int                             muxdiv_offset;
 333         u8                              mux_shift;
 334         u8                              mux_width;
 335         u8                              mux_flags;
 336         u8                              div_shift;
 337         u8                              div_width;
 338         u8                              div_flags;
 339         struct clk_div_table            *div_table;
 340         int                             gate_offset;
 341         u8                              gate_shift;
 342         u8                              gate_flags;
 343         struct rockchip_clk_branch      *child;
 344 };
 345
 346 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
 347                   df, go, gs, gf)                               \
 348         {                                                       \
 349                 .id             = _id,                          \
 350                 .branch_type    = branch_composite,             \
 351                 .name           = cname,                        \
 352                 .parent_names   = pnames,                       \
 353                 .num_parents    = ARRAY_SIZE(pnames),           \
 354                 .flags          = f,                            \
 355                 .muxdiv_offset  = mo,                           \
 356                 .mux_shift      = ms,                           \
 357                 .mux_width      = mw,                           \
 358                 .mux_flags      = mf,                           \
 359                 .div_shift      = ds,                           \
 360                 .div_width      = dw,                           \
 361                 .div_flags      = df,                           \
 362                 .gate_offset    = go,                           \
 363                 .gate_shift     = gs,                           \
 364                 .gate_flags     = gf,                           \
 365         }
 366
 367 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,   \
 368                         go, gs, gf)                             \
 369         {                                                       \
 370                 .id             = _id,                          \
 371                 .branch_type    = branch_composite,             \
 372                 .name           = cname,                        \
 373                 .parent_names   = (const char *[]){ pname },    \
 374                 .num_parents    = 1,                            \
 375                 .flags          = f,                            \
 376                 .muxdiv_offset  = mo,                           \
 377                 .div_shift      = ds,                           \
 378                 .div_width      = dw,                           \
 379                 .div_flags      = df,                           \
 380                 .gate_offset    = go,                           \
 381                 .gate_shift     = gs,                           \
 382                 .gate_flags     = gf,                           \
 383         }
 384
 385 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
 386                                df, dt, go, gs, gf)              \
 387         {                                                       \
 388                 .id             = _id,                          \
 389                 .branch_type    = branch_composite,             \
 390                 .name           = cname,                        \
 391                 .parent_names   = (const char *[]){ pname },    \
 392                 .num_parents    = 1,                            \
 393                 .flags          = f,                            \
 394                 .muxdiv_offset  = mo,                           \
 395                 .div_shift      = ds,                           \
 396                 .div_width      = dw,                           \
 397                 .div_flags      = df,                           \
 398                 .div_table      = dt,                           \
 399                 .gate_offset    = go,                           \
 400                 .gate_shift     = gs,                           \
 401                 .gate_flags     = gf,                           \
 402         }
 403
 404 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf,  \
 405                         go, gs, gf)                             \
 406         {                                                       \
 407                 .id             = _id,                          \
 408                 .branch_type    = branch_composite,             \
 409                 .name           = cname,                        \
 410                 .parent_names   = pnames,                       \
 411                 .num_parents    = ARRAY_SIZE(pnames),           \
 412                 .flags          = f,                            \
 413                 .muxdiv_offset  = mo,                           \
 414                 .mux_shift      = ms,                           \
 415                 .mux_width      = mw,                           \
 416                 .mux_flags      = mf,                           \
 417                 .gate_offset    = go,                           \
 418                 .gate_shift     = gs,                           \
 419                 .gate_flags     = gf,                           \
 420         }
 421
 422 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
 423                          ds, dw, df)                            \
 424         {                                                       \
 425                 .id             = _id,                          \
 426                 .branch_type    = branch_composite,             \
 427                 .name           = cname,                        \
 428                 .parent_names   = pnames,                       \
 429                 .num_parents    = ARRAY_SIZE(pnames),           \
 430                 .flags          = f,                            \
 431                 .muxdiv_offset  = mo,                           \
 432                 .mux_shift      = ms,                           \
 433                 .mux_width      = mw,                           \
 434                 .mux_flags      = mf,                           \
 435                 .div_shift      = ds,                           \
 436                 .div_width      = dw,                           \
 437                 .div_flags      = df,                           \
 438                 .gate_offset    = -1,                           \
 439         }
 440
 441 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,  \
 442                                 mw, mf, ds, dw, df, dt)         \
 443         {                                                       \
 444                 .id             = _id,                          \
 445                 .branch_type    = branch_composite,             \
 446                 .name           = cname,                        \
 447                 .parent_names   = pnames,                       \
 448                 .num_parents    = ARRAY_SIZE(pnames),           \
 449                 .flags          = f,                            \
 450                 .muxdiv_offset  = mo,                           \
 451                 .mux_shift      = ms,                           \
 452                 .mux_width      = mw,                           \
 453                 .mux_flags      = mf,                           \
 454                 .div_shift      = ds,                           \
 455                 .div_width      = dw,                           \
 456                 .div_flags      = df,                           \
 457                 .div_table      = dt,                           \
 458                 .gate_offset    = -1,                           \
 459         }
 460
 461 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
 462         {                                                       \
 463                 .id             = _id,                          \
 464                 .branch_type    = branch_fraction_divider,      \
 465                 .name           = cname,                        \
 466                 .parent_names   = (const char *[]){ pname },    \
 467                 .num_parents    = 1,                            \
 468                 .flags          = f,                            \
 469                 .muxdiv_offset  = mo,                           \
 470                 .div_shift      = 16,                           \
 471                 .div_width      = 16,                           \
 472                 .div_flags      = df,                           \
 473                 .gate_offset    = go,                           \
 474                 .gate_shift     = gs,                           \
 475                 .gate_flags     = gf,                           \
 476         }
 477
 478 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
 479         {                                                       \
 480                 .id             = _id,                          \
 481                 .branch_type    = branch_fraction_divider,      \
 482                 .name           = cname,                        \
 483                 .parent_names   = (const char *[]){ pname },    \
 484                 .num_parents    = 1,                            \
 485                 .flags          = f,                            \
 486                 .muxdiv_offset  = mo,                           \
 487                 .div_shift      = 16,                           \
 488                 .div_width      = 16,                           \
 489                 .div_flags      = df,                           \
 490                 .gate_offset    = go,                           \
 491                 .gate_shift     = gs,                           \
 492                 .gate_flags     = gf,                           \
 493                 .child          = ch,                           \
 494         }
 495
 496 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
 497         {                                                       \
 498                 .id             = _id,                          \
 499                 .branch_type    = branch_fraction_divider,      \
 500                 .name           = cname,                        \
 501                 .parent_names   = (const char *[]){ pname },    \
 502                 .num_parents    = 1,                            \
 503                 .flags          = f,                            \
 504                 .muxdiv_offset  = mo,                           \
 505                 .div_shift      = 16,                           \
 506                 .div_width      = 16,                           \
 507                 .div_flags      = df,                           \
 508                 .gate_offset    = -1,                           \
 509                 .child          = ch,                           \
 510         }
 511
 512 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw,     \
 513                          ds, dw, df)                            \
 514         {                                                       \
 515                 .id             = _id,                          \
 516                 .branch_type    = branch_ddrc,                  \
 517                 .name           = cname,                        \
 518                 .parent_names   = pnames,                       \
 519                 .num_parents    = ARRAY_SIZE(pnames),           \
 520                 .flags          = f,                            \
 521                 .muxdiv_offset  = mo,                           \
 522                 .mux_shift      = ms,                           \
 523                 .mux_width      = mw,                           \
 524                 .div_shift      = ds,                           \
 525                 .div_width      = dw,                           \
 526                 .div_flags      = df,                           \
 527                 .gate_offset    = -1,                           \
 528         }
 529
 530 #define MUX(_id, cname, pnames, f, o, s, w, mf)                 \
 531         {                                                       \
 532                 .id             = _id,                          \
 533                 .branch_type    = branch_mux,                   \
 534                 .name           = cname,                        \
 535                 .parent_names   = pnames,                       \
 536                 .num_parents    = ARRAY_SIZE(pnames),           \
 537                 .flags          = f,                            \
 538                 .muxdiv_offset  = o,                            \
 539                 .mux_shift      = s,                            \
 540                 .mux_width      = w,                            \
 541                 .mux_flags      = mf,                           \
 542                 .gate_offset    = -1,                           \
 543         }
 544
 545 #define DIV(_id, cname, pname, f, o, s, w, df)                  \
 546         {                                                       \
 547                 .id             = _id,                          \
 548                 .branch_type    = branch_divider,               \
 549                 .name           = cname,                        \
 550                 .parent_names   = (const char *[]){ pname },    \
 551                 .num_parents    = 1,                            \
 552                 .flags          = f,                            \
 553                 .muxdiv_offset  = o,                            \
 554                 .div_shift      = s,                            \
 555                 .div_width      = w,                            \
 556                 .div_flags      = df,                           \
 557                 .gate_offset    = -1,                           \
 558         }
 559
 560 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt)           \
 561         {                                                       \
 562                 .id             = _id,                          \
 563                 .branch_type    = branch_divider,               \
 564                 .name           = cname,                        \
 565                 .parent_names   = (const char *[]){ pname },    \
 566                 .num_parents    = 1,                            \
 567                 .flags          = f,                            \
 568                 .muxdiv_offset  = o,                            \
 569                 .div_shift      = s,                            \
 570                 .div_width      = w,                            \
 571                 .div_flags      = df,                           \
 572                 .div_table      = dt,                           \
 573         }
 574
 575 #define GATE(_id, cname, pname, f, o, b, gf)                    \
 576         {                                                       \
 577                 .id             = _id,                          \
 578                 .branch_type    = branch_gate,                  \
 579                 .name           = cname,                        \
 580                 .parent_names   = (const char *[]){ pname },    \
 581                 .num_parents    = 1,                            \
 582                 .flags          = f,                            \
 583                 .gate_offset    = o,                            \
 584                 .gate_shift     = b,                            \
 585                 .gate_flags     = gf,                           \
 586         }
 587
 588 #define MMC(_id, cname, pname, offset, shift)                   \
 589         {                                                       \
 590                 .id             = _id,                          \
 591                 .branch_type    = branch_mmc,                   \
 592                 .name           = cname,                        \
 593                 .parent_names   = (const char *[]){ pname },    \
 594                 .num_parents    = 1,                            \
 595                 .muxdiv_offset  = offset,                       \
 596                 .div_shift      = shift,                        \
 597         }
 598
 599 #define INVERTER(_id, cname, pname, io, is, if)                 \
 600         {                                                       \
 601                 .id             = _id,                          \
 602                 .branch_type    = branch_inverter,              \
 603                 .name           = cname,                        \
 604                 .parent_names   = (const char *[]){ pname },    \
 605                 .num_parents    = 1,                            \
 606                 .muxdiv_offset  = io,                           \
 607                 .div_shift      = is,                           \
 608                 .div_flags      = if,                           \
 609         }
 610
 611 #define FACTOR(_id, cname, pname,  f, fm, fd)                   \
 612         {                                                       \
 613                 .id             = _id,                          \
 614                 .branch_type    = branch_factor,                \
 615                 .name           = cname,                        \
 616                 .parent_names   = (const char *[]){ pname },    \
 617                 .num_parents    = 1,                            \
 618                 .flags          = f,                            \
 619                 .div_shift      = fm,                           \
 620                 .div_width      = fd,                           \
 621         }
 622
 623 #define FACTOR_GATE(_id, cname, pname,  f, fm, fd, go, gb, gf)  \
 624         {                                                       \
 625                 .id             = _id,                          \
 626                 .branch_type    = branch_factor,                \
 627                 .name           = cname,                        \
 628                 .parent_names   = (const char *[]){ pname },    \
 629                 .num_parents    = 1,                            \
 630                 .flags          = f,                            \
 631                 .div_shift      = fm,                           \
 632                 .div_width      = fd,                           \
 633                 .gate_offset    = go,                           \
 634                 .gate_shift     = gb,                           \
 635                 .gate_flags     = gf,                           \
 636         }
 637
 638 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
 639                         void __iomem *base, unsigned long nr_clks);
 640 void rockchip_clk_of_add_provider(struct device_node *np,
 641                                 struct rockchip_clk_provider *ctx);
 642 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
 643 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
 644                              struct clk *clk, unsigned int id);
 645 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
 646                                     struct rockchip_clk_branch *list,
 647                                     unsigned int nr_clk);
 648 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 649                                 struct rockchip_pll_clock *pll_list,
 650                                 unsigned int nr_pll, int grf_lock_offset);
 651 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
 652                         unsigned int lookup_id, const char *name,
 653                         const char *const *parent_names, u8 num_parents,
 654                         const struct rockchip_cpuclk_reg_data *reg_data,
 655                         const struct rockchip_cpuclk_rate_table *rates,
 656                         int nrates);
 657 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
 658 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
 659                                         unsigned int reg, void (*cb)(void));
 660
 661 #define ROCKCHIP_SOFTRST_HIWORD_MASK    BIT(0)
 662
 663 #ifdef CONFIG_RESET_CONTROLLER
 664 void rockchip_register_softrst(struct device_node *np,
 665                                unsigned int num_regs,
 666                                void __iomem *base, u8 flags);
 667 #else
 668 static inline void rockchip_register_softrst(struct device_node *np,
 669                                unsigned int num_regs,
 670                                void __iomem *base, u8 flags)
 671 {
 672 }
 673 #endif
 674
 675 #endif