drivers/clk/rockchip/clk.h

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * based on
   9  *
  10  * samsung/clk.h
  11  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  12  * Copyright (c) 2013 Linaro Ltd.
  13  * Author: Thomas Abraham <thomas.ab@samsung.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #ifndef CLK_ROCKCHIP_CLK_H
  27 #define CLK_ROCKCHIP_CLK_H
  28
  29 #include <linux/io.h>
  30
  31 struct clk;
  32
  33 #define HIWORD_UPDATE(val, mask, shift) \
  34                 ((val) << (shift) | (mask) << ((shift) + 16))
  35
  36 /* register positions shared by RK2928, RK3066 and RK3188 */
  37 #define RK2928_PLL_CON(x)               ((x) * 0x4)
  38 #define RK2928_MODE_CON         0x40
  39 #define RK2928_CLKSEL_CON(x)    ((x) * 0x4 + 0x44)
  40 #define RK2928_CLKGATE_CON(x)   ((x) * 0x4 + 0xd0)
  41 #define RK2928_GLB_SRST_FST             0x100
  42 #define RK2928_GLB_SRST_SND             0x104
  43 #define RK2928_SOFTRST_CON(x)   ((x) * 0x4 + 0x110)
  44 #define RK2928_MISC_CON         0x134
  45
  46 #define RK3288_PLL_CON(x)               RK2928_PLL_CON(x)
  47 #define RK3288_MODE_CON                 0x50
  48 #define RK3288_CLKSEL_CON(x)            ((x) * 0x4 + 0x60)
  49 #define RK3288_CLKGATE_CON(x)           ((x) * 0x4 + 0x160)
  50 #define RK3288_GLB_SRST_FST             0x1b0
  51 #define RK3288_GLB_SRST_SND             0x1b4
  52 #define RK3288_SOFTRST_CON(x)           ((x) * 0x4 + 0x1b8)
  53 #define RK3288_MISC_CON                 0x1e8
  54 #define RK3288_SDMMC_CON0               0x200
  55 #define RK3288_SDMMC_CON1               0x204
  56 #define RK3288_SDIO0_CON0               0x208
  57 #define RK3288_SDIO0_CON1               0x20c
  58 #define RK3288_SDIO1_CON0               0x210
  59 #define RK3288_SDIO1_CON1               0x214
  60 #define RK3288_EMMC_CON0                0x218
  61 #define RK3288_EMMC_CON1                0x21c
  62
  63 #define RK3368_PLL_CON(x)               RK2928_PLL_CON(x)
  64 #define RK3368_CLKSEL_CON(x)            ((x) * 0x4 + 0x100)
  65 #define RK3368_CLKGATE_CON(x)           ((x) * 0x4 + 0x200)
  66 #define RK3368_GLB_SRST_FST             0x280
  67 #define RK3368_GLB_SRST_SND             0x284
  68 #define RK3368_SOFTRST_CON(x)           ((x) * 0x4 + 0x300)
  69 #define RK3368_MISC_CON                 0x380
  70 #define RK3368_SDMMC_CON0               0x400
  71 #define RK3368_SDMMC_CON1               0x404
  72 #define RK3368_SDIO0_CON0               0x408
  73 #define RK3368_SDIO0_CON1               0x40c
  74 #define RK3368_SDIO1_CON0               0x410
  75 #define RK3368_SDIO1_CON1               0x414
  76 #define RK3368_EMMC_CON0                0x418
  77 #define RK3368_EMMC_CON1                0x41c
  78
  79 enum rockchip_pll_type {
  80         pll_rk3036,
  81         pll_rk3066,
  82         pll_rk3366,
  83 };
  84
  85 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
  86                         _postdiv2, _dsmpd, _frac)               \
  87 {                                                               \
  88         .rate   = _rate##U,                                     \
  89         .fbdiv = _fbdiv,                                        \
  90         .postdiv1 = _postdiv1,                                  \
  91         .refdiv = _refdiv,                                      \
  92         .postdiv2 = _postdiv2,                                  \
  93         .dsmpd = _dsmpd,                                        \
  94         .frac = _frac,                                          \
  95 }
  96
  97 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)   \
  98 {                                               \
  99         .rate   = _rate##U,                     \
 100         .nr = _nr,                              \
 101         .nf = _nf,                              \
 102         .no = _no,                              \
 103         .nb = ((_nf) < 2) ? 1 : (_nf) >> 1,     \
 104 }
 105
 106 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb)           \
 107 {                                                               \
 108         .rate   = _rate##U,                                     \
 109         .nr = _nr,                                              \
 110         .nf = _nf,                                              \
 111         .no = _no,                                              \
 112         .nb = _nb,                                              \
 113 }
 114
 115 struct rockchip_pll_rate_table {
 116         unsigned long rate;
 117         unsigned int nr;
 118         unsigned int nf;
 119         unsigned int no;
 120         unsigned int nb;
 121         /* for RK3036 */
 122         unsigned int fbdiv;
 123         unsigned int postdiv1;
 124         unsigned int refdiv;
 125         unsigned int postdiv2;
 126         unsigned int dsmpd;
 127         unsigned int frac;
 128 };
 129
 130 /**
 131  * struct rockchip_pll_clock: information about pll clock
 132  * @id: platform specific id of the clock.
 133  * @name: name of this pll clock.
 134  * @parent_name: name of the parent clock.
 135  * @flags: optional flags for basic clock.
 136  * @con_offset: offset of the register for configuring the PLL.
 137  * @mode_offset: offset of the register for configuring the PLL-mode.
 138  * @mode_shift: offset inside the mode-register for the mode of this pll.
 139  * @lock_shift: offset inside the lock register for the lock status.
 140  * @type: Type of PLL to be registered.
 141  * @pll_flags: hardware-specific flags
 142  * @rate_table: Table of usable pll rates
 143  *
 144  * Flags:
 145  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
 146  *      rate_table parameters and ajust them if necessary.
 147  */
 148 struct rockchip_pll_clock {
 149         unsigned int            id;
 150         const char              *name;
 151         const char              *const *parent_names;
 152         u8                      num_parents;
 153         unsigned long           flags;
 154         int                     con_offset;
 155         int                     mode_offset;
 156         int                     mode_shift;
 157         int                     lock_shift;
 158         enum rockchip_pll_type  type;
 159         u8                      pll_flags;
 160         struct rockchip_pll_rate_table *rate_table;
 161 };
 162
 163 #define ROCKCHIP_PLL_SYNC_RATE          BIT(0)
 164
 165 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,   \
 166                 _lshift, _pflags, _rtable)                              \
 167         {                                                               \
 168                 .id             = _id,                                  \
 169                 .type           = _type,                                \
 170                 .name           = _name,                                \
 171                 .parent_names   = _pnames,                              \
 172                 .num_parents    = ARRAY_SIZE(_pnames),                  \
 173                 .flags          = CLK_GET_RATE_NOCACHE | _flags,        \
 174                 .con_offset     = _con,                                 \
 175                 .mode_offset    = _mode,                                \
 176                 .mode_shift     = _mshift,                              \
 177                 .lock_shift     = _lshift,                              \
 178                 .pll_flags      = _pflags,                              \
 179                 .rate_table     = _rtable,                              \
 180         }
 181
 182 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
 183                 const char *name, const char *const *parent_names,
 184                 u8 num_parents, void __iomem *base, int con_offset,
 185                 int grf_lock_offset, int lock_shift, int reg_mode,
 186                 int mode_shift, struct rockchip_pll_rate_table *rate_table,
 187                 u8 clk_pll_flags, spinlock_t *lock);
 188
 189 struct rockchip_cpuclk_clksel {
 190         int reg;
 191         u32 val;
 192 };
 193
 194 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS    2
 195 struct rockchip_cpuclk_rate_table {
 196         unsigned long prate;
 197         struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
 198 };
 199
 200 /**
 201  * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
 202  * @core_reg:           register offset of the core settings register
 203  * @div_core_shift:     core divider offset used to divide the pll value
 204  * @div_core_mask:      core divider mask
 205  * @mux_core_shift:     offset of the core multiplexer
 206  */
 207 struct rockchip_cpuclk_reg_data {
 208         int             core_reg;
 209         u8              div_core_shift;
 210         u32             div_core_mask;
 211         int             mux_core_reg;
 212         u8              mux_core_shift;
 213 };
 214
 215 struct clk *rockchip_clk_register_cpuclk(const char *name,
 216                         const char *const *parent_names, u8 num_parents,
 217                         const struct rockchip_cpuclk_reg_data *reg_data,
 218                         const struct rockchip_cpuclk_rate_table *rates,
 219                         int nrates, void __iomem *reg_base, spinlock_t *lock);
 220
 221 struct clk *rockchip_clk_register_mmc(const char *name,
 222                                 const char *const *parent_names, u8 num_parents,
 223                                 void __iomem *reg, int shift);
 224
 225 #define ROCKCHIP_INVERTER_HIWORD_MASK   BIT(0)
 226
 227 struct clk *rockchip_clk_register_inverter(const char *name,
 228                                 const char *const *parent_names, u8 num_parents,
 229                                 void __iomem *reg, int shift, int flags,
 230                                 spinlock_t *lock);
 231
 232 #define PNAME(x) static const char *const x[] __initconst
 233
 234 enum rockchip_clk_branch_type {
 235         branch_composite,
 236         branch_mux,
 237         branch_divider,
 238         branch_fraction_divider,
 239         branch_gate,
 240         branch_mmc,
 241         branch_inverter,
 242 };
 243
 244 struct rockchip_clk_branch {
 245         unsigned int                    id;
 246         enum rockchip_clk_branch_type   branch_type;
 247         const char                      *name;
 248         const char                      *const *parent_names;
 249         u8                              num_parents;
 250         unsigned long                   flags;
 251         int                             muxdiv_offset;
 252         u8                              mux_shift;
 253         u8                              mux_width;
 254         u8                              mux_flags;
 255         u8                              div_shift;
 256         u8                              div_width;
 257         u8                              div_flags;
 258         struct clk_div_table            *div_table;
 259         int                             gate_offset;
 260         u8                              gate_shift;
 261         u8                              gate_flags;
 262 };
 263
 264 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
 265                   df, go, gs, gf)                               \
 266         {                                                       \
 267                 .id             = _id,                          \
 268                 .branch_type    = branch_composite,             \
 269                 .name           = cname,                        \
 270                 .parent_names   = pnames,                       \
 271                 .num_parents    = ARRAY_SIZE(pnames),           \
 272                 .flags          = f,                            \
 273                 .muxdiv_offset  = mo,                           \
 274                 .mux_shift      = ms,                           \
 275                 .mux_width      = mw,                           \
 276                 .mux_flags      = mf,                           \
 277                 .div_shift      = ds,                           \
 278                 .div_width      = dw,                           \
 279                 .div_flags      = df,                           \
 280                 .gate_offset    = go,                           \
 281                 .gate_shift     = gs,                           \
 282                 .gate_flags     = gf,                           \
 283         }
 284
 285 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,   \
 286                         go, gs, gf)                             \
 287         {                                                       \
 288                 .id             = _id,                          \
 289                 .branch_type    = branch_composite,             \
 290                 .name           = cname,                        \
 291                 .parent_names   = (const char *[]){ pname },    \
 292                 .num_parents    = 1,                            \
 293                 .flags          = f,                            \
 294                 .muxdiv_offset  = mo,                           \
 295                 .div_shift      = ds,                           \
 296                 .div_width      = dw,                           \
 297                 .div_flags      = df,                           \
 298                 .gate_offset    = go,                           \
 299                 .gate_shift     = gs,                           \
 300                 .gate_flags     = gf,                           \
 301         }
 302
 303 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
 304                                df, dt, go, gs, gf)              \
 305         {                                                       \
 306                 .id             = _id,                          \
 307                 .branch_type    = branch_composite,             \
 308                 .name           = cname,                        \
 309                 .parent_names   = (const char *[]){ pname },    \
 310                 .num_parents    = 1,                            \
 311                 .flags          = f,                            \
 312                 .muxdiv_offset  = mo,                           \
 313                 .div_shift      = ds,                           \
 314                 .div_width      = dw,                           \
 315                 .div_flags      = df,                           \
 316                 .div_table      = dt,                           \
 317                 .gate_offset    = go,                           \
 318                 .gate_shift     = gs,                           \
 319                 .gate_flags     = gf,                           \
 320         }
 321
 322 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf,  \
 323                         go, gs, gf)                             \
 324         {                                                       \
 325                 .id             = _id,                          \
 326                 .branch_type    = branch_composite,             \
 327                 .name           = cname,                        \
 328                 .parent_names   = pnames,                       \
 329                 .num_parents    = ARRAY_SIZE(pnames),           \
 330                 .flags          = f,                            \
 331                 .muxdiv_offset  = mo,                           \
 332                 .mux_shift      = ms,                           \
 333                 .mux_width      = mw,                           \
 334                 .mux_flags      = mf,                           \
 335                 .gate_offset    = go,                           \
 336                 .gate_shift     = gs,                           \
 337                 .gate_flags     = gf,                           \
 338         }
 339
 340 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
 341                          ds, dw, df)                            \
 342         {                                                       \
 343                 .id             = _id,                          \
 344                 .branch_type    = branch_composite,             \
 345                 .name           = cname,                        \
 346                 .parent_names   = pnames,                       \
 347                 .num_parents    = ARRAY_SIZE(pnames),           \
 348                 .flags          = f,                            \
 349                 .muxdiv_offset  = mo,                           \
 350                 .mux_shift      = ms,                           \
 351                 .mux_width      = mw,                           \
 352                 .mux_flags      = mf,                           \
 353                 .div_shift      = ds,                           \
 354                 .div_width      = dw,                           \
 355                 .div_flags      = df,                           \
 356                 .gate_offset    = -1,                           \
 357         }
 358
 359 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,  \
 360                                 mw, mf, ds, dw, df, dt)         \
 361         {                                                       \
 362                 .id             = _id,                          \
 363                 .branch_type    = branch_composite,             \
 364                 .name           = cname,                        \
 365                 .parent_names   = pnames,                       \
 366                 .num_parents    = ARRAY_SIZE(pnames),           \
 367                 .flags          = f,                            \
 368                 .muxdiv_offset  = mo,                           \
 369                 .mux_shift      = ms,                           \
 370                 .mux_width      = mw,                           \
 371                 .mux_flags      = mf,                           \
 372                 .div_shift      = ds,                           \
 373                 .div_width      = dw,                           \
 374                 .div_flags      = df,                           \
 375                 .div_table      = dt,                           \
 376                 .gate_offset    = -1,                           \
 377         }
 378
 379 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
 380         {                                                       \
 381                 .id             = _id,                          \
 382                 .branch_type    = branch_fraction_divider,      \
 383                 .name           = cname,                        \
 384                 .parent_names   = (const char *[]){ pname },    \
 385                 .num_parents    = 1,                            \
 386                 .flags          = f,                            \
 387                 .muxdiv_offset  = mo,                           \
 388                 .div_shift      = 16,                           \
 389                 .div_width      = 16,                           \
 390                 .div_flags      = df,                           \
 391                 .gate_offset    = go,                           \
 392                 .gate_shift     = gs,                           \
 393                 .gate_flags     = gf,                           \
 394         }
 395
 396 #define MUX(_id, cname, pnames, f, o, s, w, mf)                 \
 397         {                                                       \
 398                 .id             = _id,                          \
 399                 .branch_type    = branch_mux,                   \
 400                 .name           = cname,                        \
 401                 .parent_names   = pnames,                       \
 402                 .num_parents    = ARRAY_SIZE(pnames),           \
 403                 .flags          = f,                            \
 404                 .muxdiv_offset  = o,                            \
 405                 .mux_shift      = s,                            \
 406                 .mux_width      = w,                            \
 407                 .mux_flags      = mf,                           \
 408                 .gate_offset    = -1,                           \
 409         }
 410
 411 #define DIV(_id, cname, pname, f, o, s, w, df)                  \
 412         {                                                       \
 413                 .id             = _id,                          \
 414                 .branch_type    = branch_divider,               \
 415                 .name           = cname,                        \
 416                 .parent_names   = (const char *[]){ pname },    \
 417                 .num_parents    = 1,                            \
 418                 .flags          = f,                            \
 419                 .muxdiv_offset  = o,                            \
 420                 .div_shift      = s,                            \
 421                 .div_width      = w,                            \
 422                 .div_flags      = df,                           \
 423                 .gate_offset    = -1,                           \
 424         }
 425
 426 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt)           \
 427         {                                                       \
 428                 .id             = _id,                          \
 429                 .branch_type    = branch_divider,               \
 430                 .name           = cname,                        \
 431                 .parent_names   = (const char *[]){ pname },    \
 432                 .num_parents    = 1,                            \
 433                 .flags          = f,                            \
 434                 .muxdiv_offset  = o,                            \
 435                 .div_shift      = s,                            \
 436                 .div_width      = w,                            \
 437                 .div_flags      = df,                           \
 438                 .div_table      = dt,                           \
 439         }
 440
 441 #define GATE(_id, cname, pname, f, o, b, gf)                    \
 442         {                                                       \
 443                 .id             = _id,                          \
 444                 .branch_type    = branch_gate,                  \
 445                 .name           = cname,                        \
 446                 .parent_names   = (const char *[]){ pname },    \
 447                 .num_parents    = 1,                            \
 448                 .flags          = f,                            \
 449                 .gate_offset    = o,                            \
 450                 .gate_shift     = b,                            \
 451                 .gate_flags     = gf,                           \
 452         }
 453
 454 #define MMC(_id, cname, pname, offset, shift)                   \
 455         {                                                       \
 456                 .id             = _id,                          \
 457                 .branch_type    = branch_mmc,                   \
 458                 .name           = cname,                        \
 459                 .parent_names   = (const char *[]){ pname },    \
 460                 .num_parents    = 1,                            \
 461                 .muxdiv_offset  = offset,                       \
 462                 .div_shift      = shift,                        \
 463         }
 464
 465 #define INVERTER(_id, cname, pname, io, is, if)                 \
 466         {                                                       \
 467                 .id             = _id,                          \
 468                 .branch_type    = branch_inverter,              \
 469                 .name           = cname,                        \
 470                 .parent_names   = (const char *[]){ pname },    \
 471                 .num_parents    = 1,                            \
 472                 .muxdiv_offset  = io,                           \
 473                 .div_shift      = is,                           \
 474                 .div_flags      = if,                           \
 475         }
 476
 477 void rockchip_clk_init(struct device_node *np, void __iomem *base,
 478                        unsigned long nr_clks);
 479 struct regmap *rockchip_clk_get_grf(void);
 480 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
 481 void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
 482                                     unsigned int nr_clk);
 483 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
 484                                 unsigned int nr_pll, int grf_lock_offset);
 485 void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
 486                         const char *const *parent_names, u8 num_parents,
 487                         const struct rockchip_cpuclk_reg_data *reg_data,
 488                         const struct rockchip_cpuclk_rate_table *rates,
 489                         int nrates);
 490 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
 491 void rockchip_register_restart_notifier(unsigned int reg);
 492
 493 #define ROCKCHIP_SOFTRST_HIWORD_MASK    BIT(0)
 494
 495 #ifdef CONFIG_RESET_CONTROLLER
 496 void rockchip_register_softrst(struct device_node *np,
 497                                unsigned int num_regs,
 498                                void __iomem *base, u8 flags);
 499 #else
 500 static inline void rockchip_register_softrst(struct device_node *np,
 501                                unsigned int num_regs,
 502                                void __iomem *base, u8 flags)
 503 {
 504 }
 505 #endif
 506
 507 #endif