drivers/clk/rockchip/clk.h

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * based on
   9  *
  10  * samsung/clk.h
  11  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  12  * Copyright (c) 2013 Linaro Ltd.
  13  * Author: Thomas Abraham <thomas.ab@samsung.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #ifndef CLK_ROCKCHIP_CLK_H
  27 #define CLK_ROCKCHIP_CLK_H
  28
  29 #include <linux/io.h>
  30
  31 struct clk;
  32
  33 #define HIWORD_UPDATE(val, mask, shift) \
  34                 ((val) << (shift) | (mask) << ((shift) + 16))
  35
  36 /* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
  37 #define RK2928_PLL_CON(x)               ((x) * 0x4)
  38 #define RK2928_MODE_CON         0x40
  39 #define RK2928_CLKSEL_CON(x)    ((x) * 0x4 + 0x44)
  40 #define RK2928_CLKGATE_CON(x)   ((x) * 0x4 + 0xd0)
  41 #define RK2928_GLB_SRST_FST             0x100
  42 #define RK2928_GLB_SRST_SND             0x104
  43 #define RK2928_SOFTRST_CON(x)   ((x) * 0x4 + 0x110)
  44 #define RK2928_MISC_CON         0x134
  45
  46 #define RK3036_SDMMC_CON0               0x144
  47 #define RK3036_SDMMC_CON1               0x148
  48 #define RK3036_SDIO_CON0                0x14c
  49 #define RK3036_SDIO_CON1                0x150
  50 #define RK3036_EMMC_CON0                0x154
  51 #define RK3036_EMMC_CON1                0x158
  52
  53 #define RK3288_PLL_CON(x)               RK2928_PLL_CON(x)
  54 #define RK3288_MODE_CON                 0x50
  55 #define RK3288_CLKSEL_CON(x)            ((x) * 0x4 + 0x60)
  56 #define RK3288_CLKGATE_CON(x)           ((x) * 0x4 + 0x160)
  57 #define RK3288_GLB_SRST_FST             0x1b0
  58 #define RK3288_GLB_SRST_SND             0x1b4
  59 #define RK3288_SOFTRST_CON(x)           ((x) * 0x4 + 0x1b8)
  60 #define RK3288_MISC_CON                 0x1e8
  61 #define RK3288_SDMMC_CON0               0x200
  62 #define RK3288_SDMMC_CON1               0x204
  63 #define RK3288_SDIO0_CON0               0x208
  64 #define RK3288_SDIO0_CON1               0x20c
  65 #define RK3288_SDIO1_CON0               0x210
  66 #define RK3288_SDIO1_CON1               0x214
  67 #define RK3288_EMMC_CON0                0x218
  68 #define RK3288_EMMC_CON1                0x21c
  69
  70 #define RK3368_PLL_CON(x)               RK2928_PLL_CON(x)
  71 #define RK3368_CLKSEL_CON(x)            ((x) * 0x4 + 0x100)
  72 #define RK3368_CLKGATE_CON(x)           ((x) * 0x4 + 0x200)
  73 #define RK3368_GLB_SRST_FST             0x280
  74 #define RK3368_GLB_SRST_SND             0x284
  75 #define RK3368_SOFTRST_CON(x)           ((x) * 0x4 + 0x300)
  76 #define RK3368_MISC_CON                 0x380
  77 #define RK3368_SDMMC_CON0               0x400
  78 #define RK3368_SDMMC_CON1               0x404
  79 #define RK3368_SDIO0_CON0               0x408
  80 #define RK3368_SDIO0_CON1               0x40c
  81 #define RK3368_SDIO1_CON0               0x410
  82 #define RK3368_SDIO1_CON1               0x414
  83 #define RK3368_EMMC_CON0                0x418
  84 #define RK3368_EMMC_CON1                0x41c
  85
  86 enum rockchip_pll_type {
  87         pll_rk3036,
  88         pll_rk3066,
  89         pll_rk3366,
  90 };
  91
  92 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
  93                         _postdiv2, _dsmpd, _frac)               \
  94 {                                                               \
  95         .rate   = _rate##U,                                     \
  96         .fbdiv = _fbdiv,                                        \
  97         .postdiv1 = _postdiv1,                                  \
  98         .refdiv = _refdiv,                                      \
  99         .postdiv2 = _postdiv2,                                  \
 100         .dsmpd = _dsmpd,                                        \
 101         .frac = _frac,                                          \
 102 }
 103
 104 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)   \
 105 {                                               \
 106         .rate   = _rate##U,                     \
 107         .nr = _nr,                              \
 108         .nf = _nf,                              \
 109         .no = _no,                              \
 110         .nb = ((_nf) < 2) ? 1 : (_nf) >> 1,     \
 111 }
 112
 113 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb)           \
 114 {                                                               \
 115         .rate   = _rate##U,                                     \
 116         .nr = _nr,                                              \
 117         .nf = _nf,                                              \
 118         .no = _no,                                              \
 119         .nb = _nb,                                              \
 120 }
 121
 122 struct rockchip_pll_rate_table {
 123         unsigned long rate;
 124         unsigned int nr;
 125         unsigned int nf;
 126         unsigned int no;
 127         unsigned int nb;
 128         /* for RK3036 */
 129         unsigned int fbdiv;
 130         unsigned int postdiv1;
 131         unsigned int refdiv;
 132         unsigned int postdiv2;
 133         unsigned int dsmpd;
 134         unsigned int frac;
 135 };
 136
 137 /**
 138  * struct rockchip_pll_clock: information about pll clock
 139  * @id: platform specific id of the clock.
 140  * @name: name of this pll clock.
 141  * @parent_name: name of the parent clock.
 142  * @flags: optional flags for basic clock.
 143  * @con_offset: offset of the register for configuring the PLL.
 144  * @mode_offset: offset of the register for configuring the PLL-mode.
 145  * @mode_shift: offset inside the mode-register for the mode of this pll.
 146  * @lock_shift: offset inside the lock register for the lock status.
 147  * @type: Type of PLL to be registered.
 148  * @pll_flags: hardware-specific flags
 149  * @rate_table: Table of usable pll rates
 150  *
 151  * Flags:
 152  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
 153  *      rate_table parameters and ajust them if necessary.
 154  */
 155 struct rockchip_pll_clock {
 156         unsigned int            id;
 157         const char              *name;
 158         const char              *const *parent_names;
 159         u8                      num_parents;
 160         unsigned long           flags;
 161         int                     con_offset;
 162         int                     mode_offset;
 163         int                     mode_shift;
 164         int                     lock_shift;
 165         enum rockchip_pll_type  type;
 166         u8                      pll_flags;
 167         struct rockchip_pll_rate_table *rate_table;
 168 };
 169
 170 #define ROCKCHIP_PLL_SYNC_RATE          BIT(0)
 171
 172 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,   \
 173                 _lshift, _pflags, _rtable)                              \
 174         {                                                               \
 175                 .id             = _id,                                  \
 176                 .type           = _type,                                \
 177                 .name           = _name,                                \
 178                 .parent_names   = _pnames,                              \
 179                 .num_parents    = ARRAY_SIZE(_pnames),                  \
 180                 .flags          = CLK_GET_RATE_NOCACHE | _flags,        \
 181                 .con_offset     = _con,                                 \
 182                 .mode_offset    = _mode,                                \
 183                 .mode_shift     = _mshift,                              \
 184                 .lock_shift     = _lshift,                              \
 185                 .pll_flags      = _pflags,                              \
 186                 .rate_table     = _rtable,                              \
 187         }
 188
 189 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
 190                 const char *name, const char *const *parent_names,
 191                 u8 num_parents, void __iomem *base, int con_offset,
 192                 int grf_lock_offset, int lock_shift, int reg_mode,
 193                 int mode_shift, struct rockchip_pll_rate_table *rate_table,
 194                 u8 clk_pll_flags, spinlock_t *lock);
 195
 196 struct rockchip_cpuclk_clksel {
 197         int reg;
 198         u32 val;
 199 };
 200
 201 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS    2
 202 struct rockchip_cpuclk_rate_table {
 203         unsigned long prate;
 204         struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
 205 };
 206
 207 /**
 208  * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
 209  * @core_reg:           register offset of the core settings register
 210  * @div_core_shift:     core divider offset used to divide the pll value
 211  * @div_core_mask:      core divider mask
 212  * @mux_core_alt:       mux value to select alternate parent
 213  * @mux_core_main:      mux value to select main parent of core
 214  * @mux_core_shift:     offset of the core multiplexer
 215  * @mux_core_mask:      core multiplexer mask
 216  */
 217 struct rockchip_cpuclk_reg_data {
 218         int             core_reg;
 219         u8              div_core_shift;
 220         u32             div_core_mask;
 221         int             mux_core_reg;
 222         u8              mux_core_alt;
 223         u8              mux_core_main;
 224         u8              mux_core_shift;
 225         u32             mux_core_mask;
 226 };
 227
 228 struct clk *rockchip_clk_register_cpuclk(const char *name,
 229                         const char *const *parent_names, u8 num_parents,
 230                         const struct rockchip_cpuclk_reg_data *reg_data,
 231                         const struct rockchip_cpuclk_rate_table *rates,
 232                         int nrates, void __iomem *reg_base, spinlock_t *lock);
 233
 234 struct clk *rockchip_clk_register_mmc(const char *name,
 235                                 const char *const *parent_names, u8 num_parents,
 236                                 void __iomem *reg, int shift);
 237
 238 #define ROCKCHIP_INVERTER_HIWORD_MASK   BIT(0)
 239
 240 struct clk *rockchip_clk_register_inverter(const char *name,
 241                                 const char *const *parent_names, u8 num_parents,
 242                                 void __iomem *reg, int shift, int flags,
 243                                 spinlock_t *lock);
 244
 245 #define PNAME(x) static const char *const x[] __initconst
 246
 247 enum rockchip_clk_branch_type {
 248         branch_composite,
 249         branch_mux,
 250         branch_divider,
 251         branch_fraction_divider,
 252         branch_gate,
 253         branch_mmc,
 254         branch_inverter,
 255         branch_factor,
 256 };
 257
 258 struct rockchip_clk_branch {
 259         unsigned int                    id;
 260         enum rockchip_clk_branch_type   branch_type;
 261         const char                      *name;
 262         const char                      *const *parent_names;
 263         u8                              num_parents;
 264         unsigned long                   flags;
 265         int                             muxdiv_offset;
 266         u8                              mux_shift;
 267         u8                              mux_width;
 268         u8                              mux_flags;
 269         u8                              div_shift;
 270         u8                              div_width;
 271         u8                              div_flags;
 272         struct clk_div_table            *div_table;
 273         int                             gate_offset;
 274         u8                              gate_shift;
 275         u8                              gate_flags;
 276         struct rockchip_clk_branch      *child;
 277 };
 278
 279 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
 280                   df, go, gs, gf)                               \
 281         {                                                       \
 282                 .id             = _id,                          \
 283                 .branch_type    = branch_composite,             \
 284                 .name           = cname,                        \
 285                 .parent_names   = pnames,                       \
 286                 .num_parents    = ARRAY_SIZE(pnames),           \
 287                 .flags          = f,                            \
 288                 .muxdiv_offset  = mo,                           \
 289                 .mux_shift      = ms,                           \
 290                 .mux_width      = mw,                           \
 291                 .mux_flags      = mf,                           \
 292                 .div_shift      = ds,                           \
 293                 .div_width      = dw,                           \
 294                 .div_flags      = df,                           \
 295                 .gate_offset    = go,                           \
 296                 .gate_shift     = gs,                           \
 297                 .gate_flags     = gf,                           \
 298         }
 299
 300 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,   \
 301                         go, gs, gf)                             \
 302         {                                                       \
 303                 .id             = _id,                          \
 304                 .branch_type    = branch_composite,             \
 305                 .name           = cname,                        \
 306                 .parent_names   = (const char *[]){ pname },    \
 307                 .num_parents    = 1,                            \
 308                 .flags          = f,                            \
 309                 .muxdiv_offset  = mo,                           \
 310                 .div_shift      = ds,                           \
 311                 .div_width      = dw,                           \
 312                 .div_flags      = df,                           \
 313                 .gate_offset    = go,                           \
 314                 .gate_shift     = gs,                           \
 315                 .gate_flags     = gf,                           \
 316         }
 317
 318 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
 319                                df, dt, go, gs, gf)              \
 320         {                                                       \
 321                 .id             = _id,                          \
 322                 .branch_type    = branch_composite,             \
 323                 .name           = cname,                        \
 324                 .parent_names   = (const char *[]){ pname },    \
 325                 .num_parents    = 1,                            \
 326                 .flags          = f,                            \
 327                 .muxdiv_offset  = mo,                           \
 328                 .div_shift      = ds,                           \
 329                 .div_width      = dw,                           \
 330                 .div_flags      = df,                           \
 331                 .div_table      = dt,                           \
 332                 .gate_offset    = go,                           \
 333                 .gate_shift     = gs,                           \
 334                 .gate_flags     = gf,                           \
 335         }
 336
 337 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf,  \
 338                         go, gs, gf)                             \
 339         {                                                       \
 340                 .id             = _id,                          \
 341                 .branch_type    = branch_composite,             \
 342                 .name           = cname,                        \
 343                 .parent_names   = pnames,                       \
 344                 .num_parents    = ARRAY_SIZE(pnames),           \
 345                 .flags          = f,                            \
 346                 .muxdiv_offset  = mo,                           \
 347                 .mux_shift      = ms,                           \
 348                 .mux_width      = mw,                           \
 349                 .mux_flags      = mf,                           \
 350                 .gate_offset    = go,                           \
 351                 .gate_shift     = gs,                           \
 352                 .gate_flags     = gf,                           \
 353         }
 354
 355 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
 356                          ds, dw, df)                            \
 357         {                                                       \
 358                 .id             = _id,                          \
 359                 .branch_type    = branch_composite,             \
 360                 .name           = cname,                        \
 361                 .parent_names   = pnames,                       \
 362                 .num_parents    = ARRAY_SIZE(pnames),           \
 363                 .flags          = f,                            \
 364                 .muxdiv_offset  = mo,                           \
 365                 .mux_shift      = ms,                           \
 366                 .mux_width      = mw,                           \
 367                 .mux_flags      = mf,                           \
 368                 .div_shift      = ds,                           \
 369                 .div_width      = dw,                           \
 370                 .div_flags      = df,                           \
 371                 .gate_offset    = -1,                           \
 372         }
 373
 374 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,  \
 375                                 mw, mf, ds, dw, df, dt)         \
 376         {                                                       \
 377                 .id             = _id,                          \
 378                 .branch_type    = branch_composite,             \
 379                 .name           = cname,                        \
 380                 .parent_names   = pnames,                       \
 381                 .num_parents    = ARRAY_SIZE(pnames),           \
 382                 .flags          = f,                            \
 383                 .muxdiv_offset  = mo,                           \
 384                 .mux_shift      = ms,                           \
 385                 .mux_width      = mw,                           \
 386                 .mux_flags      = mf,                           \
 387                 .div_shift      = ds,                           \
 388                 .div_width      = dw,                           \
 389                 .div_flags      = df,                           \
 390                 .div_table      = dt,                           \
 391                 .gate_offset    = -1,                           \
 392         }
 393
 394 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
 395         {                                                       \
 396                 .id             = _id,                          \
 397                 .branch_type    = branch_fraction_divider,      \
 398                 .name           = cname,                        \
 399                 .parent_names   = (const char *[]){ pname },    \
 400                 .num_parents    = 1,                            \
 401                 .flags          = f,                            \
 402                 .muxdiv_offset  = mo,                           \
 403                 .div_shift      = 16,                           \
 404                 .div_width      = 16,                           \
 405                 .div_flags      = df,                           \
 406                 .gate_offset    = go,                           \
 407                 .gate_shift     = gs,                           \
 408                 .gate_flags     = gf,                           \
 409         }
 410
 411 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
 412         {                                                       \
 413                 .id             = _id,                          \
 414                 .branch_type    = branch_fraction_divider,      \
 415                 .name           = cname,                        \
 416                 .parent_names   = (const char *[]){ pname },    \
 417                 .num_parents    = 1,                            \
 418                 .flags          = f,                            \
 419                 .muxdiv_offset  = mo,                           \
 420                 .div_shift      = 16,                           \
 421                 .div_width      = 16,                           \
 422                 .div_flags      = df,                           \
 423                 .gate_offset    = go,                           \
 424                 .gate_shift     = gs,                           \
 425                 .gate_flags     = gf,                           \
 426                 .child          = ch,                           \
 427         }
 428
 429 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
 430         {                                                       \
 431                 .id             = _id,                          \
 432                 .branch_type    = branch_fraction_divider,      \
 433                 .name           = cname,                        \
 434                 .parent_names   = (const char *[]){ pname },    \
 435                 .num_parents    = 1,                            \
 436                 .flags          = f,                            \
 437                 .muxdiv_offset  = mo,                           \
 438                 .div_shift      = 16,                           \
 439                 .div_width      = 16,                           \
 440                 .div_flags      = df,                           \
 441                 .gate_offset    = -1,                           \
 442                 .child          = ch,                           \
 443         }
 444
 445 #define MUX(_id, cname, pnames, f, o, s, w, mf)                 \
 446         {                                                       \
 447                 .id             = _id,                          \
 448                 .branch_type    = branch_mux,                   \
 449                 .name           = cname,                        \
 450                 .parent_names   = pnames,                       \
 451                 .num_parents    = ARRAY_SIZE(pnames),           \
 452                 .flags          = f,                            \
 453                 .muxdiv_offset  = o,                            \
 454                 .mux_shift      = s,                            \
 455                 .mux_width      = w,                            \
 456                 .mux_flags      = mf,                           \
 457                 .gate_offset    = -1,                           \
 458         }
 459
 460 #define DIV(_id, cname, pname, f, o, s, w, df)                  \
 461         {                                                       \
 462                 .id             = _id,                          \
 463                 .branch_type    = branch_divider,               \
 464                 .name           = cname,                        \
 465                 .parent_names   = (const char *[]){ pname },    \
 466                 .num_parents    = 1,                            \
 467                 .flags          = f,                            \
 468                 .muxdiv_offset  = o,                            \
 469                 .div_shift      = s,                            \
 470                 .div_width      = w,                            \
 471                 .div_flags      = df,                           \
 472                 .gate_offset    = -1,                           \
 473         }
 474
 475 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt)           \
 476         {                                                       \
 477                 .id             = _id,                          \
 478                 .branch_type    = branch_divider,               \
 479                 .name           = cname,                        \
 480                 .parent_names   = (const char *[]){ pname },    \
 481                 .num_parents    = 1,                            \
 482                 .flags          = f,                            \
 483                 .muxdiv_offset  = o,                            \
 484                 .div_shift      = s,                            \
 485                 .div_width      = w,                            \
 486                 .div_flags      = df,                           \
 487                 .div_table      = dt,                           \
 488         }
 489
 490 #define GATE(_id, cname, pname, f, o, b, gf)                    \
 491         {                                                       \
 492                 .id             = _id,                          \
 493                 .branch_type    = branch_gate,                  \
 494                 .name           = cname,                        \
 495                 .parent_names   = (const char *[]){ pname },    \
 496                 .num_parents    = 1,                            \
 497                 .flags          = f,                            \
 498                 .gate_offset    = o,                            \
 499                 .gate_shift     = b,                            \
 500                 .gate_flags     = gf,                           \
 501         }
 502
 503 #define MMC(_id, cname, pname, offset, shift)                   \
 504         {                                                       \
 505                 .id             = _id,                          \
 506                 .branch_type    = branch_mmc,                   \
 507                 .name           = cname,                        \
 508                 .parent_names   = (const char *[]){ pname },    \
 509                 .num_parents    = 1,                            \
 510                 .muxdiv_offset  = offset,                       \
 511                 .div_shift      = shift,                        \
 512         }
 513
 514 #define INVERTER(_id, cname, pname, io, is, if)                 \
 515         {                                                       \
 516                 .id             = _id,                          \
 517                 .branch_type    = branch_inverter,              \
 518                 .name           = cname,                        \
 519                 .parent_names   = (const char *[]){ pname },    \
 520                 .num_parents    = 1,                            \
 521                 .muxdiv_offset  = io,                           \
 522                 .div_shift      = is,                           \
 523                 .div_flags      = if,                           \
 524         }
 525
 526 #define FACTOR(_id, cname, pname,  f, fm, fd)                   \
 527         {                                                       \
 528                 .id             = _id,                          \
 529                 .branch_type    = branch_factor,                \
 530                 .name           = cname,                        \
 531                 .parent_names   = (const char *[]){ pname },    \
 532                 .num_parents    = 1,                            \
 533                 .flags          = f,                            \
 534                 .div_shift      = fm,                           \
 535                 .div_width      = fd,                           \
 536         }
 537
 538 #define FACTOR_GATE(_id, cname, pname,  f, fm, fd, go, gb, gf)  \
 539         {                                                       \
 540                 .id             = _id,                          \
 541                 .branch_type    = branch_factor,                \
 542                 .name           = cname,                        \
 543                 .parent_names   = (const char *[]){ pname },    \
 544                 .num_parents    = 1,                            \
 545                 .flags          = f,                            \
 546                 .div_shift      = fm,                           \
 547                 .div_width      = fd,                           \
 548                 .gate_offset    = go,                           \
 549                 .gate_shift     = gb,                           \
 550                 .gate_flags     = gf,                           \
 551         }
 552
 553 void rockchip_clk_init(struct device_node *np, void __iomem *base,
 554                        unsigned long nr_clks);
 555 struct regmap *rockchip_clk_get_grf(void);
 556 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
 557 void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
 558                                     unsigned int nr_clk);
 559 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
 560                                 unsigned int nr_pll, int grf_lock_offset);
 561 void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
 562                         const char *const *parent_names, u8 num_parents,
 563                         const struct rockchip_cpuclk_reg_data *reg_data,
 564                         const struct rockchip_cpuclk_rate_table *rates,
 565                         int nrates);
 566 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
 567 void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));
 568
 569 #define ROCKCHIP_SOFTRST_HIWORD_MASK    BIT(0)
 570
 571 #ifdef CONFIG_RESET_CONTROLLER
 572 void rockchip_register_softrst(struct device_node *np,
 573                                unsigned int num_regs,
 574                                void __iomem *base, u8 flags);
 575 #else
 576 static inline void rockchip_register_softrst(struct device_node *np,
 577                                unsigned int num_regs,
 578                                void __iomem *base, u8 flags)
 579 {
 580 }
 581 #endif
 582
 583 #endif