drivers/clk/rockchip/clk.h

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * based on
   9  *
  10  * samsung/clk.h
  11  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  12  * Copyright (c) 2013 Linaro Ltd.
  13  * Author: Thomas Abraham <thomas.ab@samsung.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #ifndef CLK_ROCKCHIP_CLK_H
  27 #define CLK_ROCKCHIP_CLK_H
  28
  29 #include <linux/io.h>
  30 #include <linux/clk-provider.h>
  31
  32 struct clk;
  33
  34 #define HIWORD_UPDATE(val, mask, shift) \
  35                 ((val) << (shift) | (mask) << ((shift) + 16))
  36
  37 /* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
  38 #define RK2928_PLL_CON(x)               ((x) * 0x4)
  39 #define RK2928_MODE_CON         0x40
  40 #define RK2928_CLKSEL_CON(x)    ((x) * 0x4 + 0x44)
  41 #define RK2928_CLKGATE_CON(x)   ((x) * 0x4 + 0xd0)
  42 #define RK2928_GLB_SRST_FST             0x100
  43 #define RK2928_GLB_SRST_SND             0x104
  44 #define RK2928_SOFTRST_CON(x)   ((x) * 0x4 + 0x110)
  45 #define RK2928_MISC_CON         0x134
  46
  47 #define RK3036_SDMMC_CON0               0x144
  48 #define RK3036_SDMMC_CON1               0x148
  49 #define RK3036_SDIO_CON0                0x14c
  50 #define RK3036_SDIO_CON1                0x150
  51 #define RK3036_EMMC_CON0                0x154
  52 #define RK3036_EMMC_CON1                0x158
  53
  54 #define RK3288_PLL_CON(x)               RK2928_PLL_CON(x)
  55 #define RK3288_MODE_CON                 0x50
  56 #define RK3288_CLKSEL_CON(x)            ((x) * 0x4 + 0x60)
  57 #define RK3288_CLKGATE_CON(x)           ((x) * 0x4 + 0x160)
  58 #define RK3288_GLB_SRST_FST             0x1b0
  59 #define RK3288_GLB_SRST_SND             0x1b4
  60 #define RK3288_SOFTRST_CON(x)           ((x) * 0x4 + 0x1b8)
  61 #define RK3288_MISC_CON                 0x1e8
  62 #define RK3288_SDMMC_CON0               0x200
  63 #define RK3288_SDMMC_CON1               0x204
  64 #define RK3288_SDIO0_CON0               0x208
  65 #define RK3288_SDIO0_CON1               0x20c
  66 #define RK3288_SDIO1_CON0               0x210
  67 #define RK3288_SDIO1_CON1               0x214
  68 #define RK3288_EMMC_CON0                0x218
  69 #define RK3288_EMMC_CON1                0x21c
  70
  71 #define RK3368_PLL_CON(x)               RK2928_PLL_CON(x)
  72 #define RK3368_CLKSEL_CON(x)            ((x) * 0x4 + 0x100)
  73 #define RK3368_CLKGATE_CON(x)           ((x) * 0x4 + 0x200)
  74 #define RK3368_GLB_SRST_FST             0x280
  75 #define RK3368_GLB_SRST_SND             0x284
  76 #define RK3368_SOFTRST_CON(x)           ((x) * 0x4 + 0x300)
  77 #define RK3368_MISC_CON                 0x380
  78 #define RK3368_SDMMC_CON0               0x400
  79 #define RK3368_SDMMC_CON1               0x404
  80 #define RK3368_SDIO0_CON0               0x408
  81 #define RK3368_SDIO0_CON1               0x40c
  82 #define RK3368_SDIO1_CON0               0x410
  83 #define RK3368_SDIO1_CON1               0x414
  84 #define RK3368_EMMC_CON0                0x418
  85 #define RK3368_EMMC_CON1                0x41c
  86
  87 #define RK3399_PLL_CON(x)               RK2928_PLL_CON(x)
  88 #define RK3399_CLKSEL_CON(x)            ((x) * 0x4 + 0x100)
  89 #define RK3399_CLKGATE_CON(x)           ((x) * 0x4 + 0x300)
  90 #define RK3399_SOFTRST_CON(x)           ((x) * 0x4 + 0x400)
  91 #define RK3399_GLB_SRST_FST             0x500
  92 #define RK3399_GLB_SRST_SND             0x504
  93 #define RK3399_GLB_CNT_TH               0x508
  94 #define RK3399_MISC_CON                 0x50c
  95 #define RK3399_RST_CON                  0x510
  96 #define RK3399_RST_ST                   0x514
  97 #define RK3399_SDMMC_CON0               0x580
  98 #define RK3399_SDMMC_CON1               0x584
  99 #define RK3399_SDIO_CON0                0x588
 100 #define RK3399_SDIO_CON1                0x58c
 101
 102 #define RK3399_PMU_PLL_CON(x)           RK2928_PLL_CON(x)
 103 #define RK3399_PMU_CLKSEL_CON(x)        ((x) * 0x4 + 0x80)
 104 #define RK3399_PMU_CLKGATE_CON(x)       ((x) * 0x4 + 0x100)
 105 #define RK3399_PMU_SOFTRST_CON(x)       ((x) * 0x4 + 0x110)
 106 #define RK3399_PMU_RSTNHOLD_CON(x)      ((x) * 0x4 + 0x120)
 107 #define RK3399_PMU_GATEDIS_CON(x)       ((x) * 0x4 + 0x130)
 108
 109 enum rockchip_pll_type {
 110         pll_rk3036,
 111         pll_rk3066,
 112         pll_rk3366,
 113         pll_rk3399,
 114 };
 115
 116 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
 117                         _postdiv2, _dsmpd, _frac)               \
 118 {                                                               \
 119         .rate   = _rate##U,                                     \
 120         .fbdiv = _fbdiv,                                        \
 121         .postdiv1 = _postdiv1,                                  \
 122         .refdiv = _refdiv,                                      \
 123         .postdiv2 = _postdiv2,                                  \
 124         .dsmpd = _dsmpd,                                        \
 125         .frac = _frac,                                          \
 126 }
 127
 128 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)   \
 129 {                                               \
 130         .rate   = _rate##U,                     \
 131         .nr = _nr,                              \
 132         .nf = _nf,                              \
 133         .no = _no,                              \
 134         .nb = ((_nf) < 2) ? 1 : (_nf) >> 1,     \
 135 }
 136
 137 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb)           \
 138 {                                                               \
 139         .rate   = _rate##U,                                     \
 140         .nr = _nr,                                              \
 141         .nf = _nf,                                              \
 142         .no = _no,                                              \
 143         .nb = _nb,                                              \
 144 }
 145
 146 /**
 147  * struct rockchip_clk_provider - information about clock provider
 148  * @reg_base: virtual address for the register base.
 149  * @clk_data: holds clock related data like clk* and number of clocks.
 150  * @cru_node: device-node of the clock-provider
 151  * @grf: regmap of the general-register-files syscon
 152  * @lock: maintains exclusion between callbacks for a given clock-provider.
 153  */
 154 struct rockchip_clk_provider {
 155         void __iomem *reg_base;
 156         struct clk_onecell_data clk_data;
 157         struct device_node *cru_node;
 158         struct regmap *grf;
 159         spinlock_t lock;
 160 };
 161
 162 struct rockchip_pll_rate_table {
 163         unsigned long rate;
 164         unsigned int nr;
 165         unsigned int nf;
 166         unsigned int no;
 167         unsigned int nb;
 168         /* for RK3036/RK3399 */
 169         unsigned int fbdiv;
 170         unsigned int postdiv1;
 171         unsigned int refdiv;
 172         unsigned int postdiv2;
 173         unsigned int dsmpd;
 174         unsigned int frac;
 175 };
 176
 177 /**
 178  * struct rockchip_pll_clock - information about pll clock
 179  * @id: platform specific id of the clock.
 180  * @name: name of this pll clock.
 181  * @parent_names: name of the parent clock.
 182  * @num_parents: number of parents
 183  * @flags: optional flags for basic clock.
 184  * @con_offset: offset of the register for configuring the PLL.
 185  * @mode_offset: offset of the register for configuring the PLL-mode.
 186  * @mode_shift: offset inside the mode-register for the mode of this pll.
 187  * @lock_shift: offset inside the lock register for the lock status.
 188  * @type: Type of PLL to be registered.
 189  * @pll_flags: hardware-specific flags
 190  * @rate_table: Table of usable pll rates
 191  *
 192  * Flags:
 193  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
 194  *      rate_table parameters and ajust them if necessary.
 195  */
 196 struct rockchip_pll_clock {
 197         unsigned int            id;
 198         const char              *name;
 199         const char              *const *parent_names;
 200         u8                      num_parents;
 201         unsigned long           flags;
 202         int                     con_offset;
 203         int                     mode_offset;
 204         int                     mode_shift;
 205         int                     lock_shift;
 206         enum rockchip_pll_type  type;
 207         u8                      pll_flags;
 208         struct rockchip_pll_rate_table *rate_table;
 209 };
 210
 211 #define ROCKCHIP_PLL_SYNC_RATE          BIT(0)
 212
 213 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,   \
 214                 _lshift, _pflags, _rtable)                              \
 215         {                                                               \
 216                 .id             = _id,                                  \
 217                 .type           = _type,                                \
 218                 .name           = _name,                                \
 219                 .parent_names   = _pnames,                              \
 220                 .num_parents    = ARRAY_SIZE(_pnames),                  \
 221                 .flags          = CLK_GET_RATE_NOCACHE | _flags,        \
 222                 .con_offset     = _con,                                 \
 223                 .mode_offset    = _mode,                                \
 224                 .mode_shift     = _mshift,                              \
 225                 .lock_shift     = _lshift,                              \
 226                 .pll_flags      = _pflags,                              \
 227                 .rate_table     = _rtable,                              \
 228         }
 229
 230 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 231                 enum rockchip_pll_type pll_type,
 232                 const char *name, const char *const *parent_names,
 233                 u8 num_parents, int con_offset, int grf_lock_offset,
 234                 int lock_shift, int mode_offset, int mode_shift,
 235                 struct rockchip_pll_rate_table *rate_table,
 236                 u8 clk_pll_flags);
 237
 238 struct rockchip_cpuclk_clksel {
 239         int reg;
 240         u32 val;
 241 };
 242
 243 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS    2
 244 struct rockchip_cpuclk_rate_table {
 245         unsigned long prate;
 246         struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
 247 };
 248
 249 /**
 250  * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock
 251  * @core_reg:           register offset of the core settings register
 252  * @div_core_shift:     core divider offset used to divide the pll value
 253  * @div_core_mask:      core divider mask
 254  * @mux_core_alt:       mux value to select alternate parent
 255  * @mux_core_main:      mux value to select main parent of core
 256  * @mux_core_shift:     offset of the core multiplexer
 257  * @mux_core_mask:      core multiplexer mask
 258  */
 259 struct rockchip_cpuclk_reg_data {
 260         int             core_reg;
 261         u8              div_core_shift;
 262         u32             div_core_mask;
 263         u8              mux_core_alt;
 264         u8              mux_core_main;
 265         u8              mux_core_shift;
 266         u32             mux_core_mask;
 267 };
 268
 269 struct clk *rockchip_clk_register_cpuclk(const char *name,
 270                         const char *const *parent_names, u8 num_parents,
 271                         const struct rockchip_cpuclk_reg_data *reg_data,
 272                         const struct rockchip_cpuclk_rate_table *rates,
 273                         int nrates, void __iomem *reg_base, spinlock_t *lock);
 274
 275 struct clk *rockchip_clk_register_mmc(const char *name,
 276                                 const char *const *parent_names, u8 num_parents,
 277                                 void __iomem *reg, int shift);
 278
 279 #define ROCKCHIP_INVERTER_HIWORD_MASK   BIT(0)
 280
 281 struct clk *rockchip_clk_register_inverter(const char *name,
 282                                 const char *const *parent_names, u8 num_parents,
 283                                 void __iomem *reg, int shift, int flags,
 284                                 spinlock_t *lock);
 285
 286 #define PNAME(x) static const char *const x[] __initconst
 287
 288 enum rockchip_clk_branch_type {
 289         branch_composite,
 290         branch_mux,
 291         branch_divider,
 292         branch_fraction_divider,
 293         branch_gate,
 294         branch_mmc,
 295         branch_inverter,
 296         branch_factor,
 297 };
 298
 299 struct rockchip_clk_branch {
 300         unsigned int                    id;
 301         enum rockchip_clk_branch_type   branch_type;
 302         const char                      *name;
 303         const char                      *const *parent_names;
 304         u8                              num_parents;
 305         unsigned long                   flags;
 306         int                             muxdiv_offset;
 307         u8                              mux_shift;
 308         u8                              mux_width;
 309         u8                              mux_flags;
 310         u8                              div_shift;
 311         u8                              div_width;
 312         u8                              div_flags;
 313         struct clk_div_table            *div_table;
 314         int                             gate_offset;
 315         u8                              gate_shift;
 316         u8                              gate_flags;
 317         struct rockchip_clk_branch      *child;
 318 };
 319
 320 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
 321                   df, go, gs, gf)                               \
 322         {                                                       \
 323                 .id             = _id,                          \
 324                 .branch_type    = branch_composite,             \
 325                 .name           = cname,                        \
 326                 .parent_names   = pnames,                       \
 327                 .num_parents    = ARRAY_SIZE(pnames),           \
 328                 .flags          = f,                            \
 329                 .muxdiv_offset  = mo,                           \
 330                 .mux_shift      = ms,                           \
 331                 .mux_width      = mw,                           \
 332                 .mux_flags      = mf,                           \
 333                 .div_shift      = ds,                           \
 334                 .div_width      = dw,                           \
 335                 .div_flags      = df,                           \
 336                 .gate_offset    = go,                           \
 337                 .gate_shift     = gs,                           \
 338                 .gate_flags     = gf,                           \
 339         }
 340
 341 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,   \
 342                         go, gs, gf)                             \
 343         {                                                       \
 344                 .id             = _id,                          \
 345                 .branch_type    = branch_composite,             \
 346                 .name           = cname,                        \
 347                 .parent_names   = (const char *[]){ pname },    \
 348                 .num_parents    = 1,                            \
 349                 .flags          = f,                            \
 350                 .muxdiv_offset  = mo,                           \
 351                 .div_shift      = ds,                           \
 352                 .div_width      = dw,                           \
 353                 .div_flags      = df,                           \
 354                 .gate_offset    = go,                           \
 355                 .gate_shift     = gs,                           \
 356                 .gate_flags     = gf,                           \
 357         }
 358
 359 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
 360                                df, dt, go, gs, gf)              \
 361         {                                                       \
 362                 .id             = _id,                          \
 363                 .branch_type    = branch_composite,             \
 364                 .name           = cname,                        \
 365                 .parent_names   = (const char *[]){ pname },    \
 366                 .num_parents    = 1,                            \
 367                 .flags          = f,                            \
 368                 .muxdiv_offset  = mo,                           \
 369                 .div_shift      = ds,                           \
 370                 .div_width      = dw,                           \
 371                 .div_flags      = df,                           \
 372                 .div_table      = dt,                           \
 373                 .gate_offset    = go,                           \
 374                 .gate_shift     = gs,                           \
 375                 .gate_flags     = gf,                           \
 376         }
 377
 378 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf,  \
 379                         go, gs, gf)                             \
 380         {                                                       \
 381                 .id             = _id,                          \
 382                 .branch_type    = branch_composite,             \
 383                 .name           = cname,                        \
 384                 .parent_names   = pnames,                       \
 385                 .num_parents    = ARRAY_SIZE(pnames),           \
 386                 .flags          = f,                            \
 387                 .muxdiv_offset  = mo,                           \
 388                 .mux_shift      = ms,                           \
 389                 .mux_width      = mw,                           \
 390                 .mux_flags      = mf,                           \
 391                 .gate_offset    = go,                           \
 392                 .gate_shift     = gs,                           \
 393                 .gate_flags     = gf,                           \
 394         }
 395
 396 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
 397                          ds, dw, df)                            \
 398         {                                                       \
 399                 .id             = _id,                          \
 400                 .branch_type    = branch_composite,             \
 401                 .name           = cname,                        \
 402                 .parent_names   = pnames,                       \
 403                 .num_parents    = ARRAY_SIZE(pnames),           \
 404                 .flags          = f,                            \
 405                 .muxdiv_offset  = mo,                           \
 406                 .mux_shift      = ms,                           \
 407                 .mux_width      = mw,                           \
 408                 .mux_flags      = mf,                           \
 409                 .div_shift      = ds,                           \
 410                 .div_width      = dw,                           \
 411                 .div_flags      = df,                           \
 412                 .gate_offset    = -1,                           \
 413         }
 414
 415 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,  \
 416                                 mw, mf, ds, dw, df, dt)         \
 417         {                                                       \
 418                 .id             = _id,                          \
 419                 .branch_type    = branch_composite,             \
 420                 .name           = cname,                        \
 421                 .parent_names   = pnames,                       \
 422                 .num_parents    = ARRAY_SIZE(pnames),           \
 423                 .flags          = f,                            \
 424                 .muxdiv_offset  = mo,                           \
 425                 .mux_shift      = ms,                           \
 426                 .mux_width      = mw,                           \
 427                 .mux_flags      = mf,                           \
 428                 .div_shift      = ds,                           \
 429                 .div_width      = dw,                           \
 430                 .div_flags      = df,                           \
 431                 .div_table      = dt,                           \
 432                 .gate_offset    = -1,                           \
 433         }
 434
 435 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
 436         {                                                       \
 437                 .id             = _id,                          \
 438                 .branch_type    = branch_fraction_divider,      \
 439                 .name           = cname,                        \
 440                 .parent_names   = (const char *[]){ pname },    \
 441                 .num_parents    = 1,                            \
 442                 .flags          = f,                            \
 443                 .muxdiv_offset  = mo,                           \
 444                 .div_shift      = 16,                           \
 445                 .div_width      = 16,                           \
 446                 .div_flags      = df,                           \
 447                 .gate_offset    = go,                           \
 448                 .gate_shift     = gs,                           \
 449                 .gate_flags     = gf,                           \
 450         }
 451
 452 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
 453         {                                                       \
 454                 .id             = _id,                          \
 455                 .branch_type    = branch_fraction_divider,      \
 456                 .name           = cname,                        \
 457                 .parent_names   = (const char *[]){ pname },    \
 458                 .num_parents    = 1,                            \
 459                 .flags          = f,                            \
 460                 .muxdiv_offset  = mo,                           \
 461                 .div_shift      = 16,                           \
 462                 .div_width      = 16,                           \
 463                 .div_flags      = df,                           \
 464                 .gate_offset    = go,                           \
 465                 .gate_shift     = gs,                           \
 466                 .gate_flags     = gf,                           \
 467                 .child          = ch,                           \
 468         }
 469
 470 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
 471         {                                                       \
 472                 .id             = _id,                          \
 473                 .branch_type    = branch_fraction_divider,      \
 474                 .name           = cname,                        \
 475                 .parent_names   = (const char *[]){ pname },    \
 476                 .num_parents    = 1,                            \
 477                 .flags          = f,                            \
 478                 .muxdiv_offset  = mo,                           \
 479                 .div_shift      = 16,                           \
 480                 .div_width      = 16,                           \
 481                 .div_flags      = df,                           \
 482                 .gate_offset    = -1,                           \
 483                 .child          = ch,                           \
 484         }
 485
 486 #define MUX(_id, cname, pnames, f, o, s, w, mf)                 \
 487         {                                                       \
 488                 .id             = _id,                          \
 489                 .branch_type    = branch_mux,                   \
 490                 .name           = cname,                        \
 491                 .parent_names   = pnames,                       \
 492                 .num_parents    = ARRAY_SIZE(pnames),           \
 493                 .flags          = f,                            \
 494                 .muxdiv_offset  = o,                            \
 495                 .mux_shift      = s,                            \
 496                 .mux_width      = w,                            \
 497                 .mux_flags      = mf,                           \
 498                 .gate_offset    = -1,                           \
 499         }
 500
 501 #define DIV(_id, cname, pname, f, o, s, w, df)                  \
 502         {                                                       \
 503                 .id             = _id,                          \
 504                 .branch_type    = branch_divider,               \
 505                 .name           = cname,                        \
 506                 .parent_names   = (const char *[]){ pname },    \
 507                 .num_parents    = 1,                            \
 508                 .flags          = f,                            \
 509                 .muxdiv_offset  = o,                            \
 510                 .div_shift      = s,                            \
 511                 .div_width      = w,                            \
 512                 .div_flags      = df,                           \
 513                 .gate_offset    = -1,                           \
 514         }
 515
 516 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt)           \
 517         {                                                       \
 518                 .id             = _id,                          \
 519                 .branch_type    = branch_divider,               \
 520                 .name           = cname,                        \
 521                 .parent_names   = (const char *[]){ pname },    \
 522                 .num_parents    = 1,                            \
 523                 .flags          = f,                            \
 524                 .muxdiv_offset  = o,                            \
 525                 .div_shift      = s,                            \
 526                 .div_width      = w,                            \
 527                 .div_flags      = df,                           \
 528                 .div_table      = dt,                           \
 529         }
 530
 531 #define GATE(_id, cname, pname, f, o, b, gf)                    \
 532         {                                                       \
 533                 .id             = _id,                          \
 534                 .branch_type    = branch_gate,                  \
 535                 .name           = cname,                        \
 536                 .parent_names   = (const char *[]){ pname },    \
 537                 .num_parents    = 1,                            \
 538                 .flags          = f,                            \
 539                 .gate_offset    = o,                            \
 540                 .gate_shift     = b,                            \
 541                 .gate_flags     = gf,                           \
 542         }
 543
 544 #define MMC(_id, cname, pname, offset, shift)                   \
 545         {                                                       \
 546                 .id             = _id,                          \
 547                 .branch_type    = branch_mmc,                   \
 548                 .name           = cname,                        \
 549                 .parent_names   = (const char *[]){ pname },    \
 550                 .num_parents    = 1,                            \
 551                 .muxdiv_offset  = offset,                       \
 552                 .div_shift      = shift,                        \
 553         }
 554
 555 #define INVERTER(_id, cname, pname, io, is, if)                 \
 556         {                                                       \
 557                 .id             = _id,                          \
 558                 .branch_type    = branch_inverter,              \
 559                 .name           = cname,                        \
 560                 .parent_names   = (const char *[]){ pname },    \
 561                 .num_parents    = 1,                            \
 562                 .muxdiv_offset  = io,                           \
 563                 .div_shift      = is,                           \
 564                 .div_flags      = if,                           \
 565         }
 566
 567 #define FACTOR(_id, cname, pname,  f, fm, fd)                   \
 568         {                                                       \
 569                 .id             = _id,                          \
 570                 .branch_type    = branch_factor,                \
 571                 .name           = cname,                        \
 572                 .parent_names   = (const char *[]){ pname },    \
 573                 .num_parents    = 1,                            \
 574                 .flags          = f,                            \
 575                 .div_shift      = fm,                           \
 576                 .div_width      = fd,                           \
 577         }
 578
 579 #define FACTOR_GATE(_id, cname, pname,  f, fm, fd, go, gb, gf)  \
 580         {                                                       \
 581                 .id             = _id,                          \
 582                 .branch_type    = branch_factor,                \
 583                 .name           = cname,                        \
 584                 .parent_names   = (const char *[]){ pname },    \
 585                 .num_parents    = 1,                            \
 586                 .flags          = f,                            \
 587                 .div_shift      = fm,                           \
 588                 .div_width      = fd,                           \
 589                 .gate_offset    = go,                           \
 590                 .gate_shift     = gb,                           \
 591                 .gate_flags     = gf,                           \
 592         }
 593
 594 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
 595                         void __iomem *base, unsigned long nr_clks);
 596 void rockchip_clk_of_add_provider(struct device_node *np,
 597                                 struct rockchip_clk_provider *ctx);
 598 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
 599 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
 600                              struct clk *clk, unsigned int id);
 601 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
 602                                     struct rockchip_clk_branch *list,
 603                                     unsigned int nr_clk);
 604 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 605                                 struct rockchip_pll_clock *pll_list,
 606                                 unsigned int nr_pll, int grf_lock_offset);
 607 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
 608                         unsigned int lookup_id, const char *name,
 609                         const char *const *parent_names, u8 num_parents,
 610                         const struct rockchip_cpuclk_reg_data *reg_data,
 611                         const struct rockchip_cpuclk_rate_table *rates,
 612                         int nrates);
 613 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
 614 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
 615                                         unsigned int reg, void (*cb)(void));
 616
 617 #define ROCKCHIP_SOFTRST_HIWORD_MASK    BIT(0)
 618
 619 #ifdef CONFIG_RESET_CONTROLLER
 620 void rockchip_register_softrst(struct device_node *np,
 621                                unsigned int num_regs,
 622                                void __iomem *base, u8 flags);
 623 #else
 624 static inline void rockchip_register_softrst(struct device_node *np,
 625                                unsigned int num_regs,
 626                                void __iomem *base, u8 flags)
 627 {
 628 }
 629 #endif
 630
 631 #endif