drivers/clk/rockchip/clk-rk3288.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/syscore_ops.h>
  20 #include <dt-bindings/clock/rk3288-cru.h>
  21 #include "clk.h"
  22
  23 #define RK3288_GRF_SOC_CON(x)   (0x244 + x * 4)
  24 #define RK3288_GRF_SOC_STATUS1  0x284
  25
  26 enum rk3288_plls {
  27         apll, dpll, cpll, gpll, npll,
  28 };
  29
  30 static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
  31         RK3066_PLL_RATE(2208000000, 1, 92, 1),
  32         RK3066_PLL_RATE(2184000000, 1, 91, 1),
  33         RK3066_PLL_RATE(2160000000, 1, 90, 1),
  34         RK3066_PLL_RATE(2136000000, 1, 89, 1),
  35         RK3066_PLL_RATE(2112000000, 1, 88, 1),
  36         RK3066_PLL_RATE(2088000000, 1, 87, 1),
  37         RK3066_PLL_RATE(2064000000, 1, 86, 1),
  38         RK3066_PLL_RATE(2040000000, 1, 85, 1),
  39         RK3066_PLL_RATE(2016000000, 1, 84, 1),
  40         RK3066_PLL_RATE(1992000000, 1, 83, 1),
  41         RK3066_PLL_RATE(1968000000, 1, 82, 1),
  42         RK3066_PLL_RATE(1944000000, 1, 81, 1),
  43         RK3066_PLL_RATE(1920000000, 1, 80, 1),
  44         RK3066_PLL_RATE(1896000000, 1, 79, 1),
  45         RK3066_PLL_RATE(1872000000, 1, 78, 1),
  46         RK3066_PLL_RATE(1848000000, 1, 77, 1),
  47         RK3066_PLL_RATE(1824000000, 1, 76, 1),
  48         RK3066_PLL_RATE(1800000000, 1, 75, 1),
  49         RK3066_PLL_RATE(1776000000, 1, 74, 1),
  50         RK3066_PLL_RATE(1752000000, 1, 73, 1),
  51         RK3066_PLL_RATE(1728000000, 1, 72, 1),
  52         RK3066_PLL_RATE(1704000000, 1, 71, 1),
  53         RK3066_PLL_RATE(1680000000, 1, 70, 1),
  54         RK3066_PLL_RATE(1656000000, 1, 69, 1),
  55         RK3066_PLL_RATE(1632000000, 1, 68, 1),
  56         RK3066_PLL_RATE(1608000000, 1, 67, 1),
  57         RK3066_PLL_RATE(1560000000, 1, 65, 1),
  58         RK3066_PLL_RATE(1512000000, 1, 63, 1),
  59         RK3066_PLL_RATE(1488000000, 1, 62, 1),
  60         RK3066_PLL_RATE(1464000000, 1, 61, 1),
  61         RK3066_PLL_RATE(1440000000, 1, 60, 1),
  62         RK3066_PLL_RATE(1416000000, 1, 59, 1),
  63         RK3066_PLL_RATE(1392000000, 1, 58, 1),
  64         RK3066_PLL_RATE(1368000000, 1, 57, 1),
  65         RK3066_PLL_RATE(1344000000, 1, 56, 1),
  66         RK3066_PLL_RATE(1320000000, 1, 55, 1),
  67         RK3066_PLL_RATE(1296000000, 1, 54, 1),
  68         RK3066_PLL_RATE(1272000000, 1, 53, 1),
  69         RK3066_PLL_RATE(1248000000, 1, 52, 1),
  70         RK3066_PLL_RATE(1224000000, 1, 51, 1),
  71         RK3066_PLL_RATE(1200000000, 1, 50, 1),
  72         RK3066_PLL_RATE(1188000000, 2, 99, 1),
  73         RK3066_PLL_RATE(1176000000, 1, 49, 1),
  74         RK3066_PLL_RATE(1128000000, 1, 47, 1),
  75         RK3066_PLL_RATE(1104000000, 1, 46, 1),
  76         RK3066_PLL_RATE(1008000000, 1, 84, 2),
  77         RK3066_PLL_RATE( 912000000, 1, 76, 2),
  78         RK3066_PLL_RATE( 891000000, 8, 594, 2),
  79         RK3066_PLL_RATE( 888000000, 1, 74, 2),
  80         RK3066_PLL_RATE( 816000000, 1, 68, 2),
  81         RK3066_PLL_RATE( 798000000, 2, 133, 2),
  82         RK3066_PLL_RATE( 792000000, 1, 66, 2),
  83         RK3066_PLL_RATE( 768000000, 1, 64, 2),
  84         RK3066_PLL_RATE( 742500000, 8, 495, 2),
  85         RK3066_PLL_RATE( 696000000, 1, 58, 2),
  86         RK3066_PLL_RATE( 600000000, 1, 50, 2),
  87         RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
  88         RK3066_PLL_RATE( 552000000, 1, 46, 2),
  89         RK3066_PLL_RATE( 504000000, 1, 84, 4),
  90         RK3066_PLL_RATE( 500000000, 3, 125, 2),
  91         RK3066_PLL_RATE( 456000000, 1, 76, 4),
  92         RK3066_PLL_RATE( 408000000, 1, 68, 4),
  93         RK3066_PLL_RATE( 400000000, 3, 100, 2),
  94         RK3066_PLL_RATE( 384000000, 2, 128, 4),
  95         RK3066_PLL_RATE( 360000000, 1, 60, 4),
  96         RK3066_PLL_RATE( 312000000, 1, 52, 4),
  97         RK3066_PLL_RATE( 300000000, 1, 50, 4),
  98         RK3066_PLL_RATE( 297000000, 2, 198, 8),
  99         RK3066_PLL_RATE( 252000000, 1, 84, 8),
 100         RK3066_PLL_RATE( 216000000, 1, 72, 8),
 101         RK3066_PLL_RATE( 148500000, 2, 99, 8),
 102         RK3066_PLL_RATE( 126000000, 1, 84, 16),
 103         RK3066_PLL_RATE(  48000000, 1, 64, 32),
 104         { /* sentinel */ },
 105 };
 106
 107 #define RK3288_DIV_ACLK_CORE_M0_MASK    0xf
 108 #define RK3288_DIV_ACLK_CORE_M0_SHIFT   0
 109 #define RK3288_DIV_ACLK_CORE_MP_MASK    0xf
 110 #define RK3288_DIV_ACLK_CORE_MP_SHIFT   4
 111 #define RK3288_DIV_L2RAM_MASK           0x7
 112 #define RK3288_DIV_L2RAM_SHIFT          0
 113 #define RK3288_DIV_ATCLK_MASK           0x1f
 114 #define RK3288_DIV_ATCLK_SHIFT          4
 115 #define RK3288_DIV_PCLK_DBGPRE_MASK     0x1f
 116 #define RK3288_DIV_PCLK_DBGPRE_SHIFT    9
 117
 118 #define RK3288_CLKSEL0(_core_m0, _core_mp)                              \
 119         {                                                               \
 120                 .reg = RK3288_CLKSEL_CON(0),                            \
 121                 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
 122                                 RK3288_DIV_ACLK_CORE_M0_SHIFT) |        \
 123                        HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
 124                                 RK3288_DIV_ACLK_CORE_MP_SHIFT),         \
 125         }
 126 #define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre)                  \
 127         {                                                               \
 128                 .reg = RK3288_CLKSEL_CON(37),                           \
 129                 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK,     \
 130                                 RK3288_DIV_L2RAM_SHIFT) |               \
 131                        HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK,     \
 132                                 RK3288_DIV_ATCLK_SHIFT) |               \
 133                        HIWORD_UPDATE(_pclk_dbg_pre,                     \
 134                                 RK3288_DIV_PCLK_DBGPRE_MASK,            \
 135                                 RK3288_DIV_PCLK_DBGPRE_SHIFT),          \
 136         }
 137
 138 #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
 139         {                                                               \
 140                 .prate = _prate,                                        \
 141                 .divs = {                                               \
 142                         RK3288_CLKSEL0(_core_m0, _core_mp),             \
 143                         RK3288_CLKSEL37(_l2ram, _atclk, _pdbg),         \
 144                 },                                                      \
 145         }
 146
 147 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
 148         RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
 149         RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
 150         RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
 151         RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
 152         RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
 153         RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
 154         RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
 155         RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
 156         RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
 157         RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
 158         RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
 159         RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
 160         RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
 161         RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
 162 };
 163
 164 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
 165         .core_reg = RK3288_CLKSEL_CON(0),
 166         .div_core_shift = 8,
 167         .div_core_mask = 0x1f,
 168         .mux_core_alt = 1,
 169         .mux_core_main = 0,
 170         .mux_core_shift = 15,
 171         .mux_core_mask = 0x1,
 172 };
 173
 174 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
 175 PNAME(mux_armclk_p)             = { "apll_core", "gpll_core" };
 176 PNAME(mux_ddrphy_p)             = { "dpll_ddr", "gpll_ddr" };
 177 PNAME(mux_aclk_cpu_src_p)       = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 178
 179 PNAME(mux_pll_src_cpll_gpll_p)          = { "cpll", "gpll" };
 180 PNAME(mux_pll_src_npll_cpll_gpll_p)     = { "npll", "cpll", "gpll" };
 181 PNAME(mux_pll_src_cpll_gpll_npll_p)     = { "cpll", "gpll", "npll" };
 182 PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "usbphy480m_src" };
 183 PNAME(mux_pll_src_cpll_gll_usb_npll_p)  = { "cpll", "gpll", "usbphy480m_src", "npll" };
 184
 185 PNAME(mux_mmc_src_p)    = { "cpll", "gpll", "xin24m", "xin24m" };
 186 PNAME(mux_i2s_pre_p)    = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 187 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
 188 PNAME(mux_spdif_p)      = { "spdif_pre", "spdif_frac", "xin12m" };
 189 PNAME(mux_spdif_8ch_p)  = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
 190 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
 191 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
 192 PNAME(mux_uart2_p)      = { "uart2_src", "uart2_frac", "xin24m" };
 193 PNAME(mux_uart3_p)      = { "uart3_src", "uart3_frac", "xin24m" };
 194 PNAME(mux_uart4_p)      = { "uart4_src", "uart4_frac", "xin24m" };
 195 PNAME(mux_vip_out_p)    = { "vip_src", "xin24m" };
 196 PNAME(mux_mac_p)        = { "mac_pll_src", "ext_gmac" };
 197 PNAME(mux_hsadcout_p)   = { "hsadc_src", "ext_hsadc" };
 198 PNAME(mux_edp_24m_p)    = { "ext_edp_24m", "xin24m" };
 199 PNAME(mux_tspout_p)     = { "cpll", "gpll", "npll", "xin27m" };
 200
 201 PNAME(mux_usbphy480m_p)         = { "sclk_otgphy1", "sclk_otgphy2",
 202                                     "sclk_otgphy0" };
 203 PNAME(mux_hsicphy480m_p)        = { "cpll", "gpll", "usbphy480m_src" };
 204 PNAME(mux_hsicphy12m_p)         = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
 205
 206 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
 207         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
 208                      RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
 209         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
 210                      RK3288_MODE_CON, 4, 5, 0, NULL),
 211         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
 212                      RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 213         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
 214                      RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 215         [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
 216                      RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 217 };
 218
 219 static struct clk_div_table div_hclk_cpu_t[] = {
 220         { .val = 0, .div = 1 },
 221         { .val = 1, .div = 2 },
 222         { .val = 3, .div = 4 },
 223         { /* sentinel */},
 224 };
 225
 226 #define MFLAGS CLK_MUX_HIWORD_MASK
 227 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 228 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 229 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
 230
 231 static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =
 232         MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
 233                         RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
 234
 235 static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =
 236         MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
 237                         RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
 238
 239 static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =
 240         MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
 241                         RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
 242
 243 static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata =
 244         MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 245                         RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
 246
 247 static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata =
 248         MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
 249                         RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
 250
 251 static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata =
 252         MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 253                         RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
 254
 255 static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata =
 256         MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
 257                         RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
 258
 259 static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata =
 260         MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
 261                         RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
 262
 263 static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 264         /*
 265          * Clock-Architecture Diagram 1
 266          */
 267
 268         GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
 269                         RK3288_CLKGATE_CON(0), 1, GFLAGS),
 270         GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
 271                         RK3288_CLKGATE_CON(0), 2, GFLAGS),
 272
 273         COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
 274                         RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 275                         RK3288_CLKGATE_CON(12), 0, GFLAGS),
 276         COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
 277                         RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 278                         RK3288_CLKGATE_CON(12), 1, GFLAGS),
 279         COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
 280                         RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 281                         RK3288_CLKGATE_CON(12), 2, GFLAGS),
 282         COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
 283                         RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 284                         RK3288_CLKGATE_CON(12), 3, GFLAGS),
 285         COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
 286                         RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 287                         RK3288_CLKGATE_CON(12), 4, GFLAGS),
 288         COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
 289                         RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 290                         RK3288_CLKGATE_CON(12), 5, GFLAGS),
 291         COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
 292                         RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 293                         RK3288_CLKGATE_CON(12), 6, GFLAGS),
 294         COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
 295                         RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 296                         RK3288_CLKGATE_CON(12), 7, GFLAGS),
 297         COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
 298                         RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 299                         RK3288_CLKGATE_CON(12), 8, GFLAGS),
 300         GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
 301                         RK3288_CLKGATE_CON(12), 9, GFLAGS),
 302         GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
 303                         RK3288_CLKGATE_CON(12), 10, GFLAGS),
 304         GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
 305                         RK3288_CLKGATE_CON(12), 11, GFLAGS),
 306
 307         GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
 308                         RK3288_CLKGATE_CON(0), 8, GFLAGS),
 309         GATE(0, "gpll_ddr", "gpll", 0,
 310                         RK3288_CLKGATE_CON(0), 9, GFLAGS),
 311         COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 312                         RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
 313                                         DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 314
 315         GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
 316                         RK3288_CLKGATE_CON(0), 10, GFLAGS),
 317         GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
 318                         RK3288_CLKGATE_CON(0), 11, GFLAGS),
 319         COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
 320                         RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
 321         DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
 322                         RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
 323         GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 324                         RK3288_CLKGATE_CON(0), 3, GFLAGS),
 325         COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 326                         RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
 327                         RK3288_CLKGATE_CON(0), 5, GFLAGS),
 328         COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 329                         RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
 330                         RK3288_CLKGATE_CON(0), 4, GFLAGS),
 331         GATE(0, "c2c_host", "aclk_cpu_src", 0,
 332                         RK3288_CLKGATE_CON(13), 8, GFLAGS),
 333         COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
 334                         RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
 335                         RK3288_CLKGATE_CON(5), 4, GFLAGS),
 336         GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 337                         RK3288_CLKGATE_CON(0), 7, GFLAGS),
 338
 339         COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
 340                         RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
 341                         RK3288_CLKGATE_CON(4), 1, GFLAGS),
 342         COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
 343                         RK3288_CLKSEL_CON(8), 0,
 344                         RK3288_CLKGATE_CON(4), 2, GFLAGS,
 345                         &rk3288_i2s_fracmux),
 346         COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
 347                         RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
 348                         RK3288_CLKGATE_CON(4), 0, GFLAGS),
 349         GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
 350                         RK3288_CLKGATE_CON(4), 3, GFLAGS),
 351
 352         MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
 353                         RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
 354         COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
 355                         RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
 356                         RK3288_CLKGATE_CON(4), 4, GFLAGS),
 357         COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
 358                         RK3288_CLKSEL_CON(9), 0,
 359                         RK3288_CLKGATE_CON(4), 5, GFLAGS,
 360                         &rk3288_spdif_fracmux),
 361         GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
 362                         RK3288_CLKGATE_CON(4), 6, GFLAGS),
 363         COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
 364                         RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
 365                         RK3288_CLKGATE_CON(4), 7, GFLAGS),
 366         COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
 367                         RK3288_CLKSEL_CON(41), 0,
 368                         RK3288_CLKGATE_CON(4), 8, GFLAGS,
 369                         &rk3288_spdif_8ch_fracmux),
 370         GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
 371                         RK3288_CLKGATE_CON(4), 9, GFLAGS),
 372
 373         GATE(0, "sclk_acc_efuse", "xin24m", 0,
 374                         RK3288_CLKGATE_CON(0), 12, GFLAGS),
 375
 376         GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
 377                         RK3288_CLKGATE_CON(1), 0, GFLAGS),
 378         GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
 379                         RK3288_CLKGATE_CON(1), 1, GFLAGS),
 380         GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
 381                         RK3288_CLKGATE_CON(1), 2, GFLAGS),
 382         GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
 383                         RK3288_CLKGATE_CON(1), 3, GFLAGS),
 384         GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
 385                         RK3288_CLKGATE_CON(1), 4, GFLAGS),
 386         GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
 387                         RK3288_CLKGATE_CON(1), 5, GFLAGS),
 388
 389         /*
 390          * Clock-Architecture Diagram 2
 391          */
 392
 393         COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 394                         RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
 395                         RK3288_CLKGATE_CON(3), 9, GFLAGS),
 396         COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 397                         RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
 398                         RK3288_CLKGATE_CON(3), 11, GFLAGS),
 399         /*
 400          * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
 401          * so we ignore the mux and make clocks nodes as following,
 402          */
 403         GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
 404                 RK3288_CLKGATE_CON(9), 0, GFLAGS),
 405         /*
 406          * We introduce a virtul node of hclk_vodec_pre_v to split one clock
 407          * struct with a gate and a fix divider into two node in software.
 408          */
 409         GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,
 410                 RK3288_CLKGATE_CON(3), 10, GFLAGS),
 411         GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
 412                 RK3288_CLKGATE_CON(9), 1, GFLAGS),
 413
 414         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
 415                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
 416                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
 417         DIV(0, "hclk_vio", "aclk_vio0", 0,
 418                         RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
 419         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
 420                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
 421                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
 422
 423         COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
 424                         RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
 425                         RK3288_CLKGATE_CON(3), 5, GFLAGS),
 426         COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
 427                         RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
 428                         RK3288_CLKGATE_CON(3), 4, GFLAGS),
 429
 430         COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
 431                         RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
 432                         RK3288_CLKGATE_CON(3), 1, GFLAGS),
 433         COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
 434                         RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
 435                         RK3288_CLKGATE_CON(3), 3, GFLAGS),
 436
 437         COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
 438                         RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
 439                         RK3288_CLKGATE_CON(3), 12, GFLAGS),
 440         COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
 441                         RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
 442                         RK3288_CLKGATE_CON(3), 13, GFLAGS),
 443
 444         COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
 445                         RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
 446                         RK3288_CLKGATE_CON(3), 14, GFLAGS),
 447         COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
 448                         RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
 449                         RK3288_CLKGATE_CON(3), 15, GFLAGS),
 450
 451         GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 452                         RK3288_CLKGATE_CON(5), 12, GFLAGS),
 453         GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
 454                         RK3288_CLKGATE_CON(5), 11, GFLAGS),
 455
 456         COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
 457                         RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
 458                         RK3288_CLKGATE_CON(13), 13, GFLAGS),
 459         DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
 460                         RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
 461
 462         COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
 463                         RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
 464                         RK3288_CLKGATE_CON(13), 14, GFLAGS),
 465         COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
 466                         RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
 467                         RK3288_CLKGATE_CON(13), 15, GFLAGS),
 468
 469         COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 470                         RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
 471                         RK3288_CLKGATE_CON(3), 7, GFLAGS),
 472         COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
 473                         RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
 474
 475         DIV(0, "pclk_pd_alive", "gpll", 0,
 476                         RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
 477         COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
 478                         RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
 479                         RK3288_CLKGATE_CON(5), 8, GFLAGS),
 480
 481         COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
 482                         RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
 483                         RK3288_CLKGATE_CON(5), 7, GFLAGS),
 484
 485         COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 486                         RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
 487                         RK3288_CLKGATE_CON(2), 0, GFLAGS),
 488         COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
 489                         RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 490                         RK3288_CLKGATE_CON(2), 3, GFLAGS),
 491         COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 492                         RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 493                         RK3288_CLKGATE_CON(2), 2, GFLAGS),
 494         GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 495                         RK3288_CLKGATE_CON(2), 1, GFLAGS),
 496
 497         /*
 498          * Clock-Architecture Diagram 3
 499          */
 500
 501         COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
 502                         RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
 503                         RK3288_CLKGATE_CON(2), 9, GFLAGS),
 504         COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
 505                         RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
 506                         RK3288_CLKGATE_CON(2), 10, GFLAGS),
 507         COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
 508                         RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
 509                         RK3288_CLKGATE_CON(2), 11, GFLAGS),
 510
 511         COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
 512                         RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
 513                         RK3288_CLKGATE_CON(13), 0, GFLAGS),
 514         COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
 515                         RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
 516                         RK3288_CLKGATE_CON(13), 1, GFLAGS),
 517         COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
 518                         RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
 519                         RK3288_CLKGATE_CON(13), 2, GFLAGS),
 520         COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
 521                         RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
 522                         RK3288_CLKGATE_CON(13), 3, GFLAGS),
 523
 524         MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
 525         MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
 526
 527         MMC(SCLK_SDIO0_DRV,    "sdio0_drv",    "sclk_sdio0", RK3288_SDIO0_CON0, 1),
 528         MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
 529
 530         MMC(SCLK_SDIO1_DRV,    "sdio1_drv",    "sclk_sdio1", RK3288_SDIO1_CON0, 1),
 531         MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
 532
 533         MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3288_EMMC_CON0,  1),
 534         MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3288_EMMC_CON1,  0),
 535
 536         COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
 537                         RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
 538                         RK3288_CLKGATE_CON(4), 11, GFLAGS),
 539         COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
 540                         RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
 541                         RK3288_CLKGATE_CON(4), 10, GFLAGS),
 542
 543         GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
 544                         RK3288_CLKGATE_CON(13), 4, GFLAGS),
 545         GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
 546                         RK3288_CLKGATE_CON(13), 5, GFLAGS),
 547         GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED,
 548                         RK3288_CLKGATE_CON(13), 6, GFLAGS),
 549         GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
 550                         RK3288_CLKGATE_CON(13), 7, GFLAGS),
 551
 552         COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
 553                         RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
 554                         RK3288_CLKGATE_CON(2), 7, GFLAGS),
 555
 556         COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
 557                         RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
 558                         RK3288_CLKGATE_CON(2), 8, GFLAGS),
 559
 560         GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
 561                         RK3288_CLKGATE_CON(5), 13, GFLAGS),
 562
 563         COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
 564                         RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
 565                         RK3288_CLKGATE_CON(5), 5, GFLAGS),
 566         COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
 567                         RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
 568                         RK3288_CLKGATE_CON(5), 6, GFLAGS),
 569
 570         COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
 571                         RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
 572                         RK3288_CLKGATE_CON(1), 8, GFLAGS),
 573         COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
 574                         RK3288_CLKSEL_CON(17), 0,
 575                         RK3288_CLKGATE_CON(1), 9, GFLAGS,
 576                         &rk3288_uart0_fracmux),
 577         MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
 578                         RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
 579         COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
 580                         RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
 581                         RK3288_CLKGATE_CON(1), 10, GFLAGS),
 582         COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
 583                         RK3288_CLKSEL_CON(18), 0,
 584                         RK3288_CLKGATE_CON(1), 11, GFLAGS,
 585                         &rk3288_uart1_fracmux),
 586         COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
 587                         RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
 588                         RK3288_CLKGATE_CON(1), 12, GFLAGS),
 589         COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
 590                         RK3288_CLKSEL_CON(19), 0,
 591                         RK3288_CLKGATE_CON(1), 13, GFLAGS,
 592                         &rk3288_uart2_fracmux),
 593         COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
 594                         RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
 595                         RK3288_CLKGATE_CON(1), 14, GFLAGS),
 596         COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
 597                         RK3288_CLKSEL_CON(20), 0,
 598                         RK3288_CLKGATE_CON(1), 15, GFLAGS,
 599                         &rk3288_uart3_fracmux),
 600         COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
 601                         RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
 602                         RK3288_CLKGATE_CON(2), 12, GFLAGS),
 603         COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
 604                         RK3288_CLKSEL_CON(7), 0,
 605                         RK3288_CLKGATE_CON(2), 13, GFLAGS,
 606                         &rk3288_uart4_fracmux),
 607
 608         COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
 609                         RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
 610                         RK3288_CLKGATE_CON(2), 5, GFLAGS),
 611         MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
 612                         RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
 613         GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
 614                         RK3288_CLKGATE_CON(5), 3, GFLAGS),
 615         GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
 616                         RK3288_CLKGATE_CON(5), 2, GFLAGS),
 617         GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
 618                         RK3288_CLKGATE_CON(5), 0, GFLAGS),
 619         GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
 620                         RK3288_CLKGATE_CON(5), 1, GFLAGS),
 621
 622         COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
 623                         RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
 624                         RK3288_CLKGATE_CON(2), 6, GFLAGS),
 625         MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
 626                         RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
 627         INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
 628                         RK3288_CLKSEL_CON(22), 7, IFLAGS),
 629
 630         GATE(0, "jtag", "ext_jtag", 0,
 631                         RK3288_CLKGATE_CON(4), 14, GFLAGS),
 632
 633         COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
 634                         RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
 635                         RK3288_CLKGATE_CON(5), 14, GFLAGS),
 636         COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
 637                         RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
 638                         RK3288_CLKGATE_CON(3), 6, GFLAGS),
 639         GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
 640                         RK3288_CLKGATE_CON(13), 9, GFLAGS),
 641         DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
 642                         RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
 643         MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
 644                         RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
 645
 646         /*
 647          * Clock-Architecture Diagram 4
 648          */
 649
 650         /* aclk_cpu gates */
 651         GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
 652         GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
 653         GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
 654         GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
 655         GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
 656         GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
 657         GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
 658         GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
 659
 660         /* hclk_cpu gates */
 661         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
 662         GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
 663         GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
 664         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
 665         GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
 666
 667         /* pclk_cpu gates */
 668         GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
 669         GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
 670         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
 671         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
 672         GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
 673         GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
 674         GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
 675         GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
 676         GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
 677         GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
 678         GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
 679         GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
 680         GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 681
 682         /* ddrctrl [DDR Controller PHY clock] gates */
 683         GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
 684         GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
 685
 686         /* ddrphy gates */
 687         GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
 688         GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
 689
 690         /* aclk_peri gates */
 691         GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
 692         GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
 693         GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS),
 694         GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
 695         GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
 696         GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
 697
 698         /* hclk_peri gates */
 699         GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
 700         GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
 701         GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
 702         GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
 703         GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
 704         GATE(HCLK_USB_PERI, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
 705         GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
 706         GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
 707         GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
 708         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
 709         GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
 710         GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
 711         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
 712         GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
 713         GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
 714         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
 715         GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
 716         GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
 717
 718         /* pclk_peri gates */
 719         GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
 720         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
 721         GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
 722         GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
 723         GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
 724         GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
 725         GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
 726         GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
 727         GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
 728         GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
 729         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
 730         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
 731         GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
 732         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
 733         GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
 734         GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
 735         GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
 736
 737         GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
 738         GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
 739         GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
 740         GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
 741         GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
 742
 743         /* sclk_gpu gates */
 744         GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
 745
 746         /* pclk_pd_alive gates */
 747         GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
 748         GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
 749         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
 750         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
 751         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
 752         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
 753         GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
 754         GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
 755         GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
 756         GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS),
 757
 758         /* pclk_pd_pmu gates */
 759         GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
 760         GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
 761         GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS),
 762         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
 763         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
 764
 765         /* hclk_vio gates */
 766         GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
 767         GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
 768         GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
 769         GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
 770         GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS),
 771         GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
 772         GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
 773         GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
 774         GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
 775         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
 776         GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
 777         GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
 778         GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
 779         GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
 780         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
 781         GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
 782
 783         /* aclk_vio0 gates */
 784         GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
 785         GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
 786         GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS),
 787         GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
 788
 789         /* aclk_vio1 gates */
 790         GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
 791         GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
 792         GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS),
 793
 794         /* aclk_rga_pre gates */
 795         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
 796         GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS),
 797
 798         /*
 799          * Other ungrouped clocks.
 800          */
 801
 802         GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
 803         INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
 804         GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
 805         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
 806 };
 807
 808 static const char *const rk3288_critical_clocks[] __initconst = {
 809         "aclk_cpu",
 810         "aclk_peri",
 811         "aclk_vio1_niu",
 812         "hclk_peri",
 813         "pclk_pd_pmu",
 814         "pmu_hclk_otg0",
 815 };
 816
 817 static void __iomem *rk3288_cru_base;
 818
 819 /*
 820  * Some CRU registers will be reset in maskrom when the system
 821  * wakes up from fastboot.
 822  * So save them before suspend, restore them after resume.
 823  */
 824 static const int rk3288_saved_cru_reg_ids[] = {
 825         RK3288_MODE_CON,
 826         RK3288_CLKSEL_CON(0),
 827         RK3288_CLKSEL_CON(1),
 828         RK3288_CLKSEL_CON(10),
 829         RK3288_CLKSEL_CON(33),
 830         RK3288_CLKSEL_CON(37),
 831 };
 832
 833 static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
 834
 835 static int rk3288_clk_suspend(void)
 836 {
 837         int i, reg_id;
 838
 839         for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
 840                 reg_id = rk3288_saved_cru_reg_ids[i];
 841
 842                 rk3288_saved_cru_regs[i] =
 843                                 readl_relaxed(rk3288_cru_base + reg_id);
 844         }
 845
 846         /*
 847          * Switch PLLs other than DPLL (for SDRAM) to slow mode to
 848          * avoid crashes on resume. The Mask ROM on the system will
 849          * put APLL, CPLL, and GPLL into slow mode at resume time
 850          * anyway (which is why we restore them), but we might not
 851          * even make it to the Mask ROM if this isn't done at suspend
 852          * time.
 853          *
 854          * NOTE: only APLL truly matters here, but we'll do them all.
 855          */
 856
 857         writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
 858
 859         return 0;
 860 }
 861
 862 static void rk3288_clk_resume(void)
 863 {
 864         int i, reg_id;
 865
 866         for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
 867                 reg_id = rk3288_saved_cru_reg_ids[i];
 868
 869                 writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
 870                                rk3288_cru_base + reg_id);
 871         }
 872 }
 873
 874 static void rk3288_clk_shutdown(void)
 875 {
 876         writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
 877 }
 878
 879 static struct syscore_ops rk3288_clk_syscore_ops = {
 880         .suspend = rk3288_clk_suspend,
 881         .resume = rk3288_clk_resume,
 882 };
 883
 884 static void __init rk3288_clk_init(struct device_node *np)
 885 {
 886         struct rockchip_clk_provider *ctx;
 887         struct clk *clk;
 888
 889         rk3288_cru_base = of_iomap(np, 0);
 890         if (!rk3288_cru_base) {
 891                 pr_err("%s: could not map cru region\n", __func__);
 892                 return;
 893         }
 894
 895         ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
 896         if (IS_ERR(ctx)) {
 897                 pr_err("%s: rockchip clk init failed\n", __func__);
 898                 iounmap(rk3288_cru_base);
 899                 return;
 900         }
 901
 902         /* xin12m is created by an cru-internal divider */
 903         clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
 904         if (IS_ERR(clk))
 905                 pr_warn("%s: could not register clock xin12m: %ld\n",
 906                         __func__, PTR_ERR(clk));
 907
 908
 909         clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
 910         if (IS_ERR(clk))
 911                 pr_warn("%s: could not register clock usb480m: %ld\n",
 912                         __func__, PTR_ERR(clk));
 913
 914         clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
 915                                         "hclk_vcodec_pre_v", 0, 1, 4);
 916         if (IS_ERR(clk))
 917                 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 918                         __func__, PTR_ERR(clk));
 919
 920         /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
 921         clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
 922         if (IS_ERR(clk))
 923                 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
 924                         __func__, PTR_ERR(clk));
 925         else
 926                 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
 927
 928         rockchip_clk_register_plls(ctx, rk3288_pll_clks,
 929                                    ARRAY_SIZE(rk3288_pll_clks),
 930                                    RK3288_GRF_SOC_STATUS1);
 931         rockchip_clk_register_branches(ctx, rk3288_clk_branches,
 932                                   ARRAY_SIZE(rk3288_clk_branches));
 933         rockchip_clk_protect_critical(rk3288_critical_clocks,
 934                                       ARRAY_SIZE(rk3288_critical_clocks));
 935
 936         rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
 937                         mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
 938                         &rk3288_cpuclk_data, rk3288_cpuclk_rates,
 939                         ARRAY_SIZE(rk3288_cpuclk_rates));
 940
 941         rockchip_register_softrst(np, 12,
 942                                   rk3288_cru_base + RK3288_SOFTRST_CON(0),
 943                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 944
 945         rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,
 946                                            rk3288_clk_shutdown);
 947         register_syscore_ops(&rk3288_clk_syscore_ops);
 948
 949         rockchip_clk_of_add_provider(np, ctx);
 950 }
 951 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);