drivers/clk/rockchip/clk-pll.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <asm/div64.h>
  20 #include <linux/slab.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/regmap.h>
  25 #include <linux/clk.h>
  26 #include "clk.h"
  27
  28 #define PLL_MODE_MASK           0x3
  29 #define PLL_MODE_SLOW           0x0
  30 #define PLL_MODE_NORM           0x1
  31 #define PLL_MODE_DEEP           0x2
  32
  33 struct rockchip_clk_pll {
  34         struct clk_hw           hw;
  35
  36         struct clk_mux          pll_mux;
  37         const struct clk_ops    *pll_mux_ops;
  38
  39         struct notifier_block   clk_nb;
  40
  41         void __iomem            *reg_base;
  42         int                     lock_offset;
  43         unsigned int            lock_shift;
  44         enum rockchip_pll_type  type;
  45         u8                      flags;
  46         const struct rockchip_pll_rate_table *rate_table;
  47         unsigned int            rate_count;
  48         spinlock_t              *lock;
  49
  50         struct rockchip_clk_provider *ctx;
  51 };
  52
  53 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
  54 #define to_rockchip_clk_pll_nb(nb) \
  55                         container_of(nb, struct rockchip_clk_pll, clk_nb)
  56
  57 static void rockchip_rk3366_pll_get_params(struct rockchip_clk_pll *pll,
  58                                         struct rockchip_pll_rate_table *rate);
  59 static int rockchip_rk3366_pll_set_params(struct rockchip_clk_pll *pll,
  60                                 const struct rockchip_pll_rate_table *rate);
  61
  62 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
  63                             struct rockchip_clk_pll *pll, unsigned long rate)
  64 {
  65         const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
  66         int i;
  67
  68         for (i = 0; i < pll->rate_count; i++) {
  69                 if (rate == rate_table[i].rate)
  70                         return &rate_table[i];
  71         }
  72
  73         return NULL;
  74 }
  75
  76 static long rockchip_pll_round_rate(struct clk_hw *hw,
  77                             unsigned long drate, unsigned long *prate)
  78 {
  79         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
  80         const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
  81         int i;
  82
  83         /* Assumming rate_table is in descending order */
  84         for (i = 0; i < pll->rate_count; i++) {
  85                 if (drate >= rate_table[i].rate)
  86                         return rate_table[i].rate;
  87         }
  88
  89         /* return minimum supported value */
  90         return rate_table[i - 1].rate;
  91 }
  92
  93 /*
  94  * Wait for the pll to reach the locked state.
  95  * The calling set_rate function is responsible for making sure the
  96  * grf regmap is available.
  97  */
  98 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
  99 {
 100         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 101         unsigned int val;
 102         int delay = 24000000, ret;
 103
 104         while (delay > 0) {
 105                 ret = regmap_read(grf, pll->lock_offset, &val);
 106                 if (ret) {
 107                         pr_err("%s: failed to read pll lock status: %d\n",
 108                                __func__, ret);
 109                         return ret;
 110                 }
 111
 112                 if (val & BIT(pll->lock_shift))
 113                         return 0;
 114                 delay--;
 115         }
 116
 117         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 118         return -ETIMEDOUT;
 119 }
 120
 121 /**
 122  * PLL used in RK3036
 123  */
 124
 125 #define RK3036_PLLCON(i)                        (i * 0x4)
 126 #define RK3036_PLLCON0_FBDIV_MASK               0xfff
 127 #define RK3036_PLLCON0_FBDIV_SHIFT              0
 128 #define RK3036_PLLCON0_POSTDIV1_MASK            0x7
 129 #define RK3036_PLLCON0_POSTDIV1_SHIFT           12
 130 #define RK3036_PLLCON1_REFDIV_MASK              0x3f
 131 #define RK3036_PLLCON1_REFDIV_SHIFT             0
 132 #define RK3036_PLLCON1_POSTDIV2_MASK            0x7
 133 #define RK3036_PLLCON1_POSTDIV2_SHIFT           6
 134 #define RK3036_PLLCON1_DSMPD_MASK               0x1
 135 #define RK3036_PLLCON1_DSMPD_SHIFT              12
 136 #define RK3036_PLLCON2_FRAC_MASK                0xffffff
 137 #define RK3036_PLLCON2_FRAC_SHIFT               0
 138
 139 #define RK3036_PLLCON1_PWRDOWN                  (1 << 13)
 140
 141 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
 142                                         struct rockchip_pll_rate_table *rate)
 143 {
 144         u32 pllcon;
 145
 146         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
 147         rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
 148                                 & RK3036_PLLCON0_FBDIV_MASK);
 149         rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
 150                                 & RK3036_PLLCON0_POSTDIV1_MASK);
 151
 152         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
 153         rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
 154                                 & RK3036_PLLCON1_REFDIV_MASK);
 155         rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
 156                                 & RK3036_PLLCON1_POSTDIV2_MASK);
 157         rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
 158                                 & RK3036_PLLCON1_DSMPD_MASK);
 159
 160         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 161         rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
 162                                 & RK3036_PLLCON2_FRAC_MASK);
 163 }
 164
 165 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
 166                                                      unsigned long prate)
 167 {
 168         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 169         struct rockchip_pll_rate_table cur;
 170         u64 rate64 = prate;
 171
 172         if (pll->type == pll_rk3366)
 173                 rockchip_rk3366_pll_get_params(pll, &cur);
 174         else
 175                 rockchip_rk3036_pll_get_params(pll, &cur);
 176
 177         rate64 *= cur.fbdiv;
 178         do_div(rate64, cur.refdiv);
 179
 180         if (cur.dsmpd == 0) {
 181                 /* fractional mode */
 182                 u64 frac_rate64 = prate * cur.frac;
 183
 184                 do_div(frac_rate64, cur.refdiv);
 185                 rate64 += frac_rate64 >> 24;
 186         }
 187
 188         do_div(rate64, cur.postdiv1);
 189         do_div(rate64, cur.postdiv2);
 190
 191         return (unsigned long)rate64;
 192 }
 193
 194 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
 195                                 const struct rockchip_pll_rate_table *rate)
 196 {
 197         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 198         struct clk_mux *pll_mux = &pll->pll_mux;
 199         struct rockchip_pll_rate_table cur;
 200         u32 pllcon;
 201         int rate_change_remuxed = 0;
 202         int cur_parent;
 203         int ret;
 204
 205         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 206                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 207                 rate->postdiv2, rate->dsmpd, rate->frac);
 208
 209         rockchip_rk3036_pll_get_params(pll, &cur);
 210         cur.rate = 0;
 211
 212         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 213         if (cur_parent == PLL_MODE_NORM) {
 214                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 215                 rate_change_remuxed = 1;
 216         }
 217
 218         /* update pll values */
 219         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
 220                                           RK3036_PLLCON0_FBDIV_SHIFT) |
 221                        HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
 222                                              RK3036_PLLCON0_POSTDIV1_SHIFT),
 223                        pll->reg_base + RK3036_PLLCON(0));
 224
 225         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
 226                                                    RK3036_PLLCON1_REFDIV_SHIFT) |
 227                        HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
 228                                                      RK3036_PLLCON1_POSTDIV2_SHIFT) |
 229                        HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
 230                                                   RK3036_PLLCON1_DSMPD_SHIFT),
 231                        pll->reg_base + RK3036_PLLCON(1));
 232
 233         /* GPLL CON2 is not HIWORD_MASK */
 234         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 235         pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
 236         pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
 237         writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
 238
 239         /* wait for the pll to lock */
 240         ret = rockchip_pll_wait_lock(pll);
 241         if (ret) {
 242                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 243                         __func__);
 244                 rockchip_rk3036_pll_set_params(pll, &cur);
 245         }
 246
 247         if (rate_change_remuxed)
 248                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 249
 250         return ret;
 251 }
 252
 253 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 254                                         unsigned long prate)
 255 {
 256         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 257         const struct rockchip_pll_rate_table *rate;
 258         unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
 259         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 260
 261         if (IS_ERR(grf)) {
 262                 pr_debug("%s: grf regmap not available, aborting rate change\n",
 263                          __func__);
 264                 return PTR_ERR(grf);
 265         }
 266
 267         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 268                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
 269
 270         /* Get required rate settings from table */
 271         rate = rockchip_get_pll_settings(pll, drate);
 272         if (!rate) {
 273                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 274                         drate, __clk_get_name(hw->clk));
 275                 return -EINVAL;
 276         }
 277
 278         if (pll->type == pll_rk3366)
 279                 return rockchip_rk3366_pll_set_params(pll, rate);
 280
 281         return rockchip_rk3036_pll_set_params(pll, rate);
 282 }
 283
 284 static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
 285 {
 286         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 287
 288         writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
 289                pll->reg_base + RK3036_PLLCON(1));
 290
 291         return 0;
 292 }
 293
 294 static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
 295 {
 296         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 297
 298         writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
 299                              RK3036_PLLCON1_PWRDOWN, 0),
 300                pll->reg_base + RK3036_PLLCON(1));
 301 }
 302
 303 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
 304 {
 305         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 306         u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
 307
 308         return !(pllcon & RK3036_PLLCON1_PWRDOWN);
 309 }
 310
 311 static void rockchip_rk3036_pll_init(struct clk_hw *hw)
 312 {
 313         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 314         const struct rockchip_pll_rate_table *rate;
 315         struct rockchip_pll_rate_table cur;
 316         unsigned long drate;
 317
 318         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 319                 return;
 320
 321         drate = clk_hw_get_rate(hw);
 322         rate = rockchip_get_pll_settings(pll, drate);
 323
 324         /* when no rate setting for the current rate, rely on clk_set_rate */
 325         if (!rate)
 326                 return;
 327
 328         if (pll->type == pll_rk3366)
 329                 rockchip_rk3366_pll_get_params(pll, &cur);
 330         else
 331                 rockchip_rk3036_pll_get_params(pll, &cur);
 332
 333         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
 334                  drate);
 335         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 336                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
 337                  cur.dsmpd, cur.frac);
 338         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 339                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
 340                  rate->dsmpd, rate->frac);
 341
 342         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
 343                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
 344                 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
 345                 struct clk *parent = clk_get_parent(hw->clk);
 346
 347                 if (!parent) {
 348                         pr_warn("%s: parent of %s not available\n",
 349                                 __func__, __clk_get_name(hw->clk));
 350                         return;
 351                 }
 352
 353                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 354                          __func__, __clk_get_name(hw->clk));
 355                 if (pll->type == pll_rk3366)
 356                         rockchip_rk3366_pll_set_params(pll, rate);
 357                 else
 358                         rockchip_rk3036_pll_set_params(pll, rate);
 359         }
 360 }
 361
 362 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
 363         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 364         .enable = rockchip_rk3036_pll_enable,
 365         .disable = rockchip_rk3036_pll_disable,
 366         .is_enabled = rockchip_rk3036_pll_is_enabled,
 367 };
 368
 369 static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
 370         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 371         .round_rate = rockchip_pll_round_rate,
 372         .set_rate = rockchip_rk3036_pll_set_rate,
 373         .enable = rockchip_rk3036_pll_enable,
 374         .disable = rockchip_rk3036_pll_disable,
 375         .is_enabled = rockchip_rk3036_pll_is_enabled,
 376         .init = rockchip_rk3036_pll_init,
 377 };
 378
 379 /**
 380  * PLL used in RK3066, RK3188 and RK3288
 381  */
 382
 383 #define RK3066_PLL_RESET_DELAY(nr)      ((nr * 500) / 24 + 1)
 384
 385 #define RK3066_PLLCON(i)                (i * 0x4)
 386 #define RK3066_PLLCON0_OD_MASK          0xf
 387 #define RK3066_PLLCON0_OD_SHIFT         0
 388 #define RK3066_PLLCON0_NR_MASK          0x3f
 389 #define RK3066_PLLCON0_NR_SHIFT         8
 390 #define RK3066_PLLCON1_NF_MASK          0x1fff
 391 #define RK3066_PLLCON1_NF_SHIFT         0
 392 #define RK3066_PLLCON2_NB_MASK          0xfff
 393 #define RK3066_PLLCON2_NB_SHIFT         0
 394 #define RK3066_PLLCON3_RESET            (1 << 5)
 395 #define RK3066_PLLCON3_PWRDOWN          (1 << 1)
 396 #define RK3066_PLLCON3_BYPASS           (1 << 0)
 397
 398 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
 399                                         struct rockchip_pll_rate_table *rate)
 400 {
 401         u32 pllcon;
 402
 403         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
 404         rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
 405                                 & RK3066_PLLCON0_NR_MASK) + 1;
 406         rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
 407                                 & RK3066_PLLCON0_OD_MASK) + 1;
 408
 409         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
 410         rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
 411                                 & RK3066_PLLCON1_NF_MASK) + 1;
 412
 413         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
 414         rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
 415                                 & RK3066_PLLCON2_NB_MASK) + 1;
 416 }
 417
 418 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
 419                                                      unsigned long prate)
 420 {
 421         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 422         struct rockchip_pll_rate_table cur;
 423         u64 rate64 = prate;
 424         u32 pllcon;
 425
 426         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
 427         if (pllcon & RK3066_PLLCON3_BYPASS) {
 428                 pr_debug("%s: pll %s is bypassed\n", __func__,
 429                         clk_hw_get_name(hw));
 430                 return prate;
 431         }
 432
 433         rockchip_rk3066_pll_get_params(pll, &cur);
 434
 435         rate64 *= cur.nf;
 436         do_div(rate64, cur.nr);
 437         do_div(rate64, cur.no);
 438
 439         return (unsigned long)rate64;
 440 }
 441
 442 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
 443                                 const struct rockchip_pll_rate_table *rate)
 444 {
 445         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 446         struct clk_mux *pll_mux = &pll->pll_mux;
 447         struct rockchip_pll_rate_table cur;
 448         int rate_change_remuxed = 0;
 449         int cur_parent;
 450         int ret;
 451
 452         pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
 453                  __func__, rate->rate, rate->nr, rate->no, rate->nf);
 454
 455         rockchip_rk3066_pll_get_params(pll, &cur);
 456         cur.rate = 0;
 457
 458         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 459         if (cur_parent == PLL_MODE_NORM) {
 460                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 461                 rate_change_remuxed = 1;
 462         }
 463
 464         /* enter reset mode */
 465         writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
 466                pll->reg_base + RK3066_PLLCON(3));
 467
 468         /* update pll values */
 469         writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
 470                                            RK3066_PLLCON0_NR_SHIFT) |
 471                HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
 472                                            RK3066_PLLCON0_OD_SHIFT),
 473                pll->reg_base + RK3066_PLLCON(0));
 474
 475         writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
 476                                                    RK3066_PLLCON1_NF_SHIFT),
 477                        pll->reg_base + RK3066_PLLCON(1));
 478         writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
 479                                                    RK3066_PLLCON2_NB_SHIFT),
 480                        pll->reg_base + RK3066_PLLCON(2));
 481
 482         /* leave reset and wait the reset_delay */
 483         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
 484                pll->reg_base + RK3066_PLLCON(3));
 485         udelay(RK3066_PLL_RESET_DELAY(rate->nr));
 486
 487         /* wait for the pll to lock */
 488         ret = rockchip_pll_wait_lock(pll);
 489         if (ret) {
 490                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 491                         __func__);
 492                 rockchip_rk3066_pll_set_params(pll, &cur);
 493         }
 494
 495         if (rate_change_remuxed)
 496                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 497
 498         return ret;
 499 }
 500
 501 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 502                                         unsigned long prate)
 503 {
 504         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 505         const struct rockchip_pll_rate_table *rate;
 506         unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
 507         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 508
 509         if (IS_ERR(grf)) {
 510                 pr_debug("%s: grf regmap not available, aborting rate change\n",
 511                          __func__);
 512                 return PTR_ERR(grf);
 513         }
 514
 515         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 516                  __func__, clk_hw_get_name(hw), old_rate, drate, prate);
 517
 518         /* Get required rate settings from table */
 519         rate = rockchip_get_pll_settings(pll, drate);
 520         if (!rate) {
 521                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 522                         drate, clk_hw_get_name(hw));
 523                 return -EINVAL;
 524         }
 525
 526         return rockchip_rk3066_pll_set_params(pll, rate);
 527 }
 528
 529 static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 530 {
 531         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 532
 533         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 534                pll->reg_base + RK3066_PLLCON(3));
 535
 536         return 0;
 537 }
 538
 539 static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
 540 {
 541         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 542
 543         writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
 544                              RK3066_PLLCON3_PWRDOWN, 0),
 545                pll->reg_base + RK3066_PLLCON(3));
 546 }
 547
 548 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
 549 {
 550         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 551         u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
 552
 553         return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 554 }
 555
 556 static void rockchip_rk3066_pll_init(struct clk_hw *hw)
 557 {
 558         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 559         const struct rockchip_pll_rate_table *rate;
 560         struct rockchip_pll_rate_table cur;
 561         unsigned long drate;
 562
 563         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 564                 return;
 565
 566         drate = clk_hw_get_rate(hw);
 567         rate = rockchip_get_pll_settings(pll, drate);
 568
 569         /* when no rate setting for the current rate, rely on clk_set_rate */
 570         if (!rate)
 571                 return;
 572
 573         rockchip_rk3066_pll_get_params(pll, &cur);
 574
 575         pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
 576                  __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
 577                  rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
 578         if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
 579                                                      || rate->nb != cur.nb) {
 580                 struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 581
 582                 if (IS_ERR(grf))
 583                         return;
 584
 585                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 586                          __func__, clk_hw_get_name(hw));
 587                 rockchip_rk3066_pll_set_params(pll, rate);
 588         }
 589 }
 590
 591 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
 592         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 593         .enable = rockchip_rk3066_pll_enable,
 594         .disable = rockchip_rk3066_pll_disable,
 595         .is_enabled = rockchip_rk3066_pll_is_enabled,
 596 };
 597
 598 static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
 599         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 600         .round_rate = rockchip_pll_round_rate,
 601         .set_rate = rockchip_rk3066_pll_set_rate,
 602         .enable = rockchip_rk3066_pll_enable,
 603         .disable = rockchip_rk3066_pll_disable,
 604         .is_enabled = rockchip_rk3066_pll_is_enabled,
 605         .init = rockchip_rk3066_pll_init,
 606 };
 607
 608 /**
 609  * PLL used in RK3366
 610  */
 611
 612 #define RK3366_PLLCON(i)                        (i * 0x4)
 613 #define RK3366_PLLCON0_FBDIV_MASK               0xfff
 614 #define RK3366_PLLCON0_FBDIV_SHIFT              0
 615 #define RK3366_PLLCON0_POSTDIV1_MASK            0x7
 616 #define RK3366_PLLCON0_POSTDIV1_SHIFT           12
 617 #define RK3366_PLLCON1_REFDIV_MASK              0x3f
 618 #define RK3366_PLLCON1_REFDIV_SHIFT             0
 619 #define RK3366_PLLCON1_POSTDIV2_MASK            0x7
 620 #define RK3366_PLLCON1_POSTDIV2_SHIFT           6
 621 #define RK3366_PLLCON2_FRAC_MASK                0xffffff
 622 #define RK3366_PLLCON2_FRAC_SHIFT               0
 623 #define RK3366_PLLCON3_DSMPD_MASK               0x1
 624 #define RK3366_PLLCON3_DSMPD_SHIFT              2
 625
 626 #define RK3366_PLLCON3_PWRDOWN                  (1 << 0)
 627
 628 static void rockchip_rk3366_pll_get_params(struct rockchip_clk_pll *pll,
 629                                         struct rockchip_pll_rate_table *rate)
 630 {
 631         u32 pllcon;
 632
 633         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(0));
 634         rate->fbdiv = ((pllcon >> RK3366_PLLCON0_FBDIV_SHIFT)
 635                                 & RK3366_PLLCON0_FBDIV_MASK);
 636         rate->postdiv1 = ((pllcon >> RK3366_PLLCON0_POSTDIV1_SHIFT)
 637                                 & RK3366_PLLCON0_POSTDIV1_MASK);
 638
 639         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(1));
 640         rate->refdiv = ((pllcon >> RK3366_PLLCON1_REFDIV_SHIFT)
 641                                 & RK3366_PLLCON1_REFDIV_MASK);
 642         rate->postdiv2 = ((pllcon >> RK3366_PLLCON1_POSTDIV2_SHIFT)
 643                                 & RK3366_PLLCON1_POSTDIV2_MASK);
 644
 645         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(2));
 646         rate->frac = ((pllcon >> RK3366_PLLCON2_FRAC_SHIFT)
 647                                 & RK3366_PLLCON2_FRAC_MASK);
 648
 649         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(3));
 650         rate->dsmpd = ((pllcon >> RK3366_PLLCON3_DSMPD_SHIFT)
 651                                 & RK3366_PLLCON3_DSMPD_MASK);
 652 }
 653
 654 static int rockchip_rk3366_pll_set_params(struct rockchip_clk_pll *pll,
 655                                 const struct rockchip_pll_rate_table *rate)
 656 {
 657         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 658         struct clk_mux *pll_mux = &pll->pll_mux;
 659         struct rockchip_pll_rate_table cur;
 660         u32 pllcon;
 661         int rate_change_remuxed = 0;
 662         int cur_parent;
 663         int ret;
 664
 665         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 666                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 667                 rate->postdiv2, rate->dsmpd, rate->frac);
 668
 669         rockchip_rk3366_pll_get_params(pll, &cur);
 670         cur.rate = 0;
 671
 672         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 673         if (cur_parent == PLL_MODE_NORM) {
 674                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 675                 rate_change_remuxed = 1;
 676         }
 677
 678         /* update pll values */
 679         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3366_PLLCON0_FBDIV_MASK,
 680                                           RK3366_PLLCON0_FBDIV_SHIFT) |
 681                        HIWORD_UPDATE(rate->postdiv1, RK3366_PLLCON0_POSTDIV1_MASK,
 682                                              RK3366_PLLCON0_POSTDIV1_SHIFT),
 683                        pll->reg_base + RK3366_PLLCON(0));
 684
 685         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3366_PLLCON1_REFDIV_MASK,
 686                                                    RK3366_PLLCON1_REFDIV_SHIFT) |
 687                        HIWORD_UPDATE(rate->postdiv2, RK3366_PLLCON1_POSTDIV2_MASK,
 688                                                      RK3366_PLLCON1_POSTDIV2_SHIFT),
 689                        pll->reg_base + RK3366_PLLCON(1));
 690
 691         /* GPLL CON2 is not HIWORD_MASK */
 692         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(2));
 693         pllcon &= ~(RK3366_PLLCON2_FRAC_MASK << RK3366_PLLCON2_FRAC_SHIFT);
 694         pllcon |= rate->frac << RK3366_PLLCON2_FRAC_SHIFT;
 695         writel_relaxed(pllcon, pll->reg_base + RK3366_PLLCON(2));
 696
 697         writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3366_PLLCON3_DSMPD_MASK,
 698                                                   RK3366_PLLCON3_DSMPD_SHIFT),
 699                        pll->reg_base + RK3366_PLLCON(3));
 700
 701         /* wait for the pll to lock */
 702         ret = rockchip_pll_wait_lock(pll);
 703         if (ret) {
 704                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 705                         __func__);
 706                 rockchip_rk3366_pll_set_params(pll, &cur);
 707         }
 708
 709         if (rate_change_remuxed)
 710                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 711
 712         return ret;
 713 }
 714
 715 static int rockchip_rk3366_pll_enable(struct clk_hw *hw)
 716 {
 717         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 718
 719         writel(HIWORD_UPDATE(0, RK3366_PLLCON3_PWRDOWN, 0),
 720                pll->reg_base + RK3366_PLLCON(3));
 721
 722         return 0;
 723 }
 724
 725 static void rockchip_rk3366_pll_disable(struct clk_hw *hw)
 726 {
 727         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 728
 729         writel(HIWORD_UPDATE(RK3366_PLLCON3_PWRDOWN,
 730                              RK3366_PLLCON3_PWRDOWN, 0),
 731                pll->reg_base + RK3366_PLLCON(3));
 732 }
 733
 734 static int rockchip_rk3366_pll_is_enabled(struct clk_hw *hw)
 735 {
 736         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 737         u32 pllcon = readl(pll->reg_base + RK3366_PLLCON(3));
 738
 739         return !(pllcon & RK3366_PLLCON3_PWRDOWN);
 740 }
 741
 742 static const struct clk_ops rockchip_rk3366_pll_clk_norate_ops = {
 743         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 744         .enable = rockchip_rk3366_pll_enable,
 745         .disable = rockchip_rk3366_pll_disable,
 746         .is_enabled = rockchip_rk3366_pll_is_enabled,
 747 };
 748
 749 static const struct clk_ops rockchip_rk3366_pll_clk_ops = {
 750         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 751         .round_rate = rockchip_pll_round_rate,
 752         .set_rate = rockchip_rk3036_pll_set_rate,
 753         .enable = rockchip_rk3366_pll_enable,
 754         .disable = rockchip_rk3366_pll_disable,
 755         .is_enabled = rockchip_rk3366_pll_is_enabled,
 756         .init = rockchip_rk3036_pll_init,
 757 };
 758
 759 /**
 760  * PLL used in RK3399
 761  */
 762
 763 #define RK3399_PLLCON(i)                        (i * 0x4)
 764 #define RK3399_PLLCON0_FBDIV_MASK               0xfff
 765 #define RK3399_PLLCON0_FBDIV_SHIFT              0
 766 #define RK3399_PLLCON1_REFDIV_MASK              0x3f
 767 #define RK3399_PLLCON1_REFDIV_SHIFT             0
 768 #define RK3399_PLLCON1_POSTDIV1_MASK            0x7
 769 #define RK3399_PLLCON1_POSTDIV1_SHIFT           8
 770 #define RK3399_PLLCON1_POSTDIV2_MASK            0x7
 771 #define RK3399_PLLCON1_POSTDIV2_SHIFT           12
 772 #define RK3399_PLLCON2_FRAC_MASK                0xffffff
 773 #define RK3399_PLLCON2_FRAC_SHIFT               0
 774 #define RK3399_PLLCON2_LOCK_STATUS              BIT(31)
 775 #define RK3399_PLLCON3_PWRDOWN                  BIT(0)
 776 #define RK3399_PLLCON3_DSMPD_MASK               0x1
 777 #define RK3399_PLLCON3_DSMPD_SHIFT              3
 778
 779 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
 780 {
 781         u32 pllcon;
 782         int delay = 24000000;
 783
 784         /* poll check the lock status in rk3399 xPLLCON2 */
 785         while (delay > 0) {
 786                 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 787                 if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
 788                         return 0;
 789
 790                 delay--;
 791         }
 792
 793         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 794         return -ETIMEDOUT;
 795 }
 796
 797 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
 798                                         struct rockchip_pll_rate_table *rate)
 799 {
 800         u32 pllcon;
 801
 802         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
 803         rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
 804                                 & RK3399_PLLCON0_FBDIV_MASK);
 805
 806         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
 807         rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
 808                                 & RK3399_PLLCON1_REFDIV_MASK);
 809         rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
 810                                 & RK3399_PLLCON1_POSTDIV1_MASK);
 811         rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
 812                                 & RK3399_PLLCON1_POSTDIV2_MASK);
 813
 814         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 815         rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
 816                                 & RK3399_PLLCON2_FRAC_MASK);
 817
 818         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
 819         rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
 820                                 & RK3399_PLLCON3_DSMPD_MASK);
 821 }
 822
 823 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
 824                                                      unsigned long prate)
 825 {
 826         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 827         struct rockchip_pll_rate_table cur;
 828         u64 rate64 = prate;
 829
 830         rockchip_rk3399_pll_get_params(pll, &cur);
 831
 832         rate64 *= cur.fbdiv;
 833         do_div(rate64, cur.refdiv);
 834
 835         if (cur.dsmpd == 0) {
 836                 /* fractional mode */
 837                 u64 frac_rate64 = prate * cur.frac;
 838
 839                 do_div(frac_rate64, cur.refdiv);
 840                 rate64 += frac_rate64 >> 24;
 841         }
 842
 843         do_div(rate64, cur.postdiv1);
 844         do_div(rate64, cur.postdiv2);
 845
 846         return (unsigned long)rate64;
 847 }
 848
 849 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
 850                                 const struct rockchip_pll_rate_table *rate)
 851 {
 852         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 853         struct clk_mux *pll_mux = &pll->pll_mux;
 854         struct rockchip_pll_rate_table cur;
 855         u32 pllcon;
 856         int rate_change_remuxed = 0;
 857         int cur_parent;
 858         int ret;
 859
 860         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 861                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 862                 rate->postdiv2, rate->dsmpd, rate->frac);
 863
 864         rockchip_rk3399_pll_get_params(pll, &cur);
 865         cur.rate = 0;
 866
 867         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 868         if (cur_parent == PLL_MODE_NORM) {
 869                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 870                 rate_change_remuxed = 1;
 871         }
 872
 873         /* update pll values */
 874         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
 875                                                   RK3399_PLLCON0_FBDIV_SHIFT),
 876                        pll->reg_base + RK3399_PLLCON(0));
 877
 878         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
 879                                                    RK3399_PLLCON1_REFDIV_SHIFT) |
 880                        HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
 881                                                      RK3399_PLLCON1_POSTDIV1_SHIFT) |
 882                        HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
 883                                                      RK3399_PLLCON1_POSTDIV2_SHIFT),
 884                        pll->reg_base + RK3399_PLLCON(1));
 885
 886         /* xPLL CON2 is not HIWORD_MASK */
 887         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 888         pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT);
 889         pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
 890         writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
 891
 892         writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
 893                                             RK3399_PLLCON3_DSMPD_SHIFT),
 894                        pll->reg_base + RK3399_PLLCON(3));
 895
 896         /* wait for the pll to lock */
 897         ret = rockchip_rk3399_pll_wait_lock(pll);
 898         if (ret) {
 899                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 900                         __func__);
 901                 rockchip_rk3399_pll_set_params(pll, &cur);
 902         }
 903
 904         if (rate_change_remuxed)
 905                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 906
 907         return ret;
 908 }
 909
 910 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 911                                         unsigned long prate)
 912 {
 913         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 914         const struct rockchip_pll_rate_table *rate;
 915         unsigned long old_rate = rockchip_rk3399_pll_recalc_rate(hw, prate);
 916
 917         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 918                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
 919
 920         /* Get required rate settings from table */
 921         rate = rockchip_get_pll_settings(pll, drate);
 922         if (!rate) {
 923                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 924                         drate, __clk_get_name(hw->clk));
 925                 return -EINVAL;
 926         }
 927
 928         return rockchip_rk3399_pll_set_params(pll, rate);
 929 }
 930
 931 static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
 932 {
 933         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 934
 935         writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
 936                pll->reg_base + RK3399_PLLCON(3));
 937
 938         return 0;
 939 }
 940
 941 static void rockchip_rk3399_pll_disable(struct clk_hw *hw)
 942 {
 943         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 944
 945         writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
 946                              RK3399_PLLCON3_PWRDOWN, 0),
 947                pll->reg_base + RK3399_PLLCON(3));
 948 }
 949
 950 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw)
 951 {
 952         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 953         u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
 954
 955         return !(pllcon & RK3399_PLLCON3_PWRDOWN);
 956 }
 957
 958 static void rockchip_rk3399_pll_init(struct clk_hw *hw)
 959 {
 960         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 961         const struct rockchip_pll_rate_table *rate;
 962         struct rockchip_pll_rate_table cur;
 963         unsigned long drate;
 964
 965         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 966                 return;
 967
 968         drate = clk_hw_get_rate(hw);
 969         rate = rockchip_get_pll_settings(pll, drate);
 970
 971         /* when no rate setting for the current rate, rely on clk_set_rate */
 972         if (!rate)
 973                 return;
 974
 975         rockchip_rk3399_pll_get_params(pll, &cur);
 976
 977         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
 978                  drate);
 979         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 980                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
 981                  cur.dsmpd, cur.frac);
 982         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 983                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
 984                  rate->dsmpd, rate->frac);
 985
 986         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
 987                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
 988                 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
 989                 struct clk *parent = clk_get_parent(hw->clk);
 990
 991                 if (!parent) {
 992                         pr_warn("%s: parent of %s not available\n",
 993                                 __func__, __clk_get_name(hw->clk));
 994                         return;
 995                 }
 996
 997                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 998                          __func__, __clk_get_name(hw->clk));
 999                 rockchip_rk3399_pll_set_params(pll, rate);
1000         }
1001 }
1002
1003 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = {
1004         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
1005         .enable = rockchip_rk3399_pll_enable,
1006         .disable = rockchip_rk3399_pll_disable,
1007         .is_enabled = rockchip_rk3399_pll_is_enabled,
1008 };
1009
1010 static const struct clk_ops rockchip_rk3399_pll_clk_ops = {
1011         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
1012         .round_rate = rockchip_pll_round_rate,
1013         .set_rate = rockchip_rk3399_pll_set_rate,
1014         .enable = rockchip_rk3399_pll_enable,
1015         .disable = rockchip_rk3399_pll_disable,
1016         .is_enabled = rockchip_rk3399_pll_is_enabled,
1017         .init = rockchip_rk3399_pll_init,
1018 };
1019
1020 /*
1021  * Common registering of pll clocks
1022  */
1023
1024 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
1025                 enum rockchip_pll_type pll_type,
1026                 const char *name, const char *const *parent_names,
1027                 u8 num_parents, int con_offset, int grf_lock_offset,
1028                 int lock_shift, int mode_offset, int mode_shift,
1029                 struct rockchip_pll_rate_table *rate_table,
1030                 u8 clk_pll_flags)
1031 {
1032         const char *pll_parents[3];
1033         struct clk_init_data init;
1034         struct rockchip_clk_pll *pll;
1035         struct clk_mux *pll_mux;
1036         struct clk *pll_clk, *mux_clk;
1037         char pll_name[20];
1038
1039         if (num_parents != 2) {
1040                 pr_err("%s: needs two parent clocks\n", __func__);
1041                 return ERR_PTR(-EINVAL);
1042         }
1043
1044         /* name the actual pll */
1045         snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
1046
1047         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1048         if (!pll)
1049                 return ERR_PTR(-ENOMEM);
1050
1051         /* create the mux on top of the real pll */
1052         pll->pll_mux_ops = &clk_mux_ops;
1053         pll_mux = &pll->pll_mux;
1054         pll_mux->reg = ctx->reg_base + mode_offset;
1055         pll_mux->shift = mode_shift;
1056         pll_mux->mask = PLL_MODE_MASK;
1057         pll_mux->flags = 0;
1058         pll_mux->lock = &ctx->lock;
1059         pll_mux->hw.init = &init;
1060
1061         if (pll_type == pll_rk3036 ||
1062             pll_type == pll_rk3066 ||
1063             pll_type == pll_rk3366 ||
1064             pll_type == pll_rk3399)
1065                 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
1066
1067         /* the actual muxing is xin24m, pll-output, xin32k */
1068         pll_parents[0] = parent_names[0];
1069         pll_parents[1] = pll_name;
1070         pll_parents[2] = parent_names[1];
1071
1072         init.name = name;
1073         init.flags = CLK_SET_RATE_PARENT;
1074         init.ops = pll->pll_mux_ops;
1075         init.parent_names = pll_parents;
1076         init.num_parents = ARRAY_SIZE(pll_parents);
1077
1078         mux_clk = clk_register(NULL, &pll_mux->hw);
1079         if (IS_ERR(mux_clk))
1080                 goto err_mux;
1081
1082         /* now create the actual pll */
1083         init.name = pll_name;
1084
1085         /* keep all plls untouched for now */
1086         init.flags = CLK_IGNORE_UNUSED;
1087
1088         init.parent_names = &parent_names[0];
1089         init.num_parents = 1;
1090
1091         if (rate_table) {
1092                 int len;
1093
1094                 /* find count of rates in rate_table */
1095                 for (len = 0; rate_table[len].rate != 0; )
1096                         len++;
1097
1098                 pll->rate_count = len;
1099                 pll->rate_table = kmemdup(rate_table,
1100                                         pll->rate_count *
1101                                         sizeof(struct rockchip_pll_rate_table),
1102                                         GFP_KERNEL);
1103                 WARN(!pll->rate_table,
1104                         "%s: could not allocate rate table for %s\n",
1105                         __func__, name);
1106         }
1107
1108         switch (pll_type) {
1109         case pll_rk3036:
1110                 if (!pll->rate_table)
1111                         init.ops = &rockchip_rk3036_pll_clk_norate_ops;
1112                 else
1113                         init.ops = &rockchip_rk3036_pll_clk_ops;
1114                 break;
1115         case pll_rk3066:
1116                 if (!pll->rate_table)
1117                         init.ops = &rockchip_rk3066_pll_clk_norate_ops;
1118                 else
1119                         init.ops = &rockchip_rk3066_pll_clk_ops;
1120                 break;
1121         case pll_rk3366:
1122                 if (!pll->rate_table)
1123                         init.ops = &rockchip_rk3366_pll_clk_norate_ops;
1124                 else
1125                         init.ops = &rockchip_rk3366_pll_clk_ops;
1126                 break;
1127         case pll_rk3399:
1128                 if (!pll->rate_table)
1129                         init.ops = &rockchip_rk3399_pll_clk_norate_ops;
1130                 else
1131                         init.ops = &rockchip_rk3399_pll_clk_ops;
1132                 break;
1133         default:
1134                 pr_warn("%s: Unknown pll type for pll clk %s\n",
1135                         __func__, name);
1136         }
1137
1138         pll->hw.init = &init;
1139         pll->type = pll_type;
1140         pll->reg_base = ctx->reg_base + con_offset;
1141         pll->lock_offset = grf_lock_offset;
1142         pll->lock_shift = lock_shift;
1143         pll->flags = clk_pll_flags;
1144         pll->lock = &ctx->lock;
1145         pll->ctx = ctx;
1146
1147         pll_clk = clk_register(NULL, &pll->hw);
1148         if (IS_ERR(pll_clk)) {
1149                 pr_err("%s: failed to register pll clock %s : %ld\n",
1150                         __func__, name, PTR_ERR(pll_clk));
1151                 goto err_pll;
1152         }
1153
1154         return mux_clk;
1155
1156 err_pll:
1157         clk_unregister(mux_clk);
1158         mux_clk = pll_clk;
1159 err_mux:
1160         kfree(pll);
1161         return mux_clk;
1162 }