drivers/clk/rockchip/clk-pll.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <asm/div64.h>
  20 #include <linux/slab.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/regmap.h>
  25 #include <linux/clk.h>
  26 #include <linux/gcd.h>
  27 #include "clk.h"
  28
  29 #define PLL_MODE_MASK           0x3
  30 #define PLL_MODE_SLOW           0x0
  31 #define PLL_MODE_NORM           0x1
  32 #define PLL_MODE_DEEP           0x2
  33 #define PLL_RK3328_MODE_MASK    0x1
  34
  35 struct rockchip_clk_pll {
  36         struct clk_hw           hw;
  37
  38         struct clk_mux          pll_mux;
  39         const struct clk_ops    *pll_mux_ops;
  40
  41         struct notifier_block   clk_nb;
  42
  43         void __iomem            *reg_base;
  44         int                     lock_offset;
  45         unsigned int            lock_shift;
  46         enum rockchip_pll_type  type;
  47         u8                      flags;
  48         const struct rockchip_pll_rate_table *rate_table;
  49         unsigned int            rate_count;
  50         spinlock_t              *lock;
  51
  52         struct rockchip_clk_provider *ctx;
  53 };
  54
  55 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
  56 #define to_rockchip_clk_pll_nb(nb) \
  57                         container_of(nb, struct rockchip_clk_pll, clk_nb)
  58
  59 static void rockchip_rk3366_pll_get_params(struct rockchip_clk_pll *pll,
  60                                         struct rockchip_pll_rate_table *rate);
  61 static int rockchip_rk3366_pll_set_params(struct rockchip_clk_pll *pll,
  62                                 const struct rockchip_pll_rate_table *rate);
  63
  64 #define MHZ                     (1000UL * 1000UL)
  65 #define KHZ                     (1000UL)
  66
  67 /* CLK_PLL_TYPE_RK3066_AUTO type ops */
  68 #define PLL_FREF_MIN            (269 * KHZ)
  69 #define PLL_FREF_MAX            (2200 * MHZ)
  70
  71 #define PLL_FVCO_MIN            (440 * MHZ)
  72 #define PLL_FVCO_MAX            (2200 * MHZ)
  73
  74 #define PLL_FOUT_MIN            (27500 * KHZ)
  75 #define PLL_FOUT_MAX            (2200 * MHZ)
  76
  77 #define PLL_NF_MAX              (4096)
  78 #define PLL_NR_MAX              (64)
  79 #define PLL_NO_MAX              (16)
  80
  81 /* CLK_PLL_TYPE_RK3036/3366/3399_AUTO type ops */
  82 #define MIN_FOUTVCO_FREQ        (800 * MHZ)
  83 #define MAX_FOUTVCO_FREQ        (2000 * MHZ)
  84
  85 static struct rockchip_pll_rate_table auto_table;
  86
  87 static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
  88 {
  89         return &auto_table;
  90 }
  91
  92 static int rockchip_pll_clk_set_postdiv(unsigned long fout_hz,
  93                                         u32 *postdiv1,
  94                                         u32 *postdiv2,
  95                                         u32 *foutvco)
  96 {
  97         unsigned long freq;
  98
  99         if (fout_hz < MIN_FOUTVCO_FREQ) {
 100                 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
 101                         for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
 102                                 freq = fout_hz * (*postdiv1) * (*postdiv2);
 103                                 if (freq >= MIN_FOUTVCO_FREQ &&
 104                                     freq <= MAX_FOUTVCO_FREQ) {
 105                                         *foutvco = freq;
 106                                         return 0;
 107                                 }
 108                         }
 109                 }
 110                 pr_err("CANNOT FIND postdiv1/2 to make fout in range from 800M to 2000M,fout = %lu\n",
 111                        fout_hz);
 112         } else {
 113                 *postdiv1 = 1;
 114                 *postdiv2 = 1;
 115         }
 116         return 0;
 117 }
 118
 119 static struct rockchip_pll_rate_table *
 120 rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
 121                              unsigned long fin_hz,
 122                              unsigned long fout_hz)
 123 {
 124         struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
 125         /* FIXME set postdiv1/2 always 1*/
 126         u32 foutvco = fout_hz;
 127         u64 fin_64, frac_64;
 128         u32 f_frac, postdiv1, postdiv2;
 129         unsigned long clk_gcd = 0;
 130
 131         if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
 132                 return NULL;
 133
 134         rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
 135         rate_table->postdiv1 = postdiv1;
 136         rate_table->postdiv2 = postdiv2;
 137         rate_table->dsmpd = 1;
 138
 139         if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
 140                 fin_hz /= MHZ;
 141                 foutvco /= MHZ;
 142                 clk_gcd = gcd(fin_hz, foutvco);
 143                 rate_table->refdiv = fin_hz / clk_gcd;
 144                 rate_table->fbdiv = foutvco / clk_gcd;
 145
 146                 rate_table->frac = 0;
 147
 148                 pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u, fbdiv = %u, postdiv1 = %u, postdiv2 = %u, frac = %u\n",
 149                          fin_hz, fout_hz, clk_gcd, rate_table->refdiv,
 150                          rate_table->fbdiv, rate_table->postdiv1,
 151                          rate_table->postdiv2, rate_table->frac);
 152         } else {
 153                 pr_debug("frac div running, fin_hz = %lu, fout_hz = %lu, fin_INT_mhz = %lu, fout_INT_mhz = %lu\n",
 154                          fin_hz, fout_hz,
 155                          fin_hz / MHZ * MHZ,
 156                          fout_hz / MHZ * MHZ);
 157                 pr_debug("frac get postdiv1 = %u,  postdiv2 = %u, foutvco = %u\n",
 158                          rate_table->postdiv1, rate_table->postdiv2, foutvco);
 159                 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
 160                 rate_table->refdiv = fin_hz / MHZ / clk_gcd;
 161                 rate_table->fbdiv = foutvco / MHZ / clk_gcd;
 162                 pr_debug("frac get refdiv = %u,  fbdiv = %u\n",
 163                          rate_table->refdiv, rate_table->fbdiv);
 164
 165                 rate_table->frac = 0;
 166
 167                 f_frac = (foutvco % MHZ);
 168                 fin_64 = fin_hz;
 169                 do_div(fin_64, (u64)rate_table->refdiv);
 170                 frac_64 = (u64)f_frac << 24;
 171                 do_div(frac_64, fin_64);
 172                 rate_table->frac = (u32)frac_64;
 173                 if (rate_table->frac > 0)
 174                         rate_table->dsmpd = 0;
 175                 pr_debug("frac = %x\n", rate_table->frac);
 176         }
 177         return rate_table;
 178 }
 179
 180 static struct rockchip_pll_rate_table *
 181 rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
 182                                     unsigned long fin_hz,
 183                                     unsigned long fout_hz)
 184 {
 185         struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
 186         u32 nr, nf, no, nonr;
 187         u32 nr_out, nf_out, no_out;
 188         u32 n;
 189         u32 numerator, denominator;
 190         u64 fref, fvco, fout;
 191         unsigned long clk_gcd = 0;
 192
 193         nr_out = PLL_NR_MAX + 1;
 194         no_out = 0;
 195         nf_out = 0;
 196
 197         if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
 198                 return NULL;
 199
 200         clk_gcd = gcd(fin_hz, fout_hz);
 201
 202         numerator = fout_hz / clk_gcd;
 203         denominator = fin_hz / clk_gcd;
 204
 205         for (n = 1;; n++) {
 206                 nf = numerator * n;
 207                 nonr = denominator * n;
 208                 if (nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 209                         break;
 210
 211                 for (no = 1; no <= PLL_NO_MAX; no++) {
 212                         if (!(no == 1 || !(no % 2)))
 213                                 continue;
 214
 215                         if (nonr % no)
 216                                 continue;
 217                         nr = nonr / no;
 218
 219                         if (nr > PLL_NR_MAX)
 220                                 continue;
 221
 222                         fref = fin_hz / nr;
 223                         if (fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 224                                 continue;
 225
 226                         fvco = fref * nf;
 227                         if (fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 228                                 continue;
 229
 230                         fout = fvco / no;
 231                         if (fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 232                                 continue;
 233
 234                         /* select the best from all available PLL settings */
 235                         if ((no > no_out) ||
 236                             ((no == no_out) && (nr < nr_out))) {
 237                                 nr_out = nr;
 238                                 nf_out = nf;
 239                                 no_out = no;
 240                         }
 241                 }
 242         }
 243
 244         /* output the best PLL setting */
 245         if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
 246                 if (rate_table->nr && rate_table->nf && rate_table->no) {
 247                         rate_table->nr = nr_out;
 248                         rate_table->nf = nf_out;
 249                         rate_table->no = no_out;
 250                 }
 251         } else {
 252                 return NULL;
 253         }
 254
 255         return rate_table;
 256 }
 257
 258 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
 259                             struct rockchip_clk_pll *pll, unsigned long rate)
 260 {
 261         const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
 262         int i;
 263
 264         for (i = 0; i < pll->rate_count; i++) {
 265                 if (rate == rate_table[i].rate)
 266                         return &rate_table[i];
 267         }
 268
 269         if (pll->type == pll_rk3066 || pll->type == pll_rk3328)
 270                 return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
 271         else
 272                 return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
 273 }
 274
 275 static long rockchip_pll_round_rate(struct clk_hw *hw,
 276                             unsigned long drate, unsigned long *prate)
 277 {
 278         return drate;
 279 }
 280
 281 /*
 282  * Wait for the pll to reach the locked state.
 283  * The calling set_rate function is responsible for making sure the
 284  * grf regmap is available.
 285  */
 286 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
 287 {
 288         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 289         unsigned int val;
 290         int delay = 24000000, ret;
 291
 292         while (delay > 0) {
 293                 ret = regmap_read(grf, pll->lock_offset, &val);
 294                 if (ret) {
 295                         pr_err("%s: failed to read pll lock status: %d\n",
 296                                __func__, ret);
 297                         return ret;
 298                 }
 299
 300                 if (val & BIT(pll->lock_shift))
 301                         return 0;
 302                 delay--;
 303         }
 304
 305         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 306         return -ETIMEDOUT;
 307 }
 308
 309 /**
 310  * PLL used in RK3036
 311  */
 312
 313 #define RK3036_PLLCON(i)                        (i * 0x4)
 314 #define RK3036_PLLCON0_FBDIV_MASK               0xfff
 315 #define RK3036_PLLCON0_FBDIV_SHIFT              0
 316 #define RK3036_PLLCON0_POSTDIV1_MASK            0x7
 317 #define RK3036_PLLCON0_POSTDIV1_SHIFT           12
 318 #define RK3036_PLLCON1_REFDIV_MASK              0x3f
 319 #define RK3036_PLLCON1_REFDIV_SHIFT             0
 320 #define RK3036_PLLCON1_POSTDIV2_MASK            0x7
 321 #define RK3036_PLLCON1_POSTDIV2_SHIFT           6
 322 #define RK3036_PLLCON1_DSMPD_MASK               0x1
 323 #define RK3036_PLLCON1_DSMPD_SHIFT              12
 324 #define RK3036_PLLCON2_FRAC_MASK                0xffffff
 325 #define RK3036_PLLCON2_FRAC_SHIFT               0
 326
 327 #define RK3036_PLLCON1_PWRDOWN                  (1 << 13)
 328
 329 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
 330                                         struct rockchip_pll_rate_table *rate)
 331 {
 332         u32 pllcon;
 333
 334         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
 335         rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
 336                                 & RK3036_PLLCON0_FBDIV_MASK);
 337         rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
 338                                 & RK3036_PLLCON0_POSTDIV1_MASK);
 339
 340         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
 341         rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
 342                                 & RK3036_PLLCON1_REFDIV_MASK);
 343         rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
 344                                 & RK3036_PLLCON1_POSTDIV2_MASK);
 345         rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
 346                                 & RK3036_PLLCON1_DSMPD_MASK);
 347
 348         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 349         rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
 350                                 & RK3036_PLLCON2_FRAC_MASK);
 351 }
 352
 353 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
 354                                                      unsigned long prate)
 355 {
 356         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 357         struct rockchip_pll_rate_table cur;
 358         u64 rate64 = prate;
 359
 360         if (pll->type == pll_rk3366)
 361                 rockchip_rk3366_pll_get_params(pll, &cur);
 362         else
 363                 rockchip_rk3036_pll_get_params(pll, &cur);
 364
 365         rate64 *= cur.fbdiv;
 366         do_div(rate64, cur.refdiv);
 367
 368         if (cur.dsmpd == 0) {
 369                 /* fractional mode */
 370                 u64 frac_rate64 = prate * cur.frac;
 371
 372                 do_div(frac_rate64, cur.refdiv);
 373                 rate64 += frac_rate64 >> 24;
 374         }
 375
 376         do_div(rate64, cur.postdiv1);
 377         do_div(rate64, cur.postdiv2);
 378
 379         return (unsigned long)rate64;
 380 }
 381
 382 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
 383                                 const struct rockchip_pll_rate_table *rate)
 384 {
 385         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 386         struct clk_mux *pll_mux = &pll->pll_mux;
 387         struct rockchip_pll_rate_table cur;
 388         u32 pllcon;
 389         int rate_change_remuxed = 0;
 390         int cur_parent;
 391         int ret;
 392
 393         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 394                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 395                 rate->postdiv2, rate->dsmpd, rate->frac);
 396
 397         rockchip_rk3036_pll_get_params(pll, &cur);
 398         cur.rate = 0;
 399
 400         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 401         if (cur_parent == PLL_MODE_NORM) {
 402                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 403                 rate_change_remuxed = 1;
 404         }
 405
 406         /* update pll values */
 407         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
 408                                           RK3036_PLLCON0_FBDIV_SHIFT) |
 409                        HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
 410                                              RK3036_PLLCON0_POSTDIV1_SHIFT),
 411                        pll->reg_base + RK3036_PLLCON(0));
 412
 413         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
 414                                                    RK3036_PLLCON1_REFDIV_SHIFT) |
 415                        HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
 416                                                      RK3036_PLLCON1_POSTDIV2_SHIFT) |
 417                        HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
 418                                                   RK3036_PLLCON1_DSMPD_SHIFT),
 419                        pll->reg_base + RK3036_PLLCON(1));
 420
 421         /* GPLL CON2 is not HIWORD_MASK */
 422         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 423         pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
 424         pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
 425         writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
 426
 427         /* wait for the pll to lock */
 428         ret = rockchip_pll_wait_lock(pll);
 429         if (ret) {
 430                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 431                         __func__);
 432                 rockchip_rk3036_pll_set_params(pll, &cur);
 433         }
 434
 435         if (rate_change_remuxed)
 436                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 437
 438         return ret;
 439 }
 440
 441 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 442                                         unsigned long prate)
 443 {
 444         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 445         const struct rockchip_pll_rate_table *rate;
 446         unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
 447         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 448
 449         if (IS_ERR(grf)) {
 450                 pr_debug("%s: grf regmap not available, aborting rate change\n",
 451                          __func__);
 452                 return PTR_ERR(grf);
 453         }
 454
 455         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 456                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
 457
 458         /* Get required rate settings from table */
 459         rate = rockchip_get_pll_settings(pll, drate);
 460         if (!rate) {
 461                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 462                         drate, __clk_get_name(hw->clk));
 463                 return -EINVAL;
 464         }
 465
 466         if (pll->type == pll_rk3366)
 467                 return rockchip_rk3366_pll_set_params(pll, rate);
 468
 469         return rockchip_rk3036_pll_set_params(pll, rate);
 470 }
 471
 472 static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
 473 {
 474         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 475
 476         writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
 477                pll->reg_base + RK3036_PLLCON(1));
 478         rockchip_pll_wait_lock(pll);
 479
 480         return 0;
 481 }
 482
 483 static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
 484 {
 485         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 486
 487         writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
 488                              RK3036_PLLCON1_PWRDOWN, 0),
 489                pll->reg_base + RK3036_PLLCON(1));
 490 }
 491
 492 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
 493 {
 494         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 495         u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
 496
 497         return !(pllcon & RK3036_PLLCON1_PWRDOWN);
 498 }
 499
 500 static void rockchip_rk3036_pll_init(struct clk_hw *hw)
 501 {
 502         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 503         const struct rockchip_pll_rate_table *rate;
 504         struct rockchip_pll_rate_table cur;
 505         unsigned long drate;
 506
 507         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 508                 return;
 509
 510         drate = clk_hw_get_rate(hw);
 511         rate = rockchip_get_pll_settings(pll, drate);
 512
 513         /* when no rate setting for the current rate, rely on clk_set_rate */
 514         if (!rate)
 515                 return;
 516
 517         if (pll->type == pll_rk3366)
 518                 rockchip_rk3366_pll_get_params(pll, &cur);
 519         else
 520                 rockchip_rk3036_pll_get_params(pll, &cur);
 521
 522         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
 523                  drate);
 524         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 525                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
 526                  cur.dsmpd, cur.frac);
 527         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 528                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
 529                  rate->dsmpd, rate->frac);
 530
 531         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
 532                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
 533                 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
 534                 struct clk *parent = clk_get_parent(hw->clk);
 535
 536                 if (!parent) {
 537                         pr_warn("%s: parent of %s not available\n",
 538                                 __func__, __clk_get_name(hw->clk));
 539                         return;
 540                 }
 541
 542                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 543                          __func__, __clk_get_name(hw->clk));
 544                 if (pll->type == pll_rk3366)
 545                         rockchip_rk3366_pll_set_params(pll, rate);
 546                 else
 547                         rockchip_rk3036_pll_set_params(pll, rate);
 548         }
 549 }
 550
 551 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
 552         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 553         .enable = rockchip_rk3036_pll_enable,
 554         .disable = rockchip_rk3036_pll_disable,
 555         .is_enabled = rockchip_rk3036_pll_is_enabled,
 556 };
 557
 558 static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
 559         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 560         .round_rate = rockchip_pll_round_rate,
 561         .set_rate = rockchip_rk3036_pll_set_rate,
 562         .enable = rockchip_rk3036_pll_enable,
 563         .disable = rockchip_rk3036_pll_disable,
 564         .is_enabled = rockchip_rk3036_pll_is_enabled,
 565         .init = rockchip_rk3036_pll_init,
 566 };
 567
 568 /**
 569  * PLL used in RK3066, RK3188 and RK3288
 570  */
 571
 572 #define RK3066_PLL_RESET_DELAY(nr)      ((nr * 500) / 24 + 1)
 573
 574 #define RK3066_PLLCON(i)                (i * 0x4)
 575 #define RK3066_PLLCON0_OD_MASK          0xf
 576 #define RK3066_PLLCON0_OD_SHIFT         0
 577 #define RK3066_PLLCON0_NR_MASK          0x3f
 578 #define RK3066_PLLCON0_NR_SHIFT         8
 579 #define RK3066_PLLCON1_NF_MASK          0x1fff
 580 #define RK3066_PLLCON1_NF_SHIFT         0
 581 #define RK3066_PLLCON2_NB_MASK          0xfff
 582 #define RK3066_PLLCON2_NB_SHIFT         0
 583 #define RK3066_PLLCON3_RESET            (1 << 5)
 584 #define RK3066_PLLCON3_PWRDOWN          (1 << 1)
 585 #define RK3066_PLLCON3_BYPASS           (1 << 0)
 586
 587 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
 588                                         struct rockchip_pll_rate_table *rate)
 589 {
 590         u32 pllcon;
 591
 592         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
 593         rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
 594                                 & RK3066_PLLCON0_NR_MASK) + 1;
 595         rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
 596                                 & RK3066_PLLCON0_OD_MASK) + 1;
 597
 598         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
 599         rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
 600                                 & RK3066_PLLCON1_NF_MASK) + 1;
 601
 602         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
 603         rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
 604                                 & RK3066_PLLCON2_NB_MASK) + 1;
 605 }
 606
 607 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
 608                                                      unsigned long prate)
 609 {
 610         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 611         struct rockchip_pll_rate_table cur;
 612         u64 rate64 = prate;
 613         u32 pllcon;
 614
 615         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
 616         if (pllcon & RK3066_PLLCON3_BYPASS) {
 617                 pr_debug("%s: pll %s is bypassed\n", __func__,
 618                         clk_hw_get_name(hw));
 619                 return prate;
 620         }
 621
 622         rockchip_rk3066_pll_get_params(pll, &cur);
 623
 624         rate64 *= cur.nf;
 625         do_div(rate64, cur.nr);
 626         do_div(rate64, cur.no);
 627
 628         return (unsigned long)rate64;
 629 }
 630
 631 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
 632                                 const struct rockchip_pll_rate_table *rate)
 633 {
 634         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 635         struct clk_mux *pll_mux = &pll->pll_mux;
 636         struct rockchip_pll_rate_table cur;
 637         int rate_change_remuxed = 0;
 638         int cur_parent;
 639         int ret;
 640
 641         pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
 642                  __func__, rate->rate, rate->nr, rate->no, rate->nf);
 643
 644         rockchip_rk3066_pll_get_params(pll, &cur);
 645         cur.rate = 0;
 646
 647         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 648         if (cur_parent == PLL_MODE_NORM) {
 649                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 650                 rate_change_remuxed = 1;
 651         }
 652
 653         /* enter reset mode */
 654         writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
 655                pll->reg_base + RK3066_PLLCON(3));
 656
 657         /* update pll values */
 658         writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
 659                                            RK3066_PLLCON0_NR_SHIFT) |
 660                HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
 661                                            RK3066_PLLCON0_OD_SHIFT),
 662                pll->reg_base + RK3066_PLLCON(0));
 663
 664         writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
 665                                                    RK3066_PLLCON1_NF_SHIFT),
 666                        pll->reg_base + RK3066_PLLCON(1));
 667         writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
 668                                                    RK3066_PLLCON2_NB_SHIFT),
 669                        pll->reg_base + RK3066_PLLCON(2));
 670
 671         /* leave reset and wait the reset_delay */
 672         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
 673                pll->reg_base + RK3066_PLLCON(3));
 674         udelay(RK3066_PLL_RESET_DELAY(rate->nr));
 675
 676         /* wait for the pll to lock */
 677         ret = rockchip_pll_wait_lock(pll);
 678         if (ret) {
 679                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 680                         __func__);
 681                 rockchip_rk3066_pll_set_params(pll, &cur);
 682         }
 683
 684         if (rate_change_remuxed)
 685                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 686
 687         return ret;
 688 }
 689
 690 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 691                                         unsigned long prate)
 692 {
 693         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 694         const struct rockchip_pll_rate_table *rate;
 695         unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
 696         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 697
 698         if (IS_ERR(grf)) {
 699                 pr_debug("%s: grf regmap not available, aborting rate change\n",
 700                          __func__);
 701                 return PTR_ERR(grf);
 702         }
 703
 704         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 705                  __func__, clk_hw_get_name(hw), old_rate, drate, prate);
 706
 707         /* Get required rate settings from table */
 708         rate = rockchip_get_pll_settings(pll, drate);
 709         if (!rate) {
 710                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 711                         drate, clk_hw_get_name(hw));
 712                 return -EINVAL;
 713         }
 714
 715         return rockchip_rk3066_pll_set_params(pll, rate);
 716 }
 717
 718 static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 719 {
 720         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 721
 722         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 723                pll->reg_base + RK3066_PLLCON(3));
 724         rockchip_pll_wait_lock(pll);
 725
 726         return 0;
 727 }
 728
 729 static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
 730 {
 731         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 732
 733         writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
 734                              RK3066_PLLCON3_PWRDOWN, 0),
 735                pll->reg_base + RK3066_PLLCON(3));
 736 }
 737
 738 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
 739 {
 740         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 741         u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
 742
 743         return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 744 }
 745
 746 static void rockchip_rk3066_pll_init(struct clk_hw *hw)
 747 {
 748         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 749         const struct rockchip_pll_rate_table *rate;
 750         struct rockchip_pll_rate_table cur;
 751         unsigned long drate;
 752
 753         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 754                 return;
 755
 756         drate = clk_hw_get_rate(hw);
 757         rate = rockchip_get_pll_settings(pll, drate);
 758
 759         /* when no rate setting for the current rate, rely on clk_set_rate */
 760         if (!rate)
 761                 return;
 762
 763         rockchip_rk3066_pll_get_params(pll, &cur);
 764
 765         pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
 766                  __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
 767                  rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
 768         if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
 769                                                      || rate->nb != cur.nb) {
 770                 struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 771
 772                 if (IS_ERR(grf))
 773                         return;
 774
 775                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 776                          __func__, clk_hw_get_name(hw));
 777                 rockchip_rk3066_pll_set_params(pll, rate);
 778         }
 779 }
 780
 781 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
 782         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 783         .enable = rockchip_rk3066_pll_enable,
 784         .disable = rockchip_rk3066_pll_disable,
 785         .is_enabled = rockchip_rk3066_pll_is_enabled,
 786 };
 787
 788 static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
 789         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 790         .round_rate = rockchip_pll_round_rate,
 791         .set_rate = rockchip_rk3066_pll_set_rate,
 792         .enable = rockchip_rk3066_pll_enable,
 793         .disable = rockchip_rk3066_pll_disable,
 794         .is_enabled = rockchip_rk3066_pll_is_enabled,
 795         .init = rockchip_rk3066_pll_init,
 796 };
 797
 798 /**
 799  * PLL used in RK3366
 800  */
 801
 802 #define RK3366_PLLCON(i)                        (i * 0x4)
 803 #define RK3366_PLLCON0_FBDIV_MASK               0xfff
 804 #define RK3366_PLLCON0_FBDIV_SHIFT              0
 805 #define RK3366_PLLCON0_POSTDIV1_MASK            0x7
 806 #define RK3366_PLLCON0_POSTDIV1_SHIFT           12
 807 #define RK3366_PLLCON1_REFDIV_MASK              0x3f
 808 #define RK3366_PLLCON1_REFDIV_SHIFT             0
 809 #define RK3366_PLLCON1_POSTDIV2_MASK            0x7
 810 #define RK3366_PLLCON1_POSTDIV2_SHIFT           6
 811 #define RK3366_PLLCON2_FRAC_MASK                0xffffff
 812 #define RK3366_PLLCON2_FRAC_SHIFT               0
 813 #define RK3366_PLLCON3_DSMPD_MASK               0x1
 814 #define RK3366_PLLCON3_DSMPD_SHIFT              2
 815
 816 #define RK3366_PLLCON3_PWRDOWN                  (1 << 0)
 817
 818 static void rockchip_rk3366_pll_get_params(struct rockchip_clk_pll *pll,
 819                                         struct rockchip_pll_rate_table *rate)
 820 {
 821         u32 pllcon;
 822
 823         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(0));
 824         rate->fbdiv = ((pllcon >> RK3366_PLLCON0_FBDIV_SHIFT)
 825                                 & RK3366_PLLCON0_FBDIV_MASK);
 826         rate->postdiv1 = ((pllcon >> RK3366_PLLCON0_POSTDIV1_SHIFT)
 827                                 & RK3366_PLLCON0_POSTDIV1_MASK);
 828
 829         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(1));
 830         rate->refdiv = ((pllcon >> RK3366_PLLCON1_REFDIV_SHIFT)
 831                                 & RK3366_PLLCON1_REFDIV_MASK);
 832         rate->postdiv2 = ((pllcon >> RK3366_PLLCON1_POSTDIV2_SHIFT)
 833                                 & RK3366_PLLCON1_POSTDIV2_MASK);
 834
 835         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(2));
 836         rate->frac = ((pllcon >> RK3366_PLLCON2_FRAC_SHIFT)
 837                                 & RK3366_PLLCON2_FRAC_MASK);
 838
 839         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(3));
 840         rate->dsmpd = ((pllcon >> RK3366_PLLCON3_DSMPD_SHIFT)
 841                                 & RK3366_PLLCON3_DSMPD_MASK);
 842 }
 843
 844 static int rockchip_rk3366_pll_set_params(struct rockchip_clk_pll *pll,
 845                                 const struct rockchip_pll_rate_table *rate)
 846 {
 847         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 848         struct clk_mux *pll_mux = &pll->pll_mux;
 849         struct rockchip_pll_rate_table cur;
 850         u32 pllcon;
 851         int rate_change_remuxed = 0;
 852         int cur_parent;
 853         int ret;
 854
 855         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 856                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 857                 rate->postdiv2, rate->dsmpd, rate->frac);
 858
 859         rockchip_rk3366_pll_get_params(pll, &cur);
 860         cur.rate = 0;
 861
 862         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 863         if (cur_parent == PLL_MODE_NORM) {
 864                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 865                 rate_change_remuxed = 1;
 866         }
 867
 868         /* update pll values */
 869         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3366_PLLCON0_FBDIV_MASK,
 870                                           RK3366_PLLCON0_FBDIV_SHIFT) |
 871                        HIWORD_UPDATE(rate->postdiv1, RK3366_PLLCON0_POSTDIV1_MASK,
 872                                              RK3366_PLLCON0_POSTDIV1_SHIFT),
 873                        pll->reg_base + RK3366_PLLCON(0));
 874
 875         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3366_PLLCON1_REFDIV_MASK,
 876                                                    RK3366_PLLCON1_REFDIV_SHIFT) |
 877                        HIWORD_UPDATE(rate->postdiv2, RK3366_PLLCON1_POSTDIV2_MASK,
 878                                                      RK3366_PLLCON1_POSTDIV2_SHIFT),
 879                        pll->reg_base + RK3366_PLLCON(1));
 880
 881         /* GPLL CON2 is not HIWORD_MASK */
 882         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(2));
 883         pllcon &= ~(RK3366_PLLCON2_FRAC_MASK << RK3366_PLLCON2_FRAC_SHIFT);
 884         pllcon |= rate->frac << RK3366_PLLCON2_FRAC_SHIFT;
 885         writel_relaxed(pllcon, pll->reg_base + RK3366_PLLCON(2));
 886
 887         writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3366_PLLCON3_DSMPD_MASK,
 888                                                   RK3366_PLLCON3_DSMPD_SHIFT),
 889                        pll->reg_base + RK3366_PLLCON(3));
 890
 891         /* wait for the pll to lock */
 892         ret = rockchip_pll_wait_lock(pll);
 893         if (ret) {
 894                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 895                         __func__);
 896                 rockchip_rk3366_pll_set_params(pll, &cur);
 897         }
 898
 899         if (rate_change_remuxed)
 900                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 901
 902         return ret;
 903 }
 904
 905 static int rockchip_rk3366_pll_enable(struct clk_hw *hw)
 906 {
 907         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 908
 909         writel(HIWORD_UPDATE(0, RK3366_PLLCON3_PWRDOWN, 0),
 910                pll->reg_base + RK3366_PLLCON(3));
 911
 912         return 0;
 913 }
 914
 915 static void rockchip_rk3366_pll_disable(struct clk_hw *hw)
 916 {
 917         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 918
 919         writel(HIWORD_UPDATE(RK3366_PLLCON3_PWRDOWN,
 920                              RK3366_PLLCON3_PWRDOWN, 0),
 921                pll->reg_base + RK3366_PLLCON(3));
 922 }
 923
 924 static int rockchip_rk3366_pll_is_enabled(struct clk_hw *hw)
 925 {
 926         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 927         u32 pllcon = readl(pll->reg_base + RK3366_PLLCON(3));
 928
 929         return !(pllcon & RK3366_PLLCON3_PWRDOWN);
 930 }
 931
 932 static const struct clk_ops rockchip_rk3366_pll_clk_norate_ops = {
 933         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 934         .enable = rockchip_rk3366_pll_enable,
 935         .disable = rockchip_rk3366_pll_disable,
 936         .is_enabled = rockchip_rk3366_pll_is_enabled,
 937 };
 938
 939 static const struct clk_ops rockchip_rk3366_pll_clk_ops = {
 940         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 941         .round_rate = rockchip_pll_round_rate,
 942         .set_rate = rockchip_rk3036_pll_set_rate,
 943         .enable = rockchip_rk3366_pll_enable,
 944         .disable = rockchip_rk3366_pll_disable,
 945         .is_enabled = rockchip_rk3366_pll_is_enabled,
 946         .init = rockchip_rk3036_pll_init,
 947 };
 948
 949 /**
 950  * PLL used in RK3399
 951  */
 952
 953 #define RK3399_PLLCON(i)                        (i * 0x4)
 954 #define RK3399_PLLCON0_FBDIV_MASK               0xfff
 955 #define RK3399_PLLCON0_FBDIV_SHIFT              0
 956 #define RK3399_PLLCON1_REFDIV_MASK              0x3f
 957 #define RK3399_PLLCON1_REFDIV_SHIFT             0
 958 #define RK3399_PLLCON1_POSTDIV1_MASK            0x7
 959 #define RK3399_PLLCON1_POSTDIV1_SHIFT           8
 960 #define RK3399_PLLCON1_POSTDIV2_MASK            0x7
 961 #define RK3399_PLLCON1_POSTDIV2_SHIFT           12
 962 #define RK3399_PLLCON2_FRAC_MASK                0xffffff
 963 #define RK3399_PLLCON2_FRAC_SHIFT               0
 964 #define RK3399_PLLCON2_LOCK_STATUS              BIT(31)
 965 #define RK3399_PLLCON3_PWRDOWN                  BIT(0)
 966 #define RK3399_PLLCON3_DSMPD_MASK               0x1
 967 #define RK3399_PLLCON3_DSMPD_SHIFT              3
 968
 969 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
 970 {
 971         u32 pllcon;
 972         int delay = 24000000;
 973
 974         /* poll check the lock status in rk3399 xPLLCON2 */
 975         while (delay > 0) {
 976                 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 977                 if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
 978                         return 0;
 979
 980                 delay--;
 981         }
 982
 983         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 984         return -ETIMEDOUT;
 985 }
 986
 987 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
 988                                         struct rockchip_pll_rate_table *rate)
 989 {
 990         u32 pllcon;
 991
 992         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
 993         rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
 994                                 & RK3399_PLLCON0_FBDIV_MASK);
 995
 996         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
 997         rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
 998                                 & RK3399_PLLCON1_REFDIV_MASK);
 999         rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
1000                                 & RK3399_PLLCON1_POSTDIV1_MASK);
1001         rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
1002                                 & RK3399_PLLCON1_POSTDIV2_MASK);
1003
1004         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
1005         rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
1006                                 & RK3399_PLLCON2_FRAC_MASK);
1007
1008         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
1009         rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
1010                                 & RK3399_PLLCON3_DSMPD_MASK);
1011 }
1012
1013 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
1014                                                      unsigned long prate)
1015 {
1016         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1017         struct rockchip_pll_rate_table cur;
1018         u64 rate64 = prate;
1019
1020         rockchip_rk3399_pll_get_params(pll, &cur);
1021
1022         rate64 *= cur.fbdiv;
1023         do_div(rate64, cur.refdiv);
1024
1025         if (cur.dsmpd == 0) {
1026                 /* fractional mode */
1027                 u64 frac_rate64 = prate * cur.frac;
1028
1029                 do_div(frac_rate64, cur.refdiv);
1030                 rate64 += frac_rate64 >> 24;
1031         }
1032
1033         do_div(rate64, cur.postdiv1);
1034         do_div(rate64, cur.postdiv2);
1035
1036         return (unsigned long)rate64;
1037 }
1038
1039 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
1040                                 const struct rockchip_pll_rate_table *rate)
1041 {
1042         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
1043         struct clk_mux *pll_mux = &pll->pll_mux;
1044         struct rockchip_pll_rate_table cur;
1045         u32 pllcon;
1046         int rate_change_remuxed = 0;
1047         int cur_parent;
1048         int ret;
1049
1050         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
1051                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
1052                 rate->postdiv2, rate->dsmpd, rate->frac);
1053
1054         rockchip_rk3399_pll_get_params(pll, &cur);
1055         cur.rate = 0;
1056
1057         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
1058         if (cur_parent == PLL_MODE_NORM) {
1059                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
1060                 rate_change_remuxed = 1;
1061         }
1062
1063         /* set pll power down */
1064         writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
1065                              RK3399_PLLCON3_PWRDOWN, 0),
1066                pll->reg_base + RK3399_PLLCON(3));
1067
1068         /* update pll values */
1069         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
1070                                                   RK3399_PLLCON0_FBDIV_SHIFT),
1071                        pll->reg_base + RK3399_PLLCON(0));
1072
1073         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
1074                                                    RK3399_PLLCON1_REFDIV_SHIFT) |
1075                        HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
1076                                                      RK3399_PLLCON1_POSTDIV1_SHIFT) |
1077                        HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
1078                                                      RK3399_PLLCON1_POSTDIV2_SHIFT),
1079                        pll->reg_base + RK3399_PLLCON(1));
1080
1081         /* xPLL CON2 is not HIWORD_MASK */
1082         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
1083         pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT);
1084         pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
1085         writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
1086
1087         writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
1088                                             RK3399_PLLCON3_DSMPD_SHIFT),
1089                        pll->reg_base + RK3399_PLLCON(3));
1090
1091         /* set pll power up */
1092         writel(HIWORD_UPDATE(0,
1093                              RK3399_PLLCON3_PWRDOWN, 0),
1094                pll->reg_base + RK3399_PLLCON(3));
1095
1096         /* wait for the pll to lock */
1097         ret = rockchip_rk3399_pll_wait_lock(pll);
1098         if (ret) {
1099                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
1100                         __func__);
1101                 rockchip_rk3399_pll_set_params(pll, &cur);
1102         }
1103
1104         if (rate_change_remuxed)
1105                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
1106
1107         return ret;
1108 }
1109
1110 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
1111                                         unsigned long prate)
1112 {
1113         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1114         const struct rockchip_pll_rate_table *rate;
1115         unsigned long old_rate = rockchip_rk3399_pll_recalc_rate(hw, prate);
1116
1117         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
1118                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
1119
1120         /* Get required rate settings from table */
1121         rate = rockchip_get_pll_settings(pll, drate);
1122         if (!rate) {
1123                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1124                         drate, __clk_get_name(hw->clk));
1125                 return -EINVAL;
1126         }
1127
1128         return rockchip_rk3399_pll_set_params(pll, rate);
1129 }
1130
1131 static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
1132 {
1133         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1134
1135         writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
1136                pll->reg_base + RK3399_PLLCON(3));
1137         rockchip_rk3399_pll_wait_lock(pll);
1138
1139         return 0;
1140 }
1141
1142 static void rockchip_rk3399_pll_disable(struct clk_hw *hw)
1143 {
1144         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1145
1146         writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
1147                              RK3399_PLLCON3_PWRDOWN, 0),
1148                pll->reg_base + RK3399_PLLCON(3));
1149 }
1150
1151 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw)
1152 {
1153         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1154         u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
1155
1156         return !(pllcon & RK3399_PLLCON3_PWRDOWN);
1157 }
1158
1159 static void rockchip_rk3399_pll_init(struct clk_hw *hw)
1160 {
1161         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1162         const struct rockchip_pll_rate_table *rate;
1163         struct rockchip_pll_rate_table cur;
1164         unsigned long drate;
1165
1166         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
1167                 return;
1168
1169         drate = clk_hw_get_rate(hw);
1170         rate = rockchip_get_pll_settings(pll, drate);
1171
1172         /* when no rate setting for the current rate, rely on clk_set_rate */
1173         if (!rate)
1174                 return;
1175
1176         rockchip_rk3399_pll_get_params(pll, &cur);
1177
1178         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
1179                  drate);
1180         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
1181                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
1182                  cur.dsmpd, cur.frac);
1183         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
1184                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
1185                  rate->dsmpd, rate->frac);
1186
1187         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
1188                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
1189                 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
1190                 struct clk *parent = clk_get_parent(hw->clk);
1191
1192                 if (!parent) {
1193                         pr_warn("%s: parent of %s not available\n",
1194                                 __func__, __clk_get_name(hw->clk));
1195                         return;
1196                 }
1197
1198                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
1199                          __func__, __clk_get_name(hw->clk));
1200                 rockchip_rk3399_pll_set_params(pll, rate);
1201         }
1202 }
1203
1204 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = {
1205         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
1206         .enable = rockchip_rk3399_pll_enable,
1207         .disable = rockchip_rk3399_pll_disable,
1208         .is_enabled = rockchip_rk3399_pll_is_enabled,
1209 };
1210
1211 static const struct clk_ops rockchip_rk3399_pll_clk_ops = {
1212         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
1213         .round_rate = rockchip_pll_round_rate,
1214         .set_rate = rockchip_rk3399_pll_set_rate,
1215         .enable = rockchip_rk3399_pll_enable,
1216         .disable = rockchip_rk3399_pll_disable,
1217         .is_enabled = rockchip_rk3399_pll_is_enabled,
1218         .init = rockchip_rk3399_pll_init,
1219 };
1220
1221 /*
1222  * Common registering of pll clocks
1223  */
1224
1225 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
1226                 enum rockchip_pll_type pll_type,
1227                 const char *name, const char *const *parent_names,
1228                 u8 num_parents, int con_offset, int grf_lock_offset,
1229                 int lock_shift, int mode_offset, int mode_shift,
1230                 struct rockchip_pll_rate_table *rate_table,
1231                 unsigned long flags, u8 clk_pll_flags)
1232 {
1233         const char *pll_parents[3];
1234         struct clk_init_data init;
1235         struct rockchip_clk_pll *pll;
1236         struct clk_mux *pll_mux;
1237         struct clk *pll_clk, *mux_clk;
1238         char pll_name[20];
1239
1240         if ((pll_type != pll_rk3328 && num_parents != 2) ||
1241             (pll_type == pll_rk3328 && num_parents != 1)) {
1242                 pr_err("%s: needs two parent clocks\n", __func__);
1243                 return ERR_PTR(-EINVAL);
1244         }
1245
1246         /* name the actual pll */
1247         snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
1248
1249         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1250         if (!pll)
1251                 return ERR_PTR(-ENOMEM);
1252
1253         /* create the mux on top of the real pll */
1254         pll->pll_mux_ops = &clk_mux_ops;
1255         pll_mux = &pll->pll_mux;
1256         pll_mux->reg = ctx->reg_base + mode_offset;
1257         pll_mux->shift = mode_shift;
1258         if (pll_type == pll_rk3328)
1259                 pll_mux->mask = PLL_RK3328_MODE_MASK;
1260         else
1261                 pll_mux->mask = PLL_MODE_MASK;
1262         pll_mux->flags = 0;
1263         pll_mux->lock = &ctx->lock;
1264         pll_mux->hw.init = &init;
1265
1266         if (pll_type == pll_rk3036 ||
1267             pll_type == pll_rk3066 ||
1268             pll_type == pll_rk3328 ||
1269             pll_type == pll_rk3366 ||
1270             pll_type == pll_rk3399)
1271                 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
1272
1273         /* the actual muxing is xin24m, pll-output, xin32k */
1274         pll_parents[0] = parent_names[0];
1275         pll_parents[1] = pll_name;
1276         pll_parents[2] = parent_names[1];
1277
1278         init.name = name;
1279         init.flags = CLK_SET_RATE_PARENT;
1280         init.ops = pll->pll_mux_ops;
1281         init.parent_names = pll_parents;
1282         if (pll_type == pll_rk3328)
1283                 init.num_parents = 2;
1284         else
1285                 init.num_parents = ARRAY_SIZE(pll_parents);
1286
1287         mux_clk = clk_register(NULL, &pll_mux->hw);
1288         if (IS_ERR(mux_clk))
1289                 goto err_mux;
1290
1291         /* now create the actual pll */
1292         init.name = pll_name;
1293
1294         /* keep all plls untouched for now */
1295         init.flags = flags | CLK_IGNORE_UNUSED;
1296
1297         init.parent_names = &parent_names[0];
1298         init.num_parents = 1;
1299
1300         if (rate_table) {
1301                 int len;
1302
1303                 /* find count of rates in rate_table */
1304                 for (len = 0; rate_table[len].rate != 0; )
1305                         len++;
1306
1307                 pll->rate_count = len;
1308                 pll->rate_table = kmemdup(rate_table,
1309                                         pll->rate_count *
1310                                         sizeof(struct rockchip_pll_rate_table),
1311                                         GFP_KERNEL);
1312                 WARN(!pll->rate_table,
1313                         "%s: could not allocate rate table for %s\n",
1314                         __func__, name);
1315         }
1316
1317         switch (pll_type) {
1318         case pll_rk3036:
1319         case pll_rk3328:
1320                 if (!pll->rate_table)
1321                         init.ops = &rockchip_rk3036_pll_clk_norate_ops;
1322                 else
1323                         init.ops = &rockchip_rk3036_pll_clk_ops;
1324                 break;
1325         case pll_rk3066:
1326                 if (!pll->rate_table)
1327                         init.ops = &rockchip_rk3066_pll_clk_norate_ops;
1328                 else
1329                         init.ops = &rockchip_rk3066_pll_clk_ops;
1330                 break;
1331         case pll_rk3366:
1332                 if (!pll->rate_table)
1333                         init.ops = &rockchip_rk3366_pll_clk_norate_ops;
1334                 else
1335                         init.ops = &rockchip_rk3366_pll_clk_ops;
1336                 break;
1337         case pll_rk3399:
1338                 if (!pll->rate_table)
1339                         init.ops = &rockchip_rk3399_pll_clk_norate_ops;
1340                 else
1341                         init.ops = &rockchip_rk3399_pll_clk_ops;
1342                 break;
1343         default:
1344                 pr_warn("%s: Unknown pll type for pll clk %s\n",
1345                         __func__, name);
1346         }
1347
1348         pll->hw.init = &init;
1349         pll->type = pll_type;
1350         pll->reg_base = ctx->reg_base + con_offset;
1351         pll->lock_offset = grf_lock_offset;
1352         pll->lock_shift = lock_shift;
1353         pll->flags = clk_pll_flags;
1354         pll->lock = &ctx->lock;
1355         pll->ctx = ctx;
1356
1357         pll_clk = clk_register(NULL, &pll->hw);
1358         if (IS_ERR(pll_clk)) {
1359                 pr_err("%s: failed to register pll clock %s : %ld\n",
1360                         __func__, name, PTR_ERR(pll_clk));
1361                 goto err_pll;
1362         }
1363
1364         return mux_clk;
1365
1366 err_pll:
1367         clk_unregister(mux_clk);
1368         mux_clk = pll_clk;
1369 err_mux:
1370         kfree(pll);
1371         return mux_clk;
1372 }