arch/xtensa/kernel/setup.c

   1 /*
   2  * arch/xtensa/kernel/setup.c
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1995  Linus Torvalds
   9  * Copyright (C) 2001 - 2005  Tensilica Inc.
  10  *
  11  * Chris Zankel <chris@zankel.net>
  12  * Joe Taylor   <joe@tensilica.com, joetylr@yahoo.com>
  13  * Kevin Chea
  14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/mm.h>
  20 #include <linux/proc_fs.h>
  21 #include <linux/screen_info.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/kernel.h>
  24
  25 #ifdef CONFIG_OF
  26 #include <linux/of_fdt.h>
  27 #include <linux/of_platform.h>
  28 #endif
  29
  30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  31 # include <linux/console.h>
  32 #endif
  33
  34 #ifdef CONFIG_RTC
  35 # include <linux/timex.h>
  36 #endif
  37
  38 #ifdef CONFIG_PROC_FS
  39 # include <linux/seq_file.h>
  40 #endif
  41
  42 #include <asm/bootparam.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/processor.h>
  45 #include <asm/timex.h>
  46 #include <asm/platform.h>
  47 #include <asm/page.h>
  48 #include <asm/setup.h>
  49 #include <asm/param.h>
  50 #include <asm/traps.h>
  51
  52 #include <platform/hardware.h>
  53
  54 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  55 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
  56 #endif
  57
  58 #ifdef CONFIG_BLK_DEV_FD
  59 extern struct fd_ops no_fd_ops;
  60 struct fd_ops *fd_ops;
  61 #endif
  62
  63 extern struct rtc_ops no_rtc_ops;
  64 struct rtc_ops *rtc_ops;
  65
  66 #ifdef CONFIG_BLK_DEV_INITRD
  67 extern void *initrd_start;
  68 extern void *initrd_end;
  69 int initrd_is_mapped = 0;
  70 extern int initrd_below_start_ok;
  71 #endif
  72
  73 #ifdef CONFIG_OF
  74 extern u32 __dtb_start[];
  75 void *dtb_start = __dtb_start;
  76 #endif
  77
  78 unsigned char aux_device_present;
  79 extern unsigned long loops_per_jiffy;
  80
  81 /* Command line specified as configuration option. */
  82
  83 static char __initdata command_line[COMMAND_LINE_SIZE];
  84
  85 #ifdef CONFIG_CMDLINE_BOOL
  86 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
  87 #endif
  88
  89 sysmem_info_t __initdata sysmem;
  90
  91 #ifdef CONFIG_MMU
  92 extern void init_mmu(void);
  93 #else
  94 static inline void init_mmu(void) { }
  95 #endif
  96
  97 extern int mem_reserve(unsigned long, unsigned long, int);
  98 extern void bootmem_init(void);
  99 extern void zones_init(void);
 100
 101 /*
 102  * Boot parameter parsing.
 103  *
 104  * The Xtensa port uses a list of variable-sized tags to pass data to
 105  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
 106  * to be recognised. The list is terminated with a zero-sized
 107  * BP_TAG_LAST tag.
 108  */
 109
 110 typedef struct tagtable {
 111         u32 tag;
 112         int (*parse)(const bp_tag_t*);
 113 } tagtable_t;
 114
 115 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn           \
 116         __attribute__((used, section(".taglist"))) = { tag, fn }
 117
 118 /* parse current tag */
 119
 120 static int __init add_sysmem_bank(unsigned long type, unsigned long start,
 121                 unsigned long end)
 122 {
 123         if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
 124                 printk(KERN_WARNING
 125                                 "Ignoring memory bank 0x%08lx size %ldKB\n",
 126                                 start, end - start);
 127                 return -EINVAL;
 128         }
 129         sysmem.bank[sysmem.nr_banks].type  = type;
 130         sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(start);
 131         sysmem.bank[sysmem.nr_banks].end   = end & PAGE_MASK;
 132         sysmem.nr_banks++;
 133
 134         return 0;
 135 }
 136
 137 static int __init parse_tag_mem(const bp_tag_t *tag)
 138 {
 139         meminfo_t *mi = (meminfo_t *)(tag->data);
 140
 141         if (mi->type != MEMORY_TYPE_CONVENTIONAL)
 142                 return -1;
 143
 144         return add_sysmem_bank(mi->type, mi->start, mi->end);
 145 }
 146
 147 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
 148
 149 #ifdef CONFIG_BLK_DEV_INITRD
 150
 151 static int __init parse_tag_initrd(const bp_tag_t* tag)
 152 {
 153         meminfo_t* mi;
 154         mi = (meminfo_t*)(tag->data);
 155         initrd_start = __va(mi->start);
 156         initrd_end = __va(mi->end);
 157
 158         return 0;
 159 }
 160
 161 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
 162
 163 #ifdef CONFIG_OF
 164
 165 static int __init parse_tag_fdt(const bp_tag_t *tag)
 166 {
 167         dtb_start = __va(tag->data[0]);
 168         return 0;
 169 }
 170
 171 __tagtable(BP_TAG_FDT, parse_tag_fdt);
 172
 173 void __init early_init_dt_setup_initrd_arch(u64 start, u64 end)
 174 {
 175         initrd_start = (void *)__va(start);
 176         initrd_end = (void *)__va(end);
 177         initrd_below_start_ok = 1;
 178 }
 179
 180 #endif /* CONFIG_OF */
 181
 182 #endif /* CONFIG_BLK_DEV_INITRD */
 183
 184 static int __init parse_tag_cmdline(const bp_tag_t* tag)
 185 {
 186         strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
 187         return 0;
 188 }
 189
 190 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
 191
 192 static int __init parse_bootparam(const bp_tag_t* tag)
 193 {
 194         extern tagtable_t __tagtable_begin, __tagtable_end;
 195         tagtable_t *t;
 196
 197         /* Boot parameters must start with a BP_TAG_FIRST tag. */
 198
 199         if (tag->id != BP_TAG_FIRST) {
 200                 printk(KERN_WARNING "Invalid boot parameters!\n");
 201                 return 0;
 202         }
 203
 204         tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
 205
 206         /* Parse all tags. */
 207
 208         while (tag != NULL && tag->id != BP_TAG_LAST) {
 209                 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
 210                         if (tag->id == t->tag) {
 211                                 t->parse(tag);
 212                                 break;
 213                         }
 214                 }
 215                 if (t == &__tagtable_end)
 216                         printk(KERN_WARNING "Ignoring tag "
 217                                "0x%08x\n", tag->id);
 218                 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
 219         }
 220
 221         return 0;
 222 }
 223
 224 #ifdef CONFIG_OF
 225 bool __initdata dt_memory_scan = false;
 226
 227 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
 228 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
 229 EXPORT_SYMBOL(xtensa_kio_paddr);
 230
 231 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
 232                 int depth, void *data)
 233 {
 234         const __be32 *ranges;
 235         int len;
 236
 237         if (depth > 1)
 238                 return 0;
 239
 240         if (!of_flat_dt_is_compatible(node, "simple-bus"))
 241                 return 0;
 242
 243         ranges = of_get_flat_dt_prop(node, "ranges", &len);
 244         if (!ranges)
 245                 return 1;
 246         if (len == 0)
 247                 return 1;
 248
 249         xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
 250         /* round down to nearest 256MB boundary */
 251         xtensa_kio_paddr &= 0xf0000000;
 252
 253         return 1;
 254 }
 255 #else
 256 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
 257                 int depth, void *data)
 258 {
 259         return 1;
 260 }
 261 #endif
 262
 263 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 264 {
 265         size &= PAGE_MASK;
 266         add_sysmem_bank(MEMORY_TYPE_CONVENTIONAL, base, base + size);
 267 }
 268
 269 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 270 {
 271         return __alloc_bootmem(size, align, 0);
 272 }
 273
 274 void __init early_init_devtree(void *params)
 275 {
 276         /* Setup flat device-tree pointer */
 277         initial_boot_params = params;
 278
 279         /* Retrieve various informations from the /chosen node of the
 280          * device-tree, including the platform type, initrd location and
 281          * size, TCE reserve, and more ...
 282          */
 283         if (!command_line[0])
 284                 of_scan_flat_dt(early_init_dt_scan_chosen, command_line);
 285
 286         /* Scan memory nodes and rebuild MEMBLOCKs */
 287         of_scan_flat_dt(early_init_dt_scan_root, NULL);
 288         if (sysmem.nr_banks == 0)
 289                 of_scan_flat_dt(early_init_dt_scan_memory, NULL);
 290 }
 291
 292 static void __init copy_devtree(void)
 293 {
 294         void *alloc = early_init_dt_alloc_memory_arch(
 295                         be32_to_cpu(initial_boot_params->totalsize), 0);
 296         if (alloc) {
 297                 memcpy(alloc, initial_boot_params,
 298                                 be32_to_cpu(initial_boot_params->totalsize));
 299                 initial_boot_params = alloc;
 300         }
 301 }
 302
 303 static int __init xtensa_device_probe(void)
 304 {
 305         of_platform_populate(NULL, NULL, NULL, NULL);
 306         return 0;
 307 }
 308
 309 device_initcall(xtensa_device_probe);
 310
 311 #endif /* CONFIG_OF */
 312
 313 /*
 314  * Initialize architecture. (Early stage)
 315  */
 316
 317 void __init init_arch(bp_tag_t *bp_start)
 318 {
 319         sysmem.nr_banks = 0;
 320
 321         /* Parse boot parameters */
 322
 323         if (bp_start)
 324                 parse_bootparam(bp_start);
 325
 326 #ifdef CONFIG_OF
 327         early_init_devtree(dtb_start);
 328 #endif
 329
 330         if (sysmem.nr_banks == 0) {
 331                 sysmem.nr_banks = 1;
 332                 sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
 333                 sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
 334                                      + PLATFORM_DEFAULT_MEM_SIZE;
 335         }
 336
 337 #ifdef CONFIG_CMDLINE_BOOL
 338         if (!command_line[0])
 339                 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
 340 #endif
 341
 342         /* Early hook for platforms */
 343
 344         platform_init(bp_start);
 345
 346         /* Initialize MMU. */
 347
 348         init_mmu();
 349 }
 350
 351 /*
 352  * Initialize system. Setup memory and reserve regions.
 353  */
 354
 355 extern char _end;
 356 extern char _stext;
 357 extern char _WindowVectors_text_start;
 358 extern char _WindowVectors_text_end;
 359 extern char _DebugInterruptVector_literal_start;
 360 extern char _DebugInterruptVector_text_end;
 361 extern char _KernelExceptionVector_literal_start;
 362 extern char _KernelExceptionVector_text_end;
 363 extern char _UserExceptionVector_literal_start;
 364 extern char _UserExceptionVector_text_end;
 365 extern char _DoubleExceptionVector_literal_start;
 366 extern char _DoubleExceptionVector_text_end;
 367 #if XCHAL_EXCM_LEVEL >= 2
 368 extern char _Level2InterruptVector_text_start;
 369 extern char _Level2InterruptVector_text_end;
 370 #endif
 371 #if XCHAL_EXCM_LEVEL >= 3
 372 extern char _Level3InterruptVector_text_start;
 373 extern char _Level3InterruptVector_text_end;
 374 #endif
 375 #if XCHAL_EXCM_LEVEL >= 4
 376 extern char _Level4InterruptVector_text_start;
 377 extern char _Level4InterruptVector_text_end;
 378 #endif
 379 #if XCHAL_EXCM_LEVEL >= 5
 380 extern char _Level5InterruptVector_text_start;
 381 extern char _Level5InterruptVector_text_end;
 382 #endif
 383 #if XCHAL_EXCM_LEVEL >= 6
 384 extern char _Level6InterruptVector_text_start;
 385 extern char _Level6InterruptVector_text_end;
 386 #endif
 387
 388
 389
 390 #ifdef CONFIG_S32C1I_SELFTEST
 391 #if XCHAL_HAVE_S32C1I
 392
 393 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
 394
 395 /*
 396  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
 397  *
 398  * If *v == cmp, set *v = set.  Return previous *v.
 399  */
 400 static inline int probed_compare_swap(int *v, int cmp, int set)
 401 {
 402         int tmp;
 403
 404         __asm__ __volatile__(
 405                         "       movi    %1, 1f\n"
 406                         "       s32i    %1, %4, 0\n"
 407                         "       wsr     %2, scompare1\n"
 408                         "1:     s32c1i  %0, %3, 0\n"
 409                         : "=a" (set), "=&a" (tmp)
 410                         : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
 411                         : "memory"
 412                         );
 413         return set;
 414 }
 415
 416 /* Handle probed exception */
 417
 418 void __init do_probed_exception(struct pt_regs *regs, unsigned long exccause)
 419 {
 420         if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
 421                 regs->pc += 3;          /* skip the s32c1i instruction */
 422                 rcw_exc = exccause;
 423         } else {
 424                 do_unhandled(regs, exccause);
 425         }
 426 }
 427
 428 /* Simple test of S32C1I (soc bringup assist) */
 429
 430 void __init check_s32c1i(void)
 431 {
 432         int n, cause1, cause2;
 433         void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
 434
 435         rcw_probe_pc = 0;
 436         handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
 437                         do_probed_exception);
 438         handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
 439                         do_probed_exception);
 440         handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
 441                         do_probed_exception);
 442
 443         /* First try an S32C1I that does not store: */
 444         rcw_exc = 0;
 445         rcw_word = 1;
 446         n = probed_compare_swap(&rcw_word, 0, 2);
 447         cause1 = rcw_exc;
 448
 449         /* took exception? */
 450         if (cause1 != 0) {
 451                 /* unclean exception? */
 452                 if (n != 2 || rcw_word != 1)
 453                         panic("S32C1I exception error");
 454         } else if (rcw_word != 1 || n != 1) {
 455                 panic("S32C1I compare error");
 456         }
 457
 458         /* Then an S32C1I that stores: */
 459         rcw_exc = 0;
 460         rcw_word = 0x1234567;
 461         n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
 462         cause2 = rcw_exc;
 463
 464         if (cause2 != 0) {
 465                 /* unclean exception? */
 466                 if (n != 0xabcde || rcw_word != 0x1234567)
 467                         panic("S32C1I exception error (b)");
 468         } else if (rcw_word != 0xabcde || n != 0x1234567) {
 469                 panic("S32C1I store error");
 470         }
 471
 472         /* Verify consistency of exceptions: */
 473         if (cause1 || cause2) {
 474                 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
 475                 /* If emulation of S32C1I upon bus error gets implemented,
 476                    we can get rid of this panic for single core (not SMP) */
 477                 panic("S32C1I exceptions not currently supported");
 478         }
 479         if (cause1 != cause2)
 480                 panic("inconsistent S32C1I exceptions");
 481
 482         trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
 483         trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
 484         trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
 485 }
 486
 487 #else /* XCHAL_HAVE_S32C1I */
 488
 489 /* This condition should not occur with a commercially deployed processor.
 490    Display reminder for early engr test or demo chips / FPGA bitstreams */
 491 void __init check_s32c1i(void)
 492 {
 493         pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
 494 }
 495
 496 #endif /* XCHAL_HAVE_S32C1I */
 497 #else /* CONFIG_S32C1I_SELFTEST */
 498
 499 void __init check_s32c1i(void)
 500 {
 501 }
 502
 503 #endif /* CONFIG_S32C1I_SELFTEST */
 504
 505
 506 void __init setup_arch(char **cmdline_p)
 507 {
 508         strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
 509         *cmdline_p = command_line;
 510
 511         check_s32c1i();
 512
 513         /* Reserve some memory regions */
 514
 515 #ifdef CONFIG_BLK_DEV_INITRD
 516         if (initrd_start < initrd_end) {
 517                 initrd_is_mapped = mem_reserve(__pa(initrd_start),
 518                                                __pa(initrd_end), 0);
 519                 initrd_below_start_ok = 1;
 520         } else {
 521                 initrd_start = 0;
 522         }
 523 #endif
 524
 525         mem_reserve(__pa(&_stext),__pa(&_end), 1);
 526
 527         mem_reserve(__pa(&_WindowVectors_text_start),
 528                     __pa(&_WindowVectors_text_end), 0);
 529
 530         mem_reserve(__pa(&_DebugInterruptVector_literal_start),
 531                     __pa(&_DebugInterruptVector_text_end), 0);
 532
 533         mem_reserve(__pa(&_KernelExceptionVector_literal_start),
 534                     __pa(&_KernelExceptionVector_text_end), 0);
 535
 536         mem_reserve(__pa(&_UserExceptionVector_literal_start),
 537                     __pa(&_UserExceptionVector_text_end), 0);
 538
 539         mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
 540                     __pa(&_DoubleExceptionVector_text_end), 0);
 541
 542 #if XCHAL_EXCM_LEVEL >= 2
 543         mem_reserve(__pa(&_Level2InterruptVector_text_start),
 544                     __pa(&_Level2InterruptVector_text_end), 0);
 545 #endif
 546 #if XCHAL_EXCM_LEVEL >= 3
 547         mem_reserve(__pa(&_Level3InterruptVector_text_start),
 548                     __pa(&_Level3InterruptVector_text_end), 0);
 549 #endif
 550 #if XCHAL_EXCM_LEVEL >= 4
 551         mem_reserve(__pa(&_Level4InterruptVector_text_start),
 552                     __pa(&_Level4InterruptVector_text_end), 0);
 553 #endif
 554 #if XCHAL_EXCM_LEVEL >= 5
 555         mem_reserve(__pa(&_Level5InterruptVector_text_start),
 556                     __pa(&_Level5InterruptVector_text_end), 0);
 557 #endif
 558 #if XCHAL_EXCM_LEVEL >= 6
 559         mem_reserve(__pa(&_Level6InterruptVector_text_start),
 560                     __pa(&_Level6InterruptVector_text_end), 0);
 561 #endif
 562
 563         bootmem_init();
 564
 565 #ifdef CONFIG_OF
 566         copy_devtree();
 567         unflatten_device_tree();
 568 #endif
 569
 570         platform_setup(cmdline_p);
 571
 572         paging_init();
 573         zones_init();
 574
 575 #ifdef CONFIG_VT
 576 # if defined(CONFIG_VGA_CONSOLE)
 577         conswitchp = &vga_con;
 578 # elif defined(CONFIG_DUMMY_CONSOLE)
 579         conswitchp = &dummy_con;
 580 # endif
 581 #endif
 582
 583 #ifdef CONFIG_PCI
 584         platform_pcibios_init();
 585 #endif
 586 }
 587
 588 void machine_restart(char * cmd)
 589 {
 590         platform_restart();
 591 }
 592
 593 void machine_halt(void)
 594 {
 595         platform_halt();
 596         while (1);
 597 }
 598
 599 void machine_power_off(void)
 600 {
 601         platform_power_off();
 602         while (1);
 603 }
 604 #ifdef CONFIG_PROC_FS
 605
 606 /*
 607  * Display some core information through /proc/cpuinfo.
 608  */
 609
 610 static int
 611 c_show(struct seq_file *f, void *slot)
 612 {
 613         /* high-level stuff */
 614         seq_printf(f,"processor\t: 0\n"
 615                      "vendor_id\t: Tensilica\n"
 616                      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
 617                      "core ID\t\t: " XCHAL_CORE_ID "\n"
 618                      "build ID\t: 0x%x\n"
 619                      "byte order\t: %s\n"
 620                      "cpu MHz\t\t: %lu.%02lu\n"
 621                      "bogomips\t: %lu.%02lu\n",
 622                      XCHAL_BUILD_UNIQUE_ID,
 623                      XCHAL_HAVE_BE ?  "big" : "little",
 624                      CCOUNT_PER_JIFFY/(1000000/HZ),
 625                      (CCOUNT_PER_JIFFY/(10000/HZ)) % 100,
 626                      loops_per_jiffy/(500000/HZ),
 627                      (loops_per_jiffy/(5000/HZ)) % 100);
 628
 629         seq_printf(f,"flags\t\t: "
 630 #if XCHAL_HAVE_NMI
 631                      "nmi "
 632 #endif
 633 #if XCHAL_HAVE_DEBUG
 634                      "debug "
 635 # if XCHAL_HAVE_OCD
 636                      "ocd "
 637 # endif
 638 #endif
 639 #if XCHAL_HAVE_DENSITY
 640                      "density "
 641 #endif
 642 #if XCHAL_HAVE_BOOLEANS
 643                      "boolean "
 644 #endif
 645 #if XCHAL_HAVE_LOOPS
 646                      "loop "
 647 #endif
 648 #if XCHAL_HAVE_NSA
 649                      "nsa "
 650 #endif
 651 #if XCHAL_HAVE_MINMAX
 652                      "minmax "
 653 #endif
 654 #if XCHAL_HAVE_SEXT
 655                      "sext "
 656 #endif
 657 #if XCHAL_HAVE_CLAMPS
 658                      "clamps "
 659 #endif
 660 #if XCHAL_HAVE_MAC16
 661                      "mac16 "
 662 #endif
 663 #if XCHAL_HAVE_MUL16
 664                      "mul16 "
 665 #endif
 666 #if XCHAL_HAVE_MUL32
 667                      "mul32 "
 668 #endif
 669 #if XCHAL_HAVE_MUL32_HIGH
 670                      "mul32h "
 671 #endif
 672 #if XCHAL_HAVE_FP
 673                      "fpu "
 674 #endif
 675 #if XCHAL_HAVE_S32C1I
 676                      "s32c1i "
 677 #endif
 678                      "\n");
 679
 680         /* Registers. */
 681         seq_printf(f,"physical aregs\t: %d\n"
 682                      "misc regs\t: %d\n"
 683                      "ibreak\t\t: %d\n"
 684                      "dbreak\t\t: %d\n",
 685                      XCHAL_NUM_AREGS,
 686                      XCHAL_NUM_MISC_REGS,
 687                      XCHAL_NUM_IBREAK,
 688                      XCHAL_NUM_DBREAK);
 689
 690
 691         /* Interrupt. */
 692         seq_printf(f,"num ints\t: %d\n"
 693                      "ext ints\t: %d\n"
 694                      "int levels\t: %d\n"
 695                      "timers\t\t: %d\n"
 696                      "debug level\t: %d\n",
 697                      XCHAL_NUM_INTERRUPTS,
 698                      XCHAL_NUM_EXTINTERRUPTS,
 699                      XCHAL_NUM_INTLEVELS,
 700                      XCHAL_NUM_TIMERS,
 701                      XCHAL_DEBUGLEVEL);
 702
 703         /* Cache */
 704         seq_printf(f,"icache line size: %d\n"
 705                      "icache ways\t: %d\n"
 706                      "icache size\t: %d\n"
 707                      "icache flags\t: "
 708 #if XCHAL_ICACHE_LINE_LOCKABLE
 709                      "lock "
 710 #endif
 711                      "\n"
 712                      "dcache line size: %d\n"
 713                      "dcache ways\t: %d\n"
 714                      "dcache size\t: %d\n"
 715                      "dcache flags\t: "
 716 #if XCHAL_DCACHE_IS_WRITEBACK
 717                      "writeback "
 718 #endif
 719 #if XCHAL_DCACHE_LINE_LOCKABLE
 720                      "lock "
 721 #endif
 722                      "\n",
 723                      XCHAL_ICACHE_LINESIZE,
 724                      XCHAL_ICACHE_WAYS,
 725                      XCHAL_ICACHE_SIZE,
 726                      XCHAL_DCACHE_LINESIZE,
 727                      XCHAL_DCACHE_WAYS,
 728                      XCHAL_DCACHE_SIZE);
 729
 730         return 0;
 731 }
 732
 733 /*
 734  * We show only CPU #0 info.
 735  */
 736 static void *
 737 c_start(struct seq_file *f, loff_t *pos)
 738 {
 739         return (void *) ((*pos == 0) ? (void *)1 : NULL);
 740 }
 741
 742 static void *
 743 c_next(struct seq_file *f, void *v, loff_t *pos)
 744 {
 745         return NULL;
 746 }
 747
 748 static void
 749 c_stop(struct seq_file *f, void *v)
 750 {
 751 }
 752
 753 const struct seq_operations cpuinfo_op =
 754 {
 755         start:  c_start,
 756         next:   c_next,
 757         stop:   c_stop,
 758         show:   c_show
 759 };
 760
 761 #endif /* CONFIG_PROC_FS */