arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 114 #define KVM_VM_CR0_ALWAYS_ON                                            \
 115         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 116 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 117         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 118          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 119
 120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 122
 123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 124
 125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 126
 127 /*
 128  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 129  * ple_gap:    upper bound on the amount of time between two successive
 130  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 131  *             According to test, this time is usually smaller than 128 cycles.
 132  * ple_window: upper bound on the amount of time a guest is allowed to execute
 133  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 134  *             less than 2^12 cycles
 135  * Time is measured based on a counter that runs at the same rate as the TSC,
 136  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 137  */
 138 #define KVM_VMX_DEFAULT_PLE_GAP           128
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 143                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 144
 145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 146 module_param(ple_gap, int, S_IRUGO);
 147
 148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 149 module_param(ple_window, int, S_IRUGO);
 150
 151 /* Default doubles per-vcpu window every exit. */
 152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 153 module_param(ple_window_grow, int, S_IRUGO);
 154
 155 /* Default resets per-vcpu window every exit to ple_window. */
 156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 157 module_param(ple_window_shrink, int, S_IRUGO);
 158
 159 /* Default is to compute the maximum so we can never overflow. */
 160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 161 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 module_param(ple_window_max, int, S_IRUGO);
 163
 164 extern const ulong vmx_return;
 165
 166 #define NR_AUTOLOAD_MSRS 8
 167 #define VMCS02_POOL_SIZE 1
 168
 169 struct vmcs {
 170         u32 revision_id;
 171         u32 abort;
 172         char data[0];
 173 };
 174
 175 /*
 176  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 177  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 178  * loaded on this CPU (so we can clear them if the CPU goes down).
 179  */
 180 struct loaded_vmcs {
 181         struct vmcs *vmcs;
 182         int cpu;
 183         int launched;
 184         struct list_head loaded_vmcss_on_cpu_link;
 185 };
 186
 187 struct shared_msr_entry {
 188         unsigned index;
 189         u64 data;
 190         u64 mask;
 191 };
 192
 193 /*
 194  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 195  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 196  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 197  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 198  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 199  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 200  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 201  * underlying hardware which will be used to run L2.
 202  * This structure is packed to ensure that its layout is identical across
 203  * machines (necessary for live migration).
 204  * If there are changes in this struct, VMCS12_REVISION must be changed.
 205  */
 206 typedef u64 natural_width;
 207 struct __packed vmcs12 {
 208         /* According to the Intel spec, a VMCS region must start with the
 209          * following two fields. Then follow implementation-specific data.
 210          */
 211         u32 revision_id;
 212         u32 abort;
 213
 214         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 215         u32 padding[7]; /* room for future expansion */
 216
 217         u64 io_bitmap_a;
 218         u64 io_bitmap_b;
 219         u64 msr_bitmap;
 220         u64 vm_exit_msr_store_addr;
 221         u64 vm_exit_msr_load_addr;
 222         u64 vm_entry_msr_load_addr;
 223         u64 tsc_offset;
 224         u64 virtual_apic_page_addr;
 225         u64 apic_access_addr;
 226         u64 posted_intr_desc_addr;
 227         u64 ept_pointer;
 228         u64 eoi_exit_bitmap0;
 229         u64 eoi_exit_bitmap1;
 230         u64 eoi_exit_bitmap2;
 231         u64 eoi_exit_bitmap3;
 232         u64 xss_exit_bitmap;
 233         u64 guest_physical_address;
 234         u64 vmcs_link_pointer;
 235         u64 guest_ia32_debugctl;
 236         u64 guest_ia32_pat;
 237         u64 guest_ia32_efer;
 238         u64 guest_ia32_perf_global_ctrl;
 239         u64 guest_pdptr0;
 240         u64 guest_pdptr1;
 241         u64 guest_pdptr2;
 242         u64 guest_pdptr3;
 243         u64 guest_bndcfgs;
 244         u64 host_ia32_pat;
 245         u64 host_ia32_efer;
 246         u64 host_ia32_perf_global_ctrl;
 247         u64 padding64[8]; /* room for future expansion */
 248         /*
 249          * To allow migration of L1 (complete with its L2 guests) between
 250          * machines of different natural widths (32 or 64 bit), we cannot have
 251          * unsigned long fields with no explict size. We use u64 (aliased
 252          * natural_width) instead. Luckily, x86 is little-endian.
 253          */
 254         natural_width cr0_guest_host_mask;
 255         natural_width cr4_guest_host_mask;
 256         natural_width cr0_read_shadow;
 257         natural_width cr4_read_shadow;
 258         natural_width cr3_target_value0;
 259         natural_width cr3_target_value1;
 260         natural_width cr3_target_value2;
 261         natural_width cr3_target_value3;
 262         natural_width exit_qualification;
 263         natural_width guest_linear_address;
 264         natural_width guest_cr0;
 265         natural_width guest_cr3;
 266         natural_width guest_cr4;
 267         natural_width guest_es_base;
 268         natural_width guest_cs_base;
 269         natural_width guest_ss_base;
 270         natural_width guest_ds_base;
 271         natural_width guest_fs_base;
 272         natural_width guest_gs_base;
 273         natural_width guest_ldtr_base;
 274         natural_width guest_tr_base;
 275         natural_width guest_gdtr_base;
 276         natural_width guest_idtr_base;
 277         natural_width guest_dr7;
 278         natural_width guest_rsp;
 279         natural_width guest_rip;
 280         natural_width guest_rflags;
 281         natural_width guest_pending_dbg_exceptions;
 282         natural_width guest_sysenter_esp;
 283         natural_width guest_sysenter_eip;
 284         natural_width host_cr0;
 285         natural_width host_cr3;
 286         natural_width host_cr4;
 287         natural_width host_fs_base;
 288         natural_width host_gs_base;
 289         natural_width host_tr_base;
 290         natural_width host_gdtr_base;
 291         natural_width host_idtr_base;
 292         natural_width host_ia32_sysenter_esp;
 293         natural_width host_ia32_sysenter_eip;
 294         natural_width host_rsp;
 295         natural_width host_rip;
 296         natural_width paddingl[8]; /* room for future expansion */
 297         u32 pin_based_vm_exec_control;
 298         u32 cpu_based_vm_exec_control;
 299         u32 exception_bitmap;
 300         u32 page_fault_error_code_mask;
 301         u32 page_fault_error_code_match;
 302         u32 cr3_target_count;
 303         u32 vm_exit_controls;
 304         u32 vm_exit_msr_store_count;
 305         u32 vm_exit_msr_load_count;
 306         u32 vm_entry_controls;
 307         u32 vm_entry_msr_load_count;
 308         u32 vm_entry_intr_info_field;
 309         u32 vm_entry_exception_error_code;
 310         u32 vm_entry_instruction_len;
 311         u32 tpr_threshold;
 312         u32 secondary_vm_exec_control;
 313         u32 vm_instruction_error;
 314         u32 vm_exit_reason;
 315         u32 vm_exit_intr_info;
 316         u32 vm_exit_intr_error_code;
 317         u32 idt_vectoring_info_field;
 318         u32 idt_vectoring_error_code;
 319         u32 vm_exit_instruction_len;
 320         u32 vmx_instruction_info;
 321         u32 guest_es_limit;
 322         u32 guest_cs_limit;
 323         u32 guest_ss_limit;
 324         u32 guest_ds_limit;
 325         u32 guest_fs_limit;
 326         u32 guest_gs_limit;
 327         u32 guest_ldtr_limit;
 328         u32 guest_tr_limit;
 329         u32 guest_gdtr_limit;
 330         u32 guest_idtr_limit;
 331         u32 guest_es_ar_bytes;
 332         u32 guest_cs_ar_bytes;
 333         u32 guest_ss_ar_bytes;
 334         u32 guest_ds_ar_bytes;
 335         u32 guest_fs_ar_bytes;
 336         u32 guest_gs_ar_bytes;
 337         u32 guest_ldtr_ar_bytes;
 338         u32 guest_tr_ar_bytes;
 339         u32 guest_interruptibility_info;
 340         u32 guest_activity_state;
 341         u32 guest_sysenter_cs;
 342         u32 host_ia32_sysenter_cs;
 343         u32 vmx_preemption_timer_value;
 344         u32 padding32[7]; /* room for future expansion */
 345         u16 virtual_processor_id;
 346         u16 posted_intr_nv;
 347         u16 guest_es_selector;
 348         u16 guest_cs_selector;
 349         u16 guest_ss_selector;
 350         u16 guest_ds_selector;
 351         u16 guest_fs_selector;
 352         u16 guest_gs_selector;
 353         u16 guest_ldtr_selector;
 354         u16 guest_tr_selector;
 355         u16 guest_intr_status;
 356         u16 host_es_selector;
 357         u16 host_cs_selector;
 358         u16 host_ss_selector;
 359         u16 host_ds_selector;
 360         u16 host_fs_selector;
 361         u16 host_gs_selector;
 362         u16 host_tr_selector;
 363 };
 364
 365 /*
 366  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 367  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 368  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 369  */
 370 #define VMCS12_REVISION 0x11e57ed0
 371
 372 /*
 373  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 374  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 375  * current implementation, 4K are reserved to avoid future complications.
 376  */
 377 #define VMCS12_SIZE 0x1000
 378
 379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 380 struct vmcs02_list {
 381         struct list_head list;
 382         gpa_t vmptr;
 383         struct loaded_vmcs vmcs02;
 384 };
 385
 386 /*
 387  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 388  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 389  */
 390 struct nested_vmx {
 391         /* Has the level1 guest done vmxon? */
 392         bool vmxon;
 393         gpa_t vmxon_ptr;
 394
 395         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 396         gpa_t current_vmptr;
 397         /* The host-usable pointer to the above */
 398         struct page *current_vmcs12_page;
 399         struct vmcs12 *current_vmcs12;
 400         struct vmcs *current_shadow_vmcs;
 401         /*
 402          * Indicates if the shadow vmcs must be updated with the
 403          * data hold by vmcs12
 404          */
 405         bool sync_shadow_vmcs;
 406
 407         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 408         struct list_head vmcs02_pool;
 409         int vmcs02_num;
 410         u64 vmcs01_tsc_offset;
 411         bool change_vmcs01_virtual_x2apic_mode;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601 };
 602
 603 enum segment_cache_field {
 604         SEG_FIELD_SEL = 0,
 605         SEG_FIELD_BASE = 1,
 606         SEG_FIELD_LIMIT = 2,
 607         SEG_FIELD_AR = 3,
 608
 609         SEG_FIELD_NR = 4
 610 };
 611
 612 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 613 {
 614         return container_of(vcpu, struct vcpu_vmx, vcpu);
 615 }
 616
 617 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 618 {
 619         return &(to_vmx(vcpu)->pi_desc);
 620 }
 621
 622 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 623 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 624 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 625                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 626
 627
 628 static unsigned long shadow_read_only_fields[] = {
 629         /*
 630          * We do NOT shadow fields that are modified when L0
 631          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 632          * VMXON...) executed by L1.
 633          * For example, VM_INSTRUCTION_ERROR is read
 634          * by L1 if a vmx instruction fails (part of the error path).
 635          * Note the code assumes this logic. If for some reason
 636          * we start shadowing these fields then we need to
 637          * force a shadow sync when L0 emulates vmx instructions
 638          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 639          * by nested_vmx_failValid)
 640          */
 641         VM_EXIT_REASON,
 642         VM_EXIT_INTR_INFO,
 643         VM_EXIT_INSTRUCTION_LEN,
 644         IDT_VECTORING_INFO_FIELD,
 645         IDT_VECTORING_ERROR_CODE,
 646         VM_EXIT_INTR_ERROR_CODE,
 647         EXIT_QUALIFICATION,
 648         GUEST_LINEAR_ADDRESS,
 649         GUEST_PHYSICAL_ADDRESS
 650 };
 651 static int max_shadow_read_only_fields =
 652         ARRAY_SIZE(shadow_read_only_fields);
 653
 654 static unsigned long shadow_read_write_fields[] = {
 655         TPR_THRESHOLD,
 656         GUEST_RIP,
 657         GUEST_RSP,
 658         GUEST_CR0,
 659         GUEST_CR3,
 660         GUEST_CR4,
 661         GUEST_INTERRUPTIBILITY_INFO,
 662         GUEST_RFLAGS,
 663         GUEST_CS_SELECTOR,
 664         GUEST_CS_AR_BYTES,
 665         GUEST_CS_LIMIT,
 666         GUEST_CS_BASE,
 667         GUEST_ES_BASE,
 668         GUEST_BNDCFGS,
 669         CR0_GUEST_HOST_MASK,
 670         CR0_READ_SHADOW,
 671         CR4_READ_SHADOW,
 672         TSC_OFFSET,
 673         EXCEPTION_BITMAP,
 674         CPU_BASED_VM_EXEC_CONTROL,
 675         VM_ENTRY_EXCEPTION_ERROR_CODE,
 676         VM_ENTRY_INTR_INFO_FIELD,
 677         VM_ENTRY_INSTRUCTION_LEN,
 678         VM_ENTRY_EXCEPTION_ERROR_CODE,
 679         HOST_FS_BASE,
 680         HOST_GS_BASE,
 681         HOST_FS_SELECTOR,
 682         HOST_GS_SELECTOR
 683 };
 684 static int max_shadow_read_write_fields =
 685         ARRAY_SIZE(shadow_read_write_fields);
 686
 687 static const unsigned short vmcs_field_to_offset_table[] = {
 688         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 689         FIELD(POSTED_INTR_NV, posted_intr_nv),
 690         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 691         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 692         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 693         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 694         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 695         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 696         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 697         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 698         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 699         FIELD(HOST_ES_SELECTOR, host_es_selector),
 700         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 701         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 702         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 703         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 704         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 705         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 706         FIELD64(IO_BITMAP_A, io_bitmap_a),
 707         FIELD64(IO_BITMAP_B, io_bitmap_b),
 708         FIELD64(MSR_BITMAP, msr_bitmap),
 709         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 710         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 711         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 712         FIELD64(TSC_OFFSET, tsc_offset),
 713         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 714         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 715         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 716         FIELD64(EPT_POINTER, ept_pointer),
 717         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 718         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 719         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 720         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 721         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 722         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 723         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 724         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 725         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 726         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 727         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 728         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 729         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 730         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 731         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 732         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 733         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 734         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 735         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 736         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 737         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 738         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 740         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 741         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 742         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 743         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 744         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 745         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 746         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 747         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 748         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 749         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 750         FIELD(TPR_THRESHOLD, tpr_threshold),
 751         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 752         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 753         FIELD(VM_EXIT_REASON, vm_exit_reason),
 754         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 755         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 756         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 757         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 758         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 759         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 760         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 761         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 762         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 763         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 764         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 765         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 766         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 767         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 768         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 769         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 770         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 771         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 772         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 773         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 774         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 775         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 776         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 777         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 778         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 779         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 780         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 781         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 782         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 783         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 784         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 785         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 786         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 787         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 788         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 789         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 790         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 791         FIELD(EXIT_QUALIFICATION, exit_qualification),
 792         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 793         FIELD(GUEST_CR0, guest_cr0),
 794         FIELD(GUEST_CR3, guest_cr3),
 795         FIELD(GUEST_CR4, guest_cr4),
 796         FIELD(GUEST_ES_BASE, guest_es_base),
 797         FIELD(GUEST_CS_BASE, guest_cs_base),
 798         FIELD(GUEST_SS_BASE, guest_ss_base),
 799         FIELD(GUEST_DS_BASE, guest_ds_base),
 800         FIELD(GUEST_FS_BASE, guest_fs_base),
 801         FIELD(GUEST_GS_BASE, guest_gs_base),
 802         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 803         FIELD(GUEST_TR_BASE, guest_tr_base),
 804         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 805         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 806         FIELD(GUEST_DR7, guest_dr7),
 807         FIELD(GUEST_RSP, guest_rsp),
 808         FIELD(GUEST_RIP, guest_rip),
 809         FIELD(GUEST_RFLAGS, guest_rflags),
 810         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 811         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 812         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 813         FIELD(HOST_CR0, host_cr0),
 814         FIELD(HOST_CR3, host_cr3),
 815         FIELD(HOST_CR4, host_cr4),
 816         FIELD(HOST_FS_BASE, host_fs_base),
 817         FIELD(HOST_GS_BASE, host_gs_base),
 818         FIELD(HOST_TR_BASE, host_tr_base),
 819         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 820         FIELD(HOST_IDTR_BASE, host_idtr_base),
 821         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 822         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 823         FIELD(HOST_RSP, host_rsp),
 824         FIELD(HOST_RIP, host_rip),
 825 };
 826
 827 static inline short vmcs_field_to_offset(unsigned long field)
 828 {
 829         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 830
 831         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 832             vmcs_field_to_offset_table[field] == 0)
 833                 return -ENOENT;
 834
 835         return vmcs_field_to_offset_table[field];
 836 }
 837
 838 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 839 {
 840         return to_vmx(vcpu)->nested.current_vmcs12;
 841 }
 842
 843 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 844 {
 845         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 846         if (is_error_page(page))
 847                 return NULL;
 848
 849         return page;
 850 }
 851
 852 static void nested_release_page(struct page *page)
 853 {
 854         kvm_release_page_dirty(page);
 855 }
 856
 857 static void nested_release_page_clean(struct page *page)
 858 {
 859         kvm_release_page_clean(page);
 860 }
 861
 862 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 863 static u64 construct_eptp(unsigned long root_hpa);
 864 static void kvm_cpu_vmxon(u64 addr);
 865 static void kvm_cpu_vmxoff(void);
 866 static bool vmx_mpx_supported(void);
 867 static bool vmx_xsaves_supported(void);
 868 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 869 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 870 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 871                             struct kvm_segment *var, int seg);
 872 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 873                             struct kvm_segment *var, int seg);
 874 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 875 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 876 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 877 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 878 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 879 static int alloc_identity_pagetable(struct kvm *kvm);
 880
 881 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 882 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 883 /*
 884  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 885  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 886  */
 887 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 888 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 889
 890 /*
 891  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 892  * can find which vCPU should be waken up.
 893  */
 894 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 895 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 896
 897 static unsigned long *vmx_io_bitmap_a;
 898 static unsigned long *vmx_io_bitmap_b;
 899 static unsigned long *vmx_msr_bitmap_legacy;
 900 static unsigned long *vmx_msr_bitmap_longmode;
 901 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 902 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 903 static unsigned long *vmx_msr_bitmap_nested;
 904 static unsigned long *vmx_vmread_bitmap;
 905 static unsigned long *vmx_vmwrite_bitmap;
 906
 907 static bool cpu_has_load_ia32_efer;
 908 static bool cpu_has_load_perf_global_ctrl;
 909
 910 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 911 static DEFINE_SPINLOCK(vmx_vpid_lock);
 912
 913 static struct vmcs_config {
 914         int size;
 915         int order;
 916         u32 revision_id;
 917         u32 pin_based_exec_ctrl;
 918         u32 cpu_based_exec_ctrl;
 919         u32 cpu_based_2nd_exec_ctrl;
 920         u32 vmexit_ctrl;
 921         u32 vmentry_ctrl;
 922 } vmcs_config;
 923
 924 static struct vmx_capability {
 925         u32 ept;
 926         u32 vpid;
 927 } vmx_capability;
 928
 929 #define VMX_SEGMENT_FIELD(seg)                                  \
 930         [VCPU_SREG_##seg] = {                                   \
 931                 .selector = GUEST_##seg##_SELECTOR,             \
 932                 .base = GUEST_##seg##_BASE,                     \
 933                 .limit = GUEST_##seg##_LIMIT,                   \
 934                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 935         }
 936
 937 static const struct kvm_vmx_segment_field {
 938         unsigned selector;
 939         unsigned base;
 940         unsigned limit;
 941         unsigned ar_bytes;
 942 } kvm_vmx_segment_fields[] = {
 943         VMX_SEGMENT_FIELD(CS),
 944         VMX_SEGMENT_FIELD(DS),
 945         VMX_SEGMENT_FIELD(ES),
 946         VMX_SEGMENT_FIELD(FS),
 947         VMX_SEGMENT_FIELD(GS),
 948         VMX_SEGMENT_FIELD(SS),
 949         VMX_SEGMENT_FIELD(TR),
 950         VMX_SEGMENT_FIELD(LDTR),
 951 };
 952
 953 static u64 host_efer;
 954
 955 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 956
 957 /*
 958  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 959  * away by decrementing the array size.
 960  */
 961 static const u32 vmx_msr_index[] = {
 962 #ifdef CONFIG_X86_64
 963         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 964 #endif
 965         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 966 };
 967
 968 static inline bool is_page_fault(u32 intr_info)
 969 {
 970         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 971                              INTR_INFO_VALID_MASK)) ==
 972                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 973 }
 974
 975 static inline bool is_no_device(u32 intr_info)
 976 {
 977         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 978                              INTR_INFO_VALID_MASK)) ==
 979                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 980 }
 981
 982 static inline bool is_invalid_opcode(u32 intr_info)
 983 {
 984         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 985                              INTR_INFO_VALID_MASK)) ==
 986                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 987 }
 988
 989 static inline bool is_external_interrupt(u32 intr_info)
 990 {
 991         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 992                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 993 }
 994
 995 static inline bool is_machine_check(u32 intr_info)
 996 {
 997         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 998                              INTR_INFO_VALID_MASK)) ==
 999                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1000 }
1001
1002 static inline bool cpu_has_vmx_msr_bitmap(void)
1003 {
1004         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1005 }
1006
1007 static inline bool cpu_has_vmx_tpr_shadow(void)
1008 {
1009         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1010 }
1011
1012 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1013 {
1014         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1015 }
1016
1017 static inline bool cpu_has_secondary_exec_ctrls(void)
1018 {
1019         return vmcs_config.cpu_based_exec_ctrl &
1020                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1021 }
1022
1023 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1027 }
1028
1029 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1030 {
1031         return vmcs_config.cpu_based_2nd_exec_ctrl &
1032                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1033 }
1034
1035 static inline bool cpu_has_vmx_apic_register_virt(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1039 }
1040
1041 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1042 {
1043         return vmcs_config.cpu_based_2nd_exec_ctrl &
1044                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1045 }
1046
1047 static inline bool cpu_has_vmx_posted_intr(void)
1048 {
1049         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1050                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1051 }
1052
1053 static inline bool cpu_has_vmx_apicv(void)
1054 {
1055         return cpu_has_vmx_apic_register_virt() &&
1056                 cpu_has_vmx_virtual_intr_delivery() &&
1057                 cpu_has_vmx_posted_intr();
1058 }
1059
1060 static inline bool cpu_has_vmx_flexpriority(void)
1061 {
1062         return cpu_has_vmx_tpr_shadow() &&
1063                 cpu_has_vmx_virtualize_apic_accesses();
1064 }
1065
1066 static inline bool cpu_has_vmx_ept_execute_only(void)
1067 {
1068         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1069 }
1070
1071 static inline bool cpu_has_vmx_ept_2m_page(void)
1072 {
1073         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1074 }
1075
1076 static inline bool cpu_has_vmx_ept_1g_page(void)
1077 {
1078         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1079 }
1080
1081 static inline bool cpu_has_vmx_ept_4levels(void)
1082 {
1083         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1084 }
1085
1086 static inline bool cpu_has_vmx_ept_ad_bits(void)
1087 {
1088         return vmx_capability.ept & VMX_EPT_AD_BIT;
1089 }
1090
1091 static inline bool cpu_has_vmx_invept_context(void)
1092 {
1093         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1094 }
1095
1096 static inline bool cpu_has_vmx_invept_global(void)
1097 {
1098         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1099 }
1100
1101 static inline bool cpu_has_vmx_invvpid_single(void)
1102 {
1103         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1104 }
1105
1106 static inline bool cpu_has_vmx_invvpid_global(void)
1107 {
1108         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1109 }
1110
1111 static inline bool cpu_has_vmx_ept(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl &
1114                 SECONDARY_EXEC_ENABLE_EPT;
1115 }
1116
1117 static inline bool cpu_has_vmx_unrestricted_guest(void)
1118 {
1119         return vmcs_config.cpu_based_2nd_exec_ctrl &
1120                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1121 }
1122
1123 static inline bool cpu_has_vmx_ple(void)
1124 {
1125         return vmcs_config.cpu_based_2nd_exec_ctrl &
1126                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1127 }
1128
1129 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1130 {
1131         return flexpriority_enabled && lapic_in_kernel(vcpu);
1132 }
1133
1134 static inline bool cpu_has_vmx_vpid(void)
1135 {
1136         return vmcs_config.cpu_based_2nd_exec_ctrl &
1137                 SECONDARY_EXEC_ENABLE_VPID;
1138 }
1139
1140 static inline bool cpu_has_vmx_rdtscp(void)
1141 {
1142         return vmcs_config.cpu_based_2nd_exec_ctrl &
1143                 SECONDARY_EXEC_RDTSCP;
1144 }
1145
1146 static inline bool cpu_has_vmx_invpcid(void)
1147 {
1148         return vmcs_config.cpu_based_2nd_exec_ctrl &
1149                 SECONDARY_EXEC_ENABLE_INVPCID;
1150 }
1151
1152 static inline bool cpu_has_virtual_nmis(void)
1153 {
1154         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1155 }
1156
1157 static inline bool cpu_has_vmx_wbinvd_exit(void)
1158 {
1159         return vmcs_config.cpu_based_2nd_exec_ctrl &
1160                 SECONDARY_EXEC_WBINVD_EXITING;
1161 }
1162
1163 static inline bool cpu_has_vmx_shadow_vmcs(void)
1164 {
1165         u64 vmx_msr;
1166         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1167         /* check if the cpu supports writing r/o exit information fields */
1168         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1169                 return false;
1170
1171         return vmcs_config.cpu_based_2nd_exec_ctrl &
1172                 SECONDARY_EXEC_SHADOW_VMCS;
1173 }
1174
1175 static inline bool cpu_has_vmx_pml(void)
1176 {
1177         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1178 }
1179
1180 static inline bool cpu_has_vmx_tsc_scaling(void)
1181 {
1182         return vmcs_config.cpu_based_2nd_exec_ctrl &
1183                 SECONDARY_EXEC_TSC_SCALING;
1184 }
1185
1186 static inline bool report_flexpriority(void)
1187 {
1188         return flexpriority_enabled;
1189 }
1190
1191 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1192 {
1193         return vmcs12->cpu_based_vm_exec_control & bit;
1194 }
1195
1196 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1197 {
1198         return (vmcs12->cpu_based_vm_exec_control &
1199                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1200                 (vmcs12->secondary_vm_exec_control & bit);
1201 }
1202
1203 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1204 {
1205         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1206 }
1207
1208 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1209 {
1210         return vmcs12->pin_based_vm_exec_control &
1211                 PIN_BASED_VMX_PREEMPTION_TIMER;
1212 }
1213
1214 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1215 {
1216         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1217 }
1218
1219 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1220 {
1221         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1222                 vmx_xsaves_supported();
1223 }
1224
1225 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1226 {
1227         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1228 }
1229
1230 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1231 {
1232         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1233 }
1234
1235 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1236 {
1237         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1238 }
1239
1240 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1241 {
1242         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1243 }
1244
1245 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1246 {
1247         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1248 }
1249
1250 static inline bool is_nmi(u32 intr_info)
1251 {
1252         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1253                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1254 }
1255
1256 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1257                               u32 exit_intr_info,
1258                               unsigned long exit_qualification);
1259 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1260                         struct vmcs12 *vmcs12,
1261                         u32 reason, unsigned long qualification);
1262
1263 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1264 {
1265         int i;
1266
1267         for (i = 0; i < vmx->nmsrs; ++i)
1268                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1269                         return i;
1270         return -1;
1271 }
1272
1273 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1274 {
1275     struct {
1276         u64 vpid : 16;
1277         u64 rsvd : 48;
1278         u64 gva;
1279     } operand = { vpid, 0, gva };
1280
1281     asm volatile (__ex(ASM_VMX_INVVPID)
1282                   /* CF==1 or ZF==1 --> rc = -1 */
1283                   "; ja 1f ; ud2 ; 1:"
1284                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1285 }
1286
1287 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1288 {
1289         struct {
1290                 u64 eptp, gpa;
1291         } operand = {eptp, gpa};
1292
1293         asm volatile (__ex(ASM_VMX_INVEPT)
1294                         /* CF==1 or ZF==1 --> rc = -1 */
1295                         "; ja 1f ; ud2 ; 1:\n"
1296                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1297 }
1298
1299 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1300 {
1301         int i;
1302
1303         i = __find_msr_index(vmx, msr);
1304         if (i >= 0)
1305                 return &vmx->guest_msrs[i];
1306         return NULL;
1307 }
1308
1309 static void vmcs_clear(struct vmcs *vmcs)
1310 {
1311         u64 phys_addr = __pa(vmcs);
1312         u8 error;
1313
1314         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1315                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1316                       : "cc", "memory");
1317         if (error)
1318                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1319                        vmcs, phys_addr);
1320 }
1321
1322 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1323 {
1324         vmcs_clear(loaded_vmcs->vmcs);
1325         loaded_vmcs->cpu = -1;
1326         loaded_vmcs->launched = 0;
1327 }
1328
1329 static void vmcs_load(struct vmcs *vmcs)
1330 {
1331         u64 phys_addr = __pa(vmcs);
1332         u8 error;
1333
1334         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1335                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1336                         : "cc", "memory");
1337         if (error)
1338                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1339                        vmcs, phys_addr);
1340 }
1341
1342 #ifdef CONFIG_KEXEC_CORE
1343 /*
1344  * This bitmap is used to indicate whether the vmclear
1345  * operation is enabled on all cpus. All disabled by
1346  * default.
1347  */
1348 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1349
1350 static inline void crash_enable_local_vmclear(int cpu)
1351 {
1352         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1353 }
1354
1355 static inline void crash_disable_local_vmclear(int cpu)
1356 {
1357         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1358 }
1359
1360 static inline int crash_local_vmclear_enabled(int cpu)
1361 {
1362         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1363 }
1364
1365 static void crash_vmclear_local_loaded_vmcss(void)
1366 {
1367         int cpu = raw_smp_processor_id();
1368         struct loaded_vmcs *v;
1369
1370         if (!crash_local_vmclear_enabled(cpu))
1371                 return;
1372
1373         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1374                             loaded_vmcss_on_cpu_link)
1375                 vmcs_clear(v->vmcs);
1376 }
1377 #else
1378 static inline void crash_enable_local_vmclear(int cpu) { }
1379 static inline void crash_disable_local_vmclear(int cpu) { }
1380 #endif /* CONFIG_KEXEC_CORE */
1381
1382 static void __loaded_vmcs_clear(void *arg)
1383 {
1384         struct loaded_vmcs *loaded_vmcs = arg;
1385         int cpu = raw_smp_processor_id();
1386
1387         if (loaded_vmcs->cpu != cpu)
1388                 return; /* vcpu migration can race with cpu offline */
1389         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1390                 per_cpu(current_vmcs, cpu) = NULL;
1391         crash_disable_local_vmclear(cpu);
1392         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1393
1394         /*
1395          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1396          * is before setting loaded_vmcs->vcpu to -1 which is done in
1397          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1398          * then adds the vmcs into percpu list before it is deleted.
1399          */
1400         smp_wmb();
1401
1402         loaded_vmcs_init(loaded_vmcs);
1403         crash_enable_local_vmclear(cpu);
1404 }
1405
1406 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1407 {
1408         int cpu = loaded_vmcs->cpu;
1409
1410         if (cpu != -1)
1411                 smp_call_function_single(cpu,
1412                          __loaded_vmcs_clear, loaded_vmcs, 1);
1413 }
1414
1415 static inline void vpid_sync_vcpu_single(int vpid)
1416 {
1417         if (vpid == 0)
1418                 return;
1419
1420         if (cpu_has_vmx_invvpid_single())
1421                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1422 }
1423
1424 static inline void vpid_sync_vcpu_global(void)
1425 {
1426         if (cpu_has_vmx_invvpid_global())
1427                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1428 }
1429
1430 static inline void vpid_sync_context(int vpid)
1431 {
1432         if (cpu_has_vmx_invvpid_single())
1433                 vpid_sync_vcpu_single(vpid);
1434         else
1435                 vpid_sync_vcpu_global();
1436 }
1437
1438 static inline void ept_sync_global(void)
1439 {
1440         if (cpu_has_vmx_invept_global())
1441                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1442 }
1443
1444 static inline void ept_sync_context(u64 eptp)
1445 {
1446         if (enable_ept) {
1447                 if (cpu_has_vmx_invept_context())
1448                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1449                 else
1450                         ept_sync_global();
1451         }
1452 }
1453
1454 static __always_inline unsigned long vmcs_readl(unsigned long field)
1455 {
1456         unsigned long value;
1457
1458         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1459                       : "=a"(value) : "d"(field) : "cc");
1460         return value;
1461 }
1462
1463 static __always_inline u16 vmcs_read16(unsigned long field)
1464 {
1465         return vmcs_readl(field);
1466 }
1467
1468 static __always_inline u32 vmcs_read32(unsigned long field)
1469 {
1470         return vmcs_readl(field);
1471 }
1472
1473 static __always_inline u64 vmcs_read64(unsigned long field)
1474 {
1475 #ifdef CONFIG_X86_64
1476         return vmcs_readl(field);
1477 #else
1478         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1479 #endif
1480 }
1481
1482 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1483 {
1484         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1485                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1486         dump_stack();
1487 }
1488
1489 static void vmcs_writel(unsigned long field, unsigned long value)
1490 {
1491         u8 error;
1492
1493         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1494                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1495         if (unlikely(error))
1496                 vmwrite_error(field, value);
1497 }
1498
1499 static void vmcs_write16(unsigned long field, u16 value)
1500 {
1501         vmcs_writel(field, value);
1502 }
1503
1504 static void vmcs_write32(unsigned long field, u32 value)
1505 {
1506         vmcs_writel(field, value);
1507 }
1508
1509 static void vmcs_write64(unsigned long field, u64 value)
1510 {
1511         vmcs_writel(field, value);
1512 #ifndef CONFIG_X86_64
1513         asm volatile ("");
1514         vmcs_writel(field+1, value >> 32);
1515 #endif
1516 }
1517
1518 static void vmcs_clear_bits(unsigned long field, u32 mask)
1519 {
1520         vmcs_writel(field, vmcs_readl(field) & ~mask);
1521 }
1522
1523 static void vmcs_set_bits(unsigned long field, u32 mask)
1524 {
1525         vmcs_writel(field, vmcs_readl(field) | mask);
1526 }
1527
1528 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1529 {
1530         vmcs_write32(VM_ENTRY_CONTROLS, val);
1531         vmx->vm_entry_controls_shadow = val;
1532 }
1533
1534 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1535 {
1536         if (vmx->vm_entry_controls_shadow != val)
1537                 vm_entry_controls_init(vmx, val);
1538 }
1539
1540 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1541 {
1542         return vmx->vm_entry_controls_shadow;
1543 }
1544
1545
1546 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1547 {
1548         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1549 }
1550
1551 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1552 {
1553         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1554 }
1555
1556 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1557 {
1558         vmcs_write32(VM_EXIT_CONTROLS, val);
1559         vmx->vm_exit_controls_shadow = val;
1560 }
1561
1562 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1563 {
1564         if (vmx->vm_exit_controls_shadow != val)
1565                 vm_exit_controls_init(vmx, val);
1566 }
1567
1568 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1569 {
1570         return vmx->vm_exit_controls_shadow;
1571 }
1572
1573
1574 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1575 {
1576         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1577 }
1578
1579 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1580 {
1581         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1582 }
1583
1584 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1585 {
1586         vmx->segment_cache.bitmask = 0;
1587 }
1588
1589 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1590                                        unsigned field)
1591 {
1592         bool ret;
1593         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1594
1595         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1596                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1597                 vmx->segment_cache.bitmask = 0;
1598         }
1599         ret = vmx->segment_cache.bitmask & mask;
1600         vmx->segment_cache.bitmask |= mask;
1601         return ret;
1602 }
1603
1604 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1605 {
1606         u16 *p = &vmx->segment_cache.seg[seg].selector;
1607
1608         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1609                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1610         return *p;
1611 }
1612
1613 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1614 {
1615         ulong *p = &vmx->segment_cache.seg[seg].base;
1616
1617         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1618                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1619         return *p;
1620 }
1621
1622 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1623 {
1624         u32 *p = &vmx->segment_cache.seg[seg].limit;
1625
1626         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1627                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1628         return *p;
1629 }
1630
1631 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1632 {
1633         u32 *p = &vmx->segment_cache.seg[seg].ar;
1634
1635         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1636                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1637         return *p;
1638 }
1639
1640 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1641 {
1642         u32 eb;
1643
1644         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1645              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1646         if ((vcpu->guest_debug &
1647              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1648             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1649                 eb |= 1u << BP_VECTOR;
1650         if (to_vmx(vcpu)->rmode.vm86_active)
1651                 eb = ~0;
1652         if (enable_ept)
1653                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1654         if (vcpu->fpu_active)
1655                 eb &= ~(1u << NM_VECTOR);
1656
1657         /* When we are running a nested L2 guest and L1 specified for it a
1658          * certain exception bitmap, we must trap the same exceptions and pass
1659          * them to L1. When running L2, we will only handle the exceptions
1660          * specified above if L1 did not want them.
1661          */
1662         if (is_guest_mode(vcpu))
1663                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1664
1665         vmcs_write32(EXCEPTION_BITMAP, eb);
1666 }
1667
1668 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1669                 unsigned long entry, unsigned long exit)
1670 {
1671         vm_entry_controls_clearbit(vmx, entry);
1672         vm_exit_controls_clearbit(vmx, exit);
1673 }
1674
1675 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1676 {
1677         unsigned i;
1678         struct msr_autoload *m = &vmx->msr_autoload;
1679
1680         switch (msr) {
1681         case MSR_EFER:
1682                 if (cpu_has_load_ia32_efer) {
1683                         clear_atomic_switch_msr_special(vmx,
1684                                         VM_ENTRY_LOAD_IA32_EFER,
1685                                         VM_EXIT_LOAD_IA32_EFER);
1686                         return;
1687                 }
1688                 break;
1689         case MSR_CORE_PERF_GLOBAL_CTRL:
1690                 if (cpu_has_load_perf_global_ctrl) {
1691                         clear_atomic_switch_msr_special(vmx,
1692                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1693                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1694                         return;
1695                 }
1696                 break;
1697         }
1698
1699         for (i = 0; i < m->nr; ++i)
1700                 if (m->guest[i].index == msr)
1701                         break;
1702
1703         if (i == m->nr)
1704                 return;
1705         --m->nr;
1706         m->guest[i] = m->guest[m->nr];
1707         m->host[i] = m->host[m->nr];
1708         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1709         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1710 }
1711
1712 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1713                 unsigned long entry, unsigned long exit,
1714                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1715                 u64 guest_val, u64 host_val)
1716 {
1717         vmcs_write64(guest_val_vmcs, guest_val);
1718         vmcs_write64(host_val_vmcs, host_val);
1719         vm_entry_controls_setbit(vmx, entry);
1720         vm_exit_controls_setbit(vmx, exit);
1721 }
1722
1723 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1724                                   u64 guest_val, u64 host_val)
1725 {
1726         unsigned i;
1727         struct msr_autoload *m = &vmx->msr_autoload;
1728
1729         switch (msr) {
1730         case MSR_EFER:
1731                 if (cpu_has_load_ia32_efer) {
1732                         add_atomic_switch_msr_special(vmx,
1733                                         VM_ENTRY_LOAD_IA32_EFER,
1734                                         VM_EXIT_LOAD_IA32_EFER,
1735                                         GUEST_IA32_EFER,
1736                                         HOST_IA32_EFER,
1737                                         guest_val, host_val);
1738                         return;
1739                 }
1740                 break;
1741         case MSR_CORE_PERF_GLOBAL_CTRL:
1742                 if (cpu_has_load_perf_global_ctrl) {
1743                         add_atomic_switch_msr_special(vmx,
1744                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1745                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1746                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1747                                         HOST_IA32_PERF_GLOBAL_CTRL,
1748                                         guest_val, host_val);
1749                         return;
1750                 }
1751                 break;
1752         case MSR_IA32_PEBS_ENABLE:
1753                 /* PEBS needs a quiescent period after being disabled (to write
1754                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1755                  * provide that period, so a CPU could write host's record into
1756                  * guest's memory.
1757                  */
1758                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1759         }
1760
1761         for (i = 0; i < m->nr; ++i)
1762                 if (m->guest[i].index == msr)
1763                         break;
1764
1765         if (i == NR_AUTOLOAD_MSRS) {
1766                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1767                                 "Can't add msr %x\n", msr);
1768                 return;
1769         } else if (i == m->nr) {
1770                 ++m->nr;
1771                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1772                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1773         }
1774
1775         m->guest[i].index = msr;
1776         m->guest[i].value = guest_val;
1777         m->host[i].index = msr;
1778         m->host[i].value = host_val;
1779 }
1780
1781 static void reload_tss(void)
1782 {
1783         /*
1784          * VT restores TR but not its size.  Useless.
1785          */
1786         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1787         struct desc_struct *descs;
1788
1789         descs = (void *)gdt->address;
1790         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1791         load_TR_desc();
1792 }
1793
1794 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1795 {
1796         u64 guest_efer = vmx->vcpu.arch.efer;
1797         u64 ignore_bits = 0;
1798
1799         if (!enable_ept) {
1800                 /*
1801                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1802                  * host CPUID is more efficient than testing guest CPUID
1803                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1804                  */
1805                 if (boot_cpu_has(X86_FEATURE_SMEP))
1806                         guest_efer |= EFER_NX;
1807                 else if (!(guest_efer & EFER_NX))
1808                         ignore_bits |= EFER_NX;
1809         }
1810
1811         /*
1812          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1813          */
1814         ignore_bits |= EFER_SCE;
1815 #ifdef CONFIG_X86_64
1816         ignore_bits |= EFER_LMA | EFER_LME;
1817         /* SCE is meaningful only in long mode on Intel */
1818         if (guest_efer & EFER_LMA)
1819                 ignore_bits &= ~(u64)EFER_SCE;
1820 #endif
1821
1822         clear_atomic_switch_msr(vmx, MSR_EFER);
1823
1824         /*
1825          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1826          * On CPUs that support "load IA32_EFER", always switch EFER
1827          * atomically, since it's faster than switching it manually.
1828          */
1829         if (cpu_has_load_ia32_efer ||
1830             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1831                 if (!(guest_efer & EFER_LMA))
1832                         guest_efer &= ~EFER_LME;
1833                 if (guest_efer != host_efer)
1834                         add_atomic_switch_msr(vmx, MSR_EFER,
1835                                               guest_efer, host_efer);
1836                 return false;
1837         } else {
1838                 guest_efer &= ~ignore_bits;
1839                 guest_efer |= host_efer & ignore_bits;
1840
1841                 vmx->guest_msrs[efer_offset].data = guest_efer;
1842                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1843
1844                 return true;
1845         }
1846 }
1847
1848 static unsigned long segment_base(u16 selector)
1849 {
1850         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1851         struct desc_struct *d;
1852         unsigned long table_base;
1853         unsigned long v;
1854
1855         if (!(selector & ~3))
1856                 return 0;
1857
1858         table_base = gdt->address;
1859
1860         if (selector & 4) {           /* from ldt */
1861                 u16 ldt_selector = kvm_read_ldt();
1862
1863                 if (!(ldt_selector & ~3))
1864                         return 0;
1865
1866                 table_base = segment_base(ldt_selector);
1867         }
1868         d = (struct desc_struct *)(table_base + (selector & ~7));
1869         v = get_desc_base(d);
1870 #ifdef CONFIG_X86_64
1871        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1872                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1873 #endif
1874         return v;
1875 }
1876
1877 static inline unsigned long kvm_read_tr_base(void)
1878 {
1879         u16 tr;
1880         asm("str %0" : "=g"(tr));
1881         return segment_base(tr);
1882 }
1883
1884 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1885 {
1886         struct vcpu_vmx *vmx = to_vmx(vcpu);
1887         int i;
1888
1889         if (vmx->host_state.loaded)
1890                 return;
1891
1892         vmx->host_state.loaded = 1;
1893         /*
1894          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1895          * allow segment selectors with cpl > 0 or ti == 1.
1896          */
1897         vmx->host_state.ldt_sel = kvm_read_ldt();
1898         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1899         savesegment(fs, vmx->host_state.fs_sel);
1900         if (!(vmx->host_state.fs_sel & 7)) {
1901                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1902                 vmx->host_state.fs_reload_needed = 0;
1903         } else {
1904                 vmcs_write16(HOST_FS_SELECTOR, 0);
1905                 vmx->host_state.fs_reload_needed = 1;
1906         }
1907         savesegment(gs, vmx->host_state.gs_sel);
1908         if (!(vmx->host_state.gs_sel & 7))
1909                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1910         else {
1911                 vmcs_write16(HOST_GS_SELECTOR, 0);
1912                 vmx->host_state.gs_ldt_reload_needed = 1;
1913         }
1914
1915 #ifdef CONFIG_X86_64
1916         savesegment(ds, vmx->host_state.ds_sel);
1917         savesegment(es, vmx->host_state.es_sel);
1918 #endif
1919
1920 #ifdef CONFIG_X86_64
1921         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1922         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1923 #else
1924         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1925         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1926 #endif
1927
1928 #ifdef CONFIG_X86_64
1929         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1930         if (is_long_mode(&vmx->vcpu))
1931                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1932 #endif
1933         if (boot_cpu_has(X86_FEATURE_MPX))
1934                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1935         for (i = 0; i < vmx->save_nmsrs; ++i)
1936                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1937                                    vmx->guest_msrs[i].data,
1938                                    vmx->guest_msrs[i].mask);
1939 }
1940
1941 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1942 {
1943         if (!vmx->host_state.loaded)
1944                 return;
1945
1946         ++vmx->vcpu.stat.host_state_reload;
1947         vmx->host_state.loaded = 0;
1948 #ifdef CONFIG_X86_64
1949         if (is_long_mode(&vmx->vcpu))
1950                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1951 #endif
1952         if (vmx->host_state.gs_ldt_reload_needed) {
1953                 kvm_load_ldt(vmx->host_state.ldt_sel);
1954 #ifdef CONFIG_X86_64
1955                 load_gs_index(vmx->host_state.gs_sel);
1956 #else
1957                 loadsegment(gs, vmx->host_state.gs_sel);
1958 #endif
1959         }
1960         if (vmx->host_state.fs_reload_needed)
1961                 loadsegment(fs, vmx->host_state.fs_sel);
1962 #ifdef CONFIG_X86_64
1963         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1964                 loadsegment(ds, vmx->host_state.ds_sel);
1965                 loadsegment(es, vmx->host_state.es_sel);
1966         }
1967 #endif
1968         reload_tss();
1969 #ifdef CONFIG_X86_64
1970         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1971 #endif
1972         if (vmx->host_state.msr_host_bndcfgs)
1973                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1974         /*
1975          * If the FPU is not active (through the host task or
1976          * the guest vcpu), then restore the cr0.TS bit.
1977          */
1978         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1979                 stts();
1980         load_gdt(this_cpu_ptr(&host_gdt));
1981 }
1982
1983 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1984 {
1985         preempt_disable();
1986         __vmx_load_host_state(vmx);
1987         preempt_enable();
1988 }
1989
1990 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1991 {
1992         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1993         struct pi_desc old, new;
1994         unsigned int dest;
1995
1996         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1997                 !irq_remapping_cap(IRQ_POSTING_CAP))
1998                 return;
1999
2000         do {
2001                 old.control = new.control = pi_desc->control;
2002
2003                 /*
2004                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2005                  * are two possible cases:
2006                  * 1. After running 'pre_block', context switch
2007                  *    happened. For this case, 'sn' was set in
2008                  *    vmx_vcpu_put(), so we need to clear it here.
2009                  * 2. After running 'pre_block', we were blocked,
2010                  *    and woken up by some other guy. For this case,
2011                  *    we don't need to do anything, 'pi_post_block'
2012                  *    will do everything for us. However, we cannot
2013                  *    check whether it is case #1 or case #2 here
2014                  *    (maybe, not needed), so we also clear sn here,
2015                  *    I think it is not a big deal.
2016                  */
2017                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2018                         if (vcpu->cpu != cpu) {
2019                                 dest = cpu_physical_id(cpu);
2020
2021                                 if (x2apic_enabled())
2022                                         new.ndst = dest;
2023                                 else
2024                                         new.ndst = (dest << 8) & 0xFF00;
2025                         }
2026
2027                         /* set 'NV' to 'notification vector' */
2028                         new.nv = POSTED_INTR_VECTOR;
2029                 }
2030
2031                 /* Allow posting non-urgent interrupts */
2032                 new.sn = 0;
2033         } while (cmpxchg(&pi_desc->control, old.control,
2034                         new.control) != old.control);
2035 }
2036 /*
2037  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2038  * vcpu mutex is already taken.
2039  */
2040 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2041 {
2042         struct vcpu_vmx *vmx = to_vmx(vcpu);
2043         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2044
2045         if (!vmm_exclusive)
2046                 kvm_cpu_vmxon(phys_addr);
2047         else if (vmx->loaded_vmcs->cpu != cpu)
2048                 loaded_vmcs_clear(vmx->loaded_vmcs);
2049
2050         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2051                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2052                 vmcs_load(vmx->loaded_vmcs->vmcs);
2053         }
2054
2055         if (vmx->loaded_vmcs->cpu != cpu) {
2056                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2057                 unsigned long sysenter_esp;
2058
2059                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2060                 local_irq_disable();
2061                 crash_disable_local_vmclear(cpu);
2062
2063                 /*
2064                  * Read loaded_vmcs->cpu should be before fetching
2065                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2066                  * See the comments in __loaded_vmcs_clear().
2067                  */
2068                 smp_rmb();
2069
2070                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2071                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2072                 crash_enable_local_vmclear(cpu);
2073                 local_irq_enable();
2074
2075                 /*
2076                  * Linux uses per-cpu TSS and GDT, so set these when switching
2077                  * processors.
2078                  */
2079                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2080                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2081
2082                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2083                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2084
2085                 vmx->loaded_vmcs->cpu = cpu;
2086         }
2087
2088         /* Setup TSC multiplier */
2089         if (kvm_has_tsc_control &&
2090             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2091                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2092                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2093         }
2094
2095         vmx_vcpu_pi_load(vcpu, cpu);
2096 }
2097
2098 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2099 {
2100         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2101
2102         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2103                 !irq_remapping_cap(IRQ_POSTING_CAP))
2104                 return;
2105
2106         /* Set SN when the vCPU is preempted */
2107         if (vcpu->preempted)
2108                 pi_set_sn(pi_desc);
2109 }
2110
2111 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2112 {
2113         vmx_vcpu_pi_put(vcpu);
2114
2115         __vmx_load_host_state(to_vmx(vcpu));
2116         if (!vmm_exclusive) {
2117                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2118                 vcpu->cpu = -1;
2119                 kvm_cpu_vmxoff();
2120         }
2121 }
2122
2123 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2124 {
2125         ulong cr0;
2126
2127         if (vcpu->fpu_active)
2128                 return;
2129         vcpu->fpu_active = 1;
2130         cr0 = vmcs_readl(GUEST_CR0);
2131         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2132         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2133         vmcs_writel(GUEST_CR0, cr0);
2134         update_exception_bitmap(vcpu);
2135         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2136         if (is_guest_mode(vcpu))
2137                 vcpu->arch.cr0_guest_owned_bits &=
2138                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2139         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2140 }
2141
2142 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2143
2144 /*
2145  * Return the cr0 value that a nested guest would read. This is a combination
2146  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2147  * its hypervisor (cr0_read_shadow).
2148  */
2149 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2150 {
2151         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2152                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2153 }
2154 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2155 {
2156         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2157                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2158 }
2159
2160 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2161 {
2162         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2163          * set this *before* calling this function.
2164          */
2165         vmx_decache_cr0_guest_bits(vcpu);
2166         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2167         update_exception_bitmap(vcpu);
2168         vcpu->arch.cr0_guest_owned_bits = 0;
2169         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2170         if (is_guest_mode(vcpu)) {
2171                 /*
2172                  * L1's specified read shadow might not contain the TS bit,
2173                  * so now that we turned on shadowing of this bit, we need to
2174                  * set this bit of the shadow. Like in nested_vmx_run we need
2175                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2176                  * up-to-date here because we just decached cr0.TS (and we'll
2177                  * only update vmcs12->guest_cr0 on nested exit).
2178                  */
2179                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2180                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2181                         (vcpu->arch.cr0 & X86_CR0_TS);
2182                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2183         } else
2184                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2185 }
2186
2187 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2188 {
2189         unsigned long rflags, save_rflags;
2190
2191         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2192                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2193                 rflags = vmcs_readl(GUEST_RFLAGS);
2194                 if (to_vmx(vcpu)->rmode.vm86_active) {
2195                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2196                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2197                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2198                 }
2199                 to_vmx(vcpu)->rflags = rflags;
2200         }
2201         return to_vmx(vcpu)->rflags;
2202 }
2203
2204 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2205 {
2206         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2207         to_vmx(vcpu)->rflags = rflags;
2208         if (to_vmx(vcpu)->rmode.vm86_active) {
2209                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2210                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2211         }
2212         vmcs_writel(GUEST_RFLAGS, rflags);
2213 }
2214
2215 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2216 {
2217         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2218         int ret = 0;
2219
2220         if (interruptibility & GUEST_INTR_STATE_STI)
2221                 ret |= KVM_X86_SHADOW_INT_STI;
2222         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2223                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2224
2225         return ret;
2226 }
2227
2228 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2229 {
2230         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2231         u32 interruptibility = interruptibility_old;
2232
2233         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2234
2235         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2236                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2237         else if (mask & KVM_X86_SHADOW_INT_STI)
2238                 interruptibility |= GUEST_INTR_STATE_STI;
2239
2240         if ((interruptibility != interruptibility_old))
2241                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2242 }
2243
2244 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2245 {
2246         unsigned long rip;
2247
2248         rip = kvm_rip_read(vcpu);
2249         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2250         kvm_rip_write(vcpu, rip);
2251
2252         /* skipping an emulated instruction also counts */
2253         vmx_set_interrupt_shadow(vcpu, 0);
2254 }
2255
2256 /*
2257  * KVM wants to inject page-faults which it got to the guest. This function
2258  * checks whether in a nested guest, we need to inject them to L1 or L2.
2259  */
2260 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2261 {
2262         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2263
2264         if (!(vmcs12->exception_bitmap & (1u << nr)))
2265                 return 0;
2266
2267         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2268                           vmcs_read32(VM_EXIT_INTR_INFO),
2269                           vmcs_readl(EXIT_QUALIFICATION));
2270         return 1;
2271 }
2272
2273 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2274                                 bool has_error_code, u32 error_code,
2275                                 bool reinject)
2276 {
2277         struct vcpu_vmx *vmx = to_vmx(vcpu);
2278         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2279
2280         if (!reinject && is_guest_mode(vcpu) &&
2281             nested_vmx_check_exception(vcpu, nr))
2282                 return;
2283
2284         if (has_error_code) {
2285                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2286                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2287         }
2288
2289         if (vmx->rmode.vm86_active) {
2290                 int inc_eip = 0;
2291                 if (kvm_exception_is_soft(nr))
2292                         inc_eip = vcpu->arch.event_exit_inst_len;
2293                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2294                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2295                 return;
2296         }
2297
2298         if (kvm_exception_is_soft(nr)) {
2299                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2300                              vmx->vcpu.arch.event_exit_inst_len);
2301                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2302         } else
2303                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2304
2305         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2306 }
2307
2308 static bool vmx_rdtscp_supported(void)
2309 {
2310         return cpu_has_vmx_rdtscp();
2311 }
2312
2313 static bool vmx_invpcid_supported(void)
2314 {
2315         return cpu_has_vmx_invpcid() && enable_ept;
2316 }
2317
2318 /*
2319  * Swap MSR entry in host/guest MSR entry array.
2320  */
2321 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2322 {
2323         struct shared_msr_entry tmp;
2324
2325         tmp = vmx->guest_msrs[to];
2326         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2327         vmx->guest_msrs[from] = tmp;
2328 }
2329
2330 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2331 {
2332         unsigned long *msr_bitmap;
2333
2334         if (is_guest_mode(vcpu))
2335                 msr_bitmap = vmx_msr_bitmap_nested;
2336         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2337                 if (is_long_mode(vcpu))
2338                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2339                 else
2340                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2341         } else {
2342                 if (is_long_mode(vcpu))
2343                         msr_bitmap = vmx_msr_bitmap_longmode;
2344                 else
2345                         msr_bitmap = vmx_msr_bitmap_legacy;
2346         }
2347
2348         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2349 }
2350
2351 /*
2352  * Set up the vmcs to automatically save and restore system
2353  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2354  * mode, as fiddling with msrs is very expensive.
2355  */
2356 static void setup_msrs(struct vcpu_vmx *vmx)
2357 {
2358         int save_nmsrs, index;
2359
2360         save_nmsrs = 0;
2361 #ifdef CONFIG_X86_64
2362         if (is_long_mode(&vmx->vcpu)) {
2363                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2364                 if (index >= 0)
2365                         move_msr_up(vmx, index, save_nmsrs++);
2366                 index = __find_msr_index(vmx, MSR_LSTAR);
2367                 if (index >= 0)
2368                         move_msr_up(vmx, index, save_nmsrs++);
2369                 index = __find_msr_index(vmx, MSR_CSTAR);
2370                 if (index >= 0)
2371                         move_msr_up(vmx, index, save_nmsrs++);
2372                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2373                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2374                         move_msr_up(vmx, index, save_nmsrs++);
2375                 /*
2376                  * MSR_STAR is only needed on long mode guests, and only
2377                  * if efer.sce is enabled.
2378                  */
2379                 index = __find_msr_index(vmx, MSR_STAR);
2380                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2381                         move_msr_up(vmx, index, save_nmsrs++);
2382         }
2383 #endif
2384         index = __find_msr_index(vmx, MSR_EFER);
2385         if (index >= 0 && update_transition_efer(vmx, index))
2386                 move_msr_up(vmx, index, save_nmsrs++);
2387
2388         vmx->save_nmsrs = save_nmsrs;
2389
2390         if (cpu_has_vmx_msr_bitmap())
2391                 vmx_set_msr_bitmap(&vmx->vcpu);
2392 }
2393
2394 /*
2395  * reads and returns guest's timestamp counter "register"
2396  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2397  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2398  */
2399 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2400 {
2401         u64 host_tsc, tsc_offset;
2402
2403         host_tsc = rdtsc();
2404         tsc_offset = vmcs_read64(TSC_OFFSET);
2405         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2406 }
2407
2408 /*
2409  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2410  * counter, even if a nested guest (L2) is currently running.
2411  */
2412 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2413 {
2414         u64 tsc_offset;
2415
2416         tsc_offset = is_guest_mode(vcpu) ?
2417                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2418                 vmcs_read64(TSC_OFFSET);
2419         return host_tsc + tsc_offset;
2420 }
2421
2422 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2423 {
2424         return vmcs_read64(TSC_OFFSET);
2425 }
2426
2427 /*
2428  * writes 'offset' into guest's timestamp counter offset register
2429  */
2430 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2431 {
2432         if (is_guest_mode(vcpu)) {
2433                 /*
2434                  * We're here if L1 chose not to trap WRMSR to TSC. According
2435                  * to the spec, this should set L1's TSC; The offset that L1
2436                  * set for L2 remains unchanged, and still needs to be added
2437                  * to the newly set TSC to get L2's TSC.
2438                  */
2439                 struct vmcs12 *vmcs12;
2440                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2441                 /* recalculate vmcs02.TSC_OFFSET: */
2442                 vmcs12 = get_vmcs12(vcpu);
2443                 vmcs_write64(TSC_OFFSET, offset +
2444                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2445                          vmcs12->tsc_offset : 0));
2446         } else {
2447                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2448                                            vmcs_read64(TSC_OFFSET), offset);
2449                 vmcs_write64(TSC_OFFSET, offset);
2450         }
2451 }
2452
2453 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2454 {
2455         u64 offset = vmcs_read64(TSC_OFFSET);
2456
2457         vmcs_write64(TSC_OFFSET, offset + adjustment);
2458         if (is_guest_mode(vcpu)) {
2459                 /* Even when running L2, the adjustment needs to apply to L1 */
2460                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2461         } else
2462                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2463                                            offset + adjustment);
2464 }
2465
2466 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2467 {
2468         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2469         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2470 }
2471
2472 /*
2473  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2474  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2475  * all guests if the "nested" module option is off, and can also be disabled
2476  * for a single guest by disabling its VMX cpuid bit.
2477  */
2478 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2479 {
2480         return nested && guest_cpuid_has_vmx(vcpu);
2481 }
2482
2483 /*
2484  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2485  * returned for the various VMX controls MSRs when nested VMX is enabled.
2486  * The same values should also be used to verify that vmcs12 control fields are
2487  * valid during nested entry from L1 to L2.
2488  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2489  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2490  * bit in the high half is on if the corresponding bit in the control field
2491  * may be on. See also vmx_control_verify().
2492  */
2493 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2494 {
2495         /*
2496          * Note that as a general rule, the high half of the MSRs (bits in
2497          * the control fields which may be 1) should be initialized by the
2498          * intersection of the underlying hardware's MSR (i.e., features which
2499          * can be supported) and the list of features we want to expose -
2500          * because they are known to be properly supported in our code.
2501          * Also, usually, the low half of the MSRs (bits which must be 1) can
2502          * be set to 0, meaning that L1 may turn off any of these bits. The
2503          * reason is that if one of these bits is necessary, it will appear
2504          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2505          * fields of vmcs01 and vmcs02, will turn these bits off - and
2506          * nested_vmx_exit_handled() will not pass related exits to L1.
2507          * These rules have exceptions below.
2508          */
2509
2510         /* pin-based controls */
2511         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2512                 vmx->nested.nested_vmx_pinbased_ctls_low,
2513                 vmx->nested.nested_vmx_pinbased_ctls_high);
2514         vmx->nested.nested_vmx_pinbased_ctls_low |=
2515                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2516         vmx->nested.nested_vmx_pinbased_ctls_high &=
2517                 PIN_BASED_EXT_INTR_MASK |
2518                 PIN_BASED_NMI_EXITING |
2519                 PIN_BASED_VIRTUAL_NMIS;
2520         vmx->nested.nested_vmx_pinbased_ctls_high |=
2521                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2522                 PIN_BASED_VMX_PREEMPTION_TIMER;
2523         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2524                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2525                         PIN_BASED_POSTED_INTR;
2526
2527         /* exit controls */
2528         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2529                 vmx->nested.nested_vmx_exit_ctls_low,
2530                 vmx->nested.nested_vmx_exit_ctls_high);
2531         vmx->nested.nested_vmx_exit_ctls_low =
2532                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2533
2534         vmx->nested.nested_vmx_exit_ctls_high &=
2535 #ifdef CONFIG_X86_64
2536                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2537 #endif
2538                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2539         vmx->nested.nested_vmx_exit_ctls_high |=
2540                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2541                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2542                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2543
2544         if (vmx_mpx_supported())
2545                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2546
2547         /* We support free control of debug control saving. */
2548         vmx->nested.nested_vmx_true_exit_ctls_low =
2549                 vmx->nested.nested_vmx_exit_ctls_low &
2550                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2551
2552         /* entry controls */
2553         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2554                 vmx->nested.nested_vmx_entry_ctls_low,
2555                 vmx->nested.nested_vmx_entry_ctls_high);
2556         vmx->nested.nested_vmx_entry_ctls_low =
2557                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2558         vmx->nested.nested_vmx_entry_ctls_high &=
2559 #ifdef CONFIG_X86_64
2560                 VM_ENTRY_IA32E_MODE |
2561 #endif
2562                 VM_ENTRY_LOAD_IA32_PAT;
2563         vmx->nested.nested_vmx_entry_ctls_high |=
2564                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2565         if (vmx_mpx_supported())
2566                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2567
2568         /* We support free control of debug control loading. */
2569         vmx->nested.nested_vmx_true_entry_ctls_low =
2570                 vmx->nested.nested_vmx_entry_ctls_low &
2571                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2572
2573         /* cpu-based controls */
2574         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2575                 vmx->nested.nested_vmx_procbased_ctls_low,
2576                 vmx->nested.nested_vmx_procbased_ctls_high);
2577         vmx->nested.nested_vmx_procbased_ctls_low =
2578                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2579         vmx->nested.nested_vmx_procbased_ctls_high &=
2580                 CPU_BASED_VIRTUAL_INTR_PENDING |
2581                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2582                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2583                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2584                 CPU_BASED_CR3_STORE_EXITING |
2585 #ifdef CONFIG_X86_64
2586                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2587 #endif
2588                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2589                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2590                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2591                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2592                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2593         /*
2594          * We can allow some features even when not supported by the
2595          * hardware. For example, L1 can specify an MSR bitmap - and we
2596          * can use it to avoid exits to L1 - even when L0 runs L2
2597          * without MSR bitmaps.
2598          */
2599         vmx->nested.nested_vmx_procbased_ctls_high |=
2600                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2601                 CPU_BASED_USE_MSR_BITMAPS;
2602
2603         /* We support free control of CR3 access interception. */
2604         vmx->nested.nested_vmx_true_procbased_ctls_low =
2605                 vmx->nested.nested_vmx_procbased_ctls_low &
2606                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2607
2608         /* secondary cpu-based controls */
2609         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2610                 vmx->nested.nested_vmx_secondary_ctls_low,
2611                 vmx->nested.nested_vmx_secondary_ctls_high);
2612         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2613         vmx->nested.nested_vmx_secondary_ctls_high &=
2614                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2615                 SECONDARY_EXEC_RDTSCP |
2616                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2617                 SECONDARY_EXEC_ENABLE_VPID |
2618                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2619                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2620                 SECONDARY_EXEC_WBINVD_EXITING |
2621                 SECONDARY_EXEC_XSAVES |
2622                 SECONDARY_EXEC_PCOMMIT;
2623
2624         if (enable_ept) {
2625                 /* nested EPT: emulate EPT also to L1 */
2626                 vmx->nested.nested_vmx_secondary_ctls_high |=
2627                         SECONDARY_EXEC_ENABLE_EPT;
2628                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2629                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2630                          VMX_EPT_INVEPT_BIT;
2631                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2632                 /*
2633                  * For nested guests, we don't do anything specific
2634                  * for single context invalidation. Hence, only advertise
2635                  * support for global context invalidation.
2636                  */
2637                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2638         } else
2639                 vmx->nested.nested_vmx_ept_caps = 0;
2640
2641         /*
2642          * Old versions of KVM use the single-context version without
2643          * checking for support, so declare that it is supported even
2644          * though it is treated as global context.  The alternative is
2645          * not failing the single-context invvpid, and it is worse.
2646          */
2647         if (enable_vpid)
2648                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2649                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2650                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2651         else
2652                 vmx->nested.nested_vmx_vpid_caps = 0;
2653
2654         if (enable_unrestricted_guest)
2655                 vmx->nested.nested_vmx_secondary_ctls_high |=
2656                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2657
2658         /* miscellaneous data */
2659         rdmsr(MSR_IA32_VMX_MISC,
2660                 vmx->nested.nested_vmx_misc_low,
2661                 vmx->nested.nested_vmx_misc_high);
2662         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2663         vmx->nested.nested_vmx_misc_low |=
2664                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2665                 VMX_MISC_ACTIVITY_HLT;
2666         vmx->nested.nested_vmx_misc_high = 0;
2667 }
2668
2669 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2670 {
2671         /*
2672          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2673          */
2674         return ((control & high) | low) == control;
2675 }
2676
2677 static inline u64 vmx_control_msr(u32 low, u32 high)
2678 {
2679         return low | ((u64)high << 32);
2680 }
2681
2682 /* Returns 0 on success, non-0 otherwise. */
2683 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2684 {
2685         struct vcpu_vmx *vmx = to_vmx(vcpu);
2686
2687         switch (msr_index) {
2688         case MSR_IA32_VMX_BASIC:
2689                 /*
2690                  * This MSR reports some information about VMX support. We
2691                  * should return information about the VMX we emulate for the
2692                  * guest, and the VMCS structure we give it - not about the
2693                  * VMX support of the underlying hardware.
2694                  */
2695                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2696                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2697                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2698                 break;
2699         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2700         case MSR_IA32_VMX_PINBASED_CTLS:
2701                 *pdata = vmx_control_msr(
2702                         vmx->nested.nested_vmx_pinbased_ctls_low,
2703                         vmx->nested.nested_vmx_pinbased_ctls_high);
2704                 break;
2705         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2706                 *pdata = vmx_control_msr(
2707                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2708                         vmx->nested.nested_vmx_procbased_ctls_high);
2709                 break;
2710         case MSR_IA32_VMX_PROCBASED_CTLS:
2711                 *pdata = vmx_control_msr(
2712                         vmx->nested.nested_vmx_procbased_ctls_low,
2713                         vmx->nested.nested_vmx_procbased_ctls_high);
2714                 break;
2715         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2716                 *pdata = vmx_control_msr(
2717                         vmx->nested.nested_vmx_true_exit_ctls_low,
2718                         vmx->nested.nested_vmx_exit_ctls_high);
2719                 break;
2720         case MSR_IA32_VMX_EXIT_CTLS:
2721                 *pdata = vmx_control_msr(
2722                         vmx->nested.nested_vmx_exit_ctls_low,
2723                         vmx->nested.nested_vmx_exit_ctls_high);
2724                 break;
2725         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2726                 *pdata = vmx_control_msr(
2727                         vmx->nested.nested_vmx_true_entry_ctls_low,
2728                         vmx->nested.nested_vmx_entry_ctls_high);
2729                 break;
2730         case MSR_IA32_VMX_ENTRY_CTLS:
2731                 *pdata = vmx_control_msr(
2732                         vmx->nested.nested_vmx_entry_ctls_low,
2733                         vmx->nested.nested_vmx_entry_ctls_high);
2734                 break;
2735         case MSR_IA32_VMX_MISC:
2736                 *pdata = vmx_control_msr(
2737                         vmx->nested.nested_vmx_misc_low,
2738                         vmx->nested.nested_vmx_misc_high);
2739                 break;
2740         /*
2741          * These MSRs specify bits which the guest must keep fixed (on or off)
2742          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2743          * We picked the standard core2 setting.
2744          */
2745 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2746 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2747         case MSR_IA32_VMX_CR0_FIXED0:
2748                 *pdata = VMXON_CR0_ALWAYSON;
2749                 break;
2750         case MSR_IA32_VMX_CR0_FIXED1:
2751                 *pdata = -1ULL;
2752                 break;
2753         case MSR_IA32_VMX_CR4_FIXED0:
2754                 *pdata = VMXON_CR4_ALWAYSON;
2755                 break;
2756         case MSR_IA32_VMX_CR4_FIXED1:
2757                 *pdata = -1ULL;
2758                 break;
2759         case MSR_IA32_VMX_VMCS_ENUM:
2760                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2761                 break;
2762         case MSR_IA32_VMX_PROCBASED_CTLS2:
2763                 *pdata = vmx_control_msr(
2764                         vmx->nested.nested_vmx_secondary_ctls_low,
2765                         vmx->nested.nested_vmx_secondary_ctls_high);
2766                 break;
2767         case MSR_IA32_VMX_EPT_VPID_CAP:
2768                 /* Currently, no nested vpid support */
2769                 *pdata = vmx->nested.nested_vmx_ept_caps |
2770                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2771                 break;
2772         default:
2773                 return 1;
2774         }
2775
2776         return 0;
2777 }
2778
2779 /*
2780  * Reads an msr value (of 'msr_index') into 'pdata'.
2781  * Returns 0 on success, non-0 otherwise.
2782  * Assumes vcpu_load() was already called.
2783  */
2784 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2785 {
2786         struct shared_msr_entry *msr;
2787
2788         switch (msr_info->index) {
2789 #ifdef CONFIG_X86_64
2790         case MSR_FS_BASE:
2791                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2792                 break;
2793         case MSR_GS_BASE:
2794                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2795                 break;
2796         case MSR_KERNEL_GS_BASE:
2797                 vmx_load_host_state(to_vmx(vcpu));
2798                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2799                 break;
2800 #endif
2801         case MSR_EFER:
2802                 return kvm_get_msr_common(vcpu, msr_info);
2803         case MSR_IA32_TSC:
2804                 msr_info->data = guest_read_tsc(vcpu);
2805                 break;
2806         case MSR_IA32_SYSENTER_CS:
2807                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2808                 break;
2809         case MSR_IA32_SYSENTER_EIP:
2810                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2811                 break;
2812         case MSR_IA32_SYSENTER_ESP:
2813                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2814                 break;
2815         case MSR_IA32_BNDCFGS:
2816                 if (!vmx_mpx_supported())
2817                         return 1;
2818                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2819                 break;
2820         case MSR_IA32_FEATURE_CONTROL:
2821                 if (!nested_vmx_allowed(vcpu))
2822                         return 1;
2823                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2824                 break;
2825         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2826                 if (!nested_vmx_allowed(vcpu))
2827                         return 1;
2828                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2829         case MSR_IA32_XSS:
2830                 if (!vmx_xsaves_supported())
2831                         return 1;
2832                 msr_info->data = vcpu->arch.ia32_xss;
2833                 break;
2834         case MSR_TSC_AUX:
2835                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2836                         return 1;
2837                 /* Otherwise falls through */
2838         default:
2839                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2840                 if (msr) {
2841                         msr_info->data = msr->data;
2842                         break;
2843                 }
2844                 return kvm_get_msr_common(vcpu, msr_info);
2845         }
2846
2847         return 0;
2848 }
2849
2850 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2851
2852 /*
2853  * Writes msr value into into the appropriate "register".
2854  * Returns 0 on success, non-0 otherwise.
2855  * Assumes vcpu_load() was already called.
2856  */
2857 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2858 {
2859         struct vcpu_vmx *vmx = to_vmx(vcpu);
2860         struct shared_msr_entry *msr;
2861         int ret = 0;
2862         u32 msr_index = msr_info->index;
2863         u64 data = msr_info->data;
2864
2865         switch (msr_index) {
2866         case MSR_EFER:
2867                 ret = kvm_set_msr_common(vcpu, msr_info);
2868                 break;
2869 #ifdef CONFIG_X86_64
2870         case MSR_FS_BASE:
2871                 vmx_segment_cache_clear(vmx);
2872                 vmcs_writel(GUEST_FS_BASE, data);
2873                 break;
2874         case MSR_GS_BASE:
2875                 vmx_segment_cache_clear(vmx);
2876                 vmcs_writel(GUEST_GS_BASE, data);
2877                 break;
2878         case MSR_KERNEL_GS_BASE:
2879                 vmx_load_host_state(vmx);
2880                 vmx->msr_guest_kernel_gs_base = data;
2881                 break;
2882 #endif
2883         case MSR_IA32_SYSENTER_CS:
2884                 vmcs_write32(GUEST_SYSENTER_CS, data);
2885                 break;
2886         case MSR_IA32_SYSENTER_EIP:
2887                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2888                 break;
2889         case MSR_IA32_SYSENTER_ESP:
2890                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2891                 break;
2892         case MSR_IA32_BNDCFGS:
2893                 if (!vmx_mpx_supported())
2894                         return 1;
2895                 vmcs_write64(GUEST_BNDCFGS, data);
2896                 break;
2897         case MSR_IA32_TSC:
2898                 kvm_write_tsc(vcpu, msr_info);
2899                 break;
2900         case MSR_IA32_CR_PAT:
2901                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2902                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2903                                 return 1;
2904                         vmcs_write64(GUEST_IA32_PAT, data);
2905                         vcpu->arch.pat = data;
2906                         break;
2907                 }
2908                 ret = kvm_set_msr_common(vcpu, msr_info);
2909                 break;
2910         case MSR_IA32_TSC_ADJUST:
2911                 ret = kvm_set_msr_common(vcpu, msr_info);
2912                 break;
2913         case MSR_IA32_FEATURE_CONTROL:
2914                 if (!nested_vmx_allowed(vcpu) ||
2915                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2916                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2917                         return 1;
2918                 vmx->nested.msr_ia32_feature_control = data;
2919                 if (msr_info->host_initiated && data == 0)
2920                         vmx_leave_nested(vcpu);
2921                 break;
2922         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2923                 return 1; /* they are read-only */
2924         case MSR_IA32_XSS:
2925                 if (!vmx_xsaves_supported())
2926                         return 1;
2927                 /*
2928                  * The only supported bit as of Skylake is bit 8, but
2929                  * it is not supported on KVM.
2930                  */
2931                 if (data != 0)
2932                         return 1;
2933                 vcpu->arch.ia32_xss = data;
2934                 if (vcpu->arch.ia32_xss != host_xss)
2935                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2936                                 vcpu->arch.ia32_xss, host_xss);
2937                 else
2938                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2939                 break;
2940         case MSR_TSC_AUX:
2941                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2942                         return 1;
2943                 /* Check reserved bit, higher 32 bits should be zero */
2944                 if ((data >> 32) != 0)
2945                         return 1;
2946                 /* Otherwise falls through */
2947         default:
2948                 msr = find_msr_entry(vmx, msr_index);
2949                 if (msr) {
2950                         u64 old_msr_data = msr->data;
2951                         msr->data = data;
2952                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2953                                 preempt_disable();
2954                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2955                                                          msr->mask);
2956                                 preempt_enable();
2957                                 if (ret)
2958                                         msr->data = old_msr_data;
2959                         }
2960                         break;
2961                 }
2962                 ret = kvm_set_msr_common(vcpu, msr_info);
2963         }
2964
2965         return ret;
2966 }
2967
2968 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2969 {
2970         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2971         switch (reg) {
2972         case VCPU_REGS_RSP:
2973                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2974                 break;
2975         case VCPU_REGS_RIP:
2976                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2977                 break;
2978         case VCPU_EXREG_PDPTR:
2979                 if (enable_ept)
2980                         ept_save_pdptrs(vcpu);
2981                 break;
2982         default:
2983                 break;
2984         }
2985 }
2986
2987 static __init int cpu_has_kvm_support(void)
2988 {
2989         return cpu_has_vmx();
2990 }
2991
2992 static __init int vmx_disabled_by_bios(void)
2993 {
2994         u64 msr;
2995
2996         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2997         if (msr & FEATURE_CONTROL_LOCKED) {
2998                 /* launched w/ TXT and VMX disabled */
2999                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3000                         && tboot_enabled())
3001                         return 1;
3002                 /* launched w/o TXT and VMX only enabled w/ TXT */
3003                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3004                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3005                         && !tboot_enabled()) {
3006                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3007                                 "activate TXT before enabling KVM\n");
3008                         return 1;
3009                 }
3010                 /* launched w/o TXT and VMX disabled */
3011                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3012                         && !tboot_enabled())
3013                         return 1;
3014         }
3015
3016         return 0;
3017 }
3018
3019 static void kvm_cpu_vmxon(u64 addr)
3020 {
3021         asm volatile (ASM_VMX_VMXON_RAX
3022                         : : "a"(&addr), "m"(addr)
3023                         : "memory", "cc");
3024 }
3025
3026 static int hardware_enable(void)
3027 {
3028         int cpu = raw_smp_processor_id();
3029         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3030         u64 old, test_bits;
3031
3032         if (cr4_read_shadow() & X86_CR4_VMXE)
3033                 return -EBUSY;
3034
3035         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3036         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3037         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3038
3039         /*
3040          * Now we can enable the vmclear operation in kdump
3041          * since the loaded_vmcss_on_cpu list on this cpu
3042          * has been initialized.
3043          *
3044          * Though the cpu is not in VMX operation now, there
3045          * is no problem to enable the vmclear operation
3046          * for the loaded_vmcss_on_cpu list is empty!
3047          */
3048         crash_enable_local_vmclear(cpu);
3049
3050         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3051
3052         test_bits = FEATURE_CONTROL_LOCKED;
3053         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3054         if (tboot_enabled())
3055                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3056
3057         if ((old & test_bits) != test_bits) {
3058                 /* enable and lock */
3059                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3060         }
3061         cr4_set_bits(X86_CR4_VMXE);
3062
3063         if (vmm_exclusive) {
3064                 kvm_cpu_vmxon(phys_addr);
3065                 ept_sync_global();
3066         }
3067
3068         native_store_gdt(this_cpu_ptr(&host_gdt));
3069
3070         return 0;
3071 }
3072
3073 static void vmclear_local_loaded_vmcss(void)
3074 {
3075         int cpu = raw_smp_processor_id();
3076         struct loaded_vmcs *v, *n;
3077
3078         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3079                                  loaded_vmcss_on_cpu_link)
3080                 __loaded_vmcs_clear(v);
3081 }
3082
3083
3084 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3085  * tricks.
3086  */
3087 static void kvm_cpu_vmxoff(void)
3088 {
3089         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3090 }
3091
3092 static void hardware_disable(void)
3093 {
3094         if (vmm_exclusive) {
3095                 vmclear_local_loaded_vmcss();
3096                 kvm_cpu_vmxoff();
3097         }
3098         cr4_clear_bits(X86_CR4_VMXE);
3099 }
3100
3101 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3102                                       u32 msr, u32 *result)
3103 {
3104         u32 vmx_msr_low, vmx_msr_high;
3105         u32 ctl = ctl_min | ctl_opt;
3106
3107         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3108
3109         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3110         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3111
3112         /* Ensure minimum (required) set of control bits are supported. */
3113         if (ctl_min & ~ctl)
3114                 return -EIO;
3115
3116         *result = ctl;
3117         return 0;
3118 }
3119
3120 static __init bool allow_1_setting(u32 msr, u32 ctl)
3121 {
3122         u32 vmx_msr_low, vmx_msr_high;
3123
3124         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3125         return vmx_msr_high & ctl;
3126 }
3127
3128 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3129 {
3130         u32 vmx_msr_low, vmx_msr_high;
3131         u32 min, opt, min2, opt2;
3132         u32 _pin_based_exec_control = 0;
3133         u32 _cpu_based_exec_control = 0;
3134         u32 _cpu_based_2nd_exec_control = 0;
3135         u32 _vmexit_control = 0;
3136         u32 _vmentry_control = 0;
3137
3138         min = CPU_BASED_HLT_EXITING |
3139 #ifdef CONFIG_X86_64
3140               CPU_BASED_CR8_LOAD_EXITING |
3141               CPU_BASED_CR8_STORE_EXITING |
3142 #endif
3143               CPU_BASED_CR3_LOAD_EXITING |
3144               CPU_BASED_CR3_STORE_EXITING |
3145               CPU_BASED_USE_IO_BITMAPS |
3146               CPU_BASED_MOV_DR_EXITING |
3147               CPU_BASED_USE_TSC_OFFSETING |
3148               CPU_BASED_MWAIT_EXITING |
3149               CPU_BASED_MONITOR_EXITING |
3150               CPU_BASED_INVLPG_EXITING |
3151               CPU_BASED_RDPMC_EXITING;
3152
3153         opt = CPU_BASED_TPR_SHADOW |
3154               CPU_BASED_USE_MSR_BITMAPS |
3155               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3156         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3157                                 &_cpu_based_exec_control) < 0)
3158                 return -EIO;
3159 #ifdef CONFIG_X86_64
3160         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3161                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3162                                            ~CPU_BASED_CR8_STORE_EXITING;
3163 #endif
3164         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3165                 min2 = 0;
3166                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3167                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3168                         SECONDARY_EXEC_WBINVD_EXITING |
3169                         SECONDARY_EXEC_ENABLE_VPID |
3170                         SECONDARY_EXEC_ENABLE_EPT |
3171                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3172                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3173                         SECONDARY_EXEC_RDTSCP |
3174                         SECONDARY_EXEC_ENABLE_INVPCID |
3175                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3176                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3177                         SECONDARY_EXEC_SHADOW_VMCS |
3178                         SECONDARY_EXEC_XSAVES |
3179                         SECONDARY_EXEC_ENABLE_PML |
3180                         SECONDARY_EXEC_PCOMMIT |
3181                         SECONDARY_EXEC_TSC_SCALING;
3182                 if (adjust_vmx_controls(min2, opt2,
3183                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3184                                         &_cpu_based_2nd_exec_control) < 0)
3185                         return -EIO;
3186         }
3187 #ifndef CONFIG_X86_64
3188         if (!(_cpu_based_2nd_exec_control &
3189                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3190                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3191 #endif
3192
3193         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3194                 _cpu_based_2nd_exec_control &= ~(
3195                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3196                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3197                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3198
3199         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3200                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3201                    enabled */
3202                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3203                                              CPU_BASED_CR3_STORE_EXITING |
3204                                              CPU_BASED_INVLPG_EXITING);
3205                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3206                       vmx_capability.ept, vmx_capability.vpid);
3207         }
3208
3209         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3210 #ifdef CONFIG_X86_64
3211         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3212 #endif
3213         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3214                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3215         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3216                                 &_vmexit_control) < 0)
3217                 return -EIO;
3218
3219         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3220         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3221         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3222                                 &_pin_based_exec_control) < 0)
3223                 return -EIO;
3224
3225         if (!(_cpu_based_2nd_exec_control &
3226                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3227                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3228                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3229
3230         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3231         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3232         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3233                                 &_vmentry_control) < 0)
3234                 return -EIO;
3235
3236         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3237
3238         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3239         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3240                 return -EIO;
3241
3242 #ifdef CONFIG_X86_64
3243         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3244         if (vmx_msr_high & (1u<<16))
3245                 return -EIO;
3246 #endif
3247
3248         /* Require Write-Back (WB) memory type for VMCS accesses. */
3249         if (((vmx_msr_high >> 18) & 15) != 6)
3250                 return -EIO;
3251
3252         vmcs_conf->size = vmx_msr_high & 0x1fff;
3253         vmcs_conf->order = get_order(vmcs_config.size);
3254         vmcs_conf->revision_id = vmx_msr_low;
3255
3256         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3257         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3258         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3259         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3260         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3261
3262         cpu_has_load_ia32_efer =
3263                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3264                                 VM_ENTRY_LOAD_IA32_EFER)
3265                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3266                                    VM_EXIT_LOAD_IA32_EFER);
3267
3268         cpu_has_load_perf_global_ctrl =
3269                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3270                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3271                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3272                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3273
3274         /*
3275          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3276          * but due to arrata below it can't be used. Workaround is to use
3277          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3278          *
3279          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3280          *
3281          * AAK155             (model 26)
3282          * AAP115             (model 30)
3283          * AAT100             (model 37)
3284          * BC86,AAY89,BD102   (model 44)
3285          * BA97               (model 46)
3286          *
3287          */
3288         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3289                 switch (boot_cpu_data.x86_model) {
3290                 case 26:
3291                 case 30:
3292                 case 37:
3293                 case 44:
3294                 case 46:
3295                         cpu_has_load_perf_global_ctrl = false;
3296                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3297                                         "does not work properly. Using workaround\n");
3298                         break;
3299                 default:
3300                         break;
3301                 }
3302         }
3303
3304         if (cpu_has_xsaves)
3305                 rdmsrl(MSR_IA32_XSS, host_xss);
3306
3307         return 0;
3308 }
3309
3310 static struct vmcs *alloc_vmcs_cpu(int cpu)
3311 {
3312         int node = cpu_to_node(cpu);
3313         struct page *pages;
3314         struct vmcs *vmcs;
3315
3316         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3317         if (!pages)
3318                 return NULL;
3319         vmcs = page_address(pages);
3320         memset(vmcs, 0, vmcs_config.size);
3321         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3322         return vmcs;
3323 }
3324
3325 static struct vmcs *alloc_vmcs(void)
3326 {
3327         return alloc_vmcs_cpu(raw_smp_processor_id());
3328 }
3329
3330 static void free_vmcs(struct vmcs *vmcs)
3331 {
3332         free_pages((unsigned long)vmcs, vmcs_config.order);
3333 }
3334
3335 /*
3336  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3337  */
3338 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3339 {
3340         if (!loaded_vmcs->vmcs)
3341                 return;
3342         loaded_vmcs_clear(loaded_vmcs);
3343         free_vmcs(loaded_vmcs->vmcs);
3344         loaded_vmcs->vmcs = NULL;
3345 }
3346
3347 static void free_kvm_area(void)
3348 {
3349         int cpu;
3350
3351         for_each_possible_cpu(cpu) {
3352                 free_vmcs(per_cpu(vmxarea, cpu));
3353                 per_cpu(vmxarea, cpu) = NULL;
3354         }
3355 }
3356
3357 static void init_vmcs_shadow_fields(void)
3358 {
3359         int i, j;
3360
3361         /* No checks for read only fields yet */
3362
3363         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3364                 switch (shadow_read_write_fields[i]) {
3365                 case GUEST_BNDCFGS:
3366                         if (!vmx_mpx_supported())
3367                                 continue;
3368                         break;
3369                 default:
3370                         break;
3371                 }
3372
3373                 if (j < i)
3374                         shadow_read_write_fields[j] =
3375                                 shadow_read_write_fields[i];
3376                 j++;
3377         }
3378         max_shadow_read_write_fields = j;
3379
3380         /* shadowed fields guest access without vmexit */
3381         for (i = 0; i < max_shadow_read_write_fields; i++) {
3382                 clear_bit(shadow_read_write_fields[i],
3383                           vmx_vmwrite_bitmap);
3384                 clear_bit(shadow_read_write_fields[i],
3385                           vmx_vmread_bitmap);
3386         }
3387         for (i = 0; i < max_shadow_read_only_fields; i++)
3388                 clear_bit(shadow_read_only_fields[i],
3389                           vmx_vmread_bitmap);
3390 }
3391
3392 static __init int alloc_kvm_area(void)
3393 {
3394         int cpu;
3395
3396         for_each_possible_cpu(cpu) {
3397                 struct vmcs *vmcs;
3398
3399                 vmcs = alloc_vmcs_cpu(cpu);
3400                 if (!vmcs) {
3401                         free_kvm_area();
3402                         return -ENOMEM;
3403                 }
3404
3405                 per_cpu(vmxarea, cpu) = vmcs;
3406         }
3407         return 0;
3408 }
3409
3410 static bool emulation_required(struct kvm_vcpu *vcpu)
3411 {
3412         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3413 }
3414
3415 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3416                 struct kvm_segment *save)
3417 {
3418         if (!emulate_invalid_guest_state) {
3419                 /*
3420                  * CS and SS RPL should be equal during guest entry according
3421                  * to VMX spec, but in reality it is not always so. Since vcpu
3422                  * is in the middle of the transition from real mode to
3423                  * protected mode it is safe to assume that RPL 0 is a good
3424                  * default value.
3425                  */
3426                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3427                         save->selector &= ~SEGMENT_RPL_MASK;
3428                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3429                 save->s = 1;
3430         }
3431         vmx_set_segment(vcpu, save, seg);
3432 }
3433
3434 static void enter_pmode(struct kvm_vcpu *vcpu)
3435 {
3436         unsigned long flags;
3437         struct vcpu_vmx *vmx = to_vmx(vcpu);
3438
3439         /*
3440          * Update real mode segment cache. It may be not up-to-date if sement
3441          * register was written while vcpu was in a guest mode.
3442          */
3443         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3444         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3445         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3446         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3447         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3448         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3449
3450         vmx->rmode.vm86_active = 0;
3451
3452         vmx_segment_cache_clear(vmx);
3453
3454         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3455
3456         flags = vmcs_readl(GUEST_RFLAGS);
3457         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3458         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3459         vmcs_writel(GUEST_RFLAGS, flags);
3460
3461         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3462                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3463
3464         update_exception_bitmap(vcpu);
3465
3466         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3467         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3468         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3469         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3470         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3471         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3472 }
3473
3474 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3475 {
3476         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3477         struct kvm_segment var = *save;
3478
3479         var.dpl = 0x3;
3480         if (seg == VCPU_SREG_CS)
3481                 var.type = 0x3;
3482
3483         if (!emulate_invalid_guest_state) {
3484                 var.selector = var.base >> 4;
3485                 var.base = var.base & 0xffff0;
3486                 var.limit = 0xffff;
3487                 var.g = 0;
3488                 var.db = 0;
3489                 var.present = 1;
3490                 var.s = 1;
3491                 var.l = 0;
3492                 var.unusable = 0;
3493                 var.type = 0x3;
3494                 var.avl = 0;
3495                 if (save->base & 0xf)
3496                         printk_once(KERN_WARNING "kvm: segment base is not "
3497                                         "paragraph aligned when entering "
3498                                         "protected mode (seg=%d)", seg);
3499         }
3500
3501         vmcs_write16(sf->selector, var.selector);
3502         vmcs_write32(sf->base, var.base);
3503         vmcs_write32(sf->limit, var.limit);
3504         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3505 }
3506
3507 static void enter_rmode(struct kvm_vcpu *vcpu)
3508 {
3509         unsigned long flags;
3510         struct vcpu_vmx *vmx = to_vmx(vcpu);
3511
3512         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3513         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3514         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3515         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3516         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3517         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3518         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3519
3520         vmx->rmode.vm86_active = 1;
3521
3522         /*
3523          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3524          * vcpu. Warn the user that an update is overdue.
3525          */
3526         if (!vcpu->kvm->arch.tss_addr)
3527                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3528                              "called before entering vcpu\n");
3529
3530         vmx_segment_cache_clear(vmx);
3531
3532         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3533         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3534         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3535
3536         flags = vmcs_readl(GUEST_RFLAGS);
3537         vmx->rmode.save_rflags = flags;
3538
3539         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3540
3541         vmcs_writel(GUEST_RFLAGS, flags);
3542         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3543         update_exception_bitmap(vcpu);
3544
3545         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3546         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3547         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3548         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3549         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3550         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3551
3552         kvm_mmu_reset_context(vcpu);
3553 }
3554
3555 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3556 {
3557         struct vcpu_vmx *vmx = to_vmx(vcpu);
3558         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3559
3560         if (!msr)
3561                 return;
3562
3563         /*
3564          * Force kernel_gs_base reloading before EFER changes, as control
3565          * of this msr depends on is_long_mode().
3566          */
3567         vmx_load_host_state(to_vmx(vcpu));
3568         vcpu->arch.efer = efer;
3569         if (efer & EFER_LMA) {
3570                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3571                 msr->data = efer;
3572         } else {
3573                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3574
3575                 msr->data = efer & ~EFER_LME;
3576         }
3577         setup_msrs(vmx);
3578 }
3579
3580 #ifdef CONFIG_X86_64
3581
3582 static void enter_lmode(struct kvm_vcpu *vcpu)
3583 {
3584         u32 guest_tr_ar;
3585
3586         vmx_segment_cache_clear(to_vmx(vcpu));
3587
3588         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3589         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3590                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3591                                      __func__);
3592                 vmcs_write32(GUEST_TR_AR_BYTES,
3593                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3594                              | VMX_AR_TYPE_BUSY_64_TSS);
3595         }
3596         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3597 }
3598
3599 static void exit_lmode(struct kvm_vcpu *vcpu)
3600 {
3601         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3602         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3603 }
3604
3605 #endif
3606
3607 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3608 {
3609         vpid_sync_context(vpid);
3610         if (enable_ept) {
3611                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3612                         return;
3613                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3614         }
3615 }
3616
3617 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3618 {
3619         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3620 }
3621
3622 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3623 {
3624         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3625
3626         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3627         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3628 }
3629
3630 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3631 {
3632         if (enable_ept && is_paging(vcpu))
3633                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3634         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3635 }
3636
3637 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3638 {
3639         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3640
3641         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3642         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3643 }
3644
3645 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3646 {
3647         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3648
3649         if (!test_bit(VCPU_EXREG_PDPTR,
3650                       (unsigned long *)&vcpu->arch.regs_dirty))
3651                 return;
3652
3653         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3654                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3655                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3656                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3657                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3658         }
3659 }
3660
3661 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3662 {
3663         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3664
3665         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3666                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3667                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3668                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3669                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3670         }
3671
3672         __set_bit(VCPU_EXREG_PDPTR,
3673                   (unsigned long *)&vcpu->arch.regs_avail);
3674         __set_bit(VCPU_EXREG_PDPTR,
3675                   (unsigned long *)&vcpu->arch.regs_dirty);
3676 }
3677
3678 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3679
3680 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3681                                         unsigned long cr0,
3682                                         struct kvm_vcpu *vcpu)
3683 {
3684         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3685                 vmx_decache_cr3(vcpu);
3686         if (!(cr0 & X86_CR0_PG)) {
3687                 /* From paging/starting to nonpaging */
3688                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3689                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3690                              (CPU_BASED_CR3_LOAD_EXITING |
3691                               CPU_BASED_CR3_STORE_EXITING));
3692                 vcpu->arch.cr0 = cr0;
3693                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3694         } else if (!is_paging(vcpu)) {
3695                 /* From nonpaging to paging */
3696                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3697                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3698                              ~(CPU_BASED_CR3_LOAD_EXITING |
3699                                CPU_BASED_CR3_STORE_EXITING));
3700                 vcpu->arch.cr0 = cr0;
3701                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3702         }
3703
3704         if (!(cr0 & X86_CR0_WP))
3705                 *hw_cr0 &= ~X86_CR0_WP;
3706 }
3707
3708 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3709 {
3710         struct vcpu_vmx *vmx = to_vmx(vcpu);
3711         unsigned long hw_cr0;
3712
3713         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3714         if (enable_unrestricted_guest)
3715                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3716         else {
3717                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3718
3719                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3720                         enter_pmode(vcpu);
3721
3722                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3723                         enter_rmode(vcpu);
3724         }
3725
3726 #ifdef CONFIG_X86_64
3727         if (vcpu->arch.efer & EFER_LME) {
3728                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3729                         enter_lmode(vcpu);
3730                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3731                         exit_lmode(vcpu);
3732         }
3733 #endif
3734
3735         if (enable_ept)
3736                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3737
3738         if (!vcpu->fpu_active)
3739                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3740
3741         vmcs_writel(CR0_READ_SHADOW, cr0);
3742         vmcs_writel(GUEST_CR0, hw_cr0);
3743         vcpu->arch.cr0 = cr0;
3744
3745         /* depends on vcpu->arch.cr0 to be set to a new value */
3746         vmx->emulation_required = emulation_required(vcpu);
3747 }
3748
3749 static u64 construct_eptp(unsigned long root_hpa)
3750 {
3751         u64 eptp;
3752
3753         /* TODO write the value reading from MSR */
3754         eptp = VMX_EPT_DEFAULT_MT |
3755                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3756         if (enable_ept_ad_bits)
3757                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3758         eptp |= (root_hpa & PAGE_MASK);
3759
3760         return eptp;
3761 }
3762
3763 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3764 {
3765         unsigned long guest_cr3;
3766         u64 eptp;
3767
3768         guest_cr3 = cr3;
3769         if (enable_ept) {
3770                 eptp = construct_eptp(cr3);
3771                 vmcs_write64(EPT_POINTER, eptp);
3772                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3773                         guest_cr3 = kvm_read_cr3(vcpu);
3774                 else
3775                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3776                 ept_load_pdptrs(vcpu);
3777         }
3778
3779         vmx_flush_tlb(vcpu);
3780         vmcs_writel(GUEST_CR3, guest_cr3);
3781 }
3782
3783 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3784 {
3785         /*
3786          * Pass through host's Machine Check Enable value to hw_cr4, which
3787          * is in force while we are in guest mode.  Do not let guests control
3788          * this bit, even if host CR4.MCE == 0.
3789          */
3790         unsigned long hw_cr4 =
3791                 (cr4_read_shadow() & X86_CR4_MCE) |
3792                 (cr4 & ~X86_CR4_MCE) |
3793                 (to_vmx(vcpu)->rmode.vm86_active ?
3794                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3795
3796         if (cr4 & X86_CR4_VMXE) {
3797                 /*
3798                  * To use VMXON (and later other VMX instructions), a guest
3799                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3800                  * So basically the check on whether to allow nested VMX
3801                  * is here.
3802                  */
3803                 if (!nested_vmx_allowed(vcpu))
3804                         return 1;
3805         }
3806         if (to_vmx(vcpu)->nested.vmxon &&
3807             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3808                 return 1;
3809
3810         vcpu->arch.cr4 = cr4;
3811         if (enable_ept) {
3812                 if (!is_paging(vcpu)) {
3813                         hw_cr4 &= ~X86_CR4_PAE;
3814                         hw_cr4 |= X86_CR4_PSE;
3815                 } else if (!(cr4 & X86_CR4_PAE)) {
3816                         hw_cr4 &= ~X86_CR4_PAE;
3817                 }
3818         }
3819
3820         if (!enable_unrestricted_guest && !is_paging(vcpu))
3821                 /*
3822                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3823                  * hardware.  However KVM always uses paging mode without
3824                  * unrestricted guest.
3825                  * To emulate this behavior, SMEP/SMAP needs to be manually
3826                  * disabled when guest switches to non-paging mode.
3827                  */
3828                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3829
3830         vmcs_writel(CR4_READ_SHADOW, cr4);
3831         vmcs_writel(GUEST_CR4, hw_cr4);
3832         return 0;
3833 }
3834
3835 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3836                             struct kvm_segment *var, int seg)
3837 {
3838         struct vcpu_vmx *vmx = to_vmx(vcpu);
3839         u32 ar;
3840
3841         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3842                 *var = vmx->rmode.segs[seg];
3843                 if (seg == VCPU_SREG_TR
3844                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3845                         return;
3846                 var->base = vmx_read_guest_seg_base(vmx, seg);
3847                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3848                 return;
3849         }
3850         var->base = vmx_read_guest_seg_base(vmx, seg);
3851         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3852         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3853         ar = vmx_read_guest_seg_ar(vmx, seg);
3854         var->unusable = (ar >> 16) & 1;
3855         var->type = ar & 15;
3856         var->s = (ar >> 4) & 1;
3857         var->dpl = (ar >> 5) & 3;
3858         /*
3859          * Some userspaces do not preserve unusable property. Since usable
3860          * segment has to be present according to VMX spec we can use present
3861          * property to amend userspace bug by making unusable segment always
3862          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3863          * segment as unusable.
3864          */
3865         var->present = !var->unusable;
3866         var->avl = (ar >> 12) & 1;
3867         var->l = (ar >> 13) & 1;
3868         var->db = (ar >> 14) & 1;
3869         var->g = (ar >> 15) & 1;
3870 }
3871
3872 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3873 {
3874         struct kvm_segment s;
3875
3876         if (to_vmx(vcpu)->rmode.vm86_active) {
3877                 vmx_get_segment(vcpu, &s, seg);
3878                 return s.base;
3879         }
3880         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3881 }
3882
3883 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3884 {
3885         struct vcpu_vmx *vmx = to_vmx(vcpu);
3886
3887         if (unlikely(vmx->rmode.vm86_active))
3888                 return 0;
3889         else {
3890                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3891                 return VMX_AR_DPL(ar);
3892         }
3893 }
3894
3895 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3896 {
3897         u32 ar;
3898
3899         if (var->unusable || !var->present)
3900                 ar = 1 << 16;
3901         else {
3902                 ar = var->type & 15;
3903                 ar |= (var->s & 1) << 4;
3904                 ar |= (var->dpl & 3) << 5;
3905                 ar |= (var->present & 1) << 7;
3906                 ar |= (var->avl & 1) << 12;
3907                 ar |= (var->l & 1) << 13;
3908                 ar |= (var->db & 1) << 14;
3909                 ar |= (var->g & 1) << 15;
3910         }
3911
3912         return ar;
3913 }
3914
3915 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3916                             struct kvm_segment *var, int seg)
3917 {
3918         struct vcpu_vmx *vmx = to_vmx(vcpu);
3919         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3920
3921         vmx_segment_cache_clear(vmx);
3922
3923         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3924                 vmx->rmode.segs[seg] = *var;
3925                 if (seg == VCPU_SREG_TR)
3926                         vmcs_write16(sf->selector, var->selector);
3927                 else if (var->s)
3928                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3929                 goto out;
3930         }
3931
3932         vmcs_writel(sf->base, var->base);
3933         vmcs_write32(sf->limit, var->limit);
3934         vmcs_write16(sf->selector, var->selector);
3935
3936         /*
3937          *   Fix the "Accessed" bit in AR field of segment registers for older
3938          * qemu binaries.
3939          *   IA32 arch specifies that at the time of processor reset the
3940          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3941          * is setting it to 0 in the userland code. This causes invalid guest
3942          * state vmexit when "unrestricted guest" mode is turned on.
3943          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3944          * tree. Newer qemu binaries with that qemu fix would not need this
3945          * kvm hack.
3946          */
3947         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3948                 var->type |= 0x1; /* Accessed */
3949
3950         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3951
3952 out:
3953         vmx->emulation_required = emulation_required(vcpu);
3954 }
3955
3956 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3957 {
3958         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3959
3960         *db = (ar >> 14) & 1;
3961         *l = (ar >> 13) & 1;
3962 }
3963
3964 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3965 {
3966         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3967         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3968 }
3969
3970 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3971 {
3972         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3973         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3974 }
3975
3976 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3977 {
3978         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3979         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3980 }
3981
3982 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3983 {
3984         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3985         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3986 }
3987
3988 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3989 {
3990         struct kvm_segment var;
3991         u32 ar;
3992
3993         vmx_get_segment(vcpu, &var, seg);
3994         var.dpl = 0x3;
3995         if (seg == VCPU_SREG_CS)
3996                 var.type = 0x3;
3997         ar = vmx_segment_access_rights(&var);
3998
3999         if (var.base != (var.selector << 4))
4000                 return false;
4001         if (var.limit != 0xffff)
4002                 return false;
4003         if (ar != 0xf3)
4004                 return false;
4005
4006         return true;
4007 }
4008
4009 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4010 {
4011         struct kvm_segment cs;
4012         unsigned int cs_rpl;
4013
4014         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4015         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4016
4017         if (cs.unusable)
4018                 return false;
4019         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4020                 return false;
4021         if (!cs.s)
4022                 return false;
4023         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4024                 if (cs.dpl > cs_rpl)
4025                         return false;
4026         } else {
4027                 if (cs.dpl != cs_rpl)
4028                         return false;
4029         }
4030         if (!cs.present)
4031                 return false;
4032
4033         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4034         return true;
4035 }
4036
4037 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4038 {
4039         struct kvm_segment ss;
4040         unsigned int ss_rpl;
4041
4042         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4043         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4044
4045         if (ss.unusable)
4046                 return true;
4047         if (ss.type != 3 && ss.type != 7)
4048                 return false;
4049         if (!ss.s)
4050                 return false;
4051         if (ss.dpl != ss_rpl) /* DPL != RPL */
4052                 return false;
4053         if (!ss.present)
4054                 return false;
4055
4056         return true;
4057 }
4058
4059 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4060 {
4061         struct kvm_segment var;
4062         unsigned int rpl;
4063
4064         vmx_get_segment(vcpu, &var, seg);
4065         rpl = var.selector & SEGMENT_RPL_MASK;
4066
4067         if (var.unusable)
4068                 return true;
4069         if (!var.s)
4070                 return false;
4071         if (!var.present)
4072                 return false;
4073         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4074                 if (var.dpl < rpl) /* DPL < RPL */
4075                         return false;
4076         }
4077
4078         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4079          * rights flags
4080          */
4081         return true;
4082 }
4083
4084 static bool tr_valid(struct kvm_vcpu *vcpu)
4085 {
4086         struct kvm_segment tr;
4087
4088         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4089
4090         if (tr.unusable)
4091                 return false;
4092         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4093                 return false;
4094         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4095                 return false;
4096         if (!tr.present)
4097                 return false;
4098
4099         return true;
4100 }
4101
4102 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4103 {
4104         struct kvm_segment ldtr;
4105
4106         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4107
4108         if (ldtr.unusable)
4109                 return true;
4110         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4111                 return false;
4112         if (ldtr.type != 2)
4113                 return false;
4114         if (!ldtr.present)
4115                 return false;
4116
4117         return true;
4118 }
4119
4120 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4121 {
4122         struct kvm_segment cs, ss;
4123
4124         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4125         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4126
4127         return ((cs.selector & SEGMENT_RPL_MASK) ==
4128                  (ss.selector & SEGMENT_RPL_MASK));
4129 }
4130
4131 /*
4132  * Check if guest state is valid. Returns true if valid, false if
4133  * not.
4134  * We assume that registers are always usable
4135  */
4136 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4137 {
4138         if (enable_unrestricted_guest)
4139                 return true;
4140
4141         /* real mode guest state checks */
4142         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4143                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4144                         return false;
4145                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4146                         return false;
4147                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4148                         return false;
4149                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4150                         return false;
4151                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4152                         return false;
4153                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4154                         return false;
4155         } else {
4156         /* protected mode guest state checks */
4157                 if (!cs_ss_rpl_check(vcpu))
4158                         return false;
4159                 if (!code_segment_valid(vcpu))
4160                         return false;
4161                 if (!stack_segment_valid(vcpu))
4162                         return false;
4163                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4164                         return false;
4165                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4166                         return false;
4167                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4168                         return false;
4169                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4170                         return false;
4171                 if (!tr_valid(vcpu))
4172                         return false;
4173                 if (!ldtr_valid(vcpu))
4174                         return false;
4175         }
4176         /* TODO:
4177          * - Add checks on RIP
4178          * - Add checks on RFLAGS
4179          */
4180
4181         return true;
4182 }
4183
4184 static int init_rmode_tss(struct kvm *kvm)
4185 {
4186         gfn_t fn;
4187         u16 data = 0;
4188         int idx, r;
4189
4190         idx = srcu_read_lock(&kvm->srcu);
4191         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4192         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4193         if (r < 0)
4194                 goto out;
4195         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4196         r = kvm_write_guest_page(kvm, fn++, &data,
4197                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4198         if (r < 0)
4199                 goto out;
4200         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4201         if (r < 0)
4202                 goto out;
4203         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4204         if (r < 0)
4205                 goto out;
4206         data = ~0;
4207         r = kvm_write_guest_page(kvm, fn, &data,
4208                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4209                                  sizeof(u8));
4210 out:
4211         srcu_read_unlock(&kvm->srcu, idx);
4212         return r;
4213 }
4214
4215 static int init_rmode_identity_map(struct kvm *kvm)
4216 {
4217         int i, idx, r = 0;
4218         pfn_t identity_map_pfn;
4219         u32 tmp;
4220
4221         if (!enable_ept)
4222                 return 0;
4223
4224         /* Protect kvm->arch.ept_identity_pagetable_done. */
4225         mutex_lock(&kvm->slots_lock);
4226
4227         if (likely(kvm->arch.ept_identity_pagetable_done))
4228                 goto out2;
4229
4230         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4231
4232         r = alloc_identity_pagetable(kvm);
4233         if (r < 0)
4234                 goto out2;
4235
4236         idx = srcu_read_lock(&kvm->srcu);
4237         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4238         if (r < 0)
4239                 goto out;
4240         /* Set up identity-mapping pagetable for EPT in real mode */
4241         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4242                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4243                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4244                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4245                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4246                 if (r < 0)
4247                         goto out;
4248         }
4249         kvm->arch.ept_identity_pagetable_done = true;
4250
4251 out:
4252         srcu_read_unlock(&kvm->srcu, idx);
4253
4254 out2:
4255         mutex_unlock(&kvm->slots_lock);
4256         return r;
4257 }
4258
4259 static void seg_setup(int seg)
4260 {
4261         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4262         unsigned int ar;
4263
4264         vmcs_write16(sf->selector, 0);
4265         vmcs_writel(sf->base, 0);
4266         vmcs_write32(sf->limit, 0xffff);
4267         ar = 0x93;
4268         if (seg == VCPU_SREG_CS)
4269                 ar |= 0x08; /* code segment */
4270
4271         vmcs_write32(sf->ar_bytes, ar);
4272 }
4273
4274 static int alloc_apic_access_page(struct kvm *kvm)
4275 {
4276         struct page *page;
4277         int r = 0;
4278
4279         mutex_lock(&kvm->slots_lock);
4280         if (kvm->arch.apic_access_page_done)
4281                 goto out;
4282         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4283                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4284         if (r)
4285                 goto out;
4286
4287         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4288         if (is_error_page(page)) {
4289                 r = -EFAULT;
4290                 goto out;
4291         }
4292
4293         /*
4294          * Do not pin the page in memory, so that memory hot-unplug
4295          * is able to migrate it.
4296          */
4297         put_page(page);
4298         kvm->arch.apic_access_page_done = true;
4299 out:
4300         mutex_unlock(&kvm->slots_lock);
4301         return r;
4302 }
4303
4304 static int alloc_identity_pagetable(struct kvm *kvm)
4305 {
4306         /* Called with kvm->slots_lock held. */
4307
4308         int r = 0;
4309
4310         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4311
4312         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4313                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4314
4315         return r;
4316 }
4317
4318 static int allocate_vpid(void)
4319 {
4320         int vpid;
4321
4322         if (!enable_vpid)
4323                 return 0;
4324         spin_lock(&vmx_vpid_lock);
4325         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4326         if (vpid < VMX_NR_VPIDS)
4327                 __set_bit(vpid, vmx_vpid_bitmap);
4328         else
4329                 vpid = 0;
4330         spin_unlock(&vmx_vpid_lock);
4331         return vpid;
4332 }
4333
4334 static void free_vpid(int vpid)
4335 {
4336         if (!enable_vpid || vpid == 0)
4337                 return;
4338         spin_lock(&vmx_vpid_lock);
4339         __clear_bit(vpid, vmx_vpid_bitmap);
4340         spin_unlock(&vmx_vpid_lock);
4341 }
4342
4343 #define MSR_TYPE_R      1
4344 #define MSR_TYPE_W      2
4345 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4346                                                 u32 msr, int type)
4347 {
4348         int f = sizeof(unsigned long);
4349
4350         if (!cpu_has_vmx_msr_bitmap())
4351                 return;
4352
4353         /*
4354          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4355          * have the write-low and read-high bitmap offsets the wrong way round.
4356          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4357          */
4358         if (msr <= 0x1fff) {
4359                 if (type & MSR_TYPE_R)
4360                         /* read-low */
4361                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4362
4363                 if (type & MSR_TYPE_W)
4364                         /* write-low */
4365                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4366
4367         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4368                 msr &= 0x1fff;
4369                 if (type & MSR_TYPE_R)
4370                         /* read-high */
4371                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4372
4373                 if (type & MSR_TYPE_W)
4374                         /* write-high */
4375                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4376
4377         }
4378 }
4379
4380 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4381                                                 u32 msr, int type)
4382 {
4383         int f = sizeof(unsigned long);
4384
4385         if (!cpu_has_vmx_msr_bitmap())
4386                 return;
4387
4388         /*
4389          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4390          * have the write-low and read-high bitmap offsets the wrong way round.
4391          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4392          */
4393         if (msr <= 0x1fff) {
4394                 if (type & MSR_TYPE_R)
4395                         /* read-low */
4396                         __set_bit(msr, msr_bitmap + 0x000 / f);
4397
4398                 if (type & MSR_TYPE_W)
4399                         /* write-low */
4400                         __set_bit(msr, msr_bitmap + 0x800 / f);
4401
4402         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4403                 msr &= 0x1fff;
4404                 if (type & MSR_TYPE_R)
4405                         /* read-high */
4406                         __set_bit(msr, msr_bitmap + 0x400 / f);
4407
4408                 if (type & MSR_TYPE_W)
4409                         /* write-high */
4410                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4411
4412         }
4413 }
4414
4415 /*
4416  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4417  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4418  */
4419 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4420                                                unsigned long *msr_bitmap_nested,
4421                                                u32 msr, int type)
4422 {
4423         int f = sizeof(unsigned long);
4424
4425         if (!cpu_has_vmx_msr_bitmap()) {
4426                 WARN_ON(1);
4427                 return;
4428         }
4429
4430         /*
4431          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4432          * have the write-low and read-high bitmap offsets the wrong way round.
4433          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4434          */
4435         if (msr <= 0x1fff) {
4436                 if (type & MSR_TYPE_R &&
4437                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4438                         /* read-low */
4439                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4440
4441                 if (type & MSR_TYPE_W &&
4442                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4443                         /* write-low */
4444                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4445
4446         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4447                 msr &= 0x1fff;
4448                 if (type & MSR_TYPE_R &&
4449                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4450                         /* read-high */
4451                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4452
4453                 if (type & MSR_TYPE_W &&
4454                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4455                         /* write-high */
4456                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4457
4458         }
4459 }
4460
4461 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4462 {
4463         if (!longmode_only)
4464                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4465                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4466         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4467                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4468 }
4469
4470 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4471 {
4472         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4473                         msr, MSR_TYPE_R);
4474         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4475                         msr, MSR_TYPE_R);
4476 }
4477
4478 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4479 {
4480         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4481                         msr, MSR_TYPE_R);
4482         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4483                         msr, MSR_TYPE_R);
4484 }
4485
4486 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4487 {
4488         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4489                         msr, MSR_TYPE_W);
4490         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4491                         msr, MSR_TYPE_W);
4492 }
4493
4494 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4495 {
4496         return enable_apicv && lapic_in_kernel(vcpu);
4497 }
4498
4499 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4500 {
4501         struct vcpu_vmx *vmx = to_vmx(vcpu);
4502         int max_irr;
4503         void *vapic_page;
4504         u16 status;
4505
4506         if (vmx->nested.pi_desc &&
4507             vmx->nested.pi_pending) {
4508                 vmx->nested.pi_pending = false;
4509                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4510                         return 0;
4511
4512                 max_irr = find_last_bit(
4513                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4514
4515                 if (max_irr == 256)
4516                         return 0;
4517
4518                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4519                 if (!vapic_page) {
4520                         WARN_ON(1);
4521                         return -ENOMEM;
4522                 }
4523                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4524                 kunmap(vmx->nested.virtual_apic_page);
4525
4526                 status = vmcs_read16(GUEST_INTR_STATUS);
4527                 if ((u8)max_irr > ((u8)status & 0xff)) {
4528                         status &= ~0xff;
4529                         status |= (u8)max_irr;
4530                         vmcs_write16(GUEST_INTR_STATUS, status);
4531                 }
4532         }
4533         return 0;
4534 }
4535
4536 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4537 {
4538 #ifdef CONFIG_SMP
4539         if (vcpu->mode == IN_GUEST_MODE) {
4540                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4541
4542                 /*
4543                  * Currently, we don't support urgent interrupt,
4544                  * all interrupts are recognized as non-urgent
4545                  * interrupt, so we cannot post interrupts when
4546                  * 'SN' is set.
4547                  *
4548                  * If the vcpu is in guest mode, it means it is
4549                  * running instead of being scheduled out and
4550                  * waiting in the run queue, and that's the only
4551                  * case when 'SN' is set currently, warning if
4552                  * 'SN' is set.
4553                  */
4554                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4555
4556                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4557                                 POSTED_INTR_VECTOR);
4558                 return true;
4559         }
4560 #endif
4561         return false;
4562 }
4563
4564 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4565                                                 int vector)
4566 {
4567         struct vcpu_vmx *vmx = to_vmx(vcpu);
4568
4569         if (is_guest_mode(vcpu) &&
4570             vector == vmx->nested.posted_intr_nv) {
4571                 /* the PIR and ON have been set by L1. */
4572                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4573                 /*
4574                  * If a posted intr is not recognized by hardware,
4575                  * we will accomplish it in the next vmentry.
4576                  */
4577                 vmx->nested.pi_pending = true;
4578                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4579                 return 0;
4580         }
4581         return -1;
4582 }
4583 /*
4584  * Send interrupt to vcpu via posted interrupt way.
4585  * 1. If target vcpu is running(non-root mode), send posted interrupt
4586  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4587  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4588  * interrupt from PIR in next vmentry.
4589  */
4590 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4591 {
4592         struct vcpu_vmx *vmx = to_vmx(vcpu);
4593         int r;
4594
4595         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4596         if (!r)
4597                 return;
4598
4599         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4600                 return;
4601
4602         r = pi_test_and_set_on(&vmx->pi_desc);
4603         kvm_make_request(KVM_REQ_EVENT, vcpu);
4604         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4605                 kvm_vcpu_kick(vcpu);
4606 }
4607
4608 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4609 {
4610         struct vcpu_vmx *vmx = to_vmx(vcpu);
4611
4612         if (!pi_test_and_clear_on(&vmx->pi_desc))
4613                 return;
4614
4615         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4616 }
4617
4618 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4619 {
4620         return;
4621 }
4622
4623 /*
4624  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4625  * will not change in the lifetime of the guest.
4626  * Note that host-state that does change is set elsewhere. E.g., host-state
4627  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4628  */
4629 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4630 {
4631         u32 low32, high32;
4632         unsigned long tmpl;
4633         struct desc_ptr dt;
4634         unsigned long cr4;
4635
4636         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4637         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4638
4639         /* Save the most likely value for this task's CR4 in the VMCS. */
4640         cr4 = cr4_read_shadow();
4641         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4642         vmx->host_state.vmcs_host_cr4 = cr4;
4643
4644         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4645 #ifdef CONFIG_X86_64
4646         /*
4647          * Load null selectors, so we can avoid reloading them in
4648          * __vmx_load_host_state(), in case userspace uses the null selectors
4649          * too (the expected case).
4650          */
4651         vmcs_write16(HOST_DS_SELECTOR, 0);
4652         vmcs_write16(HOST_ES_SELECTOR, 0);
4653 #else
4654         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4655         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4656 #endif
4657         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4658         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4659
4660         native_store_idt(&dt);
4661         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4662         vmx->host_idt_base = dt.address;
4663
4664         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4665
4666         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4667         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4668         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4669         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4670
4671         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4672                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4673                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4674         }
4675 }
4676
4677 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4678 {
4679         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4680         if (enable_ept)
4681                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4682         if (is_guest_mode(&vmx->vcpu))
4683                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4684                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4685         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4686 }
4687
4688 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4689 {
4690         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4691
4692         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4693                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4694         return pin_based_exec_ctrl;
4695 }
4696
4697 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4698 {
4699         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4700
4701         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4702                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4703
4704         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4705                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4706 #ifdef CONFIG_X86_64
4707                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4708                                 CPU_BASED_CR8_LOAD_EXITING;
4709 #endif
4710         }
4711         if (!enable_ept)
4712                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4713                                 CPU_BASED_CR3_LOAD_EXITING  |
4714                                 CPU_BASED_INVLPG_EXITING;
4715         return exec_control;
4716 }
4717
4718 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4719 {
4720         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4721         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4722                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4723         if (vmx->vpid == 0)
4724                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4725         if (!enable_ept) {
4726                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4727                 enable_unrestricted_guest = 0;
4728                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4729                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4730         }
4731         if (!enable_unrestricted_guest)
4732                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4733         if (!ple_gap)
4734                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4735         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4736                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4737                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4738         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4739         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4740            (handle_vmptrld).
4741            We can NOT enable shadow_vmcs here because we don't have yet
4742            a current VMCS12
4743         */
4744         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4745
4746         if (!enable_pml)
4747                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4748
4749         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4750         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4751
4752         return exec_control;
4753 }
4754
4755 static void ept_set_mmio_spte_mask(void)
4756 {
4757         /*
4758          * EPT Misconfigurations can be generated if the value of bits 2:0
4759          * of an EPT paging-structure entry is 110b (write/execute).
4760          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4761          * spte.
4762          */
4763         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4764 }
4765
4766 #define VMX_XSS_EXIT_BITMAP 0
4767 /*
4768  * Sets up the vmcs for emulated real mode.
4769  */
4770 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4771 {
4772 #ifdef CONFIG_X86_64
4773         unsigned long a;
4774 #endif
4775         int i;
4776
4777         /* I/O */
4778         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4779         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4780
4781         if (enable_shadow_vmcs) {
4782                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4783                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4784         }
4785         if (cpu_has_vmx_msr_bitmap())
4786                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4787
4788         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4789
4790         /* Control */
4791         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4792
4793         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4794
4795         if (cpu_has_secondary_exec_ctrls())
4796                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4797                                 vmx_secondary_exec_control(vmx));
4798
4799         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4800                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4801                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4802                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4803                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4804
4805                 vmcs_write16(GUEST_INTR_STATUS, 0);
4806
4807                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4808                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4809         }
4810
4811         if (ple_gap) {
4812                 vmcs_write32(PLE_GAP, ple_gap);
4813                 vmx->ple_window = ple_window;
4814                 vmx->ple_window_dirty = true;
4815         }
4816
4817         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4818         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4819         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4820
4821         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4822         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4823         vmx_set_constant_host_state(vmx);
4824 #ifdef CONFIG_X86_64
4825         rdmsrl(MSR_FS_BASE, a);
4826         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4827         rdmsrl(MSR_GS_BASE, a);
4828         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4829 #else
4830         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4831         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4832 #endif
4833
4834         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4835         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4836         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4837         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4838         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4839
4840         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4841                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4842
4843         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4844                 u32 index = vmx_msr_index[i];
4845                 u32 data_low, data_high;
4846                 int j = vmx->nmsrs;
4847
4848                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4849                         continue;
4850                 if (wrmsr_safe(index, data_low, data_high) < 0)
4851                         continue;
4852                 vmx->guest_msrs[j].index = i;
4853                 vmx->guest_msrs[j].data = 0;
4854                 vmx->guest_msrs[j].mask = -1ull;
4855                 ++vmx->nmsrs;
4856         }
4857
4858
4859         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4860
4861         /* 22.2.1, 20.8.1 */
4862         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4863
4864         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4865         set_cr4_guest_host_mask(vmx);
4866
4867         if (vmx_xsaves_supported())
4868                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4869
4870         return 0;
4871 }
4872
4873 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4874 {
4875         struct vcpu_vmx *vmx = to_vmx(vcpu);
4876         struct msr_data apic_base_msr;
4877         u64 cr0;
4878
4879         vmx->rmode.vm86_active = 0;
4880
4881         vmx->soft_vnmi_blocked = 0;
4882
4883         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4884         kvm_set_cr8(vcpu, 0);
4885
4886         if (!init_event) {
4887                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4888                                      MSR_IA32_APICBASE_ENABLE;
4889                 if (kvm_vcpu_is_reset_bsp(vcpu))
4890                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4891                 apic_base_msr.host_initiated = true;
4892                 kvm_set_apic_base(vcpu, &apic_base_msr);
4893         }
4894
4895         vmx_segment_cache_clear(vmx);
4896
4897         seg_setup(VCPU_SREG_CS);
4898         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4899         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4900
4901         seg_setup(VCPU_SREG_DS);
4902         seg_setup(VCPU_SREG_ES);
4903         seg_setup(VCPU_SREG_FS);
4904         seg_setup(VCPU_SREG_GS);
4905         seg_setup(VCPU_SREG_SS);
4906
4907         vmcs_write16(GUEST_TR_SELECTOR, 0);
4908         vmcs_writel(GUEST_TR_BASE, 0);
4909         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4910         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4911
4912         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4913         vmcs_writel(GUEST_LDTR_BASE, 0);
4914         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4915         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4916
4917         if (!init_event) {
4918                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4919                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4920                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4921                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4922         }
4923
4924         vmcs_writel(GUEST_RFLAGS, 0x02);
4925         kvm_rip_write(vcpu, 0xfff0);
4926
4927         vmcs_writel(GUEST_GDTR_BASE, 0);
4928         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4929
4930         vmcs_writel(GUEST_IDTR_BASE, 0);
4931         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4932
4933         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4934         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4935         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4936
4937         setup_msrs(vmx);
4938
4939         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4940
4941         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4942                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4943                 if (cpu_need_tpr_shadow(vcpu))
4944                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4945                                      __pa(vcpu->arch.apic->regs));
4946                 vmcs_write32(TPR_THRESHOLD, 0);
4947         }
4948
4949         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4950
4951         if (vmx_cpu_uses_apicv(vcpu))
4952                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4953
4954         if (vmx->vpid != 0)
4955                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4956
4957         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4958         vmx->vcpu.arch.cr0 = cr0;
4959         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4960         vmx_set_cr4(vcpu, 0);
4961         vmx_set_efer(vcpu, 0);
4962         vmx_fpu_activate(vcpu);
4963         update_exception_bitmap(vcpu);
4964
4965         vpid_sync_context(vmx->vpid);
4966 }
4967
4968 /*
4969  * In nested virtualization, check if L1 asked to exit on external interrupts.
4970  * For most existing hypervisors, this will always return true.
4971  */
4972 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4973 {
4974         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4975                 PIN_BASED_EXT_INTR_MASK;
4976 }
4977
4978 /*
4979  * In nested virtualization, check if L1 has set
4980  * VM_EXIT_ACK_INTR_ON_EXIT
4981  */
4982 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4983 {
4984         return get_vmcs12(vcpu)->vm_exit_controls &
4985                 VM_EXIT_ACK_INTR_ON_EXIT;
4986 }
4987
4988 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4989 {
4990         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4991                 PIN_BASED_NMI_EXITING;
4992 }
4993
4994 static void enable_irq_window(struct kvm_vcpu *vcpu)
4995 {
4996         u32 cpu_based_vm_exec_control;
4997
4998         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4999         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5000         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5001 }
5002
5003 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5004 {
5005         u32 cpu_based_vm_exec_control;
5006
5007         if (!cpu_has_virtual_nmis() ||
5008             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5009                 enable_irq_window(vcpu);
5010                 return;
5011         }
5012
5013         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5014         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5015         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5016 }
5017
5018 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5019 {
5020         struct vcpu_vmx *vmx = to_vmx(vcpu);
5021         uint32_t intr;
5022         int irq = vcpu->arch.interrupt.nr;
5023
5024         trace_kvm_inj_virq(irq);
5025
5026         ++vcpu->stat.irq_injections;
5027         if (vmx->rmode.vm86_active) {
5028                 int inc_eip = 0;
5029                 if (vcpu->arch.interrupt.soft)
5030                         inc_eip = vcpu->arch.event_exit_inst_len;
5031                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5032                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5033                 return;
5034         }
5035         intr = irq | INTR_INFO_VALID_MASK;
5036         if (vcpu->arch.interrupt.soft) {
5037                 intr |= INTR_TYPE_SOFT_INTR;
5038                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5039                              vmx->vcpu.arch.event_exit_inst_len);
5040         } else
5041                 intr |= INTR_TYPE_EXT_INTR;
5042         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5043 }
5044
5045 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5046 {
5047         struct vcpu_vmx *vmx = to_vmx(vcpu);
5048
5049         if (is_guest_mode(vcpu))
5050                 return;
5051
5052         if (!cpu_has_virtual_nmis()) {
5053                 /*
5054                  * Tracking the NMI-blocked state in software is built upon
5055                  * finding the next open IRQ window. This, in turn, depends on
5056                  * well-behaving guests: They have to keep IRQs disabled at
5057                  * least as long as the NMI handler runs. Otherwise we may
5058                  * cause NMI nesting, maybe breaking the guest. But as this is
5059                  * highly unlikely, we can live with the residual risk.
5060                  */
5061                 vmx->soft_vnmi_blocked = 1;
5062                 vmx->vnmi_blocked_time = 0;
5063         }
5064
5065         ++vcpu->stat.nmi_injections;
5066         vmx->nmi_known_unmasked = false;
5067         if (vmx->rmode.vm86_active) {
5068                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5069                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5070                 return;
5071         }
5072         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5073                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5074 }
5075
5076 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5077 {
5078         if (!cpu_has_virtual_nmis())
5079                 return to_vmx(vcpu)->soft_vnmi_blocked;
5080         if (to_vmx(vcpu)->nmi_known_unmasked)
5081                 return false;
5082         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5083 }
5084
5085 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5086 {
5087         struct vcpu_vmx *vmx = to_vmx(vcpu);
5088
5089         if (!cpu_has_virtual_nmis()) {
5090                 if (vmx->soft_vnmi_blocked != masked) {
5091                         vmx->soft_vnmi_blocked = masked;
5092                         vmx->vnmi_blocked_time = 0;
5093                 }
5094         } else {
5095                 vmx->nmi_known_unmasked = !masked;
5096                 if (masked)
5097                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5098                                       GUEST_INTR_STATE_NMI);
5099                 else
5100                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5101                                         GUEST_INTR_STATE_NMI);
5102         }
5103 }
5104
5105 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5106 {
5107         if (to_vmx(vcpu)->nested.nested_run_pending)
5108                 return 0;
5109
5110         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5111                 return 0;
5112
5113         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5114                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5115                    | GUEST_INTR_STATE_NMI));
5116 }
5117
5118 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5119 {
5120         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5121                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5122                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5123                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5124 }
5125
5126 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5127 {
5128         int ret;
5129
5130         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5131                                     PAGE_SIZE * 3);
5132         if (ret)
5133                 return ret;
5134         kvm->arch.tss_addr = addr;
5135         return init_rmode_tss(kvm);
5136 }
5137
5138 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5139 {
5140         switch (vec) {
5141         case BP_VECTOR:
5142                 /*
5143                  * Update instruction length as we may reinject the exception
5144                  * from user space while in guest debugging mode.
5145                  */
5146                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5147                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5148                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5149                         return false;
5150                 /* fall through */
5151         case DB_VECTOR:
5152                 if (vcpu->guest_debug &
5153                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5154                         return false;
5155                 /* fall through */
5156         case DE_VECTOR:
5157         case OF_VECTOR:
5158         case BR_VECTOR:
5159         case UD_VECTOR:
5160         case DF_VECTOR:
5161         case SS_VECTOR:
5162         case GP_VECTOR:
5163         case MF_VECTOR:
5164                 return true;
5165         break;
5166         }
5167         return false;
5168 }
5169
5170 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5171                                   int vec, u32 err_code)
5172 {
5173         /*
5174          * Instruction with address size override prefix opcode 0x67
5175          * Cause the #SS fault with 0 error code in VM86 mode.
5176          */
5177         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5178                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5179                         if (vcpu->arch.halt_request) {
5180                                 vcpu->arch.halt_request = 0;
5181                                 return kvm_vcpu_halt(vcpu);
5182                         }
5183                         return 1;
5184                 }
5185                 return 0;
5186         }
5187
5188         /*
5189          * Forward all other exceptions that are valid in real mode.
5190          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5191          *        the required debugging infrastructure rework.
5192          */
5193         kvm_queue_exception(vcpu, vec);
5194         return 1;
5195 }
5196
5197 /*
5198  * Trigger machine check on the host. We assume all the MSRs are already set up
5199  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5200  * We pass a fake environment to the machine check handler because we want
5201  * the guest to be always treated like user space, no matter what context
5202  * it used internally.
5203  */
5204 static void kvm_machine_check(void)
5205 {
5206 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5207         struct pt_regs regs = {
5208                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5209                 .flags = X86_EFLAGS_IF,
5210         };
5211
5212         do_machine_check(&regs, 0);
5213 #endif
5214 }
5215
5216 static int handle_machine_check(struct kvm_vcpu *vcpu)
5217 {
5218         /* already handled by vcpu_run */
5219         return 1;
5220 }
5221
5222 static int handle_exception(struct kvm_vcpu *vcpu)
5223 {
5224         struct vcpu_vmx *vmx = to_vmx(vcpu);
5225         struct kvm_run *kvm_run = vcpu->run;
5226         u32 intr_info, ex_no, error_code;
5227         unsigned long cr2, rip, dr6;
5228         u32 vect_info;
5229         enum emulation_result er;
5230
5231         vect_info = vmx->idt_vectoring_info;
5232         intr_info = vmx->exit_intr_info;
5233
5234         if (is_machine_check(intr_info))
5235                 return handle_machine_check(vcpu);
5236
5237         if (is_nmi(intr_info))
5238                 return 1;  /* already handled by vmx_vcpu_run() */
5239
5240         if (is_no_device(intr_info)) {
5241                 vmx_fpu_activate(vcpu);
5242                 return 1;
5243         }
5244
5245         if (is_invalid_opcode(intr_info)) {
5246                 if (is_guest_mode(vcpu)) {
5247                         kvm_queue_exception(vcpu, UD_VECTOR);
5248                         return 1;
5249                 }
5250                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5251                 if (er != EMULATE_DONE)
5252                         kvm_queue_exception(vcpu, UD_VECTOR);
5253                 return 1;
5254         }
5255
5256         error_code = 0;
5257         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5258                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5259
5260         /*
5261          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5262          * MMIO, it is better to report an internal error.
5263          * See the comments in vmx_handle_exit.
5264          */
5265         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5266             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5267                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5268                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5269                 vcpu->run->internal.ndata = 3;
5270                 vcpu->run->internal.data[0] = vect_info;
5271                 vcpu->run->internal.data[1] = intr_info;
5272                 vcpu->run->internal.data[2] = error_code;
5273                 return 0;
5274         }
5275
5276         if (is_page_fault(intr_info)) {
5277                 /* EPT won't cause page fault directly */
5278                 BUG_ON(enable_ept);
5279                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5280                 trace_kvm_page_fault(cr2, error_code);
5281
5282                 if (kvm_event_needs_reinjection(vcpu))
5283                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5284                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5285         }
5286
5287         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5288
5289         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5290                 return handle_rmode_exception(vcpu, ex_no, error_code);
5291
5292         switch (ex_no) {
5293         case AC_VECTOR:
5294                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5295                 return 1;
5296         case DB_VECTOR:
5297                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5298                 if (!(vcpu->guest_debug &
5299                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5300                         vcpu->arch.dr6 &= ~15;
5301                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5302                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5303                                 skip_emulated_instruction(vcpu);
5304
5305                         kvm_queue_exception(vcpu, DB_VECTOR);
5306                         return 1;
5307                 }
5308                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5309                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5310                 /* fall through */
5311         case BP_VECTOR:
5312                 /*
5313                  * Update instruction length as we may reinject #BP from
5314                  * user space while in guest debugging mode. Reading it for
5315                  * #DB as well causes no harm, it is not used in that case.
5316                  */
5317                 vmx->vcpu.arch.event_exit_inst_len =
5318                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5319                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5320                 rip = kvm_rip_read(vcpu);
5321                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5322                 kvm_run->debug.arch.exception = ex_no;
5323                 break;
5324         default:
5325                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5326                 kvm_run->ex.exception = ex_no;
5327                 kvm_run->ex.error_code = error_code;
5328                 break;
5329         }
5330         return 0;
5331 }
5332
5333 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5334 {
5335         ++vcpu->stat.irq_exits;
5336         return 1;
5337 }
5338
5339 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5340 {
5341         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5342         return 0;
5343 }
5344
5345 static int handle_io(struct kvm_vcpu *vcpu)
5346 {
5347         unsigned long exit_qualification;
5348         int size, in, string;
5349         unsigned port;
5350
5351         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5352         string = (exit_qualification & 16) != 0;
5353         in = (exit_qualification & 8) != 0;
5354
5355         ++vcpu->stat.io_exits;
5356
5357         if (string || in)
5358                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5359
5360         port = exit_qualification >> 16;
5361         size = (exit_qualification & 7) + 1;
5362         skip_emulated_instruction(vcpu);
5363
5364         return kvm_fast_pio_out(vcpu, size, port);
5365 }
5366
5367 static void
5368 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5369 {
5370         /*
5371          * Patch in the VMCALL instruction:
5372          */
5373         hypercall[0] = 0x0f;
5374         hypercall[1] = 0x01;
5375         hypercall[2] = 0xc1;
5376 }
5377
5378 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5379 {
5380         unsigned long always_on = VMXON_CR0_ALWAYSON;
5381         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5382
5383         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5384                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5385             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5386                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5387         return (val & always_on) == always_on;
5388 }
5389
5390 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5391 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5392 {
5393         if (is_guest_mode(vcpu)) {
5394                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5395                 unsigned long orig_val = val;
5396
5397                 /*
5398                  * We get here when L2 changed cr0 in a way that did not change
5399                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5400                  * but did change L0 shadowed bits. So we first calculate the
5401                  * effective cr0 value that L1 would like to write into the
5402                  * hardware. It consists of the L2-owned bits from the new
5403                  * value combined with the L1-owned bits from L1's guest_cr0.
5404                  */
5405                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5406                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5407
5408                 if (!nested_cr0_valid(vcpu, val))
5409                         return 1;
5410
5411                 if (kvm_set_cr0(vcpu, val))
5412                         return 1;
5413                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5414                 return 0;
5415         } else {
5416                 if (to_vmx(vcpu)->nested.vmxon &&
5417                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5418                         return 1;
5419                 return kvm_set_cr0(vcpu, val);
5420         }
5421 }
5422
5423 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5424 {
5425         if (is_guest_mode(vcpu)) {
5426                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5427                 unsigned long orig_val = val;
5428
5429                 /* analogously to handle_set_cr0 */
5430                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5431                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5432                 if (kvm_set_cr4(vcpu, val))
5433                         return 1;
5434                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5435                 return 0;
5436         } else
5437                 return kvm_set_cr4(vcpu, val);
5438 }
5439
5440 /* called to set cr0 as approriate for clts instruction exit. */
5441 static void handle_clts(struct kvm_vcpu *vcpu)
5442 {
5443         if (is_guest_mode(vcpu)) {
5444                 /*
5445                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5446                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5447                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5448                  */
5449                 vmcs_writel(CR0_READ_SHADOW,
5450                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5451                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5452         } else
5453                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5454 }
5455
5456 static int handle_cr(struct kvm_vcpu *vcpu)
5457 {
5458         unsigned long exit_qualification, val;
5459         int cr;
5460         int reg;
5461         int err;
5462
5463         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5464         cr = exit_qualification & 15;
5465         reg = (exit_qualification >> 8) & 15;
5466         switch ((exit_qualification >> 4) & 3) {
5467         case 0: /* mov to cr */
5468                 val = kvm_register_readl(vcpu, reg);
5469                 trace_kvm_cr_write(cr, val);
5470                 switch (cr) {
5471                 case 0:
5472                         err = handle_set_cr0(vcpu, val);
5473                         kvm_complete_insn_gp(vcpu, err);
5474                         return 1;
5475                 case 3:
5476                         err = kvm_set_cr3(vcpu, val);
5477                         kvm_complete_insn_gp(vcpu, err);
5478                         return 1;
5479                 case 4:
5480                         err = handle_set_cr4(vcpu, val);
5481                         kvm_complete_insn_gp(vcpu, err);
5482                         return 1;
5483                 case 8: {
5484                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5485                                 u8 cr8 = (u8)val;
5486                                 err = kvm_set_cr8(vcpu, cr8);
5487                                 kvm_complete_insn_gp(vcpu, err);
5488                                 if (lapic_in_kernel(vcpu))
5489                                         return 1;
5490                                 if (cr8_prev <= cr8)
5491                                         return 1;
5492                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5493                                 return 0;
5494                         }
5495                 }
5496                 break;
5497         case 2: /* clts */
5498                 handle_clts(vcpu);
5499                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5500                 skip_emulated_instruction(vcpu);
5501                 vmx_fpu_activate(vcpu);
5502                 return 1;
5503         case 1: /*mov from cr*/
5504                 switch (cr) {
5505                 case 3:
5506                         val = kvm_read_cr3(vcpu);
5507                         kvm_register_write(vcpu, reg, val);
5508                         trace_kvm_cr_read(cr, val);
5509                         skip_emulated_instruction(vcpu);
5510                         return 1;
5511                 case 8:
5512                         val = kvm_get_cr8(vcpu);
5513                         kvm_register_write(vcpu, reg, val);
5514                         trace_kvm_cr_read(cr, val);
5515                         skip_emulated_instruction(vcpu);
5516                         return 1;
5517                 }
5518                 break;
5519         case 3: /* lmsw */
5520                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5521                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5522                 kvm_lmsw(vcpu, val);
5523
5524                 skip_emulated_instruction(vcpu);
5525                 return 1;
5526         default:
5527                 break;
5528         }
5529         vcpu->run->exit_reason = 0;
5530         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5531                (int)(exit_qualification >> 4) & 3, cr);
5532         return 0;
5533 }
5534
5535 static int handle_dr(struct kvm_vcpu *vcpu)
5536 {
5537         unsigned long exit_qualification;
5538         int dr, dr7, reg;
5539
5540         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5541         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5542
5543         /* First, if DR does not exist, trigger UD */
5544         if (!kvm_require_dr(vcpu, dr))
5545                 return 1;
5546
5547         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5548         if (!kvm_require_cpl(vcpu, 0))
5549                 return 1;
5550         dr7 = vmcs_readl(GUEST_DR7);
5551         if (dr7 & DR7_GD) {
5552                 /*
5553                  * As the vm-exit takes precedence over the debug trap, we
5554                  * need to emulate the latter, either for the host or the
5555                  * guest debugging itself.
5556                  */
5557                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5558                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5559                         vcpu->run->debug.arch.dr7 = dr7;
5560                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5561                         vcpu->run->debug.arch.exception = DB_VECTOR;
5562                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5563                         return 0;
5564                 } else {
5565                         vcpu->arch.dr6 &= ~15;
5566                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5567                         kvm_queue_exception(vcpu, DB_VECTOR);
5568                         return 1;
5569                 }
5570         }
5571
5572         if (vcpu->guest_debug == 0) {
5573                 u32 cpu_based_vm_exec_control;
5574
5575                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5576                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5577                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5578
5579                 /*
5580                  * No more DR vmexits; force a reload of the debug registers
5581                  * and reenter on this instruction.  The next vmexit will
5582                  * retrieve the full state of the debug registers.
5583                  */
5584                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5585                 return 1;
5586         }
5587
5588         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5589         if (exit_qualification & TYPE_MOV_FROM_DR) {
5590                 unsigned long val;
5591
5592                 if (kvm_get_dr(vcpu, dr, &val))
5593                         return 1;
5594                 kvm_register_write(vcpu, reg, val);
5595         } else
5596                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5597                         return 1;
5598
5599         skip_emulated_instruction(vcpu);
5600         return 1;
5601 }
5602
5603 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5604 {
5605         return vcpu->arch.dr6;
5606 }
5607
5608 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5609 {
5610 }
5611
5612 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5613 {
5614         u32 cpu_based_vm_exec_control;
5615
5616         get_debugreg(vcpu->arch.db[0], 0);
5617         get_debugreg(vcpu->arch.db[1], 1);
5618         get_debugreg(vcpu->arch.db[2], 2);
5619         get_debugreg(vcpu->arch.db[3], 3);
5620         get_debugreg(vcpu->arch.dr6, 6);
5621         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5622
5623         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5624
5625         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5626         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5627         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5628 }
5629
5630 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5631 {
5632         vmcs_writel(GUEST_DR7, val);
5633 }
5634
5635 static int handle_cpuid(struct kvm_vcpu *vcpu)
5636 {
5637         kvm_emulate_cpuid(vcpu);
5638         return 1;
5639 }
5640
5641 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5642 {
5643         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5644         struct msr_data msr_info;
5645
5646         msr_info.index = ecx;
5647         msr_info.host_initiated = false;
5648         if (vmx_get_msr(vcpu, &msr_info)) {
5649                 trace_kvm_msr_read_ex(ecx);
5650                 kvm_inject_gp(vcpu, 0);
5651                 return 1;
5652         }
5653
5654         trace_kvm_msr_read(ecx, msr_info.data);
5655
5656         /* FIXME: handling of bits 32:63 of rax, rdx */
5657         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5658         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5659         skip_emulated_instruction(vcpu);
5660         return 1;
5661 }
5662
5663 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5664 {
5665         struct msr_data msr;
5666         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5667         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5668                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5669
5670         msr.data = data;
5671         msr.index = ecx;
5672         msr.host_initiated = false;
5673         if (kvm_set_msr(vcpu, &msr) != 0) {
5674                 trace_kvm_msr_write_ex(ecx, data);
5675                 kvm_inject_gp(vcpu, 0);
5676                 return 1;
5677         }
5678
5679         trace_kvm_msr_write(ecx, data);
5680         skip_emulated_instruction(vcpu);
5681         return 1;
5682 }
5683
5684 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5685 {
5686         kvm_make_request(KVM_REQ_EVENT, vcpu);
5687         return 1;
5688 }
5689
5690 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5691 {
5692         u32 cpu_based_vm_exec_control;
5693
5694         /* clear pending irq */
5695         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5696         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5697         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5698
5699         kvm_make_request(KVM_REQ_EVENT, vcpu);
5700
5701         ++vcpu->stat.irq_window_exits;
5702         return 1;
5703 }
5704
5705 static int handle_halt(struct kvm_vcpu *vcpu)
5706 {
5707         return kvm_emulate_halt(vcpu);
5708 }
5709
5710 static int handle_vmcall(struct kvm_vcpu *vcpu)
5711 {
5712         kvm_emulate_hypercall(vcpu);
5713         return 1;
5714 }
5715
5716 static int handle_invd(struct kvm_vcpu *vcpu)
5717 {
5718         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5719 }
5720
5721 static int handle_invlpg(struct kvm_vcpu *vcpu)
5722 {
5723         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5724
5725         kvm_mmu_invlpg(vcpu, exit_qualification);
5726         skip_emulated_instruction(vcpu);
5727         return 1;
5728 }
5729
5730 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5731 {
5732         int err;
5733
5734         err = kvm_rdpmc(vcpu);
5735         kvm_complete_insn_gp(vcpu, err);
5736
5737         return 1;
5738 }
5739
5740 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5741 {
5742         kvm_emulate_wbinvd(vcpu);
5743         return 1;
5744 }
5745
5746 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5747 {
5748         u64 new_bv = kvm_read_edx_eax(vcpu);
5749         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5750
5751         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5752                 skip_emulated_instruction(vcpu);
5753         return 1;
5754 }
5755
5756 static int handle_xsaves(struct kvm_vcpu *vcpu)
5757 {
5758         skip_emulated_instruction(vcpu);
5759         WARN(1, "this should never happen\n");
5760         return 1;
5761 }
5762
5763 static int handle_xrstors(struct kvm_vcpu *vcpu)
5764 {
5765         skip_emulated_instruction(vcpu);
5766         WARN(1, "this should never happen\n");
5767         return 1;
5768 }
5769
5770 static int handle_apic_access(struct kvm_vcpu *vcpu)
5771 {
5772         if (likely(fasteoi)) {
5773                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5774                 int access_type, offset;
5775
5776                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5777                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5778                 /*
5779                  * Sane guest uses MOV to write EOI, with written value
5780                  * not cared. So make a short-circuit here by avoiding
5781                  * heavy instruction emulation.
5782                  */
5783                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5784                     (offset == APIC_EOI)) {
5785                         kvm_lapic_set_eoi(vcpu);
5786                         skip_emulated_instruction(vcpu);
5787                         return 1;
5788                 }
5789         }
5790         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5791 }
5792
5793 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5794 {
5795         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5796         int vector = exit_qualification & 0xff;
5797
5798         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5799         kvm_apic_set_eoi_accelerated(vcpu, vector);
5800         return 1;
5801 }
5802
5803 static int handle_apic_write(struct kvm_vcpu *vcpu)
5804 {
5805         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5806         u32 offset = exit_qualification & 0xfff;
5807
5808         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5809         kvm_apic_write_nodecode(vcpu, offset);
5810         return 1;
5811 }
5812
5813 static int handle_task_switch(struct kvm_vcpu *vcpu)
5814 {
5815         struct vcpu_vmx *vmx = to_vmx(vcpu);
5816         unsigned long exit_qualification;
5817         bool has_error_code = false;
5818         u32 error_code = 0;
5819         u16 tss_selector;
5820         int reason, type, idt_v, idt_index;
5821
5822         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5823         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5824         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5825
5826         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5827
5828         reason = (u32)exit_qualification >> 30;
5829         if (reason == TASK_SWITCH_GATE && idt_v) {
5830                 switch (type) {
5831                 case INTR_TYPE_NMI_INTR:
5832                         vcpu->arch.nmi_injected = false;
5833                         vmx_set_nmi_mask(vcpu, true);
5834                         break;
5835                 case INTR_TYPE_EXT_INTR:
5836                 case INTR_TYPE_SOFT_INTR:
5837                         kvm_clear_interrupt_queue(vcpu);
5838                         break;
5839                 case INTR_TYPE_HARD_EXCEPTION:
5840                         if (vmx->idt_vectoring_info &
5841                             VECTORING_INFO_DELIVER_CODE_MASK) {
5842                                 has_error_code = true;
5843                                 error_code =
5844                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5845                         }
5846                         /* fall through */
5847                 case INTR_TYPE_SOFT_EXCEPTION:
5848                         kvm_clear_exception_queue(vcpu);
5849                         break;
5850                 default:
5851                         break;
5852                 }
5853         }
5854         tss_selector = exit_qualification;
5855
5856         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5857                        type != INTR_TYPE_EXT_INTR &&
5858                        type != INTR_TYPE_NMI_INTR))
5859                 skip_emulated_instruction(vcpu);
5860
5861         if (kvm_task_switch(vcpu, tss_selector,
5862                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5863                             has_error_code, error_code) == EMULATE_FAIL) {
5864                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5865                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5866                 vcpu->run->internal.ndata = 0;
5867                 return 0;
5868         }
5869
5870         /*
5871          * TODO: What about debug traps on tss switch?
5872          *       Are we supposed to inject them and update dr6?
5873          */
5874
5875         return 1;
5876 }
5877
5878 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5879 {
5880         unsigned long exit_qualification;
5881         gpa_t gpa;
5882         u32 error_code;
5883         int gla_validity;
5884
5885         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5886
5887         gla_validity = (exit_qualification >> 7) & 0x3;
5888         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5889                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5890                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5891                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5892                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5893                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5894                         (long unsigned int)exit_qualification);
5895                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5896                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5897                 return 0;
5898         }
5899
5900         /*
5901          * EPT violation happened while executing iret from NMI,
5902          * "blocked by NMI" bit has to be set before next VM entry.
5903          * There are errata that may cause this bit to not be set:
5904          * AAK134, BY25.
5905          */
5906         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5907                         cpu_has_virtual_nmis() &&
5908                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5909                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5910
5911         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5912         trace_kvm_page_fault(gpa, exit_qualification);
5913
5914         /* It is a write fault? */
5915         error_code = exit_qualification & PFERR_WRITE_MASK;
5916         /* It is a fetch fault? */
5917         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5918         /* ept page table is present? */
5919         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5920
5921         vcpu->arch.exit_qualification = exit_qualification;
5922
5923         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5924 }
5925
5926 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5927 {
5928         int ret;
5929         gpa_t gpa;
5930
5931         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5932         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5933                 skip_emulated_instruction(vcpu);
5934                 trace_kvm_fast_mmio(gpa);
5935                 return 1;
5936         }
5937
5938         ret = handle_mmio_page_fault(vcpu, gpa, true);
5939         if (likely(ret == RET_MMIO_PF_EMULATE))
5940                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5941                                               EMULATE_DONE;
5942
5943         if (unlikely(ret == RET_MMIO_PF_INVALID))
5944                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5945
5946         if (unlikely(ret == RET_MMIO_PF_RETRY))
5947                 return 1;
5948
5949         /* It is the real ept misconfig */
5950         WARN_ON(1);
5951
5952         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5953         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5954
5955         return 0;
5956 }
5957
5958 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5959 {
5960         u32 cpu_based_vm_exec_control;
5961
5962         /* clear pending NMI */
5963         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5964         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5965         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5966         ++vcpu->stat.nmi_window_exits;
5967         kvm_make_request(KVM_REQ_EVENT, vcpu);
5968
5969         return 1;
5970 }
5971
5972 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5973 {
5974         struct vcpu_vmx *vmx = to_vmx(vcpu);
5975         enum emulation_result err = EMULATE_DONE;
5976         int ret = 1;
5977         u32 cpu_exec_ctrl;
5978         bool intr_window_requested;
5979         unsigned count = 130;
5980
5981         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5982         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5983
5984         while (vmx->emulation_required && count-- != 0) {
5985                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5986                         return handle_interrupt_window(&vmx->vcpu);
5987
5988                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5989                         return 1;
5990
5991                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5992
5993                 if (err == EMULATE_USER_EXIT) {
5994                         ++vcpu->stat.mmio_exits;
5995                         ret = 0;
5996                         goto out;
5997                 }
5998
5999                 if (err != EMULATE_DONE) {
6000                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6001                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6002                         vcpu->run->internal.ndata = 0;
6003                         return 0;
6004                 }
6005
6006                 if (vcpu->arch.halt_request) {
6007                         vcpu->arch.halt_request = 0;
6008                         ret = kvm_vcpu_halt(vcpu);
6009                         goto out;
6010                 }
6011
6012                 if (signal_pending(current))
6013                         goto out;
6014                 if (need_resched())
6015                         schedule();
6016         }
6017
6018 out:
6019         return ret;
6020 }
6021
6022 static int __grow_ple_window(int val)
6023 {
6024         if (ple_window_grow < 1)
6025                 return ple_window;
6026
6027         val = min(val, ple_window_actual_max);
6028
6029         if (ple_window_grow < ple_window)
6030                 val *= ple_window_grow;
6031         else
6032                 val += ple_window_grow;
6033
6034         return val;
6035 }
6036
6037 static int __shrink_ple_window(int val, int modifier, int minimum)
6038 {
6039         if (modifier < 1)
6040                 return ple_window;
6041
6042         if (modifier < ple_window)
6043                 val /= modifier;
6044         else
6045                 val -= modifier;
6046
6047         return max(val, minimum);
6048 }
6049
6050 static void grow_ple_window(struct kvm_vcpu *vcpu)
6051 {
6052         struct vcpu_vmx *vmx = to_vmx(vcpu);
6053         int old = vmx->ple_window;
6054
6055         vmx->ple_window = __grow_ple_window(old);
6056
6057         if (vmx->ple_window != old)
6058                 vmx->ple_window_dirty = true;
6059
6060         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6061 }
6062
6063 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6064 {
6065         struct vcpu_vmx *vmx = to_vmx(vcpu);
6066         int old = vmx->ple_window;
6067
6068         vmx->ple_window = __shrink_ple_window(old,
6069                                               ple_window_shrink, ple_window);
6070
6071         if (vmx->ple_window != old)
6072                 vmx->ple_window_dirty = true;
6073
6074         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6075 }
6076
6077 /*
6078  * ple_window_actual_max is computed to be one grow_ple_window() below
6079  * ple_window_max. (See __grow_ple_window for the reason.)
6080  * This prevents overflows, because ple_window_max is int.
6081  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6082  * this process.
6083  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6084  */
6085 static void update_ple_window_actual_max(void)
6086 {
6087         ple_window_actual_max =
6088                         __shrink_ple_window(max(ple_window_max, ple_window),
6089                                             ple_window_grow, INT_MIN);
6090 }
6091
6092 /*
6093  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6094  */
6095 static void wakeup_handler(void)
6096 {
6097         struct kvm_vcpu *vcpu;
6098         int cpu = smp_processor_id();
6099
6100         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6101         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6102                         blocked_vcpu_list) {
6103                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6104
6105                 if (pi_test_on(pi_desc) == 1)
6106                         kvm_vcpu_kick(vcpu);
6107         }
6108         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6109 }
6110
6111 static __init int hardware_setup(void)
6112 {
6113         int r = -ENOMEM, i, msr;
6114
6115         rdmsrl_safe(MSR_EFER, &host_efer);
6116
6117         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6118                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6119
6120         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6121         if (!vmx_io_bitmap_a)
6122                 return r;
6123
6124         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6125         if (!vmx_io_bitmap_b)
6126                 goto out;
6127
6128         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6129         if (!vmx_msr_bitmap_legacy)
6130                 goto out1;
6131
6132         vmx_msr_bitmap_legacy_x2apic =
6133                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6134         if (!vmx_msr_bitmap_legacy_x2apic)
6135                 goto out2;
6136
6137         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6138         if (!vmx_msr_bitmap_longmode)
6139                 goto out3;
6140
6141         vmx_msr_bitmap_longmode_x2apic =
6142                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6143         if (!vmx_msr_bitmap_longmode_x2apic)
6144                 goto out4;
6145
6146         if (nested) {
6147                 vmx_msr_bitmap_nested =
6148                         (unsigned long *)__get_free_page(GFP_KERNEL);
6149                 if (!vmx_msr_bitmap_nested)
6150                         goto out5;
6151         }
6152
6153         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6154         if (!vmx_vmread_bitmap)
6155                 goto out6;
6156
6157         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6158         if (!vmx_vmwrite_bitmap)
6159                 goto out7;
6160
6161         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6162         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6163
6164         /*
6165          * Allow direct access to the PC debug port (it is often used for I/O
6166          * delays, but the vmexits simply slow things down).
6167          */
6168         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6169         clear_bit(0x80, vmx_io_bitmap_a);
6170
6171         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6172
6173         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6174         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6175         if (nested)
6176                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6177
6178         if (setup_vmcs_config(&vmcs_config) < 0) {
6179                 r = -EIO;
6180                 goto out8;
6181         }
6182
6183         if (boot_cpu_has(X86_FEATURE_NX))
6184                 kvm_enable_efer_bits(EFER_NX);
6185
6186         if (!cpu_has_vmx_vpid())
6187                 enable_vpid = 0;
6188         if (!cpu_has_vmx_shadow_vmcs())
6189                 enable_shadow_vmcs = 0;
6190         if (enable_shadow_vmcs)
6191                 init_vmcs_shadow_fields();
6192
6193         if (!cpu_has_vmx_ept() ||
6194             !cpu_has_vmx_ept_4levels()) {
6195                 enable_ept = 0;
6196                 enable_unrestricted_guest = 0;
6197                 enable_ept_ad_bits = 0;
6198         }
6199
6200         if (!cpu_has_vmx_ept_ad_bits())
6201                 enable_ept_ad_bits = 0;
6202
6203         if (!cpu_has_vmx_unrestricted_guest())
6204                 enable_unrestricted_guest = 0;
6205
6206         if (!cpu_has_vmx_flexpriority())
6207                 flexpriority_enabled = 0;
6208
6209         /*
6210          * set_apic_access_page_addr() is used to reload apic access
6211          * page upon invalidation.  No need to do anything if not
6212          * using the APIC_ACCESS_ADDR VMCS field.
6213          */
6214         if (!flexpriority_enabled)
6215                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6216
6217         if (!cpu_has_vmx_tpr_shadow())
6218                 kvm_x86_ops->update_cr8_intercept = NULL;
6219
6220         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6221                 kvm_disable_largepages();
6222
6223         if (!cpu_has_vmx_ple())
6224                 ple_gap = 0;
6225
6226         if (!cpu_has_vmx_apicv())
6227                 enable_apicv = 0;
6228
6229         if (cpu_has_vmx_tsc_scaling()) {
6230                 kvm_has_tsc_control = true;
6231                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6232                 kvm_tsc_scaling_ratio_frac_bits = 48;
6233         }
6234
6235         if (enable_apicv)
6236                 kvm_x86_ops->update_cr8_intercept = NULL;
6237         else {
6238                 kvm_x86_ops->hwapic_irr_update = NULL;
6239                 kvm_x86_ops->hwapic_isr_update = NULL;
6240                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6241                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6242         }
6243
6244         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6245         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6246         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6247         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6248         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6249         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6250         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6251
6252         memcpy(vmx_msr_bitmap_legacy_x2apic,
6253                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6254         memcpy(vmx_msr_bitmap_longmode_x2apic,
6255                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6256
6257         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6258
6259         if (enable_apicv) {
6260                 for (msr = 0x800; msr <= 0x8ff; msr++)
6261                         vmx_disable_intercept_msr_read_x2apic(msr);
6262
6263                 /* According SDM, in x2apic mode, the whole id reg is used.
6264                  * But in KVM, it only use the highest eight bits. Need to
6265                  * intercept it */
6266                 vmx_enable_intercept_msr_read_x2apic(0x802);
6267                 /* TMCCT */
6268                 vmx_enable_intercept_msr_read_x2apic(0x839);
6269                 /* TPR */
6270                 vmx_disable_intercept_msr_write_x2apic(0x808);
6271                 /* EOI */
6272                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6273                 /* SELF-IPI */
6274                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6275         }
6276
6277         if (enable_ept) {
6278                 kvm_mmu_set_mask_ptes(0ull,
6279                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6280                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6281                         0ull, VMX_EPT_EXECUTABLE_MASK);
6282                 ept_set_mmio_spte_mask();
6283                 kvm_enable_tdp();
6284         } else
6285                 kvm_disable_tdp();
6286
6287         update_ple_window_actual_max();
6288
6289         /*
6290          * Only enable PML when hardware supports PML feature, and both EPT
6291          * and EPT A/D bit features are enabled -- PML depends on them to work.
6292          */
6293         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6294                 enable_pml = 0;
6295
6296         if (!enable_pml) {
6297                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6298                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6299                 kvm_x86_ops->flush_log_dirty = NULL;
6300                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6301         }
6302
6303         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6304
6305         return alloc_kvm_area();
6306
6307 out8:
6308         free_page((unsigned long)vmx_vmwrite_bitmap);
6309 out7:
6310         free_page((unsigned long)vmx_vmread_bitmap);
6311 out6:
6312         if (nested)
6313                 free_page((unsigned long)vmx_msr_bitmap_nested);
6314 out5:
6315         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6316 out4:
6317         free_page((unsigned long)vmx_msr_bitmap_longmode);
6318 out3:
6319         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6320 out2:
6321         free_page((unsigned long)vmx_msr_bitmap_legacy);
6322 out1:
6323         free_page((unsigned long)vmx_io_bitmap_b);
6324 out:
6325         free_page((unsigned long)vmx_io_bitmap_a);
6326
6327     return r;
6328 }
6329
6330 static __exit void hardware_unsetup(void)
6331 {
6332         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6333         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6334         free_page((unsigned long)vmx_msr_bitmap_legacy);
6335         free_page((unsigned long)vmx_msr_bitmap_longmode);
6336         free_page((unsigned long)vmx_io_bitmap_b);
6337         free_page((unsigned long)vmx_io_bitmap_a);
6338         free_page((unsigned long)vmx_vmwrite_bitmap);
6339         free_page((unsigned long)vmx_vmread_bitmap);
6340         if (nested)
6341                 free_page((unsigned long)vmx_msr_bitmap_nested);
6342
6343         free_kvm_area();
6344 }
6345
6346 /*
6347  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6348  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6349  */
6350 static int handle_pause(struct kvm_vcpu *vcpu)
6351 {
6352         if (ple_gap)
6353                 grow_ple_window(vcpu);
6354
6355         skip_emulated_instruction(vcpu);
6356         kvm_vcpu_on_spin(vcpu);
6357
6358         return 1;
6359 }
6360
6361 static int handle_nop(struct kvm_vcpu *vcpu)
6362 {
6363         skip_emulated_instruction(vcpu);
6364         return 1;
6365 }
6366
6367 static int handle_mwait(struct kvm_vcpu *vcpu)
6368 {
6369         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6370         return handle_nop(vcpu);
6371 }
6372
6373 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6374 {
6375         return 1;
6376 }
6377
6378 static int handle_monitor(struct kvm_vcpu *vcpu)
6379 {
6380         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6381         return handle_nop(vcpu);
6382 }
6383
6384 /*
6385  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6386  * We could reuse a single VMCS for all the L2 guests, but we also want the
6387  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6388  * allows keeping them loaded on the processor, and in the future will allow
6389  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6390  * every entry if they never change.
6391  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6392  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6393  *
6394  * The following functions allocate and free a vmcs02 in this pool.
6395  */
6396
6397 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6398 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6399 {
6400         struct vmcs02_list *item;
6401         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6402                 if (item->vmptr == vmx->nested.current_vmptr) {
6403                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6404                         return &item->vmcs02;
6405                 }
6406
6407         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6408                 /* Recycle the least recently used VMCS. */
6409                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6410                         struct vmcs02_list, list);
6411                 item->vmptr = vmx->nested.current_vmptr;
6412                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6413                 return &item->vmcs02;
6414         }
6415
6416         /* Create a new VMCS */
6417         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6418         if (!item)
6419                 return NULL;
6420         item->vmcs02.vmcs = alloc_vmcs();
6421         if (!item->vmcs02.vmcs) {
6422                 kfree(item);
6423                 return NULL;
6424         }
6425         loaded_vmcs_init(&item->vmcs02);
6426         item->vmptr = vmx->nested.current_vmptr;
6427         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6428         vmx->nested.vmcs02_num++;
6429         return &item->vmcs02;
6430 }
6431
6432 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6433 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6434 {
6435         struct vmcs02_list *item;
6436         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6437                 if (item->vmptr == vmptr) {
6438                         free_loaded_vmcs(&item->vmcs02);
6439                         list_del(&item->list);
6440                         kfree(item);
6441                         vmx->nested.vmcs02_num--;
6442                         return;
6443                 }
6444 }
6445
6446 /*
6447  * Free all VMCSs saved for this vcpu, except the one pointed by
6448  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6449  * must be &vmx->vmcs01.
6450  */
6451 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6452 {
6453         struct vmcs02_list *item, *n;
6454
6455         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6456         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6457                 /*
6458                  * Something will leak if the above WARN triggers.  Better than
6459                  * a use-after-free.
6460                  */
6461                 if (vmx->loaded_vmcs == &item->vmcs02)
6462                         continue;
6463
6464                 free_loaded_vmcs(&item->vmcs02);
6465                 list_del(&item->list);
6466                 kfree(item);
6467                 vmx->nested.vmcs02_num--;
6468         }
6469 }
6470
6471 /*
6472  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6473  * set the success or error code of an emulated VMX instruction, as specified
6474  * by Vol 2B, VMX Instruction Reference, "Conventions".
6475  */
6476 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6477 {
6478         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6479                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6480                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6481 }
6482
6483 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6484 {
6485         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6486                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6487                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6488                         | X86_EFLAGS_CF);
6489 }
6490
6491 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6492                                         u32 vm_instruction_error)
6493 {
6494         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6495                 /*
6496                  * failValid writes the error number to the current VMCS, which
6497                  * can't be done there isn't a current VMCS.
6498                  */
6499                 nested_vmx_failInvalid(vcpu);
6500                 return;
6501         }
6502         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6503                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6504                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6505                         | X86_EFLAGS_ZF);
6506         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6507         /*
6508          * We don't need to force a shadow sync because
6509          * VM_INSTRUCTION_ERROR is not shadowed
6510          */
6511 }
6512
6513 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6514 {
6515         /* TODO: not to reset guest simply here. */
6516         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6517         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6518 }
6519
6520 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6521 {
6522         struct vcpu_vmx *vmx =
6523                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6524
6525         vmx->nested.preemption_timer_expired = true;
6526         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6527         kvm_vcpu_kick(&vmx->vcpu);
6528
6529         return HRTIMER_NORESTART;
6530 }
6531
6532 /*
6533  * Decode the memory-address operand of a vmx instruction, as recorded on an
6534  * exit caused by such an instruction (run by a guest hypervisor).
6535  * On success, returns 0. When the operand is invalid, returns 1 and throws
6536  * #UD or #GP.
6537  */
6538 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6539                                  unsigned long exit_qualification,
6540                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6541 {
6542         gva_t off;
6543         bool exn;
6544         struct kvm_segment s;
6545
6546         /*
6547          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6548          * Execution", on an exit, vmx_instruction_info holds most of the
6549          * addressing components of the operand. Only the displacement part
6550          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6551          * For how an actual address is calculated from all these components,
6552          * refer to Vol. 1, "Operand Addressing".
6553          */
6554         int  scaling = vmx_instruction_info & 3;
6555         int  addr_size = (vmx_instruction_info >> 7) & 7;
6556         bool is_reg = vmx_instruction_info & (1u << 10);
6557         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6558         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6559         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6560         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6561         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6562
6563         if (is_reg) {
6564                 kvm_queue_exception(vcpu, UD_VECTOR);
6565                 return 1;
6566         }
6567
6568         /* Addr = segment_base + offset */
6569         /* offset = base + [index * scale] + displacement */
6570         off = exit_qualification; /* holds the displacement */
6571         if (base_is_valid)
6572                 off += kvm_register_read(vcpu, base_reg);
6573         if (index_is_valid)
6574                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6575         vmx_get_segment(vcpu, &s, seg_reg);
6576         *ret = s.base + off;
6577
6578         if (addr_size == 1) /* 32 bit */
6579                 *ret &= 0xffffffff;
6580
6581         /* Checks for #GP/#SS exceptions. */
6582         exn = false;
6583         if (is_long_mode(vcpu)) {
6584                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6585                  * non-canonical form. This is the only check on the memory
6586                  * destination for long mode!
6587                  */
6588                 exn = is_noncanonical_address(*ret);
6589         } else if (is_protmode(vcpu)) {
6590                 /* Protected mode: apply checks for segment validity in the
6591                  * following order:
6592                  * - segment type check (#GP(0) may be thrown)
6593                  * - usability check (#GP(0)/#SS(0))
6594                  * - limit check (#GP(0)/#SS(0))
6595                  */
6596                 if (wr)
6597                         /* #GP(0) if the destination operand is located in a
6598                          * read-only data segment or any code segment.
6599                          */
6600                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6601                 else
6602                         /* #GP(0) if the source operand is located in an
6603                          * execute-only code segment
6604                          */
6605                         exn = ((s.type & 0xa) == 8);
6606                 if (exn) {
6607                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6608                         return 1;
6609                 }
6610                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6611                  */
6612                 exn = (s.unusable != 0);
6613                 /* Protected mode: #GP(0)/#SS(0) if the memory
6614                  * operand is outside the segment limit.
6615                  */
6616                 exn = exn || (off + sizeof(u64) > s.limit);
6617         }
6618         if (exn) {
6619                 kvm_queue_exception_e(vcpu,
6620                                       seg_reg == VCPU_SREG_SS ?
6621                                                 SS_VECTOR : GP_VECTOR,
6622                                       0);
6623                 return 1;
6624         }
6625
6626         return 0;
6627 }
6628
6629 /*
6630  * This function performs the various checks including
6631  * - if it's 4KB aligned
6632  * - No bits beyond the physical address width are set
6633  * - Returns 0 on success or else 1
6634  * (Intel SDM Section 30.3)
6635  */
6636 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6637                                   gpa_t *vmpointer)
6638 {
6639         gva_t gva;
6640         gpa_t vmptr;
6641         struct x86_exception e;
6642         struct page *page;
6643         struct vcpu_vmx *vmx = to_vmx(vcpu);
6644         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6645
6646         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6647                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6648                 return 1;
6649
6650         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6651                                 sizeof(vmptr), &e)) {
6652                 kvm_inject_page_fault(vcpu, &e);
6653                 return 1;
6654         }
6655
6656         switch (exit_reason) {
6657         case EXIT_REASON_VMON:
6658                 /*
6659                  * SDM 3: 24.11.5
6660                  * The first 4 bytes of VMXON region contain the supported
6661                  * VMCS revision identifier
6662                  *
6663                  * Note - IA32_VMX_BASIC[48] will never be 1
6664                  * for the nested case;
6665                  * which replaces physical address width with 32
6666                  *
6667                  */
6668                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6669                         nested_vmx_failInvalid(vcpu);
6670                         skip_emulated_instruction(vcpu);
6671                         return 1;
6672                 }
6673
6674                 page = nested_get_page(vcpu, vmptr);
6675                 if (page == NULL ||
6676                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6677                         nested_vmx_failInvalid(vcpu);
6678                         kunmap(page);
6679                         skip_emulated_instruction(vcpu);
6680                         return 1;
6681                 }
6682                 kunmap(page);
6683                 vmx->nested.vmxon_ptr = vmptr;
6684                 break;
6685         case EXIT_REASON_VMCLEAR:
6686                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6687                         nested_vmx_failValid(vcpu,
6688                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6689                         skip_emulated_instruction(vcpu);
6690                         return 1;
6691                 }
6692
6693                 if (vmptr == vmx->nested.vmxon_ptr) {
6694                         nested_vmx_failValid(vcpu,
6695                                              VMXERR_VMCLEAR_VMXON_POINTER);
6696                         skip_emulated_instruction(vcpu);
6697                         return 1;
6698                 }
6699                 break;
6700         case EXIT_REASON_VMPTRLD:
6701                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6702                         nested_vmx_failValid(vcpu,
6703                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6704                         skip_emulated_instruction(vcpu);
6705                         return 1;
6706                 }
6707
6708                 if (vmptr == vmx->nested.vmxon_ptr) {
6709                         nested_vmx_failValid(vcpu,
6710                                              VMXERR_VMCLEAR_VMXON_POINTER);
6711                         skip_emulated_instruction(vcpu);
6712                         return 1;
6713                 }
6714                 break;
6715         default:
6716                 return 1; /* shouldn't happen */
6717         }
6718
6719         if (vmpointer)
6720                 *vmpointer = vmptr;
6721         return 0;
6722 }
6723
6724 /*
6725  * Emulate the VMXON instruction.
6726  * Currently, we just remember that VMX is active, and do not save or even
6727  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6728  * do not currently need to store anything in that guest-allocated memory
6729  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6730  * argument is different from the VMXON pointer (which the spec says they do).
6731  */
6732 static int handle_vmon(struct kvm_vcpu *vcpu)
6733 {
6734         struct kvm_segment cs;
6735         struct vcpu_vmx *vmx = to_vmx(vcpu);
6736         struct vmcs *shadow_vmcs;
6737         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6738                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6739
6740         /* The Intel VMX Instruction Reference lists a bunch of bits that
6741          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6742          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6743          * Otherwise, we should fail with #UD. We test these now:
6744          */
6745         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6746             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6747             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6748                 kvm_queue_exception(vcpu, UD_VECTOR);
6749                 return 1;
6750         }
6751
6752         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6753         if (is_long_mode(vcpu) && !cs.l) {
6754                 kvm_queue_exception(vcpu, UD_VECTOR);
6755                 return 1;
6756         }
6757
6758         if (vmx_get_cpl(vcpu)) {
6759                 kvm_inject_gp(vcpu, 0);
6760                 return 1;
6761         }
6762
6763         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6764                 return 1;
6765
6766         if (vmx->nested.vmxon) {
6767                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6768                 skip_emulated_instruction(vcpu);
6769                 return 1;
6770         }
6771
6772         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6773                         != VMXON_NEEDED_FEATURES) {
6774                 kvm_inject_gp(vcpu, 0);
6775                 return 1;
6776         }
6777
6778         if (enable_shadow_vmcs) {
6779                 shadow_vmcs = alloc_vmcs();
6780                 if (!shadow_vmcs)
6781                         return -ENOMEM;
6782                 /* mark vmcs as shadow */
6783                 shadow_vmcs->revision_id |= (1u << 31);
6784                 /* init shadow vmcs */
6785                 vmcs_clear(shadow_vmcs);
6786                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6787         }
6788
6789         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6790         vmx->nested.vmcs02_num = 0;
6791
6792         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6793                      HRTIMER_MODE_REL);
6794         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6795
6796         vmx->nested.vmxon = true;
6797
6798         skip_emulated_instruction(vcpu);
6799         nested_vmx_succeed(vcpu);
6800         return 1;
6801 }
6802
6803 /*
6804  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6805  * for running VMX instructions (except VMXON, whose prerequisites are
6806  * slightly different). It also specifies what exception to inject otherwise.
6807  */
6808 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6809 {
6810         struct kvm_segment cs;
6811         struct vcpu_vmx *vmx = to_vmx(vcpu);
6812
6813         if (!vmx->nested.vmxon) {
6814                 kvm_queue_exception(vcpu, UD_VECTOR);
6815                 return 0;
6816         }
6817
6818         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6819         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6820             (is_long_mode(vcpu) && !cs.l)) {
6821                 kvm_queue_exception(vcpu, UD_VECTOR);
6822                 return 0;
6823         }
6824
6825         if (vmx_get_cpl(vcpu)) {
6826                 kvm_inject_gp(vcpu, 0);
6827                 return 0;
6828         }
6829
6830         return 1;
6831 }
6832
6833 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6834 {
6835         if (vmx->nested.current_vmptr == -1ull)
6836                 return;
6837
6838         /* current_vmptr and current_vmcs12 are always set/reset together */
6839         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6840                 return;
6841
6842         if (enable_shadow_vmcs) {
6843                 /* copy to memory all shadowed fields in case
6844                    they were modified */
6845                 copy_shadow_to_vmcs12(vmx);
6846                 vmx->nested.sync_shadow_vmcs = false;
6847                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6848                                 SECONDARY_EXEC_SHADOW_VMCS);
6849                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6850         }
6851         vmx->nested.posted_intr_nv = -1;
6852         kunmap(vmx->nested.current_vmcs12_page);
6853         nested_release_page(vmx->nested.current_vmcs12_page);
6854         vmx->nested.current_vmptr = -1ull;
6855         vmx->nested.current_vmcs12 = NULL;
6856 }
6857
6858 /*
6859  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6860  * just stops using VMX.
6861  */
6862 static void free_nested(struct vcpu_vmx *vmx)
6863 {
6864         if (!vmx->nested.vmxon)
6865                 return;
6866
6867         vmx->nested.vmxon = false;
6868         free_vpid(vmx->nested.vpid02);
6869         nested_release_vmcs12(vmx);
6870         if (enable_shadow_vmcs)
6871                 free_vmcs(vmx->nested.current_shadow_vmcs);
6872         /* Unpin physical memory we referred to in current vmcs02 */
6873         if (vmx->nested.apic_access_page) {
6874                 nested_release_page(vmx->nested.apic_access_page);
6875                 vmx->nested.apic_access_page = NULL;
6876         }
6877         if (vmx->nested.virtual_apic_page) {
6878                 nested_release_page(vmx->nested.virtual_apic_page);
6879                 vmx->nested.virtual_apic_page = NULL;
6880         }
6881         if (vmx->nested.pi_desc_page) {
6882                 kunmap(vmx->nested.pi_desc_page);
6883                 nested_release_page(vmx->nested.pi_desc_page);
6884                 vmx->nested.pi_desc_page = NULL;
6885                 vmx->nested.pi_desc = NULL;
6886         }
6887
6888         nested_free_all_saved_vmcss(vmx);
6889 }
6890
6891 /* Emulate the VMXOFF instruction */
6892 static int handle_vmoff(struct kvm_vcpu *vcpu)
6893 {
6894         if (!nested_vmx_check_permission(vcpu))
6895                 return 1;
6896         free_nested(to_vmx(vcpu));
6897         skip_emulated_instruction(vcpu);
6898         nested_vmx_succeed(vcpu);
6899         return 1;
6900 }
6901
6902 /* Emulate the VMCLEAR instruction */
6903 static int handle_vmclear(struct kvm_vcpu *vcpu)
6904 {
6905         struct vcpu_vmx *vmx = to_vmx(vcpu);
6906         gpa_t vmptr;
6907         struct vmcs12 *vmcs12;
6908         struct page *page;
6909
6910         if (!nested_vmx_check_permission(vcpu))
6911                 return 1;
6912
6913         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6914                 return 1;
6915
6916         if (vmptr == vmx->nested.current_vmptr)
6917                 nested_release_vmcs12(vmx);
6918
6919         page = nested_get_page(vcpu, vmptr);
6920         if (page == NULL) {
6921                 /*
6922                  * For accurate processor emulation, VMCLEAR beyond available
6923                  * physical memory should do nothing at all. However, it is
6924                  * possible that a nested vmx bug, not a guest hypervisor bug,
6925                  * resulted in this case, so let's shut down before doing any
6926                  * more damage:
6927                  */
6928                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6929                 return 1;
6930         }
6931         vmcs12 = kmap(page);
6932         vmcs12->launch_state = 0;
6933         kunmap(page);
6934         nested_release_page(page);
6935
6936         nested_free_vmcs02(vmx, vmptr);
6937
6938         skip_emulated_instruction(vcpu);
6939         nested_vmx_succeed(vcpu);
6940         return 1;
6941 }
6942
6943 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6944
6945 /* Emulate the VMLAUNCH instruction */
6946 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6947 {
6948         return nested_vmx_run(vcpu, true);
6949 }
6950
6951 /* Emulate the VMRESUME instruction */
6952 static int handle_vmresume(struct kvm_vcpu *vcpu)
6953 {
6954
6955         return nested_vmx_run(vcpu, false);
6956 }
6957
6958 enum vmcs_field_type {
6959         VMCS_FIELD_TYPE_U16 = 0,
6960         VMCS_FIELD_TYPE_U64 = 1,
6961         VMCS_FIELD_TYPE_U32 = 2,
6962         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6963 };
6964
6965 static inline int vmcs_field_type(unsigned long field)
6966 {
6967         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6968                 return VMCS_FIELD_TYPE_U32;
6969         return (field >> 13) & 0x3 ;
6970 }
6971
6972 static inline int vmcs_field_readonly(unsigned long field)
6973 {
6974         return (((field >> 10) & 0x3) == 1);
6975 }
6976
6977 /*
6978  * Read a vmcs12 field. Since these can have varying lengths and we return
6979  * one type, we chose the biggest type (u64) and zero-extend the return value
6980  * to that size. Note that the caller, handle_vmread, might need to use only
6981  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6982  * 64-bit fields are to be returned).
6983  */
6984 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6985                                   unsigned long field, u64 *ret)
6986 {
6987         short offset = vmcs_field_to_offset(field);
6988         char *p;
6989
6990         if (offset < 0)
6991                 return offset;
6992
6993         p = ((char *)(get_vmcs12(vcpu))) + offset;
6994
6995         switch (vmcs_field_type(field)) {
6996         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6997                 *ret = *((natural_width *)p);
6998                 return 0;
6999         case VMCS_FIELD_TYPE_U16:
7000                 *ret = *((u16 *)p);
7001                 return 0;
7002         case VMCS_FIELD_TYPE_U32:
7003                 *ret = *((u32 *)p);
7004                 return 0;
7005         case VMCS_FIELD_TYPE_U64:
7006                 *ret = *((u64 *)p);
7007                 return 0;
7008         default:
7009                 WARN_ON(1);
7010                 return -ENOENT;
7011         }
7012 }
7013
7014
7015 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7016                                    unsigned long field, u64 field_value){
7017         short offset = vmcs_field_to_offset(field);
7018         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7019         if (offset < 0)
7020                 return offset;
7021
7022         switch (vmcs_field_type(field)) {
7023         case VMCS_FIELD_TYPE_U16:
7024                 *(u16 *)p = field_value;
7025                 return 0;
7026         case VMCS_FIELD_TYPE_U32:
7027                 *(u32 *)p = field_value;
7028                 return 0;
7029         case VMCS_FIELD_TYPE_U64:
7030                 *(u64 *)p = field_value;
7031                 return 0;
7032         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7033                 *(natural_width *)p = field_value;
7034                 return 0;
7035         default:
7036                 WARN_ON(1);
7037                 return -ENOENT;
7038         }
7039
7040 }
7041
7042 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7043 {
7044         int i;
7045         unsigned long field;
7046         u64 field_value;
7047         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7048         const unsigned long *fields = shadow_read_write_fields;
7049         const int num_fields = max_shadow_read_write_fields;
7050
7051         preempt_disable();
7052
7053         vmcs_load(shadow_vmcs);
7054
7055         for (i = 0; i < num_fields; i++) {
7056                 field = fields[i];
7057                 switch (vmcs_field_type(field)) {
7058                 case VMCS_FIELD_TYPE_U16:
7059                         field_value = vmcs_read16(field);
7060                         break;
7061                 case VMCS_FIELD_TYPE_U32:
7062                         field_value = vmcs_read32(field);
7063                         break;
7064                 case VMCS_FIELD_TYPE_U64:
7065                         field_value = vmcs_read64(field);
7066                         break;
7067                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7068                         field_value = vmcs_readl(field);
7069                         break;
7070                 default:
7071                         WARN_ON(1);
7072                         continue;
7073                 }
7074                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7075         }
7076
7077         vmcs_clear(shadow_vmcs);
7078         vmcs_load(vmx->loaded_vmcs->vmcs);
7079
7080         preempt_enable();
7081 }
7082
7083 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7084 {
7085         const unsigned long *fields[] = {
7086                 shadow_read_write_fields,
7087                 shadow_read_only_fields
7088         };
7089         const int max_fields[] = {
7090                 max_shadow_read_write_fields,
7091                 max_shadow_read_only_fields
7092         };
7093         int i, q;
7094         unsigned long field;
7095         u64 field_value = 0;
7096         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7097
7098         vmcs_load(shadow_vmcs);
7099
7100         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7101                 for (i = 0; i < max_fields[q]; i++) {
7102                         field = fields[q][i];
7103                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7104
7105                         switch (vmcs_field_type(field)) {
7106                         case VMCS_FIELD_TYPE_U16:
7107                                 vmcs_write16(field, (u16)field_value);
7108                                 break;
7109                         case VMCS_FIELD_TYPE_U32:
7110                                 vmcs_write32(field, (u32)field_value);
7111                                 break;
7112                         case VMCS_FIELD_TYPE_U64:
7113                                 vmcs_write64(field, (u64)field_value);
7114                                 break;
7115                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7116                                 vmcs_writel(field, (long)field_value);
7117                                 break;
7118                         default:
7119                                 WARN_ON(1);
7120                                 break;
7121                         }
7122                 }
7123         }
7124
7125         vmcs_clear(shadow_vmcs);
7126         vmcs_load(vmx->loaded_vmcs->vmcs);
7127 }
7128
7129 /*
7130  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7131  * used before) all generate the same failure when it is missing.
7132  */
7133 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7134 {
7135         struct vcpu_vmx *vmx = to_vmx(vcpu);
7136         if (vmx->nested.current_vmptr == -1ull) {
7137                 nested_vmx_failInvalid(vcpu);
7138                 skip_emulated_instruction(vcpu);
7139                 return 0;
7140         }
7141         return 1;
7142 }
7143
7144 static int handle_vmread(struct kvm_vcpu *vcpu)
7145 {
7146         unsigned long field;
7147         u64 field_value;
7148         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7149         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7150         gva_t gva = 0;
7151
7152         if (!nested_vmx_check_permission(vcpu) ||
7153             !nested_vmx_check_vmcs12(vcpu))
7154                 return 1;
7155
7156         /* Decode instruction info and find the field to read */
7157         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7158         /* Read the field, zero-extended to a u64 field_value */
7159         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7160                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7161                 skip_emulated_instruction(vcpu);
7162                 return 1;
7163         }
7164         /*
7165          * Now copy part of this value to register or memory, as requested.
7166          * Note that the number of bits actually copied is 32 or 64 depending
7167          * on the guest's mode (32 or 64 bit), not on the given field's length.
7168          */
7169         if (vmx_instruction_info & (1u << 10)) {
7170                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7171                         field_value);
7172         } else {
7173                 if (get_vmx_mem_address(vcpu, exit_qualification,
7174                                 vmx_instruction_info, true, &gva))
7175                         return 1;
7176                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7177                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7178                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7179         }
7180
7181         nested_vmx_succeed(vcpu);
7182         skip_emulated_instruction(vcpu);
7183         return 1;
7184 }
7185
7186
7187 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7188 {
7189         unsigned long field;
7190         gva_t gva;
7191         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7192         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7193         /* The value to write might be 32 or 64 bits, depending on L1's long
7194          * mode, and eventually we need to write that into a field of several
7195          * possible lengths. The code below first zero-extends the value to 64
7196          * bit (field_value), and then copies only the approriate number of
7197          * bits into the vmcs12 field.
7198          */
7199         u64 field_value = 0;
7200         struct x86_exception e;
7201
7202         if (!nested_vmx_check_permission(vcpu) ||
7203             !nested_vmx_check_vmcs12(vcpu))
7204                 return 1;
7205
7206         if (vmx_instruction_info & (1u << 10))
7207                 field_value = kvm_register_readl(vcpu,
7208                         (((vmx_instruction_info) >> 3) & 0xf));
7209         else {
7210                 if (get_vmx_mem_address(vcpu, exit_qualification,
7211                                 vmx_instruction_info, false, &gva))
7212                         return 1;
7213                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7214                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7215                         kvm_inject_page_fault(vcpu, &e);
7216                         return 1;
7217                 }
7218         }
7219
7220
7221         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7222         if (vmcs_field_readonly(field)) {
7223                 nested_vmx_failValid(vcpu,
7224                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7225                 skip_emulated_instruction(vcpu);
7226                 return 1;
7227         }
7228
7229         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7230                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7231                 skip_emulated_instruction(vcpu);
7232                 return 1;
7233         }
7234
7235         nested_vmx_succeed(vcpu);
7236         skip_emulated_instruction(vcpu);
7237         return 1;
7238 }
7239
7240 /* Emulate the VMPTRLD instruction */
7241 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7242 {
7243         struct vcpu_vmx *vmx = to_vmx(vcpu);
7244         gpa_t vmptr;
7245
7246         if (!nested_vmx_check_permission(vcpu))
7247                 return 1;
7248
7249         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7250                 return 1;
7251
7252         if (vmx->nested.current_vmptr != vmptr) {
7253                 struct vmcs12 *new_vmcs12;
7254                 struct page *page;
7255                 page = nested_get_page(vcpu, vmptr);
7256                 if (page == NULL) {
7257                         nested_vmx_failInvalid(vcpu);
7258                         skip_emulated_instruction(vcpu);
7259                         return 1;
7260                 }
7261                 new_vmcs12 = kmap(page);
7262                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7263                         kunmap(page);
7264                         nested_release_page_clean(page);
7265                         nested_vmx_failValid(vcpu,
7266                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7267                         skip_emulated_instruction(vcpu);
7268                         return 1;
7269                 }
7270
7271                 nested_release_vmcs12(vmx);
7272                 vmx->nested.current_vmptr = vmptr;
7273                 vmx->nested.current_vmcs12 = new_vmcs12;
7274                 vmx->nested.current_vmcs12_page = page;
7275                 if (enable_shadow_vmcs) {
7276                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7277                                       SECONDARY_EXEC_SHADOW_VMCS);
7278                         vmcs_write64(VMCS_LINK_POINTER,
7279                                      __pa(vmx->nested.current_shadow_vmcs));
7280                         vmx->nested.sync_shadow_vmcs = true;
7281                 }
7282         }
7283
7284         nested_vmx_succeed(vcpu);
7285         skip_emulated_instruction(vcpu);
7286         return 1;
7287 }
7288
7289 /* Emulate the VMPTRST instruction */
7290 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7291 {
7292         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7293         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7294         gva_t vmcs_gva;
7295         struct x86_exception e;
7296
7297         if (!nested_vmx_check_permission(vcpu))
7298                 return 1;
7299
7300         if (get_vmx_mem_address(vcpu, exit_qualification,
7301                         vmx_instruction_info, true, &vmcs_gva))
7302                 return 1;
7303         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7304         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7305                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7306                                  sizeof(u64), &e)) {
7307                 kvm_inject_page_fault(vcpu, &e);
7308                 return 1;
7309         }
7310         nested_vmx_succeed(vcpu);
7311         skip_emulated_instruction(vcpu);
7312         return 1;
7313 }
7314
7315 /* Emulate the INVEPT instruction */
7316 static int handle_invept(struct kvm_vcpu *vcpu)
7317 {
7318         struct vcpu_vmx *vmx = to_vmx(vcpu);
7319         u32 vmx_instruction_info, types;
7320         unsigned long type;
7321         gva_t gva;
7322         struct x86_exception e;
7323         struct {
7324                 u64 eptp, gpa;
7325         } operand;
7326
7327         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7328               SECONDARY_EXEC_ENABLE_EPT) ||
7329             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7330                 kvm_queue_exception(vcpu, UD_VECTOR);
7331                 return 1;
7332         }
7333
7334         if (!nested_vmx_check_permission(vcpu))
7335                 return 1;
7336
7337         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7338                 kvm_queue_exception(vcpu, UD_VECTOR);
7339                 return 1;
7340         }
7341
7342         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7343         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7344
7345         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7346
7347         if (!(types & (1UL << type))) {
7348                 nested_vmx_failValid(vcpu,
7349                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7350                 skip_emulated_instruction(vcpu);
7351                 return 1;
7352         }
7353
7354         /* According to the Intel VMX instruction reference, the memory
7355          * operand is read even if it isn't needed (e.g., for type==global)
7356          */
7357         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7358                         vmx_instruction_info, false, &gva))
7359                 return 1;
7360         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7361                                 sizeof(operand), &e)) {
7362                 kvm_inject_page_fault(vcpu, &e);
7363                 return 1;
7364         }
7365
7366         switch (type) {
7367         case VMX_EPT_EXTENT_GLOBAL:
7368                 kvm_mmu_sync_roots(vcpu);
7369                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7370                 nested_vmx_succeed(vcpu);
7371                 break;
7372         default:
7373                 /* Trap single context invalidation invept calls */
7374                 BUG_ON(1);
7375                 break;
7376         }
7377
7378         skip_emulated_instruction(vcpu);
7379         return 1;
7380 }
7381
7382 static int handle_invvpid(struct kvm_vcpu *vcpu)
7383 {
7384         struct vcpu_vmx *vmx = to_vmx(vcpu);
7385         u32 vmx_instruction_info;
7386         unsigned long type, types;
7387         gva_t gva;
7388         struct x86_exception e;
7389         int vpid;
7390
7391         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7392               SECONDARY_EXEC_ENABLE_VPID) ||
7393                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7394                 kvm_queue_exception(vcpu, UD_VECTOR);
7395                 return 1;
7396         }
7397
7398         if (!nested_vmx_check_permission(vcpu))
7399                 return 1;
7400
7401         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7402         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7403
7404         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7405
7406         if (!(types & (1UL << type))) {
7407                 nested_vmx_failValid(vcpu,
7408                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7409                 skip_emulated_instruction(vcpu);
7410                 return 1;
7411         }
7412
7413         /* according to the intel vmx instruction reference, the memory
7414          * operand is read even if it isn't needed (e.g., for type==global)
7415          */
7416         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7417                         vmx_instruction_info, false, &gva))
7418                 return 1;
7419         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7420                                 sizeof(u32), &e)) {
7421                 kvm_inject_page_fault(vcpu, &e);
7422                 return 1;
7423         }
7424
7425         switch (type) {
7426         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7427                 /*
7428                  * Old versions of KVM use the single-context version so we
7429                  * have to support it; just treat it the same as all-context.
7430                  */
7431         case VMX_VPID_EXTENT_ALL_CONTEXT:
7432                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7433                 nested_vmx_succeed(vcpu);
7434                 break;
7435         default:
7436                 /* Trap individual address invalidation invvpid calls */
7437                 BUG_ON(1);
7438                 break;
7439         }
7440
7441         skip_emulated_instruction(vcpu);
7442         return 1;
7443 }
7444
7445 static int handle_pml_full(struct kvm_vcpu *vcpu)
7446 {
7447         unsigned long exit_qualification;
7448
7449         trace_kvm_pml_full(vcpu->vcpu_id);
7450
7451         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7452
7453         /*
7454          * PML buffer FULL happened while executing iret from NMI,
7455          * "blocked by NMI" bit has to be set before next VM entry.
7456          */
7457         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7458                         cpu_has_virtual_nmis() &&
7459                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7460                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7461                                 GUEST_INTR_STATE_NMI);
7462
7463         /*
7464          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7465          * here.., and there's no userspace involvement needed for PML.
7466          */
7467         return 1;
7468 }
7469
7470 static int handle_pcommit(struct kvm_vcpu *vcpu)
7471 {
7472         /* we never catch pcommit instruct for L1 guest. */
7473         WARN_ON(1);
7474         return 1;
7475 }
7476
7477 /*
7478  * The exit handlers return 1 if the exit was handled fully and guest execution
7479  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7480  * to be done to userspace and return 0.
7481  */
7482 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7483         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7484         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7485         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7486         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7487         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7488         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7489         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7490         [EXIT_REASON_CPUID]                   = handle_cpuid,
7491         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7492         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7493         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7494         [EXIT_REASON_HLT]                     = handle_halt,
7495         [EXIT_REASON_INVD]                    = handle_invd,
7496         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7497         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7498         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7499         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7500         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7501         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7502         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7503         [EXIT_REASON_VMREAD]                  = handle_vmread,
7504         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7505         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7506         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7507         [EXIT_REASON_VMON]                    = handle_vmon,
7508         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7509         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7510         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7511         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7512         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7513         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7514         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7515         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7516         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7517         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7518         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7519         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7520         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7521         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7522         [EXIT_REASON_INVEPT]                  = handle_invept,
7523         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7524         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7525         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7526         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7527         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7528 };
7529
7530 static const int kvm_vmx_max_exit_handlers =
7531         ARRAY_SIZE(kvm_vmx_exit_handlers);
7532
7533 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7534                                        struct vmcs12 *vmcs12)
7535 {
7536         unsigned long exit_qualification;
7537         gpa_t bitmap, last_bitmap;
7538         unsigned int port;
7539         int size;
7540         u8 b;
7541
7542         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7543                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7544
7545         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7546
7547         port = exit_qualification >> 16;
7548         size = (exit_qualification & 7) + 1;
7549
7550         last_bitmap = (gpa_t)-1;
7551         b = -1;
7552
7553         while (size > 0) {
7554                 if (port < 0x8000)
7555                         bitmap = vmcs12->io_bitmap_a;
7556                 else if (port < 0x10000)
7557                         bitmap = vmcs12->io_bitmap_b;
7558                 else
7559                         return true;
7560                 bitmap += (port & 0x7fff) / 8;
7561
7562                 if (last_bitmap != bitmap)
7563                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7564                                 return true;
7565                 if (b & (1 << (port & 7)))
7566                         return true;
7567
7568                 port++;
7569                 size--;
7570                 last_bitmap = bitmap;
7571         }
7572
7573         return false;
7574 }
7575
7576 /*
7577  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7578  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7579  * disinterest in the current event (read or write a specific MSR) by using an
7580  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7581  */
7582 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7583         struct vmcs12 *vmcs12, u32 exit_reason)
7584 {
7585         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7586         gpa_t bitmap;
7587
7588         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7589                 return true;
7590
7591         /*
7592          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7593          * for the four combinations of read/write and low/high MSR numbers.
7594          * First we need to figure out which of the four to use:
7595          */
7596         bitmap = vmcs12->msr_bitmap;
7597         if (exit_reason == EXIT_REASON_MSR_WRITE)
7598                 bitmap += 2048;
7599         if (msr_index >= 0xc0000000) {
7600                 msr_index -= 0xc0000000;
7601                 bitmap += 1024;
7602         }
7603
7604         /* Then read the msr_index'th bit from this bitmap: */
7605         if (msr_index < 1024*8) {
7606                 unsigned char b;
7607                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7608                         return true;
7609                 return 1 & (b >> (msr_index & 7));
7610         } else
7611                 return true; /* let L1 handle the wrong parameter */
7612 }
7613
7614 /*
7615  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7616  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7617  * intercept (via guest_host_mask etc.) the current event.
7618  */
7619 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7620         struct vmcs12 *vmcs12)
7621 {
7622         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7623         int cr = exit_qualification & 15;
7624         int reg = (exit_qualification >> 8) & 15;
7625         unsigned long val = kvm_register_readl(vcpu, reg);
7626
7627         switch ((exit_qualification >> 4) & 3) {
7628         case 0: /* mov to cr */
7629                 switch (cr) {
7630                 case 0:
7631                         if (vmcs12->cr0_guest_host_mask &
7632                             (val ^ vmcs12->cr0_read_shadow))
7633                                 return true;
7634                         break;
7635                 case 3:
7636                         if ((vmcs12->cr3_target_count >= 1 &&
7637                                         vmcs12->cr3_target_value0 == val) ||
7638                                 (vmcs12->cr3_target_count >= 2 &&
7639                                         vmcs12->cr3_target_value1 == val) ||
7640                                 (vmcs12->cr3_target_count >= 3 &&
7641                                         vmcs12->cr3_target_value2 == val) ||
7642                                 (vmcs12->cr3_target_count >= 4 &&
7643                                         vmcs12->cr3_target_value3 == val))
7644                                 return false;
7645                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7646                                 return true;
7647                         break;
7648                 case 4:
7649                         if (vmcs12->cr4_guest_host_mask &
7650                             (vmcs12->cr4_read_shadow ^ val))
7651                                 return true;
7652                         break;
7653                 case 8:
7654                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7655                                 return true;
7656                         break;
7657                 }
7658                 break;
7659         case 2: /* clts */
7660                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7661                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7662                         return true;
7663                 break;
7664         case 1: /* mov from cr */
7665                 switch (cr) {
7666                 case 3:
7667                         if (vmcs12->cpu_based_vm_exec_control &
7668                             CPU_BASED_CR3_STORE_EXITING)
7669                                 return true;
7670                         break;
7671                 case 8:
7672                         if (vmcs12->cpu_based_vm_exec_control &
7673                             CPU_BASED_CR8_STORE_EXITING)
7674                                 return true;
7675                         break;
7676                 }
7677                 break;
7678         case 3: /* lmsw */
7679                 /*
7680                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7681                  * cr0. Other attempted changes are ignored, with no exit.
7682                  */
7683                 if (vmcs12->cr0_guest_host_mask & 0xe &
7684                     (val ^ vmcs12->cr0_read_shadow))
7685                         return true;
7686                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7687                     !(vmcs12->cr0_read_shadow & 0x1) &&
7688                     (val & 0x1))
7689                         return true;
7690                 break;
7691         }
7692         return false;
7693 }
7694
7695 /*
7696  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7697  * should handle it ourselves in L0 (and then continue L2). Only call this
7698  * when in is_guest_mode (L2).
7699  */
7700 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7701 {
7702         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7703         struct vcpu_vmx *vmx = to_vmx(vcpu);
7704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7705         u32 exit_reason = vmx->exit_reason;
7706
7707         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7708                                 vmcs_readl(EXIT_QUALIFICATION),
7709                                 vmx->idt_vectoring_info,
7710                                 intr_info,
7711                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7712                                 KVM_ISA_VMX);
7713
7714         if (vmx->nested.nested_run_pending)
7715                 return false;
7716
7717         if (unlikely(vmx->fail)) {
7718                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7719                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7720                 return true;
7721         }
7722
7723         switch (exit_reason) {
7724         case EXIT_REASON_EXCEPTION_NMI:
7725                 if (is_nmi(intr_info))
7726                         return false;
7727                 else if (is_page_fault(intr_info))
7728                         return enable_ept;
7729                 else if (is_no_device(intr_info) &&
7730                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7731                         return false;
7732                 return vmcs12->exception_bitmap &
7733                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7734         case EXIT_REASON_EXTERNAL_INTERRUPT:
7735                 return false;
7736         case EXIT_REASON_TRIPLE_FAULT:
7737                 return true;
7738         case EXIT_REASON_PENDING_INTERRUPT:
7739                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7740         case EXIT_REASON_NMI_WINDOW:
7741                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7742         case EXIT_REASON_TASK_SWITCH:
7743                 return true;
7744         case EXIT_REASON_CPUID:
7745                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7746                         return false;
7747                 return true;
7748         case EXIT_REASON_HLT:
7749                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7750         case EXIT_REASON_INVD:
7751                 return true;
7752         case EXIT_REASON_INVLPG:
7753                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7754         case EXIT_REASON_RDPMC:
7755                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7756         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7757                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7758         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7759         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7760         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7761         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7762         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7763         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7764                 /*
7765                  * VMX instructions trap unconditionally. This allows L1 to
7766                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7767                  */
7768                 return true;
7769         case EXIT_REASON_CR_ACCESS:
7770                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7771         case EXIT_REASON_DR_ACCESS:
7772                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7773         case EXIT_REASON_IO_INSTRUCTION:
7774                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7775         case EXIT_REASON_MSR_READ:
7776         case EXIT_REASON_MSR_WRITE:
7777                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7778         case EXIT_REASON_INVALID_STATE:
7779                 return true;
7780         case EXIT_REASON_MWAIT_INSTRUCTION:
7781                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7782         case EXIT_REASON_MONITOR_TRAP_FLAG:
7783                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7784         case EXIT_REASON_MONITOR_INSTRUCTION:
7785                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7786         case EXIT_REASON_PAUSE_INSTRUCTION:
7787                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7788                         nested_cpu_has2(vmcs12,
7789                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7790         case EXIT_REASON_MCE_DURING_VMENTRY:
7791                 return false;
7792         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7793                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7794         case EXIT_REASON_APIC_ACCESS:
7795                 return nested_cpu_has2(vmcs12,
7796                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7797         case EXIT_REASON_APIC_WRITE:
7798         case EXIT_REASON_EOI_INDUCED:
7799                 /* apic_write and eoi_induced should exit unconditionally. */
7800                 return true;
7801         case EXIT_REASON_EPT_VIOLATION:
7802                 /*
7803                  * L0 always deals with the EPT violation. If nested EPT is
7804                  * used, and the nested mmu code discovers that the address is
7805                  * missing in the guest EPT table (EPT12), the EPT violation
7806                  * will be injected with nested_ept_inject_page_fault()
7807                  */
7808                 return false;
7809         case EXIT_REASON_EPT_MISCONFIG:
7810                 /*
7811                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7812                  * table (shadow on EPT) or a merged EPT table that L0 built
7813                  * (EPT on EPT). So any problems with the structure of the
7814                  * table is L0's fault.
7815                  */
7816                 return false;
7817         case EXIT_REASON_WBINVD:
7818                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7819         case EXIT_REASON_XSETBV:
7820                 return true;
7821         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7822                 /*
7823                  * This should never happen, since it is not possible to
7824                  * set XSS to a non-zero value---neither in L1 nor in L2.
7825                  * If if it were, XSS would have to be checked against
7826                  * the XSS exit bitmap in vmcs12.
7827                  */
7828                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7829         case EXIT_REASON_PCOMMIT:
7830                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7831         default:
7832                 return true;
7833         }
7834 }
7835
7836 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7837 {
7838         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7839         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7840 }
7841
7842 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7843 {
7844         struct page *pml_pg;
7845
7846         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7847         if (!pml_pg)
7848                 return -ENOMEM;
7849
7850         vmx->pml_pg = pml_pg;
7851
7852         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7853         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7854
7855         return 0;
7856 }
7857
7858 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7859 {
7860         if (vmx->pml_pg) {
7861                 __free_page(vmx->pml_pg);
7862                 vmx->pml_pg = NULL;
7863         }
7864 }
7865
7866 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7867 {
7868         struct vcpu_vmx *vmx = to_vmx(vcpu);
7869         u64 *pml_buf;
7870         u16 pml_idx;
7871
7872         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7873
7874         /* Do nothing if PML buffer is empty */
7875         if (pml_idx == (PML_ENTITY_NUM - 1))
7876                 return;
7877
7878         /* PML index always points to next available PML buffer entity */
7879         if (pml_idx >= PML_ENTITY_NUM)
7880                 pml_idx = 0;
7881         else
7882                 pml_idx++;
7883
7884         pml_buf = page_address(vmx->pml_pg);
7885         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7886                 u64 gpa;
7887
7888                 gpa = pml_buf[pml_idx];
7889                 WARN_ON(gpa & (PAGE_SIZE - 1));
7890                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7891         }
7892
7893         /* reset PML index */
7894         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7895 }
7896
7897 /*
7898  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7899  * Called before reporting dirty_bitmap to userspace.
7900  */
7901 static void kvm_flush_pml_buffers(struct kvm *kvm)
7902 {
7903         int i;
7904         struct kvm_vcpu *vcpu;
7905         /*
7906          * We only need to kick vcpu out of guest mode here, as PML buffer
7907          * is flushed at beginning of all VMEXITs, and it's obvious that only
7908          * vcpus running in guest are possible to have unflushed GPAs in PML
7909          * buffer.
7910          */
7911         kvm_for_each_vcpu(i, vcpu, kvm)
7912                 kvm_vcpu_kick(vcpu);
7913 }
7914
7915 static void vmx_dump_sel(char *name, uint32_t sel)
7916 {
7917         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7918                name, vmcs_read32(sel),
7919                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7920                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7921                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7922 }
7923
7924 static void vmx_dump_dtsel(char *name, uint32_t limit)
7925 {
7926         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7927                name, vmcs_read32(limit),
7928                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7929 }
7930
7931 static void dump_vmcs(void)
7932 {
7933         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7934         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7935         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7936         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7937         u32 secondary_exec_control = 0;
7938         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7939         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7940         int i, n;
7941
7942         if (cpu_has_secondary_exec_ctrls())
7943                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7944
7945         pr_err("*** Guest State ***\n");
7946         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7947                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7948                vmcs_readl(CR0_GUEST_HOST_MASK));
7949         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7950                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7951         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7952         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7953             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7954         {
7955                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7956                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7957                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7958                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7959         }
7960         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7961                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7962         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7963                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7964         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7965                vmcs_readl(GUEST_SYSENTER_ESP),
7966                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7967         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7968         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7969         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7970         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7971         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7972         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7973         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7974         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7975         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7976         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7977         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7978             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7979                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7980                        efer, vmcs_readl(GUEST_IA32_PAT));
7981         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7982                vmcs_readl(GUEST_IA32_DEBUGCTL),
7983                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7984         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7985                 pr_err("PerfGlobCtl = 0x%016lx\n",
7986                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7987         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7988                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7989         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7990                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7991                vmcs_read32(GUEST_ACTIVITY_STATE));
7992         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7993                 pr_err("InterruptStatus = %04x\n",
7994                        vmcs_read16(GUEST_INTR_STATUS));
7995
7996         pr_err("*** Host State ***\n");
7997         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7998                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7999         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8000                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8001                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8002                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8003                vmcs_read16(HOST_TR_SELECTOR));
8004         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8005                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8006                vmcs_readl(HOST_TR_BASE));
8007         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8008                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8009         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8010                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8011                vmcs_readl(HOST_CR4));
8012         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8013                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8014                vmcs_read32(HOST_IA32_SYSENTER_CS),
8015                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8016         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8017                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
8018                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
8019         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8020                 pr_err("PerfGlobCtl = 0x%016lx\n",
8021                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
8022
8023         pr_err("*** Control State ***\n");
8024         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8025                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8026         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8027         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8028                vmcs_read32(EXCEPTION_BITMAP),
8029                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8030                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8031         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8032                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8033                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8034                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8035         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8036                vmcs_read32(VM_EXIT_INTR_INFO),
8037                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8038                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8039         pr_err("        reason=%08x qualification=%016lx\n",
8040                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8041         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8042                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8043                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8044         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8045         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8046                 pr_err("TSC Multiplier = 0x%016lx\n",
8047                        vmcs_readl(TSC_MULTIPLIER));
8048         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8049                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8050         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8051                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8052         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8053                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8054         n = vmcs_read32(CR3_TARGET_COUNT);
8055         for (i = 0; i + 1 < n; i += 4)
8056                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8057                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8058                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8059         if (i < n)
8060                 pr_err("CR3 target%u=%016lx\n",
8061                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8062         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8063                 pr_err("PLE Gap=%08x Window=%08x\n",
8064                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8065         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8066                 pr_err("Virtual processor ID = 0x%04x\n",
8067                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8068 }
8069
8070 /*
8071  * The guest has exited.  See if we can fix it or if we need userspace
8072  * assistance.
8073  */
8074 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8075 {
8076         struct vcpu_vmx *vmx = to_vmx(vcpu);
8077         u32 exit_reason = vmx->exit_reason;
8078         u32 vectoring_info = vmx->idt_vectoring_info;
8079
8080         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8081
8082         /*
8083          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8084          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8085          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8086          * mode as if vcpus is in root mode, the PML buffer must has been
8087          * flushed already.
8088          */
8089         if (enable_pml)
8090                 vmx_flush_pml_buffer(vcpu);
8091
8092         /* If guest state is invalid, start emulating */
8093         if (vmx->emulation_required)
8094                 return handle_invalid_guest_state(vcpu);
8095
8096         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8097                 nested_vmx_vmexit(vcpu, exit_reason,
8098                                   vmcs_read32(VM_EXIT_INTR_INFO),
8099                                   vmcs_readl(EXIT_QUALIFICATION));
8100                 return 1;
8101         }
8102
8103         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8104                 dump_vmcs();
8105                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8106                 vcpu->run->fail_entry.hardware_entry_failure_reason
8107                         = exit_reason;
8108                 return 0;
8109         }
8110
8111         if (unlikely(vmx->fail)) {
8112                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8113                 vcpu->run->fail_entry.hardware_entry_failure_reason
8114                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8115                 return 0;
8116         }
8117
8118         /*
8119          * Note:
8120          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8121          * delivery event since it indicates guest is accessing MMIO.
8122          * The vm-exit can be triggered again after return to guest that
8123          * will cause infinite loop.
8124          */
8125         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8126                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8127                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8128                         exit_reason != EXIT_REASON_PML_FULL &&
8129                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8130                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8131                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8132                 vcpu->run->internal.ndata = 2;
8133                 vcpu->run->internal.data[0] = vectoring_info;
8134                 vcpu->run->internal.data[1] = exit_reason;
8135                 return 0;
8136         }
8137
8138         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8139             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8140                                         get_vmcs12(vcpu))))) {
8141                 if (vmx_interrupt_allowed(vcpu)) {
8142                         vmx->soft_vnmi_blocked = 0;
8143                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8144                            vcpu->arch.nmi_pending) {
8145                         /*
8146                          * This CPU don't support us in finding the end of an
8147                          * NMI-blocked window if the guest runs with IRQs
8148                          * disabled. So we pull the trigger after 1 s of
8149                          * futile waiting, but inform the user about this.
8150                          */
8151                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8152                                "state on VCPU %d after 1 s timeout\n",
8153                                __func__, vcpu->vcpu_id);
8154                         vmx->soft_vnmi_blocked = 0;
8155                 }
8156         }
8157
8158         if (exit_reason < kvm_vmx_max_exit_handlers
8159             && kvm_vmx_exit_handlers[exit_reason])
8160                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8161         else {
8162                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8163                 kvm_queue_exception(vcpu, UD_VECTOR);
8164                 return 1;
8165         }
8166 }
8167
8168 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8169 {
8170         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8171
8172         if (is_guest_mode(vcpu) &&
8173                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8174                 return;
8175
8176         if (irr == -1 || tpr < irr) {
8177                 vmcs_write32(TPR_THRESHOLD, 0);
8178                 return;
8179         }
8180
8181         vmcs_write32(TPR_THRESHOLD, irr);
8182 }
8183
8184 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8185 {
8186         u32 sec_exec_control;
8187
8188         /* Postpone execution until vmcs01 is the current VMCS. */
8189         if (is_guest_mode(vcpu)) {
8190                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8191                 return;
8192         }
8193
8194         /*
8195          * There is not point to enable virtualize x2apic without enable
8196          * apicv
8197          */
8198         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8199                                 !vmx_cpu_uses_apicv(vcpu))
8200                 return;
8201
8202         if (!cpu_need_tpr_shadow(vcpu))
8203                 return;
8204
8205         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8206
8207         if (set) {
8208                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8209                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8210         } else {
8211                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8212                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8213         }
8214         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8215
8216         vmx_set_msr_bitmap(vcpu);
8217 }
8218
8219 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8220 {
8221         struct vcpu_vmx *vmx = to_vmx(vcpu);
8222
8223         /*
8224          * Currently we do not handle the nested case where L2 has an
8225          * APIC access page of its own; that page is still pinned.
8226          * Hence, we skip the case where the VCPU is in guest mode _and_
8227          * L1 prepared an APIC access page for L2.
8228          *
8229          * For the case where L1 and L2 share the same APIC access page
8230          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8231          * in the vmcs12), this function will only update either the vmcs01
8232          * or the vmcs02.  If the former, the vmcs02 will be updated by
8233          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8234          * the next L2->L1 exit.
8235          */
8236         if (!is_guest_mode(vcpu) ||
8237             !nested_cpu_has2(vmx->nested.current_vmcs12,
8238                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8239                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8240 }
8241
8242 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8243 {
8244         u16 status;
8245         u8 old;
8246
8247         if (isr == -1)
8248                 isr = 0;
8249
8250         status = vmcs_read16(GUEST_INTR_STATUS);
8251         old = status >> 8;
8252         if (isr != old) {
8253                 status &= 0xff;
8254                 status |= isr << 8;
8255                 vmcs_write16(GUEST_INTR_STATUS, status);
8256         }
8257 }
8258
8259 static void vmx_set_rvi(int vector)
8260 {
8261         u16 status;
8262         u8 old;
8263
8264         if (vector == -1)
8265                 vector = 0;
8266
8267         status = vmcs_read16(GUEST_INTR_STATUS);
8268         old = (u8)status & 0xff;
8269         if ((u8)vector != old) {
8270                 status &= ~0xff;
8271                 status |= (u8)vector;
8272                 vmcs_write16(GUEST_INTR_STATUS, status);
8273         }
8274 }
8275
8276 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8277 {
8278         if (!is_guest_mode(vcpu)) {
8279                 vmx_set_rvi(max_irr);
8280                 return;
8281         }
8282
8283         if (max_irr == -1)
8284                 return;
8285
8286         /*
8287          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8288          * handles it.
8289          */
8290         if (nested_exit_on_intr(vcpu))
8291                 return;
8292
8293         /*
8294          * Else, fall back to pre-APICv interrupt injection since L2
8295          * is run without virtual interrupt delivery.
8296          */
8297         if (!kvm_event_needs_reinjection(vcpu) &&
8298             vmx_interrupt_allowed(vcpu)) {
8299                 kvm_queue_interrupt(vcpu, max_irr, false);
8300                 vmx_inject_irq(vcpu);
8301         }
8302 }
8303
8304 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8305 {
8306         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8307         if (!vmx_cpu_uses_apicv(vcpu))
8308                 return;
8309
8310         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8311         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8312         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8313         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8314 }
8315
8316 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8317 {
8318         u32 exit_intr_info;
8319
8320         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8321               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8322                 return;
8323
8324         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8325         exit_intr_info = vmx->exit_intr_info;
8326
8327         /* Handle machine checks before interrupts are enabled */
8328         if (is_machine_check(exit_intr_info))
8329                 kvm_machine_check();
8330
8331         /* We need to handle NMIs before interrupts are enabled */
8332         if (is_nmi(exit_intr_info)) {
8333                 kvm_before_handle_nmi(&vmx->vcpu);
8334                 asm("int $2");
8335                 kvm_after_handle_nmi(&vmx->vcpu);
8336         }
8337 }
8338
8339 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8340 {
8341         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8342
8343         /*
8344          * If external interrupt exists, IF bit is set in rflags/eflags on the
8345          * interrupt stack frame, and interrupt will be enabled on a return
8346          * from interrupt handler.
8347          */
8348         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8349                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8350                 unsigned int vector;
8351                 unsigned long entry;
8352                 gate_desc *desc;
8353                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8354 #ifdef CONFIG_X86_64
8355                 unsigned long tmp;
8356 #endif
8357
8358                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8359                 desc = (gate_desc *)vmx->host_idt_base + vector;
8360                 entry = gate_offset(*desc);
8361                 asm volatile(
8362 #ifdef CONFIG_X86_64
8363                         "mov %%" _ASM_SP ", %[sp]\n\t"
8364                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8365                         "push $%c[ss]\n\t"
8366                         "push %[sp]\n\t"
8367 #endif
8368                         "pushf\n\t"
8369                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8370                         __ASM_SIZE(push) " $%c[cs]\n\t"
8371                         "call *%[entry]\n\t"
8372                         :
8373 #ifdef CONFIG_X86_64
8374                         [sp]"=&r"(tmp)
8375 #endif
8376                         :
8377                         [entry]"r"(entry),
8378                         [ss]"i"(__KERNEL_DS),
8379                         [cs]"i"(__KERNEL_CS)
8380                         );
8381         } else
8382                 local_irq_enable();
8383 }
8384
8385 static bool vmx_has_high_real_mode_segbase(void)
8386 {
8387         return enable_unrestricted_guest || emulate_invalid_guest_state;
8388 }
8389
8390 static bool vmx_mpx_supported(void)
8391 {
8392         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8393                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8394 }
8395
8396 static bool vmx_xsaves_supported(void)
8397 {
8398         return vmcs_config.cpu_based_2nd_exec_ctrl &
8399                 SECONDARY_EXEC_XSAVES;
8400 }
8401
8402 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8403 {
8404         u32 exit_intr_info;
8405         bool unblock_nmi;
8406         u8 vector;
8407         bool idtv_info_valid;
8408
8409         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8410
8411         if (cpu_has_virtual_nmis()) {
8412                 if (vmx->nmi_known_unmasked)
8413                         return;
8414                 /*
8415                  * Can't use vmx->exit_intr_info since we're not sure what
8416                  * the exit reason is.
8417                  */
8418                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8419                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8420                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8421                 /*
8422                  * SDM 3: 27.7.1.2 (September 2008)
8423                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8424                  * a guest IRET fault.
8425                  * SDM 3: 23.2.2 (September 2008)
8426                  * Bit 12 is undefined in any of the following cases:
8427                  *  If the VM exit sets the valid bit in the IDT-vectoring
8428                  *   information field.
8429                  *  If the VM exit is due to a double fault.
8430                  */
8431                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8432                     vector != DF_VECTOR && !idtv_info_valid)
8433                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8434                                       GUEST_INTR_STATE_NMI);
8435                 else
8436                         vmx->nmi_known_unmasked =
8437                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8438                                   & GUEST_INTR_STATE_NMI);
8439         } else if (unlikely(vmx->soft_vnmi_blocked))
8440                 vmx->vnmi_blocked_time +=
8441                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8442 }
8443
8444 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8445                                       u32 idt_vectoring_info,
8446                                       int instr_len_field,
8447                                       int error_code_field)
8448 {
8449         u8 vector;
8450         int type;
8451         bool idtv_info_valid;
8452
8453         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8454
8455         vcpu->arch.nmi_injected = false;
8456         kvm_clear_exception_queue(vcpu);
8457         kvm_clear_interrupt_queue(vcpu);
8458
8459         if (!idtv_info_valid)
8460                 return;
8461
8462         kvm_make_request(KVM_REQ_EVENT, vcpu);
8463
8464         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8465         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8466
8467         switch (type) {
8468         case INTR_TYPE_NMI_INTR:
8469                 vcpu->arch.nmi_injected = true;
8470                 /*
8471                  * SDM 3: 27.7.1.2 (September 2008)
8472                  * Clear bit "block by NMI" before VM entry if a NMI
8473                  * delivery faulted.
8474                  */
8475                 vmx_set_nmi_mask(vcpu, false);
8476                 break;
8477         case INTR_TYPE_SOFT_EXCEPTION:
8478                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8479                 /* fall through */
8480         case INTR_TYPE_HARD_EXCEPTION:
8481                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8482                         u32 err = vmcs_read32(error_code_field);
8483                         kvm_requeue_exception_e(vcpu, vector, err);
8484                 } else
8485                         kvm_requeue_exception(vcpu, vector);
8486                 break;
8487         case INTR_TYPE_SOFT_INTR:
8488                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8489                 /* fall through */
8490         case INTR_TYPE_EXT_INTR:
8491                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8492                 break;
8493         default:
8494                 break;
8495         }
8496 }
8497
8498 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8499 {
8500         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8501                                   VM_EXIT_INSTRUCTION_LEN,
8502                                   IDT_VECTORING_ERROR_CODE);
8503 }
8504
8505 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8506 {
8507         __vmx_complete_interrupts(vcpu,
8508                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8509                                   VM_ENTRY_INSTRUCTION_LEN,
8510                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8511
8512         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8513 }
8514
8515 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8516 {
8517         int i, nr_msrs;
8518         struct perf_guest_switch_msr *msrs;
8519
8520         msrs = perf_guest_get_msrs(&nr_msrs);
8521
8522         if (!msrs)
8523                 return;
8524
8525         for (i = 0; i < nr_msrs; i++)
8526                 if (msrs[i].host == msrs[i].guest)
8527                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8528                 else
8529                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8530                                         msrs[i].host);
8531 }
8532
8533 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8534 {
8535         struct vcpu_vmx *vmx = to_vmx(vcpu);
8536         unsigned long debugctlmsr, cr4;
8537
8538         /* Record the guest's net vcpu time for enforced NMI injections. */
8539         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8540                 vmx->entry_time = ktime_get();
8541
8542         /* Don't enter VMX if guest state is invalid, let the exit handler
8543            start emulation until we arrive back to a valid state */
8544         if (vmx->emulation_required)
8545                 return;
8546
8547         if (vmx->ple_window_dirty) {
8548                 vmx->ple_window_dirty = false;
8549                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8550         }
8551
8552         if (vmx->nested.sync_shadow_vmcs) {
8553                 copy_vmcs12_to_shadow(vmx);
8554                 vmx->nested.sync_shadow_vmcs = false;
8555         }
8556
8557         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8558                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8559         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8560                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8561
8562         cr4 = cr4_read_shadow();
8563         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8564                 vmcs_writel(HOST_CR4, cr4);
8565                 vmx->host_state.vmcs_host_cr4 = cr4;
8566         }
8567
8568         /* When single-stepping over STI and MOV SS, we must clear the
8569          * corresponding interruptibility bits in the guest state. Otherwise
8570          * vmentry fails as it then expects bit 14 (BS) in pending debug
8571          * exceptions being set, but that's not correct for the guest debugging
8572          * case. */
8573         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8574                 vmx_set_interrupt_shadow(vcpu, 0);
8575
8576         atomic_switch_perf_msrs(vmx);
8577         debugctlmsr = get_debugctlmsr();
8578
8579         vmx->__launched = vmx->loaded_vmcs->launched;
8580         asm(
8581                 /* Store host registers */
8582                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8583                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8584                 "push %%" _ASM_CX " \n\t"
8585                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8586                 "je 1f \n\t"
8587                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8588                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8589                 "1: \n\t"
8590                 /* Reload cr2 if changed */
8591                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8592                 "mov %%cr2, %%" _ASM_DX " \n\t"
8593                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8594                 "je 2f \n\t"
8595                 "mov %%" _ASM_AX", %%cr2 \n\t"
8596                 "2: \n\t"
8597                 /* Check if vmlaunch of vmresume is needed */
8598                 "cmpl $0, %c[launched](%0) \n\t"
8599                 /* Load guest registers.  Don't clobber flags. */
8600                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8601                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8602                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8603                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8604                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8605                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8606 #ifdef CONFIG_X86_64
8607                 "mov %c[r8](%0),  %%r8  \n\t"
8608                 "mov %c[r9](%0),  %%r9  \n\t"
8609                 "mov %c[r10](%0), %%r10 \n\t"
8610                 "mov %c[r11](%0), %%r11 \n\t"
8611                 "mov %c[r12](%0), %%r12 \n\t"
8612                 "mov %c[r13](%0), %%r13 \n\t"
8613                 "mov %c[r14](%0), %%r14 \n\t"
8614                 "mov %c[r15](%0), %%r15 \n\t"
8615 #endif
8616                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8617
8618                 /* Enter guest mode */
8619                 "jne 1f \n\t"
8620                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8621                 "jmp 2f \n\t"
8622                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8623                 "2: "
8624                 /* Save guest registers, load host registers, keep flags */
8625                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8626                 "pop %0 \n\t"
8627                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8628                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8629                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8630                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8631                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8632                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8633                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8634 #ifdef CONFIG_X86_64
8635                 "mov %%r8,  %c[r8](%0) \n\t"
8636                 "mov %%r9,  %c[r9](%0) \n\t"
8637                 "mov %%r10, %c[r10](%0) \n\t"
8638                 "mov %%r11, %c[r11](%0) \n\t"
8639                 "mov %%r12, %c[r12](%0) \n\t"
8640                 "mov %%r13, %c[r13](%0) \n\t"
8641                 "mov %%r14, %c[r14](%0) \n\t"
8642                 "mov %%r15, %c[r15](%0) \n\t"
8643 #endif
8644                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8645                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8646
8647                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8648                 "setbe %c[fail](%0) \n\t"
8649                 ".pushsection .rodata \n\t"
8650                 ".global vmx_return \n\t"
8651                 "vmx_return: " _ASM_PTR " 2b \n\t"
8652                 ".popsection"
8653               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8654                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8655                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8656                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8657                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8658                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8659                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8660                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8661                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8662                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8663                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8664 #ifdef CONFIG_X86_64
8665                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8666                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8667                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8668                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8669                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8670                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8671                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8672                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8673 #endif
8674                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8675                 [wordsize]"i"(sizeof(ulong))
8676               : "cc", "memory"
8677 #ifdef CONFIG_X86_64
8678                 , "rax", "rbx", "rdi", "rsi"
8679                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8680 #else
8681                 , "eax", "ebx", "edi", "esi"
8682 #endif
8683               );
8684
8685         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8686         if (debugctlmsr)
8687                 update_debugctlmsr(debugctlmsr);
8688
8689 #ifndef CONFIG_X86_64
8690         /*
8691          * The sysexit path does not restore ds/es, so we must set them to
8692          * a reasonable value ourselves.
8693          *
8694          * We can't defer this to vmx_load_host_state() since that function
8695          * may be executed in interrupt context, which saves and restore segments
8696          * around it, nullifying its effect.
8697          */
8698         loadsegment(ds, __USER_DS);
8699         loadsegment(es, __USER_DS);
8700 #endif
8701
8702         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8703                                   | (1 << VCPU_EXREG_RFLAGS)
8704                                   | (1 << VCPU_EXREG_PDPTR)
8705                                   | (1 << VCPU_EXREG_SEGMENTS)
8706                                   | (1 << VCPU_EXREG_CR3));
8707         vcpu->arch.regs_dirty = 0;
8708
8709         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8710
8711         vmx->loaded_vmcs->launched = 1;
8712
8713         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8714
8715         /*
8716          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8717          * we did not inject a still-pending event to L1 now because of
8718          * nested_run_pending, we need to re-enable this bit.
8719          */
8720         if (vmx->nested.nested_run_pending)
8721                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8722
8723         vmx->nested.nested_run_pending = 0;
8724
8725         vmx_complete_atomic_exit(vmx);
8726         vmx_recover_nmi_blocking(vmx);
8727         vmx_complete_interrupts(vmx);
8728 }
8729
8730 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8731 {
8732         struct vcpu_vmx *vmx = to_vmx(vcpu);
8733         int cpu;
8734
8735         if (vmx->loaded_vmcs == &vmx->vmcs01)
8736                 return;
8737
8738         cpu = get_cpu();
8739         vmx->loaded_vmcs = &vmx->vmcs01;
8740         vmx_vcpu_put(vcpu);
8741         vmx_vcpu_load(vcpu, cpu);
8742         vcpu->cpu = cpu;
8743         put_cpu();
8744 }
8745
8746 /*
8747  * Ensure that the current vmcs of the logical processor is the
8748  * vmcs01 of the vcpu before calling free_nested().
8749  */
8750 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
8751 {
8752        struct vcpu_vmx *vmx = to_vmx(vcpu);
8753        int r;
8754
8755        r = vcpu_load(vcpu);
8756        BUG_ON(r);
8757        vmx_load_vmcs01(vcpu);
8758        free_nested(vmx);
8759        vcpu_put(vcpu);
8760 }
8761
8762 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8763 {
8764         struct vcpu_vmx *vmx = to_vmx(vcpu);
8765
8766         if (enable_pml)
8767                 vmx_destroy_pml_buffer(vmx);
8768         free_vpid(vmx->vpid);
8769         leave_guest_mode(vcpu);
8770         vmx_free_vcpu_nested(vcpu);
8771         free_loaded_vmcs(vmx->loaded_vmcs);
8772         kfree(vmx->guest_msrs);
8773         kvm_vcpu_uninit(vcpu);
8774         kmem_cache_free(kvm_vcpu_cache, vmx);
8775 }
8776
8777 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8778 {
8779         int err;
8780         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8781         int cpu;
8782
8783         if (!vmx)
8784                 return ERR_PTR(-ENOMEM);
8785
8786         vmx->vpid = allocate_vpid();
8787
8788         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8789         if (err)
8790                 goto free_vcpu;
8791
8792         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8793         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8794                      > PAGE_SIZE);
8795
8796         err = -ENOMEM;
8797         if (!vmx->guest_msrs) {
8798                 goto uninit_vcpu;
8799         }
8800
8801         vmx->loaded_vmcs = &vmx->vmcs01;
8802         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8803         if (!vmx->loaded_vmcs->vmcs)
8804                 goto free_msrs;
8805         if (!vmm_exclusive)
8806                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8807         loaded_vmcs_init(vmx->loaded_vmcs);
8808         if (!vmm_exclusive)
8809                 kvm_cpu_vmxoff();
8810
8811         cpu = get_cpu();
8812         vmx_vcpu_load(&vmx->vcpu, cpu);
8813         vmx->vcpu.cpu = cpu;
8814         err = vmx_vcpu_setup(vmx);
8815         vmx_vcpu_put(&vmx->vcpu);
8816         put_cpu();
8817         if (err)
8818                 goto free_vmcs;
8819         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8820                 err = alloc_apic_access_page(kvm);
8821                 if (err)
8822                         goto free_vmcs;
8823         }
8824
8825         if (enable_ept) {
8826                 if (!kvm->arch.ept_identity_map_addr)
8827                         kvm->arch.ept_identity_map_addr =
8828                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8829                 err = init_rmode_identity_map(kvm);
8830                 if (err)
8831                         goto free_vmcs;
8832         }
8833
8834         if (nested) {
8835                 nested_vmx_setup_ctls_msrs(vmx);
8836                 vmx->nested.vpid02 = allocate_vpid();
8837         }
8838
8839         vmx->nested.posted_intr_nv = -1;
8840         vmx->nested.current_vmptr = -1ull;
8841         vmx->nested.current_vmcs12 = NULL;
8842
8843         /*
8844          * If PML is turned on, failure on enabling PML just results in failure
8845          * of creating the vcpu, therefore we can simplify PML logic (by
8846          * avoiding dealing with cases, such as enabling PML partially on vcpus
8847          * for the guest, etc.
8848          */
8849         if (enable_pml) {
8850                 err = vmx_create_pml_buffer(vmx);
8851                 if (err)
8852                         goto free_vmcs;
8853         }
8854
8855         return &vmx->vcpu;
8856
8857 free_vmcs:
8858         free_vpid(vmx->nested.vpid02);
8859         free_loaded_vmcs(vmx->loaded_vmcs);
8860 free_msrs:
8861         kfree(vmx->guest_msrs);
8862 uninit_vcpu:
8863         kvm_vcpu_uninit(&vmx->vcpu);
8864 free_vcpu:
8865         free_vpid(vmx->vpid);
8866         kmem_cache_free(kvm_vcpu_cache, vmx);
8867         return ERR_PTR(err);
8868 }
8869
8870 static void __init vmx_check_processor_compat(void *rtn)
8871 {
8872         struct vmcs_config vmcs_conf;
8873
8874         *(int *)rtn = 0;
8875         if (setup_vmcs_config(&vmcs_conf) < 0)
8876                 *(int *)rtn = -EIO;
8877         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8878                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8879                                 smp_processor_id());
8880                 *(int *)rtn = -EIO;
8881         }
8882 }
8883
8884 static int get_ept_level(void)
8885 {
8886         return VMX_EPT_DEFAULT_GAW + 1;
8887 }
8888
8889 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8890 {
8891         u8 cache;
8892         u64 ipat = 0;
8893
8894         /* For VT-d and EPT combination
8895          * 1. MMIO: always map as UC
8896          * 2. EPT with VT-d:
8897          *   a. VT-d without snooping control feature: can't guarantee the
8898          *      result, try to trust guest.
8899          *   b. VT-d with snooping control feature: snooping control feature of
8900          *      VT-d engine can guarantee the cache correctness. Just set it
8901          *      to WB to keep consistent with host. So the same as item 3.
8902          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8903          *    consistent with host MTRR
8904          */
8905         if (is_mmio) {
8906                 cache = MTRR_TYPE_UNCACHABLE;
8907                 goto exit;
8908         }
8909
8910         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8911                 ipat = VMX_EPT_IPAT_BIT;
8912                 cache = MTRR_TYPE_WRBACK;
8913                 goto exit;
8914         }
8915
8916         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8917                 ipat = VMX_EPT_IPAT_BIT;
8918                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8919                         cache = MTRR_TYPE_WRBACK;
8920                 else
8921                         cache = MTRR_TYPE_UNCACHABLE;
8922                 goto exit;
8923         }
8924
8925         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8926
8927 exit:
8928         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8929 }
8930
8931 static int vmx_get_lpage_level(void)
8932 {
8933         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8934                 return PT_DIRECTORY_LEVEL;
8935         else
8936                 /* For shadow and EPT supported 1GB page */
8937                 return PT_PDPE_LEVEL;
8938 }
8939
8940 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8941 {
8942         /*
8943          * These bits in the secondary execution controls field
8944          * are dynamic, the others are mostly based on the hypervisor
8945          * architecture and the guest's CPUID.  Do not touch the
8946          * dynamic bits.
8947          */
8948         u32 mask =
8949                 SECONDARY_EXEC_SHADOW_VMCS |
8950                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8951                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8952
8953         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8954
8955         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8956                      (new_ctl & ~mask) | (cur_ctl & mask));
8957 }
8958
8959 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8960 {
8961         struct kvm_cpuid_entry2 *best;
8962         struct vcpu_vmx *vmx = to_vmx(vcpu);
8963         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8964
8965         if (vmx_rdtscp_supported()) {
8966                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8967                 if (!rdtscp_enabled)
8968                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8969
8970                 if (nested) {
8971                         if (rdtscp_enabled)
8972                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8973                                         SECONDARY_EXEC_RDTSCP;
8974                         else
8975                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8976                                         ~SECONDARY_EXEC_RDTSCP;
8977                 }
8978         }
8979
8980         /* Exposing INVPCID only when PCID is exposed */
8981         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8982         if (vmx_invpcid_supported() &&
8983             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8984             !guest_cpuid_has_pcid(vcpu))) {
8985                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8986
8987                 if (best)
8988                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8989         }
8990
8991         if (cpu_has_secondary_exec_ctrls())
8992                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8993
8994         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8995                 if (guest_cpuid_has_pcommit(vcpu))
8996                         vmx->nested.nested_vmx_secondary_ctls_high |=
8997                                 SECONDARY_EXEC_PCOMMIT;
8998                 else
8999                         vmx->nested.nested_vmx_secondary_ctls_high &=
9000                                 ~SECONDARY_EXEC_PCOMMIT;
9001         }
9002 }
9003
9004 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9005 {
9006         if (func == 1 && nested)
9007                 entry->ecx |= bit(X86_FEATURE_VMX);
9008 }
9009
9010 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9011                 struct x86_exception *fault)
9012 {
9013         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9014         u32 exit_reason;
9015
9016         if (fault->error_code & PFERR_RSVD_MASK)
9017                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9018         else
9019                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9020         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9021         vmcs12->guest_physical_address = fault->address;
9022 }
9023
9024 /* Callbacks for nested_ept_init_mmu_context: */
9025
9026 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9027 {
9028         /* return the page table to be shadowed - in our case, EPT12 */
9029         return get_vmcs12(vcpu)->ept_pointer;
9030 }
9031
9032 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9033 {
9034         WARN_ON(mmu_is_nested(vcpu));
9035         kvm_init_shadow_ept_mmu(vcpu,
9036                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9037                         VMX_EPT_EXECUTE_ONLY_BIT);
9038         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9039         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9040         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9041
9042         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9043 }
9044
9045 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9046 {
9047         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9048 }
9049
9050 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9051                                             u16 error_code)
9052 {
9053         bool inequality, bit;
9054
9055         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9056         inequality =
9057                 (error_code & vmcs12->page_fault_error_code_mask) !=
9058                  vmcs12->page_fault_error_code_match;
9059         return inequality ^ bit;
9060 }
9061
9062 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9063                 struct x86_exception *fault)
9064 {
9065         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9066
9067         WARN_ON(!is_guest_mode(vcpu));
9068
9069         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9070                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9071                                   vmcs_read32(VM_EXIT_INTR_INFO),
9072                                   vmcs_readl(EXIT_QUALIFICATION));
9073         else
9074                 kvm_inject_page_fault(vcpu, fault);
9075 }
9076
9077 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9078                                         struct vmcs12 *vmcs12)
9079 {
9080         struct vcpu_vmx *vmx = to_vmx(vcpu);
9081         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9082
9083         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9084                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9085                     vmcs12->apic_access_addr >> maxphyaddr)
9086                         return false;
9087
9088                 /*
9089                  * Translate L1 physical address to host physical
9090                  * address for vmcs02. Keep the page pinned, so this
9091                  * physical address remains valid. We keep a reference
9092                  * to it so we can release it later.
9093                  */
9094                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9095                         nested_release_page(vmx->nested.apic_access_page);
9096                 vmx->nested.apic_access_page =
9097                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9098         }
9099
9100         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9101                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9102                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9103                         return false;
9104
9105                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9106                         nested_release_page(vmx->nested.virtual_apic_page);
9107                 vmx->nested.virtual_apic_page =
9108                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9109
9110                 /*
9111                  * Failing the vm entry is _not_ what the processor does
9112                  * but it's basically the only possibility we have.
9113                  * We could still enter the guest if CR8 load exits are
9114                  * enabled, CR8 store exits are enabled, and virtualize APIC
9115                  * access is disabled; in this case the processor would never
9116                  * use the TPR shadow and we could simply clear the bit from
9117                  * the execution control.  But such a configuration is useless,
9118                  * so let's keep the code simple.
9119                  */
9120                 if (!vmx->nested.virtual_apic_page)
9121                         return false;
9122         }
9123
9124         if (nested_cpu_has_posted_intr(vmcs12)) {
9125                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9126                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9127                         return false;
9128
9129                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9130                         kunmap(vmx->nested.pi_desc_page);
9131                         nested_release_page(vmx->nested.pi_desc_page);
9132                 }
9133                 vmx->nested.pi_desc_page =
9134                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9135                 if (!vmx->nested.pi_desc_page)
9136                         return false;
9137
9138                 vmx->nested.pi_desc =
9139                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9140                 if (!vmx->nested.pi_desc) {
9141                         nested_release_page_clean(vmx->nested.pi_desc_page);
9142                         return false;
9143                 }
9144                 vmx->nested.pi_desc =
9145                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9146                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9147                         (PAGE_SIZE - 1)));
9148         }
9149
9150         return true;
9151 }
9152
9153 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9154 {
9155         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9156         struct vcpu_vmx *vmx = to_vmx(vcpu);
9157
9158         if (vcpu->arch.virtual_tsc_khz == 0)
9159                 return;
9160
9161         /* Make sure short timeouts reliably trigger an immediate vmexit.
9162          * hrtimer_start does not guarantee this. */
9163         if (preemption_timeout <= 1) {
9164                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9165                 return;
9166         }
9167
9168         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9169         preemption_timeout *= 1000000;
9170         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9171         hrtimer_start(&vmx->nested.preemption_timer,
9172                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9173 }
9174
9175 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9176                                                 struct vmcs12 *vmcs12)
9177 {
9178         int maxphyaddr;
9179         u64 addr;
9180
9181         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9182                 return 0;
9183
9184         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9185                 WARN_ON(1);
9186                 return -EINVAL;
9187         }
9188         maxphyaddr = cpuid_maxphyaddr(vcpu);
9189
9190         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9191            ((addr + PAGE_SIZE) >> maxphyaddr))
9192                 return -EINVAL;
9193
9194         return 0;
9195 }
9196
9197 /*
9198  * Merge L0's and L1's MSR bitmap, return false to indicate that
9199  * we do not use the hardware.
9200  */
9201 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9202                                                struct vmcs12 *vmcs12)
9203 {
9204         int msr;
9205         struct page *page;
9206         unsigned long *msr_bitmap;
9207
9208         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9209                 return false;
9210
9211         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9212         if (!page) {
9213                 WARN_ON(1);
9214                 return false;
9215         }
9216         msr_bitmap = (unsigned long *)kmap(page);
9217         if (!msr_bitmap) {
9218                 nested_release_page_clean(page);
9219                 WARN_ON(1);
9220                 return false;
9221         }
9222
9223         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9224                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9225                         for (msr = 0x800; msr <= 0x8ff; msr++)
9226                                 nested_vmx_disable_intercept_for_msr(
9227                                         msr_bitmap,
9228                                         vmx_msr_bitmap_nested,
9229                                         msr, MSR_TYPE_R);
9230                 /* TPR is allowed */
9231                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9232                                 vmx_msr_bitmap_nested,
9233                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9234                                 MSR_TYPE_R | MSR_TYPE_W);
9235                 if (nested_cpu_has_vid(vmcs12)) {
9236                         /* EOI and self-IPI are allowed */
9237                         nested_vmx_disable_intercept_for_msr(
9238                                 msr_bitmap,
9239                                 vmx_msr_bitmap_nested,
9240                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9241                                 MSR_TYPE_W);
9242                         nested_vmx_disable_intercept_for_msr(
9243                                 msr_bitmap,
9244                                 vmx_msr_bitmap_nested,
9245                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9246                                 MSR_TYPE_W);
9247                 }
9248         } else {
9249                 /*
9250                  * Enable reading intercept of all the x2apic
9251                  * MSRs. We should not rely on vmcs12 to do any
9252                  * optimizations here, it may have been modified
9253                  * by L1.
9254                  */
9255                 for (msr = 0x800; msr <= 0x8ff; msr++)
9256                         __vmx_enable_intercept_for_msr(
9257                                 vmx_msr_bitmap_nested,
9258                                 msr,
9259                                 MSR_TYPE_R);
9260
9261                 __vmx_enable_intercept_for_msr(
9262                                 vmx_msr_bitmap_nested,
9263                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9264                                 MSR_TYPE_W);
9265                 __vmx_enable_intercept_for_msr(
9266                                 vmx_msr_bitmap_nested,
9267                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9268                                 MSR_TYPE_W);
9269                 __vmx_enable_intercept_for_msr(
9270                                 vmx_msr_bitmap_nested,
9271                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9272                                 MSR_TYPE_W);
9273         }
9274         kunmap(page);
9275         nested_release_page_clean(page);
9276
9277         return true;
9278 }
9279
9280 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9281                                            struct vmcs12 *vmcs12)
9282 {
9283         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9284             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9285             !nested_cpu_has_vid(vmcs12) &&
9286             !nested_cpu_has_posted_intr(vmcs12))
9287                 return 0;
9288
9289         /*
9290          * If virtualize x2apic mode is enabled,
9291          * virtualize apic access must be disabled.
9292          */
9293         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9294             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9295                 return -EINVAL;
9296
9297         /*
9298          * If virtual interrupt delivery is enabled,
9299          * we must exit on external interrupts.
9300          */
9301         if (nested_cpu_has_vid(vmcs12) &&
9302            !nested_exit_on_intr(vcpu))
9303                 return -EINVAL;
9304
9305         /*
9306          * bits 15:8 should be zero in posted_intr_nv,
9307          * the descriptor address has been already checked
9308          * in nested_get_vmcs12_pages.
9309          */
9310         if (nested_cpu_has_posted_intr(vmcs12) &&
9311            (!nested_cpu_has_vid(vmcs12) ||
9312             !nested_exit_intr_ack_set(vcpu) ||
9313             vmcs12->posted_intr_nv & 0xff00))
9314                 return -EINVAL;
9315
9316         /* tpr shadow is needed by all apicv features. */
9317         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9318                 return -EINVAL;
9319
9320         return 0;
9321 }
9322
9323 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9324                                        unsigned long count_field,
9325                                        unsigned long addr_field)
9326 {
9327         int maxphyaddr;
9328         u64 count, addr;
9329
9330         if (vmcs12_read_any(vcpu, count_field, &count) ||
9331             vmcs12_read_any(vcpu, addr_field, &addr)) {
9332                 WARN_ON(1);
9333                 return -EINVAL;
9334         }
9335         if (count == 0)
9336                 return 0;
9337         maxphyaddr = cpuid_maxphyaddr(vcpu);
9338         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9339             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9340                 pr_warn_ratelimited(
9341                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9342                         addr_field, maxphyaddr, count, addr);
9343                 return -EINVAL;
9344         }
9345         return 0;
9346 }
9347
9348 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9349                                                 struct vmcs12 *vmcs12)
9350 {
9351         if (vmcs12->vm_exit_msr_load_count == 0 &&
9352             vmcs12->vm_exit_msr_store_count == 0 &&
9353             vmcs12->vm_entry_msr_load_count == 0)
9354                 return 0; /* Fast path */
9355         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9356                                         VM_EXIT_MSR_LOAD_ADDR) ||
9357             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9358                                         VM_EXIT_MSR_STORE_ADDR) ||
9359             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9360                                         VM_ENTRY_MSR_LOAD_ADDR))
9361                 return -EINVAL;
9362         return 0;
9363 }
9364
9365 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9366                                        struct vmx_msr_entry *e)
9367 {
9368         /* x2APIC MSR accesses are not allowed */
9369         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9370                 return -EINVAL;
9371         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9372             e->index == MSR_IA32_UCODE_REV)
9373                 return -EINVAL;
9374         if (e->reserved != 0)
9375                 return -EINVAL;
9376         return 0;
9377 }
9378
9379 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9380                                      struct vmx_msr_entry *e)
9381 {
9382         if (e->index == MSR_FS_BASE ||
9383             e->index == MSR_GS_BASE ||
9384             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9385             nested_vmx_msr_check_common(vcpu, e))
9386                 return -EINVAL;
9387         return 0;
9388 }
9389
9390 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9391                                       struct vmx_msr_entry *e)
9392 {
9393         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9394             nested_vmx_msr_check_common(vcpu, e))
9395                 return -EINVAL;
9396         return 0;
9397 }
9398
9399 /*
9400  * Load guest's/host's msr at nested entry/exit.
9401  * return 0 for success, entry index for failure.
9402  */
9403 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9404 {
9405         u32 i;
9406         struct vmx_msr_entry e;
9407         struct msr_data msr;
9408
9409         msr.host_initiated = false;
9410         for (i = 0; i < count; i++) {
9411                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9412                                         &e, sizeof(e))) {
9413                         pr_warn_ratelimited(
9414                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9415                                 __func__, i, gpa + i * sizeof(e));
9416                         goto fail;
9417                 }
9418                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9419                         pr_warn_ratelimited(
9420                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9421                                 __func__, i, e.index, e.reserved);
9422                         goto fail;
9423                 }
9424                 msr.index = e.index;
9425                 msr.data = e.value;
9426                 if (kvm_set_msr(vcpu, &msr)) {
9427                         pr_warn_ratelimited(
9428                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9429                                 __func__, i, e.index, e.value);
9430                         goto fail;
9431                 }
9432         }
9433         return 0;
9434 fail:
9435         return i + 1;
9436 }
9437
9438 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9439 {
9440         u32 i;
9441         struct vmx_msr_entry e;
9442
9443         for (i = 0; i < count; i++) {
9444                 struct msr_data msr_info;
9445                 if (kvm_vcpu_read_guest(vcpu,
9446                                         gpa + i * sizeof(e),
9447                                         &e, 2 * sizeof(u32))) {
9448                         pr_warn_ratelimited(
9449                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9450                                 __func__, i, gpa + i * sizeof(e));
9451                         return -EINVAL;
9452                 }
9453                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9454                         pr_warn_ratelimited(
9455                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9456                                 __func__, i, e.index, e.reserved);
9457                         return -EINVAL;
9458                 }
9459                 msr_info.host_initiated = false;
9460                 msr_info.index = e.index;
9461                 if (kvm_get_msr(vcpu, &msr_info)) {
9462                         pr_warn_ratelimited(
9463                                 "%s cannot read MSR (%u, 0x%x)\n",
9464                                 __func__, i, e.index);
9465                         return -EINVAL;
9466                 }
9467                 if (kvm_vcpu_write_guest(vcpu,
9468                                          gpa + i * sizeof(e) +
9469                                              offsetof(struct vmx_msr_entry, value),
9470                                          &msr_info.data, sizeof(msr_info.data))) {
9471                         pr_warn_ratelimited(
9472                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9473                                 __func__, i, e.index, msr_info.data);
9474                         return -EINVAL;
9475                 }
9476         }
9477         return 0;
9478 }
9479
9480 /*
9481  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9482  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9483  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9484  * guest in a way that will both be appropriate to L1's requests, and our
9485  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9486  * function also has additional necessary side-effects, like setting various
9487  * vcpu->arch fields.
9488  */
9489 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9490 {
9491         struct vcpu_vmx *vmx = to_vmx(vcpu);
9492         u32 exec_control;
9493
9494         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9495         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9496         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9497         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9498         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9499         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9500         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9501         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9502         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9503         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9504         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9505         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9506         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9507         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9508         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9509         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9510         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9511         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9512         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9513         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9514         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9515         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9516         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9517         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9518         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9519         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9520         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9521         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9522         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9523         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9524         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9525         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9526         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9527         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9528         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9529         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9530
9531         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9532                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9533                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9534         } else {
9535                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9536                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9537         }
9538         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9539                 vmcs12->vm_entry_intr_info_field);
9540         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9541                 vmcs12->vm_entry_exception_error_code);
9542         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9543                 vmcs12->vm_entry_instruction_len);
9544         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9545                 vmcs12->guest_interruptibility_info);
9546         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9547         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9548         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9549                 vmcs12->guest_pending_dbg_exceptions);
9550         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9551         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9552
9553         if (nested_cpu_has_xsaves(vmcs12))
9554                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9555         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9556
9557         exec_control = vmcs12->pin_based_vm_exec_control;
9558         exec_control |= vmcs_config.pin_based_exec_ctrl;
9559         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9560
9561         if (nested_cpu_has_posted_intr(vmcs12)) {
9562                 /*
9563                  * Note that we use L0's vector here and in
9564                  * vmx_deliver_nested_posted_interrupt.
9565                  */
9566                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9567                 vmx->nested.pi_pending = false;
9568                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9569                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9570                         page_to_phys(vmx->nested.pi_desc_page) +
9571                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9572                         (PAGE_SIZE - 1)));
9573         } else
9574                 exec_control &= ~PIN_BASED_POSTED_INTR;
9575
9576         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9577
9578         vmx->nested.preemption_timer_expired = false;
9579         if (nested_cpu_has_preemption_timer(vmcs12))
9580                 vmx_start_preemption_timer(vcpu);
9581
9582         /*
9583          * Whether page-faults are trapped is determined by a combination of
9584          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9585          * If enable_ept, L0 doesn't care about page faults and we should
9586          * set all of these to L1's desires. However, if !enable_ept, L0 does
9587          * care about (at least some) page faults, and because it is not easy
9588          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9589          * to exit on each and every L2 page fault. This is done by setting
9590          * MASK=MATCH=0 and (see below) EB.PF=1.
9591          * Note that below we don't need special code to set EB.PF beyond the
9592          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9593          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9594          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9595          *
9596          * A problem with this approach (when !enable_ept) is that L1 may be
9597          * injected with more page faults than it asked for. This could have
9598          * caused problems, but in practice existing hypervisors don't care.
9599          * To fix this, we will need to emulate the PFEC checking (on the L1
9600          * page tables), using walk_addr(), when injecting PFs to L1.
9601          */
9602         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9603                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9604         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9605                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9606
9607         if (cpu_has_secondary_exec_ctrls()) {
9608                 exec_control = vmx_secondary_exec_control(vmx);
9609
9610                 /* Take the following fields only from vmcs12 */
9611                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9612                                   SECONDARY_EXEC_RDTSCP |
9613                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9614                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9615                                   SECONDARY_EXEC_PCOMMIT);
9616                 if (nested_cpu_has(vmcs12,
9617                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9618                         exec_control |= vmcs12->secondary_vm_exec_control;
9619
9620                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9621                         /*
9622                          * If translation failed, no matter: This feature asks
9623                          * to exit when accessing the given address, and if it
9624                          * can never be accessed, this feature won't do
9625                          * anything anyway.
9626                          */
9627                         if (!vmx->nested.apic_access_page)
9628                                 exec_control &=
9629                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9630                         else
9631                                 vmcs_write64(APIC_ACCESS_ADDR,
9632                                   page_to_phys(vmx->nested.apic_access_page));
9633                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9634                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9635                         exec_control |=
9636                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9637                         kvm_vcpu_reload_apic_access_page(vcpu);
9638                 }
9639
9640                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9641                         vmcs_write64(EOI_EXIT_BITMAP0,
9642                                 vmcs12->eoi_exit_bitmap0);
9643                         vmcs_write64(EOI_EXIT_BITMAP1,
9644                                 vmcs12->eoi_exit_bitmap1);
9645                         vmcs_write64(EOI_EXIT_BITMAP2,
9646                                 vmcs12->eoi_exit_bitmap2);
9647                         vmcs_write64(EOI_EXIT_BITMAP3,
9648                                 vmcs12->eoi_exit_bitmap3);
9649                         vmcs_write16(GUEST_INTR_STATUS,
9650                                 vmcs12->guest_intr_status);
9651                 }
9652
9653                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9654         }
9655
9656
9657         /*
9658          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9659          * Some constant fields are set here by vmx_set_constant_host_state().
9660          * Other fields are different per CPU, and will be set later when
9661          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9662          */
9663         vmx_set_constant_host_state(vmx);
9664
9665         /*
9666          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9667          * entry, but only if the current (host) sp changed from the value
9668          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9669          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9670          * here we just force the write to happen on entry.
9671          */
9672         vmx->host_rsp = 0;
9673
9674         exec_control = vmx_exec_control(vmx); /* L0's desires */
9675         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9676         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9677         exec_control &= ~CPU_BASED_TPR_SHADOW;
9678         exec_control |= vmcs12->cpu_based_vm_exec_control;
9679
9680         if (exec_control & CPU_BASED_TPR_SHADOW) {
9681                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9682                                 page_to_phys(vmx->nested.virtual_apic_page));
9683                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9684         }
9685
9686         if (cpu_has_vmx_msr_bitmap() &&
9687             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9688                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9689                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9690         } else
9691                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9692
9693         /*
9694          * Merging of IO bitmap not currently supported.
9695          * Rather, exit every time.
9696          */
9697         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9698         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9699
9700         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9701
9702         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9703          * bitwise-or of what L1 wants to trap for L2, and what we want to
9704          * trap. Note that CR0.TS also needs updating - we do this later.
9705          */
9706         update_exception_bitmap(vcpu);
9707         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9708         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9709
9710         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9711          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9712          * bits are further modified by vmx_set_efer() below.
9713          */
9714         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9715
9716         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9717          * emulated by vmx_set_efer(), below.
9718          */
9719         vm_entry_controls_init(vmx,
9720                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9721                         ~VM_ENTRY_IA32E_MODE) |
9722                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9723
9724         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9725                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9726                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9727         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9728                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9729
9730
9731         set_cr4_guest_host_mask(vmx);
9732
9733         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9734                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9735
9736         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9737                 vmcs_write64(TSC_OFFSET,
9738                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9739         else
9740                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9741
9742         if (enable_vpid) {
9743                 /*
9744                  * There is no direct mapping between vpid02 and vpid12, the
9745                  * vpid02 is per-vCPU for L0 and reused while the value of
9746                  * vpid12 is changed w/ one invvpid during nested vmentry.
9747                  * The vpid12 is allocated by L1 for L2, so it will not
9748                  * influence global bitmap(for vpid01 and vpid02 allocation)
9749                  * even if spawn a lot of nested vCPUs.
9750                  */
9751                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9752                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9753                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9754                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9755                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9756                         }
9757                 } else {
9758                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9759                         vmx_flush_tlb(vcpu);
9760                 }
9761
9762         }
9763
9764         if (nested_cpu_has_ept(vmcs12)) {
9765                 kvm_mmu_unload(vcpu);
9766                 nested_ept_init_mmu_context(vcpu);
9767         }
9768
9769         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9770                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9771         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9772                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9773         else
9774                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9775         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9776         vmx_set_efer(vcpu, vcpu->arch.efer);
9777
9778         /*
9779          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9780          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9781          * The CR0_READ_SHADOW is what L2 should have expected to read given
9782          * the specifications by L1; It's not enough to take
9783          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9784          * have more bits than L1 expected.
9785          */
9786         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9787         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9788
9789         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9790         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9791
9792         /* shadow page tables on either EPT or shadow page tables */
9793         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9794         kvm_mmu_reset_context(vcpu);
9795
9796         if (!enable_ept)
9797                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9798
9799         /*
9800          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9801          */
9802         if (enable_ept) {
9803                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9804                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9805                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9806                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9807         }
9808
9809         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9810         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9811 }
9812
9813 /*
9814  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9815  * for running an L2 nested guest.
9816  */
9817 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9818 {
9819         struct vmcs12 *vmcs12;
9820         struct vcpu_vmx *vmx = to_vmx(vcpu);
9821         int cpu;
9822         struct loaded_vmcs *vmcs02;
9823         bool ia32e;
9824         u32 msr_entry_idx;
9825
9826         if (!nested_vmx_check_permission(vcpu) ||
9827             !nested_vmx_check_vmcs12(vcpu))
9828                 return 1;
9829
9830         skip_emulated_instruction(vcpu);
9831         vmcs12 = get_vmcs12(vcpu);
9832
9833         if (enable_shadow_vmcs)
9834                 copy_shadow_to_vmcs12(vmx);
9835
9836         /*
9837          * The nested entry process starts with enforcing various prerequisites
9838          * on vmcs12 as required by the Intel SDM, and act appropriately when
9839          * they fail: As the SDM explains, some conditions should cause the
9840          * instruction to fail, while others will cause the instruction to seem
9841          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9842          * To speed up the normal (success) code path, we should avoid checking
9843          * for misconfigurations which will anyway be caught by the processor
9844          * when using the merged vmcs02.
9845          */
9846         if (vmcs12->launch_state == launch) {
9847                 nested_vmx_failValid(vcpu,
9848                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9849                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9850                 return 1;
9851         }
9852
9853         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9854             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9855                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9856                 return 1;
9857         }
9858
9859         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9860                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9861                 return 1;
9862         }
9863
9864         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9865                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9866                 return 1;
9867         }
9868
9869         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9870                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9871                 return 1;
9872         }
9873
9874         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9875                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9876                 return 1;
9877         }
9878
9879         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9880                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9881                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9882             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9883                                 vmx->nested.nested_vmx_secondary_ctls_low,
9884                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9885             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9886                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9887                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9888             !vmx_control_verify(vmcs12->vm_exit_controls,
9889                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9890                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9891             !vmx_control_verify(vmcs12->vm_entry_controls,
9892                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9893                                 vmx->nested.nested_vmx_entry_ctls_high))
9894         {
9895                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9896                 return 1;
9897         }
9898
9899         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9900             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9901                 nested_vmx_failValid(vcpu,
9902                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9903                 return 1;
9904         }
9905
9906         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9907             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9908                 nested_vmx_entry_failure(vcpu, vmcs12,
9909                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9910                 return 1;
9911         }
9912         if (vmcs12->vmcs_link_pointer != -1ull) {
9913                 nested_vmx_entry_failure(vcpu, vmcs12,
9914                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9915                 return 1;
9916         }
9917
9918         /*
9919          * If the load IA32_EFER VM-entry control is 1, the following checks
9920          * are performed on the field for the IA32_EFER MSR:
9921          * - Bits reserved in the IA32_EFER MSR must be 0.
9922          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9923          *   the IA-32e mode guest VM-exit control. It must also be identical
9924          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9925          *   CR0.PG) is 1.
9926          */
9927         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9928                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9929                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9930                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9931                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9932                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9933                         nested_vmx_entry_failure(vcpu, vmcs12,
9934                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9935                         return 1;
9936                 }
9937         }
9938
9939         /*
9940          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9941          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9942          * the values of the LMA and LME bits in the field must each be that of
9943          * the host address-space size VM-exit control.
9944          */
9945         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9946                 ia32e = (vmcs12->vm_exit_controls &
9947                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9948                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9949                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9950                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9951                         nested_vmx_entry_failure(vcpu, vmcs12,
9952                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9953                         return 1;
9954                 }
9955         }
9956
9957         /*
9958          * We're finally done with prerequisite checking, and can start with
9959          * the nested entry.
9960          */
9961
9962         vmcs02 = nested_get_current_vmcs02(vmx);
9963         if (!vmcs02)
9964                 return -ENOMEM;
9965
9966         enter_guest_mode(vcpu);
9967
9968         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9969
9970         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9971                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9972
9973         cpu = get_cpu();
9974         vmx->loaded_vmcs = vmcs02;
9975         vmx_vcpu_put(vcpu);
9976         vmx_vcpu_load(vcpu, cpu);
9977         vcpu->cpu = cpu;
9978         put_cpu();
9979
9980         vmx_segment_cache_clear(vmx);
9981
9982         prepare_vmcs02(vcpu, vmcs12);
9983
9984         msr_entry_idx = nested_vmx_load_msr(vcpu,
9985                                             vmcs12->vm_entry_msr_load_addr,
9986                                             vmcs12->vm_entry_msr_load_count);
9987         if (msr_entry_idx) {
9988                 leave_guest_mode(vcpu);
9989                 vmx_load_vmcs01(vcpu);
9990                 nested_vmx_entry_failure(vcpu, vmcs12,
9991                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9992                 return 1;
9993         }
9994
9995         vmcs12->launch_state = 1;
9996
9997         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9998                 return kvm_vcpu_halt(vcpu);
9999
10000         vmx->nested.nested_run_pending = 1;
10001
10002         /*
10003          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10004          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10005          * returned as far as L1 is concerned. It will only return (and set
10006          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10007          */
10008         return 1;
10009 }
10010
10011 /*
10012  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10013  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10014  * This function returns the new value we should put in vmcs12.guest_cr0.
10015  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10016  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10017  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10018  *     didn't trap the bit, because if L1 did, so would L0).
10019  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10020  *     been modified by L2, and L1 knows it. So just leave the old value of
10021  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10022  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10023  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10024  *     changed these bits, and therefore they need to be updated, but L0
10025  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10026  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10027  */
10028 static inline unsigned long
10029 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10030 {
10031         return
10032         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10033         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10034         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10035                         vcpu->arch.cr0_guest_owned_bits));
10036 }
10037
10038 static inline unsigned long
10039 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10040 {
10041         return
10042         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10043         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10044         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10045                         vcpu->arch.cr4_guest_owned_bits));
10046 }
10047
10048 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10049                                        struct vmcs12 *vmcs12)
10050 {
10051         u32 idt_vectoring;
10052         unsigned int nr;
10053
10054         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10055                 nr = vcpu->arch.exception.nr;
10056                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10057
10058                 if (kvm_exception_is_soft(nr)) {
10059                         vmcs12->vm_exit_instruction_len =
10060                                 vcpu->arch.event_exit_inst_len;
10061                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10062                 } else
10063                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10064
10065                 if (vcpu->arch.exception.has_error_code) {
10066                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10067                         vmcs12->idt_vectoring_error_code =
10068                                 vcpu->arch.exception.error_code;
10069                 }
10070
10071                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10072         } else if (vcpu->arch.nmi_injected) {
10073                 vmcs12->idt_vectoring_info_field =
10074                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10075         } else if (vcpu->arch.interrupt.pending) {
10076                 nr = vcpu->arch.interrupt.nr;
10077                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10078
10079                 if (vcpu->arch.interrupt.soft) {
10080                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10081                         vmcs12->vm_entry_instruction_len =
10082                                 vcpu->arch.event_exit_inst_len;
10083                 } else
10084                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10085
10086                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10087         }
10088 }
10089
10090 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10091 {
10092         struct vcpu_vmx *vmx = to_vmx(vcpu);
10093
10094         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10095             vmx->nested.preemption_timer_expired) {
10096                 if (vmx->nested.nested_run_pending)
10097                         return -EBUSY;
10098                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10099                 return 0;
10100         }
10101
10102         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10103                 if (vmx->nested.nested_run_pending ||
10104                     vcpu->arch.interrupt.pending)
10105                         return -EBUSY;
10106                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10107                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10108                                   INTR_INFO_VALID_MASK, 0);
10109                 /*
10110                  * The NMI-triggered VM exit counts as injection:
10111                  * clear this one and block further NMIs.
10112                  */
10113                 vcpu->arch.nmi_pending = 0;
10114                 vmx_set_nmi_mask(vcpu, true);
10115                 return 0;
10116         }
10117
10118         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10119             nested_exit_on_intr(vcpu)) {
10120                 if (vmx->nested.nested_run_pending)
10121                         return -EBUSY;
10122                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10123                 return 0;
10124         }
10125
10126         return vmx_complete_nested_posted_interrupt(vcpu);
10127 }
10128
10129 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10130 {
10131         ktime_t remaining =
10132                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10133         u64 value;
10134
10135         if (ktime_to_ns(remaining) <= 0)
10136                 return 0;
10137
10138         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10139         do_div(value, 1000000);
10140         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10141 }
10142
10143 /*
10144  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10145  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10146  * and this function updates it to reflect the changes to the guest state while
10147  * L2 was running (and perhaps made some exits which were handled directly by L0
10148  * without going back to L1), and to reflect the exit reason.
10149  * Note that we do not have to copy here all VMCS fields, just those that
10150  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10151  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10152  * which already writes to vmcs12 directly.
10153  */
10154 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10155                            u32 exit_reason, u32 exit_intr_info,
10156                            unsigned long exit_qualification)
10157 {
10158         /* update guest state fields: */
10159         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10160         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10161
10162         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10163         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10164         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10165
10166         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10167         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10168         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10169         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10170         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10171         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10172         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10173         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10174         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10175         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10176         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10177         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10178         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10179         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10180         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10181         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10182         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10183         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10184         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10185         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10186         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10187         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10188         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10189         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10190         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10191         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10192         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10193         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10194         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10195         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10196         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10197         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10198         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10199         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10200         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10201         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10202
10203         vmcs12->guest_interruptibility_info =
10204                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10205         vmcs12->guest_pending_dbg_exceptions =
10206                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10207         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10208                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10209         else
10210                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10211
10212         if (nested_cpu_has_preemption_timer(vmcs12)) {
10213                 if (vmcs12->vm_exit_controls &
10214                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10215                         vmcs12->vmx_preemption_timer_value =
10216                                 vmx_get_preemption_timer_value(vcpu);
10217                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10218         }
10219
10220         /*
10221          * In some cases (usually, nested EPT), L2 is allowed to change its
10222          * own CR3 without exiting. If it has changed it, we must keep it.
10223          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10224          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10225          *
10226          * Additionally, restore L2's PDPTR to vmcs12.
10227          */
10228         if (enable_ept) {
10229                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10230                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10231                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10232                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10233                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10234         }
10235
10236         if (nested_cpu_has_vid(vmcs12))
10237                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10238
10239         vmcs12->vm_entry_controls =
10240                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10241                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10242
10243         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10244                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10245                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10246         }
10247
10248         /* TODO: These cannot have changed unless we have MSR bitmaps and
10249          * the relevant bit asks not to trap the change */
10250         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10251                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10252         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10253                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10254         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10255         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10256         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10257         if (vmx_mpx_supported())
10258                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10259         if (nested_cpu_has_xsaves(vmcs12))
10260                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10261
10262         /* update exit information fields: */
10263
10264         vmcs12->vm_exit_reason = exit_reason;
10265         vmcs12->exit_qualification = exit_qualification;
10266
10267         vmcs12->vm_exit_intr_info = exit_intr_info;
10268         if ((vmcs12->vm_exit_intr_info &
10269              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10270             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10271                 vmcs12->vm_exit_intr_error_code =
10272                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10273         vmcs12->idt_vectoring_info_field = 0;
10274         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10275         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10276
10277         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10278                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10279                  * instead of reading the real value. */
10280                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10281
10282                 /*
10283                  * Transfer the event that L0 or L1 may wanted to inject into
10284                  * L2 to IDT_VECTORING_INFO_FIELD.
10285                  */
10286                 vmcs12_save_pending_event(vcpu, vmcs12);
10287         }
10288
10289         /*
10290          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10291          * preserved above and would only end up incorrectly in L1.
10292          */
10293         vcpu->arch.nmi_injected = false;
10294         kvm_clear_exception_queue(vcpu);
10295         kvm_clear_interrupt_queue(vcpu);
10296 }
10297
10298 /*
10299  * A part of what we need to when the nested L2 guest exits and we want to
10300  * run its L1 parent, is to reset L1's guest state to the host state specified
10301  * in vmcs12.
10302  * This function is to be called not only on normal nested exit, but also on
10303  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10304  * Failures During or After Loading Guest State").
10305  * This function should be called when the active VMCS is L1's (vmcs01).
10306  */
10307 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10308                                    struct vmcs12 *vmcs12)
10309 {
10310         struct kvm_segment seg;
10311
10312         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10313                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10314         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10315                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10316         else
10317                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10318         vmx_set_efer(vcpu, vcpu->arch.efer);
10319
10320         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10321         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10322         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10323         /*
10324          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10325          * actually changed, because it depends on the current state of
10326          * fpu_active (which may have changed).
10327          * Note that vmx_set_cr0 refers to efer set above.
10328          */
10329         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10330         /*
10331          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10332          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10333          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10334          */
10335         update_exception_bitmap(vcpu);
10336         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10337         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10338
10339         /*
10340          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10341          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10342          */
10343         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10344         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10345
10346         nested_ept_uninit_mmu_context(vcpu);
10347
10348         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10349         kvm_mmu_reset_context(vcpu);
10350
10351         if (!enable_ept)
10352                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10353
10354         if (enable_vpid) {
10355                 /*
10356                  * Trivially support vpid by letting L2s share their parent
10357                  * L1's vpid. TODO: move to a more elaborate solution, giving
10358                  * each L2 its own vpid and exposing the vpid feature to L1.
10359                  */
10360                 vmx_flush_tlb(vcpu);
10361         }
10362
10363
10364         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10365         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10366         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10367         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10368         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10369
10370         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10371         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10372                 vmcs_write64(GUEST_BNDCFGS, 0);
10373
10374         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10375                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10376                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10377         }
10378         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10379                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10380                         vmcs12->host_ia32_perf_global_ctrl);
10381
10382         /* Set L1 segment info according to Intel SDM
10383             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10384         seg = (struct kvm_segment) {
10385                 .base = 0,
10386                 .limit = 0xFFFFFFFF,
10387                 .selector = vmcs12->host_cs_selector,
10388                 .type = 11,
10389                 .present = 1,
10390                 .s = 1,
10391                 .g = 1
10392         };
10393         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10394                 seg.l = 1;
10395         else
10396                 seg.db = 1;
10397         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10398         seg = (struct kvm_segment) {
10399                 .base = 0,
10400                 .limit = 0xFFFFFFFF,
10401                 .type = 3,
10402                 .present = 1,
10403                 .s = 1,
10404                 .db = 1,
10405                 .g = 1
10406         };
10407         seg.selector = vmcs12->host_ds_selector;
10408         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10409         seg.selector = vmcs12->host_es_selector;
10410         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10411         seg.selector = vmcs12->host_ss_selector;
10412         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10413         seg.selector = vmcs12->host_fs_selector;
10414         seg.base = vmcs12->host_fs_base;
10415         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10416         seg.selector = vmcs12->host_gs_selector;
10417         seg.base = vmcs12->host_gs_base;
10418         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10419         seg = (struct kvm_segment) {
10420                 .base = vmcs12->host_tr_base,
10421                 .limit = 0x67,
10422                 .selector = vmcs12->host_tr_selector,
10423                 .type = 11,
10424                 .present = 1
10425         };
10426         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10427
10428         kvm_set_dr(vcpu, 7, 0x400);
10429         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10430
10431         if (cpu_has_vmx_msr_bitmap())
10432                 vmx_set_msr_bitmap(vcpu);
10433
10434         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10435                                 vmcs12->vm_exit_msr_load_count))
10436                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10437 }
10438
10439 /*
10440  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10441  * and modify vmcs12 to make it see what it would expect to see there if
10442  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10443  */
10444 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10445                               u32 exit_intr_info,
10446                               unsigned long exit_qualification)
10447 {
10448         struct vcpu_vmx *vmx = to_vmx(vcpu);
10449         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10450
10451         /* trying to cancel vmlaunch/vmresume is a bug */
10452         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10453
10454         leave_guest_mode(vcpu);
10455         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10456                        exit_qualification);
10457
10458         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10459                                  vmcs12->vm_exit_msr_store_count))
10460                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10461
10462         vmx_load_vmcs01(vcpu);
10463
10464         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10465             && nested_exit_intr_ack_set(vcpu)) {
10466                 int irq = kvm_cpu_get_interrupt(vcpu);
10467                 WARN_ON(irq < 0);
10468                 vmcs12->vm_exit_intr_info = irq |
10469                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10470         }
10471
10472         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10473                                        vmcs12->exit_qualification,
10474                                        vmcs12->idt_vectoring_info_field,
10475                                        vmcs12->vm_exit_intr_info,
10476                                        vmcs12->vm_exit_intr_error_code,
10477                                        KVM_ISA_VMX);
10478
10479         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10480         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10481         vmx_segment_cache_clear(vmx);
10482
10483         /* if no vmcs02 cache requested, remove the one we used */
10484         if (VMCS02_POOL_SIZE == 0)
10485                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10486
10487         load_vmcs12_host_state(vcpu, vmcs12);
10488
10489         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10490         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10491
10492         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10493                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10494                 vmx_set_virtual_x2apic_mode(vcpu,
10495                                 vcpu->arch.apic_base & X2APIC_ENABLE);
10496         }
10497
10498         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10499         vmx->host_rsp = 0;
10500
10501         /* Unpin physical memory we referred to in vmcs02 */
10502         if (vmx->nested.apic_access_page) {
10503                 nested_release_page(vmx->nested.apic_access_page);
10504                 vmx->nested.apic_access_page = NULL;
10505         }
10506         if (vmx->nested.virtual_apic_page) {
10507                 nested_release_page(vmx->nested.virtual_apic_page);
10508                 vmx->nested.virtual_apic_page = NULL;
10509         }
10510         if (vmx->nested.pi_desc_page) {
10511                 kunmap(vmx->nested.pi_desc_page);
10512                 nested_release_page(vmx->nested.pi_desc_page);
10513                 vmx->nested.pi_desc_page = NULL;
10514                 vmx->nested.pi_desc = NULL;
10515         }
10516
10517         /*
10518          * We are now running in L2, mmu_notifier will force to reload the
10519          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10520          */
10521         kvm_vcpu_reload_apic_access_page(vcpu);
10522
10523         /*
10524          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10525          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10526          * success or failure flag accordingly.
10527          */
10528         if (unlikely(vmx->fail)) {
10529                 vmx->fail = 0;
10530                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10531         } else
10532                 nested_vmx_succeed(vcpu);
10533         if (enable_shadow_vmcs)
10534                 vmx->nested.sync_shadow_vmcs = true;
10535
10536         /* in case we halted in L2 */
10537         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10538 }
10539
10540 /*
10541  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10542  */
10543 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10544 {
10545         if (is_guest_mode(vcpu))
10546                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10547         free_nested(to_vmx(vcpu));
10548 }
10549
10550 /*
10551  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10552  * 23.7 "VM-entry failures during or after loading guest state" (this also
10553  * lists the acceptable exit-reason and exit-qualification parameters).
10554  * It should only be called before L2 actually succeeded to run, and when
10555  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10556  */
10557 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10558                         struct vmcs12 *vmcs12,
10559                         u32 reason, unsigned long qualification)
10560 {
10561         load_vmcs12_host_state(vcpu, vmcs12);
10562         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10563         vmcs12->exit_qualification = qualification;
10564         nested_vmx_succeed(vcpu);
10565         if (enable_shadow_vmcs)
10566                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10567 }
10568
10569 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10570                                struct x86_instruction_info *info,
10571                                enum x86_intercept_stage stage)
10572 {
10573         return X86EMUL_CONTINUE;
10574 }
10575
10576 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10577 {
10578         if (ple_gap)
10579                 shrink_ple_window(vcpu);
10580 }
10581
10582 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10583                                      struct kvm_memory_slot *slot)
10584 {
10585         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10586         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10587 }
10588
10589 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10590                                        struct kvm_memory_slot *slot)
10591 {
10592         kvm_mmu_slot_set_dirty(kvm, slot);
10593 }
10594
10595 static void vmx_flush_log_dirty(struct kvm *kvm)
10596 {
10597         kvm_flush_pml_buffers(kvm);
10598 }
10599
10600 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10601                                            struct kvm_memory_slot *memslot,
10602                                            gfn_t offset, unsigned long mask)
10603 {
10604         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10605 }
10606
10607 /*
10608  * This routine does the following things for vCPU which is going
10609  * to be blocked if VT-d PI is enabled.
10610  * - Store the vCPU to the wakeup list, so when interrupts happen
10611  *   we can find the right vCPU to wake up.
10612  * - Change the Posted-interrupt descriptor as below:
10613  *      'NDST' <-- vcpu->pre_pcpu
10614  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10615  * - If 'ON' is set during this process, which means at least one
10616  *   interrupt is posted for this vCPU, we cannot block it, in
10617  *   this case, return 1, otherwise, return 0.
10618  *
10619  */
10620 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10621 {
10622         unsigned long flags;
10623         unsigned int dest;
10624         struct pi_desc old, new;
10625         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10626
10627         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10628                 !irq_remapping_cap(IRQ_POSTING_CAP))
10629                 return 0;
10630
10631         vcpu->pre_pcpu = vcpu->cpu;
10632         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10633                           vcpu->pre_pcpu), flags);
10634         list_add_tail(&vcpu->blocked_vcpu_list,
10635                       &per_cpu(blocked_vcpu_on_cpu,
10636                       vcpu->pre_pcpu));
10637         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10638                                vcpu->pre_pcpu), flags);
10639
10640         do {
10641                 old.control = new.control = pi_desc->control;
10642
10643                 /*
10644                  * We should not block the vCPU if
10645                  * an interrupt is posted for it.
10646                  */
10647                 if (pi_test_on(pi_desc) == 1) {
10648                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10649                                           vcpu->pre_pcpu), flags);
10650                         list_del(&vcpu->blocked_vcpu_list);
10651                         spin_unlock_irqrestore(
10652                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10653                                         vcpu->pre_pcpu), flags);
10654                         vcpu->pre_pcpu = -1;
10655
10656                         return 1;
10657                 }
10658
10659                 WARN((pi_desc->sn == 1),
10660                      "Warning: SN field of posted-interrupts "
10661                      "is set before blocking\n");
10662
10663                 /*
10664                  * Since vCPU can be preempted during this process,
10665                  * vcpu->cpu could be different with pre_pcpu, we
10666                  * need to set pre_pcpu as the destination of wakeup
10667                  * notification event, then we can find the right vCPU
10668                  * to wakeup in wakeup handler if interrupts happen
10669                  * when the vCPU is in blocked state.
10670                  */
10671                 dest = cpu_physical_id(vcpu->pre_pcpu);
10672
10673                 if (x2apic_enabled())
10674                         new.ndst = dest;
10675                 else
10676                         new.ndst = (dest << 8) & 0xFF00;
10677
10678                 /* set 'NV' to 'wakeup vector' */
10679                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10680         } while (cmpxchg(&pi_desc->control, old.control,
10681                         new.control) != old.control);
10682
10683         return 0;
10684 }
10685
10686 static void vmx_post_block(struct kvm_vcpu *vcpu)
10687 {
10688         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10689         struct pi_desc old, new;
10690         unsigned int dest;
10691         unsigned long flags;
10692
10693         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10694                 !irq_remapping_cap(IRQ_POSTING_CAP))
10695                 return;
10696
10697         do {
10698                 old.control = new.control = pi_desc->control;
10699
10700                 dest = cpu_physical_id(vcpu->cpu);
10701
10702                 if (x2apic_enabled())
10703                         new.ndst = dest;
10704                 else
10705                         new.ndst = (dest << 8) & 0xFF00;
10706
10707                 /* Allow posting non-urgent interrupts */
10708                 new.sn = 0;
10709
10710                 /* set 'NV' to 'notification vector' */
10711                 new.nv = POSTED_INTR_VECTOR;
10712         } while (cmpxchg(&pi_desc->control, old.control,
10713                         new.control) != old.control);
10714
10715         if(vcpu->pre_pcpu != -1) {
10716                 spin_lock_irqsave(
10717                         &per_cpu(blocked_vcpu_on_cpu_lock,
10718                         vcpu->pre_pcpu), flags);
10719                 list_del(&vcpu->blocked_vcpu_list);
10720                 spin_unlock_irqrestore(
10721                         &per_cpu(blocked_vcpu_on_cpu_lock,
10722                         vcpu->pre_pcpu), flags);
10723                 vcpu->pre_pcpu = -1;
10724         }
10725 }
10726
10727 /*
10728  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10729  *
10730  * @kvm: kvm
10731  * @host_irq: host irq of the interrupt
10732  * @guest_irq: gsi of the interrupt
10733  * @set: set or unset PI
10734  * returns 0 on success, < 0 on failure
10735  */
10736 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10737                               uint32_t guest_irq, bool set)
10738 {
10739         struct kvm_kernel_irq_routing_entry *e;
10740         struct kvm_irq_routing_table *irq_rt;
10741         struct kvm_lapic_irq irq;
10742         struct kvm_vcpu *vcpu;
10743         struct vcpu_data vcpu_info;
10744         int idx, ret = -EINVAL;
10745
10746         if (!kvm_arch_has_assigned_device(kvm) ||
10747                 !irq_remapping_cap(IRQ_POSTING_CAP))
10748                 return 0;
10749
10750         idx = srcu_read_lock(&kvm->irq_srcu);
10751         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10752         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10753
10754         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10755                 if (e->type != KVM_IRQ_ROUTING_MSI)
10756                         continue;
10757                 /*
10758                  * VT-d PI cannot support posting multicast/broadcast
10759                  * interrupts to a vCPU, we still use interrupt remapping
10760                  * for these kind of interrupts.
10761                  *
10762                  * For lowest-priority interrupts, we only support
10763                  * those with single CPU as the destination, e.g. user
10764                  * configures the interrupts via /proc/irq or uses
10765                  * irqbalance to make the interrupts single-CPU.
10766                  *
10767                  * We will support full lowest-priority interrupt later.
10768                  */
10769
10770                 kvm_set_msi_irq(e, &irq);
10771                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10772                         continue;
10773
10774                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10775                 vcpu_info.vector = irq.vector;
10776
10777                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10778                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10779
10780                 if (set)
10781                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10782                 else {
10783                         /* suppress notification event before unposting */
10784                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10785                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10786                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10787                 }
10788
10789                 if (ret < 0) {
10790                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10791                                         __func__);
10792                         goto out;
10793                 }
10794         }
10795
10796         ret = 0;
10797 out:
10798         srcu_read_unlock(&kvm->irq_srcu, idx);
10799         return ret;
10800 }
10801
10802 static struct kvm_x86_ops vmx_x86_ops = {
10803         .cpu_has_kvm_support = cpu_has_kvm_support,
10804         .disabled_by_bios = vmx_disabled_by_bios,
10805         .hardware_setup = hardware_setup,
10806         .hardware_unsetup = hardware_unsetup,
10807         .check_processor_compatibility = vmx_check_processor_compat,
10808         .hardware_enable = hardware_enable,
10809         .hardware_disable = hardware_disable,
10810         .cpu_has_accelerated_tpr = report_flexpriority,
10811         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10812
10813         .vcpu_create = vmx_create_vcpu,
10814         .vcpu_free = vmx_free_vcpu,
10815         .vcpu_reset = vmx_vcpu_reset,
10816
10817         .prepare_guest_switch = vmx_save_host_state,
10818         .vcpu_load = vmx_vcpu_load,
10819         .vcpu_put = vmx_vcpu_put,
10820
10821         .update_bp_intercept = update_exception_bitmap,
10822         .get_msr = vmx_get_msr,
10823         .set_msr = vmx_set_msr,
10824         .get_segment_base = vmx_get_segment_base,
10825         .get_segment = vmx_get_segment,
10826         .set_segment = vmx_set_segment,
10827         .get_cpl = vmx_get_cpl,
10828         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10829         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10830         .decache_cr3 = vmx_decache_cr3,
10831         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10832         .set_cr0 = vmx_set_cr0,
10833         .set_cr3 = vmx_set_cr3,
10834         .set_cr4 = vmx_set_cr4,
10835         .set_efer = vmx_set_efer,
10836         .get_idt = vmx_get_idt,
10837         .set_idt = vmx_set_idt,
10838         .get_gdt = vmx_get_gdt,
10839         .set_gdt = vmx_set_gdt,
10840         .get_dr6 = vmx_get_dr6,
10841         .set_dr6 = vmx_set_dr6,
10842         .set_dr7 = vmx_set_dr7,
10843         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10844         .cache_reg = vmx_cache_reg,
10845         .get_rflags = vmx_get_rflags,
10846         .set_rflags = vmx_set_rflags,
10847         .fpu_activate = vmx_fpu_activate,
10848         .fpu_deactivate = vmx_fpu_deactivate,
10849
10850         .tlb_flush = vmx_flush_tlb,
10851
10852         .run = vmx_vcpu_run,
10853         .handle_exit = vmx_handle_exit,
10854         .skip_emulated_instruction = skip_emulated_instruction,
10855         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10856         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10857         .patch_hypercall = vmx_patch_hypercall,
10858         .set_irq = vmx_inject_irq,
10859         .set_nmi = vmx_inject_nmi,
10860         .queue_exception = vmx_queue_exception,
10861         .cancel_injection = vmx_cancel_injection,
10862         .interrupt_allowed = vmx_interrupt_allowed,
10863         .nmi_allowed = vmx_nmi_allowed,
10864         .get_nmi_mask = vmx_get_nmi_mask,
10865         .set_nmi_mask = vmx_set_nmi_mask,
10866         .enable_nmi_window = enable_nmi_window,
10867         .enable_irq_window = enable_irq_window,
10868         .update_cr8_intercept = update_cr8_intercept,
10869         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10870         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10871         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10872         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10873         .hwapic_irr_update = vmx_hwapic_irr_update,
10874         .hwapic_isr_update = vmx_hwapic_isr_update,
10875         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10876         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10877
10878         .set_tss_addr = vmx_set_tss_addr,
10879         .get_tdp_level = get_ept_level,
10880         .get_mt_mask = vmx_get_mt_mask,
10881
10882         .get_exit_info = vmx_get_exit_info,
10883
10884         .get_lpage_level = vmx_get_lpage_level,
10885
10886         .cpuid_update = vmx_cpuid_update,
10887
10888         .rdtscp_supported = vmx_rdtscp_supported,
10889         .invpcid_supported = vmx_invpcid_supported,
10890
10891         .set_supported_cpuid = vmx_set_supported_cpuid,
10892
10893         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10894
10895         .read_tsc_offset = vmx_read_tsc_offset,
10896         .write_tsc_offset = vmx_write_tsc_offset,
10897         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10898         .read_l1_tsc = vmx_read_l1_tsc,
10899
10900         .set_tdp_cr3 = vmx_set_cr3,
10901
10902         .check_intercept = vmx_check_intercept,
10903         .handle_external_intr = vmx_handle_external_intr,
10904         .mpx_supported = vmx_mpx_supported,
10905         .xsaves_supported = vmx_xsaves_supported,
10906
10907         .check_nested_events = vmx_check_nested_events,
10908
10909         .sched_in = vmx_sched_in,
10910
10911         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10912         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10913         .flush_log_dirty = vmx_flush_log_dirty,
10914         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10915
10916         .pre_block = vmx_pre_block,
10917         .post_block = vmx_post_block,
10918
10919         .pmu_ops = &intel_pmu_ops,
10920
10921         .update_pi_irte = vmx_update_pi_irte,
10922 };
10923
10924 static int __init vmx_init(void)
10925 {
10926         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10927                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10928         if (r)
10929                 return r;
10930
10931 #ifdef CONFIG_KEXEC_CORE
10932         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10933                            crash_vmclear_local_loaded_vmcss);
10934 #endif
10935
10936         return 0;
10937 }
10938
10939 static void __exit vmx_exit(void)
10940 {
10941 #ifdef CONFIG_KEXEC_CORE
10942         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10943         synchronize_rcu();
10944 #endif
10945
10946         kvm_exit();
10947 }
10948
10949 module_init(vmx_init)
10950 module_exit(vmx_exit)