arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23 #include "cpuid.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/mod_devicetable.h>
  27 #include <linux/kernel.h>
  28 #include <linux/vmalloc.h>
  29 #include <linux/highmem.h>
  30 #include <linux/sched.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33
  34 #include <asm/perf_event.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/desc.h>
  37 #include <asm/kvm_para.h>
  38
  39 #include <asm/virtext.h>
  40 #include "trace.h"
  41
  42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  43
  44 MODULE_AUTHOR("Qumranet");
  45 MODULE_LICENSE("GPL");
  46
  47 static const struct x86_cpu_id svm_cpu_id[] = {
  48         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  49         {}
  50 };
  51 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  52
  53 #define IOPM_ALLOC_ORDER 2
  54 #define MSRPM_ALLOC_ORDER 1
  55
  56 #define SEG_TYPE_LDT 2
  57 #define SEG_TYPE_BUSY_TSS16 3
  58
  59 #define SVM_FEATURE_NPT            (1 <<  0)
  60 #define SVM_FEATURE_LBRV           (1 <<  1)
  61 #define SVM_FEATURE_SVML           (1 <<  2)
  62 #define SVM_FEATURE_NRIP           (1 <<  3)
  63 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  64 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  65 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  66 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  67 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  68
  69 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  70 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  71 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  72
  73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  74
  75 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  76 #define TSC_RATIO_MIN           0x0000000000000001ULL
  77 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  78
  79 static bool erratum_383_found __read_mostly;
  80
  81 static const u32 host_save_user_msrs[] = {
  82 #ifdef CONFIG_X86_64
  83         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  84         MSR_FS_BASE,
  85 #endif
  86         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  87 };
  88
  89 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  90
  91 struct kvm_vcpu;
  92
  93 struct nested_state {
  94         struct vmcb *hsave;
  95         u64 hsave_msr;
  96         u64 vm_cr_msr;
  97         u64 vmcb;
  98
  99         /* These are the merged vectors */
 100         u32 *msrpm;
 101
 102         /* gpa pointers to the real vectors */
 103         u64 vmcb_msrpm;
 104         u64 vmcb_iopm;
 105
 106         /* A VMEXIT is required but not yet emulated */
 107         bool exit_required;
 108
 109         /* cache for intercepts of the guest */
 110         u32 intercept_cr;
 111         u32 intercept_dr;
 112         u32 intercept_exceptions;
 113         u64 intercept;
 114
 115         /* Nested Paging related state */
 116         u64 nested_cr3;
 117 };
 118
 119 #define MSRPM_OFFSETS   16
 120 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 121
 122 /*
 123  * Set osvw_len to higher value when updated Revision Guides
 124  * are published and we know what the new status bits are
 125  */
 126 static uint64_t osvw_len = 4, osvw_status;
 127
 128 struct vcpu_svm {
 129         struct kvm_vcpu vcpu;
 130         struct vmcb *vmcb;
 131         unsigned long vmcb_pa;
 132         struct svm_cpu_data *svm_data;
 133         uint64_t asid_generation;
 134         uint64_t sysenter_esp;
 135         uint64_t sysenter_eip;
 136
 137         u64 next_rip;
 138
 139         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 140         struct {
 141                 u16 fs;
 142                 u16 gs;
 143                 u16 ldt;
 144                 u64 gs_base;
 145         } host;
 146
 147         u32 *msrpm;
 148
 149         ulong nmi_iret_rip;
 150
 151         struct nested_state nested;
 152
 153         bool nmi_singlestep;
 154
 155         unsigned int3_injected;
 156         unsigned long int3_rip;
 157         u32 apf_reason;
 158
 159         u64  tsc_ratio;
 160 };
 161
 162 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 163 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 164
 165 #define MSR_INVALID                     0xffffffffU
 166
 167 static const struct svm_direct_access_msrs {
 168         u32 index;   /* Index of the MSR */
 169         bool always; /* True if intercept is always on */
 170 } direct_access_msrs[] = {
 171         { .index = MSR_STAR,                            .always = true  },
 172         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 173 #ifdef CONFIG_X86_64
 174         { .index = MSR_GS_BASE,                         .always = true  },
 175         { .index = MSR_FS_BASE,                         .always = true  },
 176         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 177         { .index = MSR_LSTAR,                           .always = true  },
 178         { .index = MSR_CSTAR,                           .always = true  },
 179         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 180 #endif
 181         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 182         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 183         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 184         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 185         { .index = MSR_INVALID,                         .always = false },
 186 };
 187
 188 /* enable NPT for AMD64 and X86 with PAE */
 189 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 190 static bool npt_enabled = true;
 191 #else
 192 static bool npt_enabled;
 193 #endif
 194
 195 /* allow nested paging (virtualized MMU) for all guests */
 196 static int npt = true;
 197 module_param(npt, int, S_IRUGO);
 198
 199 /* allow nested virtualization in KVM/SVM */
 200 static int nested = true;
 201 module_param(nested, int, S_IRUGO);
 202
 203 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 204 static void svm_complete_interrupts(struct vcpu_svm *svm);
 205
 206 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 207 static int nested_svm_intercept(struct vcpu_svm *svm);
 208 static int nested_svm_vmexit(struct vcpu_svm *svm);
 209 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 210                                       bool has_error_code, u32 error_code);
 211 static u64 __scale_tsc(u64 ratio, u64 tsc);
 212
 213 enum {
 214         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 215                             pause filter count */
 216         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 217         VMCB_ASID,       /* ASID */
 218         VMCB_INTR,       /* int_ctl, int_vector */
 219         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 220         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 221         VMCB_DR,         /* DR6, DR7 */
 222         VMCB_DT,         /* GDT, IDT */
 223         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 224         VMCB_CR2,        /* CR2 only */
 225         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 226         VMCB_DIRTY_MAX,
 227 };
 228
 229 /* TPR and CR2 are always written before VMRUN */
 230 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 231
 232 static inline void mark_all_dirty(struct vmcb *vmcb)
 233 {
 234         vmcb->control.clean = 0;
 235 }
 236
 237 static inline void mark_all_clean(struct vmcb *vmcb)
 238 {
 239         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 240                                & ~VMCB_ALWAYS_DIRTY_MASK;
 241 }
 242
 243 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 244 {
 245         vmcb->control.clean &= ~(1 << bit);
 246 }
 247
 248 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 249 {
 250         return container_of(vcpu, struct vcpu_svm, vcpu);
 251 }
 252
 253 static void recalc_intercepts(struct vcpu_svm *svm)
 254 {
 255         struct vmcb_control_area *c, *h;
 256         struct nested_state *g;
 257
 258         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 259
 260         if (!is_guest_mode(&svm->vcpu))
 261                 return;
 262
 263         c = &svm->vmcb->control;
 264         h = &svm->nested.hsave->control;
 265         g = &svm->nested;
 266
 267         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 268         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 269         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 270         c->intercept = h->intercept | g->intercept;
 271 }
 272
 273 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 274 {
 275         if (is_guest_mode(&svm->vcpu))
 276                 return svm->nested.hsave;
 277         else
 278                 return svm->vmcb;
 279 }
 280
 281 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 282 {
 283         struct vmcb *vmcb = get_host_vmcb(svm);
 284
 285         vmcb->control.intercept_cr |= (1U << bit);
 286
 287         recalc_intercepts(svm);
 288 }
 289
 290 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 291 {
 292         struct vmcb *vmcb = get_host_vmcb(svm);
 293
 294         vmcb->control.intercept_cr &= ~(1U << bit);
 295
 296         recalc_intercepts(svm);
 297 }
 298
 299 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 300 {
 301         struct vmcb *vmcb = get_host_vmcb(svm);
 302
 303         return vmcb->control.intercept_cr & (1U << bit);
 304 }
 305
 306 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 307 {
 308         struct vmcb *vmcb = get_host_vmcb(svm);
 309
 310         vmcb->control.intercept_dr |= (1U << bit);
 311
 312         recalc_intercepts(svm);
 313 }
 314
 315 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 316 {
 317         struct vmcb *vmcb = get_host_vmcb(svm);
 318
 319         vmcb->control.intercept_dr &= ~(1U << bit);
 320
 321         recalc_intercepts(svm);
 322 }
 323
 324 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 325 {
 326         struct vmcb *vmcb = get_host_vmcb(svm);
 327
 328         vmcb->control.intercept_exceptions |= (1U << bit);
 329
 330         recalc_intercepts(svm);
 331 }
 332
 333 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 334 {
 335         struct vmcb *vmcb = get_host_vmcb(svm);
 336
 337         vmcb->control.intercept_exceptions &= ~(1U << bit);
 338
 339         recalc_intercepts(svm);
 340 }
 341
 342 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 343 {
 344         struct vmcb *vmcb = get_host_vmcb(svm);
 345
 346         vmcb->control.intercept |= (1ULL << bit);
 347
 348         recalc_intercepts(svm);
 349 }
 350
 351 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 352 {
 353         struct vmcb *vmcb = get_host_vmcb(svm);
 354
 355         vmcb->control.intercept &= ~(1ULL << bit);
 356
 357         recalc_intercepts(svm);
 358 }
 359
 360 static inline void enable_gif(struct vcpu_svm *svm)
 361 {
 362         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 363 }
 364
 365 static inline void disable_gif(struct vcpu_svm *svm)
 366 {
 367         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 368 }
 369
 370 static inline bool gif_set(struct vcpu_svm *svm)
 371 {
 372         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 373 }
 374
 375 static unsigned long iopm_base;
 376
 377 struct kvm_ldttss_desc {
 378         u16 limit0;
 379         u16 base0;
 380         unsigned base1:8, type:5, dpl:2, p:1;
 381         unsigned limit1:4, zero0:3, g:1, base2:8;
 382         u32 base3;
 383         u32 zero1;
 384 } __attribute__((packed));
 385
 386 struct svm_cpu_data {
 387         int cpu;
 388
 389         u64 asid_generation;
 390         u32 max_asid;
 391         u32 next_asid;
 392         struct kvm_ldttss_desc *tss_desc;
 393
 394         struct page *save_area;
 395 };
 396
 397 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 398
 399 struct svm_init_data {
 400         int cpu;
 401         int r;
 402 };
 403
 404 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 405
 406 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 407 #define MSRS_RANGE_SIZE 2048
 408 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 409
 410 static u32 svm_msrpm_offset(u32 msr)
 411 {
 412         u32 offset;
 413         int i;
 414
 415         for (i = 0; i < NUM_MSR_MAPS; i++) {
 416                 if (msr < msrpm_ranges[i] ||
 417                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 418                         continue;
 419
 420                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 421                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 422
 423                 /* Now we have the u8 offset - but need the u32 offset */
 424                 return offset / 4;
 425         }
 426
 427         /* MSR not in any range */
 428         return MSR_INVALID;
 429 }
 430
 431 #define MAX_INST_SIZE 15
 432
 433 static inline void clgi(void)
 434 {
 435         asm volatile (__ex(SVM_CLGI));
 436 }
 437
 438 static inline void stgi(void)
 439 {
 440         asm volatile (__ex(SVM_STGI));
 441 }
 442
 443 static inline void invlpga(unsigned long addr, u32 asid)
 444 {
 445         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 446 }
 447
 448 static int get_npt_level(void)
 449 {
 450 #ifdef CONFIG_X86_64
 451         return PT64_ROOT_LEVEL;
 452 #else
 453         return PT32E_ROOT_LEVEL;
 454 #endif
 455 }
 456
 457 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 458 {
 459         vcpu->arch.efer = efer;
 460         if (!npt_enabled && !(efer & EFER_LMA))
 461                 efer &= ~EFER_LME;
 462
 463         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 464         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 465 }
 466
 467 static int is_external_interrupt(u32 info)
 468 {
 469         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 470         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 471 }
 472
 473 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 474 {
 475         struct vcpu_svm *svm = to_svm(vcpu);
 476         u32 ret = 0;
 477
 478         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 479                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 480         return ret & mask;
 481 }
 482
 483 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 484 {
 485         struct vcpu_svm *svm = to_svm(vcpu);
 486
 487         if (mask == 0)
 488                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 489         else
 490                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 491
 492 }
 493
 494 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 495 {
 496         struct vcpu_svm *svm = to_svm(vcpu);
 497
 498         if (svm->vmcb->control.next_rip != 0)
 499                 svm->next_rip = svm->vmcb->control.next_rip;
 500
 501         if (!svm->next_rip) {
 502                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 503                                 EMULATE_DONE)
 504                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 505                 return;
 506         }
 507         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 508                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 509                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 510
 511         kvm_rip_write(vcpu, svm->next_rip);
 512         svm_set_interrupt_shadow(vcpu, 0);
 513 }
 514
 515 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 516                                 bool has_error_code, u32 error_code,
 517                                 bool reinject)
 518 {
 519         struct vcpu_svm *svm = to_svm(vcpu);
 520
 521         /*
 522          * If we are within a nested VM we'd better #VMEXIT and let the guest
 523          * handle the exception
 524          */
 525         if (!reinject &&
 526             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 527                 return;
 528
 529         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 530                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 531
 532                 /*
 533                  * For guest debugging where we have to reinject #BP if some
 534                  * INT3 is guest-owned:
 535                  * Emulate nRIP by moving RIP forward. Will fail if injection
 536                  * raises a fault that is not intercepted. Still better than
 537                  * failing in all cases.
 538                  */
 539                 skip_emulated_instruction(&svm->vcpu);
 540                 rip = kvm_rip_read(&svm->vcpu);
 541                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 542                 svm->int3_injected = rip - old_rip;
 543         }
 544
 545         svm->vmcb->control.event_inj = nr
 546                 | SVM_EVTINJ_VALID
 547                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 548                 | SVM_EVTINJ_TYPE_EXEPT;
 549         svm->vmcb->control.event_inj_err = error_code;
 550 }
 551
 552 static void svm_init_erratum_383(void)
 553 {
 554         u32 low, high;
 555         int err;
 556         u64 val;
 557
 558         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 559                 return;
 560
 561         /* Use _safe variants to not break nested virtualization */
 562         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 563         if (err)
 564                 return;
 565
 566         val |= (1ULL << 47);
 567
 568         low  = lower_32_bits(val);
 569         high = upper_32_bits(val);
 570
 571         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 572
 573         erratum_383_found = true;
 574 }
 575
 576 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 577 {
 578         /*
 579          * Guests should see errata 400 and 415 as fixed (assuming that
 580          * HLT and IO instructions are intercepted).
 581          */
 582         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 583         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 584
 585         /*
 586          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 587          * all osvw.status bits inside that length, including bit 0 (which is
 588          * reserved for erratum 298), are valid. However, if host processor's
 589          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 590          * be conservative here and therefore we tell the guest that erratum 298
 591          * is present (because we really don't know).
 592          */
 593         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 594                 vcpu->arch.osvw.status |= 1;
 595 }
 596
 597 static int has_svm(void)
 598 {
 599         const char *msg;
 600
 601         if (!cpu_has_svm(&msg)) {
 602                 printk(KERN_INFO "has_svm: %s\n", msg);
 603                 return 0;
 604         }
 605
 606         return 1;
 607 }
 608
 609 static void svm_hardware_disable(void *garbage)
 610 {
 611         /* Make sure we clean up behind us */
 612         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 613                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 614
 615         cpu_svm_disable();
 616
 617         amd_pmu_disable_virt();
 618 }
 619
 620 static int svm_hardware_enable(void *garbage)
 621 {
 622
 623         struct svm_cpu_data *sd;
 624         uint64_t efer;
 625         struct desc_ptr gdt_descr;
 626         struct desc_struct *gdt;
 627         int me = raw_smp_processor_id();
 628
 629         rdmsrl(MSR_EFER, efer);
 630         if (efer & EFER_SVME)
 631                 return -EBUSY;
 632
 633         if (!has_svm()) {
 634                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 635                 return -EINVAL;
 636         }
 637         sd = per_cpu(svm_data, me);
 638         if (!sd) {
 639                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 640                 return -EINVAL;
 641         }
 642
 643         sd->asid_generation = 1;
 644         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 645         sd->next_asid = sd->max_asid + 1;
 646
 647         native_store_gdt(&gdt_descr);
 648         gdt = (struct desc_struct *)gdt_descr.address;
 649         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 650
 651         wrmsrl(MSR_EFER, efer | EFER_SVME);
 652
 653         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 654
 655         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 656                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 657                 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
 658         }
 659
 660
 661         /*
 662          * Get OSVW bits.
 663          *
 664          * Note that it is possible to have a system with mixed processor
 665          * revisions and therefore different OSVW bits. If bits are not the same
 666          * on different processors then choose the worst case (i.e. if erratum
 667          * is present on one processor and not on another then assume that the
 668          * erratum is present everywhere).
 669          */
 670         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 671                 uint64_t len, status = 0;
 672                 int err;
 673
 674                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 675                 if (!err)
 676                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 677                                                       &err);
 678
 679                 if (err)
 680                         osvw_status = osvw_len = 0;
 681                 else {
 682                         if (len < osvw_len)
 683                                 osvw_len = len;
 684                         osvw_status |= status;
 685                         osvw_status &= (1ULL << osvw_len) - 1;
 686                 }
 687         } else
 688                 osvw_status = osvw_len = 0;
 689
 690         svm_init_erratum_383();
 691
 692         amd_pmu_enable_virt();
 693
 694         return 0;
 695 }
 696
 697 static void svm_cpu_uninit(int cpu)
 698 {
 699         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 700
 701         if (!sd)
 702                 return;
 703
 704         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 705         __free_page(sd->save_area);
 706         kfree(sd);
 707 }
 708
 709 static int svm_cpu_init(int cpu)
 710 {
 711         struct svm_cpu_data *sd;
 712         int r;
 713
 714         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 715         if (!sd)
 716                 return -ENOMEM;
 717         sd->cpu = cpu;
 718         sd->save_area = alloc_page(GFP_KERNEL);
 719         r = -ENOMEM;
 720         if (!sd->save_area)
 721                 goto err_1;
 722
 723         per_cpu(svm_data, cpu) = sd;
 724
 725         return 0;
 726
 727 err_1:
 728         kfree(sd);
 729         return r;
 730
 731 }
 732
 733 static bool valid_msr_intercept(u32 index)
 734 {
 735         int i;
 736
 737         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 738                 if (direct_access_msrs[i].index == index)
 739                         return true;
 740
 741         return false;
 742 }
 743
 744 static void set_msr_interception(u32 *msrpm, unsigned msr,
 745                                  int read, int write)
 746 {
 747         u8 bit_read, bit_write;
 748         unsigned long tmp;
 749         u32 offset;
 750
 751         /*
 752          * If this warning triggers extend the direct_access_msrs list at the
 753          * beginning of the file
 754          */
 755         WARN_ON(!valid_msr_intercept(msr));
 756
 757         offset    = svm_msrpm_offset(msr);
 758         bit_read  = 2 * (msr & 0x0f);
 759         bit_write = 2 * (msr & 0x0f) + 1;
 760         tmp       = msrpm[offset];
 761
 762         BUG_ON(offset == MSR_INVALID);
 763
 764         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 765         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 766
 767         msrpm[offset] = tmp;
 768 }
 769
 770 static void svm_vcpu_init_msrpm(u32 *msrpm)
 771 {
 772         int i;
 773
 774         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 775
 776         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 777                 if (!direct_access_msrs[i].always)
 778                         continue;
 779
 780                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 781         }
 782 }
 783
 784 static void add_msr_offset(u32 offset)
 785 {
 786         int i;
 787
 788         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 789
 790                 /* Offset already in list? */
 791                 if (msrpm_offsets[i] == offset)
 792                         return;
 793
 794                 /* Slot used by another offset? */
 795                 if (msrpm_offsets[i] != MSR_INVALID)
 796                         continue;
 797
 798                 /* Add offset to list */
 799                 msrpm_offsets[i] = offset;
 800
 801                 return;
 802         }
 803
 804         /*
 805          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 806          * increase MSRPM_OFFSETS in this case.
 807          */
 808         BUG();
 809 }
 810
 811 static void init_msrpm_offsets(void)
 812 {
 813         int i;
 814
 815         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 816
 817         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 818                 u32 offset;
 819
 820                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 821                 BUG_ON(offset == MSR_INVALID);
 822
 823                 add_msr_offset(offset);
 824         }
 825 }
 826
 827 static void svm_enable_lbrv(struct vcpu_svm *svm)
 828 {
 829         u32 *msrpm = svm->msrpm;
 830
 831         svm->vmcb->control.lbr_ctl = 1;
 832         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 833         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 834         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 835         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 836 }
 837
 838 static void svm_disable_lbrv(struct vcpu_svm *svm)
 839 {
 840         u32 *msrpm = svm->msrpm;
 841
 842         svm->vmcb->control.lbr_ctl = 0;
 843         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 844         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 845         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 846         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 847 }
 848
 849 static __init int svm_hardware_setup(void)
 850 {
 851         int cpu;
 852         struct page *iopm_pages;
 853         void *iopm_va;
 854         int r;
 855
 856         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 857
 858         if (!iopm_pages)
 859                 return -ENOMEM;
 860
 861         iopm_va = page_address(iopm_pages);
 862         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 863         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 864
 865         init_msrpm_offsets();
 866
 867         if (boot_cpu_has(X86_FEATURE_NX))
 868                 kvm_enable_efer_bits(EFER_NX);
 869
 870         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 871                 kvm_enable_efer_bits(EFER_FFXSR);
 872
 873         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 874                 u64 max;
 875
 876                 kvm_has_tsc_control = true;
 877
 878                 /*
 879                  * Make sure the user can only configure tsc_khz values that
 880                  * fit into a signed integer.
 881                  * A min value is not calculated needed because it will always
 882                  * be 1 on all machines and a value of 0 is used to disable
 883                  * tsc-scaling for the vcpu.
 884                  */
 885                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 886
 887                 kvm_max_guest_tsc_khz = max;
 888         }
 889
 890         if (nested) {
 891                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 892                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 893         }
 894
 895         for_each_possible_cpu(cpu) {
 896                 r = svm_cpu_init(cpu);
 897                 if (r)
 898                         goto err;
 899         }
 900
 901         if (!boot_cpu_has(X86_FEATURE_NPT))
 902                 npt_enabled = false;
 903
 904         if (npt_enabled && !npt) {
 905                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 906                 npt_enabled = false;
 907         }
 908
 909         if (npt_enabled) {
 910                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 911                 kvm_enable_tdp();
 912         } else
 913                 kvm_disable_tdp();
 914
 915         return 0;
 916
 917 err:
 918         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 919         iopm_base = 0;
 920         return r;
 921 }
 922
 923 static __exit void svm_hardware_unsetup(void)
 924 {
 925         int cpu;
 926
 927         for_each_possible_cpu(cpu)
 928                 svm_cpu_uninit(cpu);
 929
 930         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 931         iopm_base = 0;
 932 }
 933
 934 static void init_seg(struct vmcb_seg *seg)
 935 {
 936         seg->selector = 0;
 937         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 938                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 939         seg->limit = 0xffff;
 940         seg->base = 0;
 941 }
 942
 943 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 944 {
 945         seg->selector = 0;
 946         seg->attrib = SVM_SELECTOR_P_MASK | type;
 947         seg->limit = 0xffff;
 948         seg->base = 0;
 949 }
 950
 951 static u64 __scale_tsc(u64 ratio, u64 tsc)
 952 {
 953         u64 mult, frac, _tsc;
 954
 955         mult  = ratio >> 32;
 956         frac  = ratio & ((1ULL << 32) - 1);
 957
 958         _tsc  = tsc;
 959         _tsc *= mult;
 960         _tsc += (tsc >> 32) * frac;
 961         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
 962
 963         return _tsc;
 964 }
 965
 966 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
 967 {
 968         struct vcpu_svm *svm = to_svm(vcpu);
 969         u64 _tsc = tsc;
 970
 971         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
 972                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
 973
 974         return _tsc;
 975 }
 976
 977 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 978 {
 979         struct vcpu_svm *svm = to_svm(vcpu);
 980         u64 ratio;
 981         u64 khz;
 982
 983         /* Guest TSC same frequency as host TSC? */
 984         if (!scale) {
 985                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
 986                 return;
 987         }
 988
 989         /* TSC scaling supported? */
 990         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 991                 if (user_tsc_khz > tsc_khz) {
 992                         vcpu->arch.tsc_catchup = 1;
 993                         vcpu->arch.tsc_always_catchup = 1;
 994                 } else
 995                         WARN(1, "user requested TSC rate below hardware speed\n");
 996                 return;
 997         }
 998
 999         khz = user_tsc_khz;
1000
1001         /* TSC scaling required  - calculate ratio */
1002         ratio = khz << 32;
1003         do_div(ratio, tsc_khz);
1004
1005         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1006                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1007                                 user_tsc_khz);
1008                 return;
1009         }
1010         svm->tsc_ratio             = ratio;
1011 }
1012
1013 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1014 {
1015         struct vcpu_svm *svm = to_svm(vcpu);
1016
1017         return svm->vmcb->control.tsc_offset;
1018 }
1019
1020 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1021 {
1022         struct vcpu_svm *svm = to_svm(vcpu);
1023         u64 g_tsc_offset = 0;
1024
1025         if (is_guest_mode(vcpu)) {
1026                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1027                                svm->nested.hsave->control.tsc_offset;
1028                 svm->nested.hsave->control.tsc_offset = offset;
1029         }
1030
1031         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1032
1033         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1034 }
1035
1036 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1037 {
1038         struct vcpu_svm *svm = to_svm(vcpu);
1039
1040         WARN_ON(adjustment < 0);
1041         if (host)
1042                 adjustment = svm_scale_tsc(vcpu, adjustment);
1043
1044         svm->vmcb->control.tsc_offset += adjustment;
1045         if (is_guest_mode(vcpu))
1046                 svm->nested.hsave->control.tsc_offset += adjustment;
1047         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1048 }
1049
1050 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1051 {
1052         u64 tsc;
1053
1054         tsc = svm_scale_tsc(vcpu, native_read_tsc());
1055
1056         return target_tsc - tsc;
1057 }
1058
1059 static void init_vmcb(struct vcpu_svm *svm)
1060 {
1061         struct vmcb_control_area *control = &svm->vmcb->control;
1062         struct vmcb_save_area *save = &svm->vmcb->save;
1063
1064         svm->vcpu.fpu_active = 1;
1065         svm->vcpu.arch.hflags = 0;
1066
1067         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1068         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1069         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1070         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1071         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1072         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1073         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1074
1075         set_dr_intercept(svm, INTERCEPT_DR0_READ);
1076         set_dr_intercept(svm, INTERCEPT_DR1_READ);
1077         set_dr_intercept(svm, INTERCEPT_DR2_READ);
1078         set_dr_intercept(svm, INTERCEPT_DR3_READ);
1079         set_dr_intercept(svm, INTERCEPT_DR4_READ);
1080         set_dr_intercept(svm, INTERCEPT_DR5_READ);
1081         set_dr_intercept(svm, INTERCEPT_DR6_READ);
1082         set_dr_intercept(svm, INTERCEPT_DR7_READ);
1083
1084         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1085         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1086         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1087         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1088         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1089         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1090         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1091         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1092
1093         set_exception_intercept(svm, PF_VECTOR);
1094         set_exception_intercept(svm, UD_VECTOR);
1095         set_exception_intercept(svm, MC_VECTOR);
1096
1097         set_intercept(svm, INTERCEPT_INTR);
1098         set_intercept(svm, INTERCEPT_NMI);
1099         set_intercept(svm, INTERCEPT_SMI);
1100         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1101         set_intercept(svm, INTERCEPT_RDPMC);
1102         set_intercept(svm, INTERCEPT_CPUID);
1103         set_intercept(svm, INTERCEPT_INVD);
1104         set_intercept(svm, INTERCEPT_HLT);
1105         set_intercept(svm, INTERCEPT_INVLPG);
1106         set_intercept(svm, INTERCEPT_INVLPGA);
1107         set_intercept(svm, INTERCEPT_IOIO_PROT);
1108         set_intercept(svm, INTERCEPT_MSR_PROT);
1109         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1110         set_intercept(svm, INTERCEPT_SHUTDOWN);
1111         set_intercept(svm, INTERCEPT_VMRUN);
1112         set_intercept(svm, INTERCEPT_VMMCALL);
1113         set_intercept(svm, INTERCEPT_VMLOAD);
1114         set_intercept(svm, INTERCEPT_VMSAVE);
1115         set_intercept(svm, INTERCEPT_STGI);
1116         set_intercept(svm, INTERCEPT_CLGI);
1117         set_intercept(svm, INTERCEPT_SKINIT);
1118         set_intercept(svm, INTERCEPT_WBINVD);
1119         set_intercept(svm, INTERCEPT_MONITOR);
1120         set_intercept(svm, INTERCEPT_MWAIT);
1121         set_intercept(svm, INTERCEPT_XSETBV);
1122
1123         control->iopm_base_pa = iopm_base;
1124         control->msrpm_base_pa = __pa(svm->msrpm);
1125         control->int_ctl = V_INTR_MASKING_MASK;
1126
1127         init_seg(&save->es);
1128         init_seg(&save->ss);
1129         init_seg(&save->ds);
1130         init_seg(&save->fs);
1131         init_seg(&save->gs);
1132
1133         save->cs.selector = 0xf000;
1134         save->cs.base = 0xffff0000;
1135         /* Executable/Readable Code Segment */
1136         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1137                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1138         save->cs.limit = 0xffff;
1139
1140         save->gdtr.limit = 0xffff;
1141         save->idtr.limit = 0xffff;
1142
1143         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1144         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1145
1146         svm_set_efer(&svm->vcpu, 0);
1147         save->dr6 = 0xffff0ff0;
1148         kvm_set_rflags(&svm->vcpu, 2);
1149         save->rip = 0x0000fff0;
1150         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1151
1152         /*
1153          * This is the guest-visible cr0 value.
1154          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1155          */
1156         svm->vcpu.arch.cr0 = 0;
1157         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1158
1159         save->cr4 = X86_CR4_PAE;
1160         /* rdx = ?? */
1161
1162         if (npt_enabled) {
1163                 /* Setup VMCB for Nested Paging */
1164                 control->nested_ctl = 1;
1165                 clr_intercept(svm, INTERCEPT_INVLPG);
1166                 clr_exception_intercept(svm, PF_VECTOR);
1167                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1168                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1169                 save->g_pat = 0x0007040600070406ULL;
1170                 save->cr3 = 0;
1171                 save->cr4 = 0;
1172         }
1173         svm->asid_generation = 0;
1174
1175         svm->nested.vmcb = 0;
1176         svm->vcpu.arch.hflags = 0;
1177
1178         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1179                 control->pause_filter_count = 3000;
1180                 set_intercept(svm, INTERCEPT_PAUSE);
1181         }
1182
1183         mark_all_dirty(svm->vmcb);
1184
1185         enable_gif(svm);
1186 }
1187
1188 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1189 {
1190         struct vcpu_svm *svm = to_svm(vcpu);
1191         u32 dummy;
1192         u32 eax = 1;
1193
1194         init_vmcb(svm);
1195
1196         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1197         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1198 }
1199
1200 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1201 {
1202         struct vcpu_svm *svm;
1203         struct page *page;
1204         struct page *msrpm_pages;
1205         struct page *hsave_page;
1206         struct page *nested_msrpm_pages;
1207         int err;
1208
1209         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1210         if (!svm) {
1211                 err = -ENOMEM;
1212                 goto out;
1213         }
1214
1215         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1216
1217         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1218         if (err)
1219                 goto free_svm;
1220
1221         err = -ENOMEM;
1222         page = alloc_page(GFP_KERNEL);
1223         if (!page)
1224                 goto uninit;
1225
1226         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1227         if (!msrpm_pages)
1228                 goto free_page1;
1229
1230         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1231         if (!nested_msrpm_pages)
1232                 goto free_page2;
1233
1234         hsave_page = alloc_page(GFP_KERNEL);
1235         if (!hsave_page)
1236                 goto free_page3;
1237
1238         svm->nested.hsave = page_address(hsave_page);
1239
1240         svm->msrpm = page_address(msrpm_pages);
1241         svm_vcpu_init_msrpm(svm->msrpm);
1242
1243         svm->nested.msrpm = page_address(nested_msrpm_pages);
1244         svm_vcpu_init_msrpm(svm->nested.msrpm);
1245
1246         svm->vmcb = page_address(page);
1247         clear_page(svm->vmcb);
1248         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1249         svm->asid_generation = 0;
1250         init_vmcb(svm);
1251
1252         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1253         if (kvm_vcpu_is_bsp(&svm->vcpu))
1254                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1255
1256         svm_init_osvw(&svm->vcpu);
1257
1258         return &svm->vcpu;
1259
1260 free_page3:
1261         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1262 free_page2:
1263         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1264 free_page1:
1265         __free_page(page);
1266 uninit:
1267         kvm_vcpu_uninit(&svm->vcpu);
1268 free_svm:
1269         kmem_cache_free(kvm_vcpu_cache, svm);
1270 out:
1271         return ERR_PTR(err);
1272 }
1273
1274 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1275 {
1276         struct vcpu_svm *svm = to_svm(vcpu);
1277
1278         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1279         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1280         __free_page(virt_to_page(svm->nested.hsave));
1281         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1282         kvm_vcpu_uninit(vcpu);
1283         kmem_cache_free(kvm_vcpu_cache, svm);
1284 }
1285
1286 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1287 {
1288         struct vcpu_svm *svm = to_svm(vcpu);
1289         int i;
1290
1291         if (unlikely(cpu != vcpu->cpu)) {
1292                 svm->asid_generation = 0;
1293                 mark_all_dirty(svm->vmcb);
1294         }
1295
1296 #ifdef CONFIG_X86_64
1297         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1298 #endif
1299         savesegment(fs, svm->host.fs);
1300         savesegment(gs, svm->host.gs);
1301         svm->host.ldt = kvm_read_ldt();
1302
1303         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1304                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1305
1306         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1307             svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1308                 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1309                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1310         }
1311 }
1312
1313 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1314 {
1315         struct vcpu_svm *svm = to_svm(vcpu);
1316         int i;
1317
1318         ++vcpu->stat.host_state_reload;
1319         kvm_load_ldt(svm->host.ldt);
1320 #ifdef CONFIG_X86_64
1321         loadsegment(fs, svm->host.fs);
1322         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1323         load_gs_index(svm->host.gs);
1324 #else
1325 #ifdef CONFIG_X86_32_LAZY_GS
1326         loadsegment(gs, svm->host.gs);
1327 #endif
1328 #endif
1329         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1330                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1331 }
1332
1333 static void svm_update_cpl(struct kvm_vcpu *vcpu)
1334 {
1335         struct vcpu_svm *svm = to_svm(vcpu);
1336         int cpl;
1337
1338         if (!is_protmode(vcpu))
1339                 cpl = 0;
1340         else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1341                 cpl = 3;
1342         else
1343                 cpl = svm->vmcb->save.cs.selector & 0x3;
1344
1345         svm->vmcb->save.cpl = cpl;
1346 }
1347
1348 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1349 {
1350         return to_svm(vcpu)->vmcb->save.rflags;
1351 }
1352
1353 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1354 {
1355         unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1356
1357         to_svm(vcpu)->vmcb->save.rflags = rflags;
1358         if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1359                 svm_update_cpl(vcpu);
1360 }
1361
1362 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1363 {
1364         switch (reg) {
1365         case VCPU_EXREG_PDPTR:
1366                 BUG_ON(!npt_enabled);
1367                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1368                 break;
1369         default:
1370                 BUG();
1371         }
1372 }
1373
1374 static void svm_set_vintr(struct vcpu_svm *svm)
1375 {
1376         set_intercept(svm, INTERCEPT_VINTR);
1377 }
1378
1379 static void svm_clear_vintr(struct vcpu_svm *svm)
1380 {
1381         clr_intercept(svm, INTERCEPT_VINTR);
1382 }
1383
1384 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1385 {
1386         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1387
1388         switch (seg) {
1389         case VCPU_SREG_CS: return &save->cs;
1390         case VCPU_SREG_DS: return &save->ds;
1391         case VCPU_SREG_ES: return &save->es;
1392         case VCPU_SREG_FS: return &save->fs;
1393         case VCPU_SREG_GS: return &save->gs;
1394         case VCPU_SREG_SS: return &save->ss;
1395         case VCPU_SREG_TR: return &save->tr;
1396         case VCPU_SREG_LDTR: return &save->ldtr;
1397         }
1398         BUG();
1399         return NULL;
1400 }
1401
1402 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1403 {
1404         struct vmcb_seg *s = svm_seg(vcpu, seg);
1405
1406         return s->base;
1407 }
1408
1409 static void svm_get_segment(struct kvm_vcpu *vcpu,
1410                             struct kvm_segment *var, int seg)
1411 {
1412         struct vmcb_seg *s = svm_seg(vcpu, seg);
1413
1414         var->base = s->base;
1415         var->limit = s->limit;
1416         var->selector = s->selector;
1417         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1418         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1419         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1420         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1421         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1422         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1423         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1424         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1425
1426         /*
1427          * AMD's VMCB does not have an explicit unusable field, so emulate it
1428          * for cross vendor migration purposes by "not present"
1429          */
1430         var->unusable = !var->present || (var->type == 0);
1431
1432         switch (seg) {
1433         case VCPU_SREG_CS:
1434                 /*
1435                  * SVM always stores 0 for the 'G' bit in the CS selector in
1436                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1437                  * Intel's VMENTRY has a check on the 'G' bit.
1438                  */
1439                 var->g = s->limit > 0xfffff;
1440                 break;
1441         case VCPU_SREG_TR:
1442                 /*
1443                  * Work around a bug where the busy flag in the tr selector
1444                  * isn't exposed
1445                  */
1446                 var->type |= 0x2;
1447                 break;
1448         case VCPU_SREG_DS:
1449         case VCPU_SREG_ES:
1450         case VCPU_SREG_FS:
1451         case VCPU_SREG_GS:
1452                 /*
1453                  * The accessed bit must always be set in the segment
1454                  * descriptor cache, although it can be cleared in the
1455                  * descriptor, the cached bit always remains at 1. Since
1456                  * Intel has a check on this, set it here to support
1457                  * cross-vendor migration.
1458                  */
1459                 if (!var->unusable)
1460                         var->type |= 0x1;
1461                 break;
1462         case VCPU_SREG_SS:
1463                 /*
1464                  * On AMD CPUs sometimes the DB bit in the segment
1465                  * descriptor is left as 1, although the whole segment has
1466                  * been made unusable. Clear it here to pass an Intel VMX
1467                  * entry check when cross vendor migrating.
1468                  */
1469                 if (var->unusable)
1470                         var->db = 0;
1471                 break;
1472         }
1473 }
1474
1475 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1476 {
1477         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1478
1479         return save->cpl;
1480 }
1481
1482 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1483 {
1484         struct vcpu_svm *svm = to_svm(vcpu);
1485
1486         dt->size = svm->vmcb->save.idtr.limit;
1487         dt->address = svm->vmcb->save.idtr.base;
1488 }
1489
1490 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1491 {
1492         struct vcpu_svm *svm = to_svm(vcpu);
1493
1494         svm->vmcb->save.idtr.limit = dt->size;
1495         svm->vmcb->save.idtr.base = dt->address ;
1496         mark_dirty(svm->vmcb, VMCB_DT);
1497 }
1498
1499 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1500 {
1501         struct vcpu_svm *svm = to_svm(vcpu);
1502
1503         dt->size = svm->vmcb->save.gdtr.limit;
1504         dt->address = svm->vmcb->save.gdtr.base;
1505 }
1506
1507 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1508 {
1509         struct vcpu_svm *svm = to_svm(vcpu);
1510
1511         svm->vmcb->save.gdtr.limit = dt->size;
1512         svm->vmcb->save.gdtr.base = dt->address ;
1513         mark_dirty(svm->vmcb, VMCB_DT);
1514 }
1515
1516 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1517 {
1518 }
1519
1520 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1521 {
1522 }
1523
1524 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1525 {
1526 }
1527
1528 static void update_cr0_intercept(struct vcpu_svm *svm)
1529 {
1530         ulong gcr0 = svm->vcpu.arch.cr0;
1531         u64 *hcr0 = &svm->vmcb->save.cr0;
1532
1533         if (!svm->vcpu.fpu_active)
1534                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1535         else
1536                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1537                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1538
1539         mark_dirty(svm->vmcb, VMCB_CR);
1540
1541         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1542                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1543                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1544         } else {
1545                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1546                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1547         }
1548 }
1549
1550 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1551 {
1552         struct vcpu_svm *svm = to_svm(vcpu);
1553
1554 #ifdef CONFIG_X86_64
1555         if (vcpu->arch.efer & EFER_LME) {
1556                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1557                         vcpu->arch.efer |= EFER_LMA;
1558                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1559                 }
1560
1561                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1562                         vcpu->arch.efer &= ~EFER_LMA;
1563                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1564                 }
1565         }
1566 #endif
1567         vcpu->arch.cr0 = cr0;
1568
1569         if (!npt_enabled)
1570                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1571
1572         if (!vcpu->fpu_active)
1573                 cr0 |= X86_CR0_TS;
1574         /*
1575          * re-enable caching here because the QEMU bios
1576          * does not do it - this results in some delay at
1577          * reboot
1578          */
1579         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1580         svm->vmcb->save.cr0 = cr0;
1581         mark_dirty(svm->vmcb, VMCB_CR);
1582         update_cr0_intercept(svm);
1583 }
1584
1585 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1586 {
1587         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1588         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1589
1590         if (cr4 & X86_CR4_VMXE)
1591                 return 1;
1592
1593         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1594                 svm_flush_tlb(vcpu);
1595
1596         vcpu->arch.cr4 = cr4;
1597         if (!npt_enabled)
1598                 cr4 |= X86_CR4_PAE;
1599         cr4 |= host_cr4_mce;
1600         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1601         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1602         return 0;
1603 }
1604
1605 static void svm_set_segment(struct kvm_vcpu *vcpu,
1606                             struct kvm_segment *var, int seg)
1607 {
1608         struct vcpu_svm *svm = to_svm(vcpu);
1609         struct vmcb_seg *s = svm_seg(vcpu, seg);
1610
1611         s->base = var->base;
1612         s->limit = var->limit;
1613         s->selector = var->selector;
1614         if (var->unusable)
1615                 s->attrib = 0;
1616         else {
1617                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1618                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1619                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1620                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1621                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1622                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1623                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1624                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1625         }
1626         if (seg == VCPU_SREG_CS)
1627                 svm_update_cpl(vcpu);
1628
1629         mark_dirty(svm->vmcb, VMCB_SEG);
1630 }
1631
1632 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1633 {
1634         struct vcpu_svm *svm = to_svm(vcpu);
1635
1636         clr_exception_intercept(svm, DB_VECTOR);
1637         clr_exception_intercept(svm, BP_VECTOR);
1638
1639         if (svm->nmi_singlestep)
1640                 set_exception_intercept(svm, DB_VECTOR);
1641
1642         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1643                 if (vcpu->guest_debug &
1644                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1645                         set_exception_intercept(svm, DB_VECTOR);
1646                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1647                         set_exception_intercept(svm, BP_VECTOR);
1648         } else
1649                 vcpu->guest_debug = 0;
1650 }
1651
1652 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1653 {
1654         if (sd->next_asid > sd->max_asid) {
1655                 ++sd->asid_generation;
1656                 sd->next_asid = 1;
1657                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1658         }
1659
1660         svm->asid_generation = sd->asid_generation;
1661         svm->vmcb->control.asid = sd->next_asid++;
1662
1663         mark_dirty(svm->vmcb, VMCB_ASID);
1664 }
1665
1666 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1667 {
1668         struct vcpu_svm *svm = to_svm(vcpu);
1669
1670         svm->vmcb->save.dr7 = value;
1671         mark_dirty(svm->vmcb, VMCB_DR);
1672 }
1673
1674 static int pf_interception(struct vcpu_svm *svm)
1675 {
1676         u64 fault_address = svm->vmcb->control.exit_info_2;
1677         u32 error_code;
1678         int r = 1;
1679
1680         switch (svm->apf_reason) {
1681         default:
1682                 error_code = svm->vmcb->control.exit_info_1;
1683
1684                 trace_kvm_page_fault(fault_address, error_code);
1685                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1686                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1687                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1688                         svm->vmcb->control.insn_bytes,
1689                         svm->vmcb->control.insn_len);
1690                 break;
1691         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1692                 svm->apf_reason = 0;
1693                 local_irq_disable();
1694                 kvm_async_pf_task_wait(fault_address);
1695                 local_irq_enable();
1696                 break;
1697         case KVM_PV_REASON_PAGE_READY:
1698                 svm->apf_reason = 0;
1699                 local_irq_disable();
1700                 kvm_async_pf_task_wake(fault_address);
1701                 local_irq_enable();
1702                 break;
1703         }
1704         return r;
1705 }
1706
1707 static int db_interception(struct vcpu_svm *svm)
1708 {
1709         struct kvm_run *kvm_run = svm->vcpu.run;
1710
1711         if (!(svm->vcpu.guest_debug &
1712               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1713                 !svm->nmi_singlestep) {
1714                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1715                 return 1;
1716         }
1717
1718         if (svm->nmi_singlestep) {
1719                 svm->nmi_singlestep = false;
1720                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1721                         svm->vmcb->save.rflags &=
1722                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1723                 update_db_bp_intercept(&svm->vcpu);
1724         }
1725
1726         if (svm->vcpu.guest_debug &
1727             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1728                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1729                 kvm_run->debug.arch.pc =
1730                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1731                 kvm_run->debug.arch.exception = DB_VECTOR;
1732                 return 0;
1733         }
1734
1735         return 1;
1736 }
1737
1738 static int bp_interception(struct vcpu_svm *svm)
1739 {
1740         struct kvm_run *kvm_run = svm->vcpu.run;
1741
1742         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1743         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1744         kvm_run->debug.arch.exception = BP_VECTOR;
1745         return 0;
1746 }
1747
1748 static int ud_interception(struct vcpu_svm *svm)
1749 {
1750         int er;
1751
1752         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1753         if (er != EMULATE_DONE)
1754                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1755         return 1;
1756 }
1757
1758 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1759 {
1760         struct vcpu_svm *svm = to_svm(vcpu);
1761
1762         clr_exception_intercept(svm, NM_VECTOR);
1763
1764         svm->vcpu.fpu_active = 1;
1765         update_cr0_intercept(svm);
1766 }
1767
1768 static int nm_interception(struct vcpu_svm *svm)
1769 {
1770         svm_fpu_activate(&svm->vcpu);
1771         return 1;
1772 }
1773
1774 static bool is_erratum_383(void)
1775 {
1776         int err, i;
1777         u64 value;
1778
1779         if (!erratum_383_found)
1780                 return false;
1781
1782         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1783         if (err)
1784                 return false;
1785
1786         /* Bit 62 may or may not be set for this mce */
1787         value &= ~(1ULL << 62);
1788
1789         if (value != 0xb600000000010015ULL)
1790                 return false;
1791
1792         /* Clear MCi_STATUS registers */
1793         for (i = 0; i < 6; ++i)
1794                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1795
1796         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1797         if (!err) {
1798                 u32 low, high;
1799
1800                 value &= ~(1ULL << 2);
1801                 low    = lower_32_bits(value);
1802                 high   = upper_32_bits(value);
1803
1804                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1805         }
1806
1807         /* Flush tlb to evict multi-match entries */
1808         __flush_tlb_all();
1809
1810         return true;
1811 }
1812
1813 static void svm_handle_mce(struct vcpu_svm *svm)
1814 {
1815         if (is_erratum_383()) {
1816                 /*
1817                  * Erratum 383 triggered. Guest state is corrupt so kill the
1818                  * guest.
1819                  */
1820                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1821
1822                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1823
1824                 return;
1825         }
1826
1827         /*
1828          * On an #MC intercept the MCE handler is not called automatically in
1829          * the host. So do it by hand here.
1830          */
1831         asm volatile (
1832                 "int $0x12\n");
1833         /* not sure if we ever come back to this point */
1834
1835         return;
1836 }
1837
1838 static int mc_interception(struct vcpu_svm *svm)
1839 {
1840         return 1;
1841 }
1842
1843 static int shutdown_interception(struct vcpu_svm *svm)
1844 {
1845         struct kvm_run *kvm_run = svm->vcpu.run;
1846
1847         /*
1848          * VMCB is undefined after a SHUTDOWN intercept
1849          * so reinitialize it.
1850          */
1851         clear_page(svm->vmcb);
1852         init_vmcb(svm);
1853
1854         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1855         return 0;
1856 }
1857
1858 static int io_interception(struct vcpu_svm *svm)
1859 {
1860         struct kvm_vcpu *vcpu = &svm->vcpu;
1861         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1862         int size, in, string;
1863         unsigned port;
1864
1865         ++svm->vcpu.stat.io_exits;
1866         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1867         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1868         if (string || in)
1869                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1870
1871         port = io_info >> 16;
1872         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1873         svm->next_rip = svm->vmcb->control.exit_info_2;
1874         skip_emulated_instruction(&svm->vcpu);
1875
1876         return kvm_fast_pio_out(vcpu, size, port);
1877 }
1878
1879 static int nmi_interception(struct vcpu_svm *svm)
1880 {
1881         return 1;
1882 }
1883
1884 static int intr_interception(struct vcpu_svm *svm)
1885 {
1886         ++svm->vcpu.stat.irq_exits;
1887         return 1;
1888 }
1889
1890 static int nop_on_interception(struct vcpu_svm *svm)
1891 {
1892         return 1;
1893 }
1894
1895 static int halt_interception(struct vcpu_svm *svm)
1896 {
1897         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1898         skip_emulated_instruction(&svm->vcpu);
1899         return kvm_emulate_halt(&svm->vcpu);
1900 }
1901
1902 static int vmmcall_interception(struct vcpu_svm *svm)
1903 {
1904         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1905         skip_emulated_instruction(&svm->vcpu);
1906         kvm_emulate_hypercall(&svm->vcpu);
1907         return 1;
1908 }
1909
1910 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1911 {
1912         struct vcpu_svm *svm = to_svm(vcpu);
1913
1914         return svm->nested.nested_cr3;
1915 }
1916
1917 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1918 {
1919         struct vcpu_svm *svm = to_svm(vcpu);
1920         u64 cr3 = svm->nested.nested_cr3;
1921         u64 pdpte;
1922         int ret;
1923
1924         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1925                                   offset_in_page(cr3) + index * 8, 8);
1926         if (ret)
1927                 return 0;
1928         return pdpte;
1929 }
1930
1931 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1932                                    unsigned long root)
1933 {
1934         struct vcpu_svm *svm = to_svm(vcpu);
1935
1936         svm->vmcb->control.nested_cr3 = root;
1937         mark_dirty(svm->vmcb, VMCB_NPT);
1938         svm_flush_tlb(vcpu);
1939 }
1940
1941 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1942                                        struct x86_exception *fault)
1943 {
1944         struct vcpu_svm *svm = to_svm(vcpu);
1945
1946         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1947         svm->vmcb->control.exit_code_hi = 0;
1948         svm->vmcb->control.exit_info_1 = fault->error_code;
1949         svm->vmcb->control.exit_info_2 = fault->address;
1950
1951         nested_svm_vmexit(svm);
1952 }
1953
1954 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1955 {
1956         int r;
1957
1958         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1959
1960         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1961         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1962         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
1963         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1964         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1965         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1966
1967         return r;
1968 }
1969
1970 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1971 {
1972         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1973 }
1974
1975 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1976 {
1977         if (!(svm->vcpu.arch.efer & EFER_SVME)
1978             || !is_paging(&svm->vcpu)) {
1979                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1980                 return 1;
1981         }
1982
1983         if (svm->vmcb->save.cpl) {
1984                 kvm_inject_gp(&svm->vcpu, 0);
1985                 return 1;
1986         }
1987
1988        return 0;
1989 }
1990
1991 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1992                                       bool has_error_code, u32 error_code)
1993 {
1994         int vmexit;
1995
1996         if (!is_guest_mode(&svm->vcpu))
1997                 return 0;
1998
1999         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2000         svm->vmcb->control.exit_code_hi = 0;
2001         svm->vmcb->control.exit_info_1 = error_code;
2002         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2003
2004         vmexit = nested_svm_intercept(svm);
2005         if (vmexit == NESTED_EXIT_DONE)
2006                 svm->nested.exit_required = true;
2007
2008         return vmexit;
2009 }
2010
2011 /* This function returns true if it is save to enable the irq window */
2012 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2013 {
2014         if (!is_guest_mode(&svm->vcpu))
2015                 return true;
2016
2017         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2018                 return true;
2019
2020         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2021                 return false;
2022
2023         /*
2024          * if vmexit was already requested (by intercepted exception
2025          * for instance) do not overwrite it with "external interrupt"
2026          * vmexit.
2027          */
2028         if (svm->nested.exit_required)
2029                 return false;
2030
2031         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2032         svm->vmcb->control.exit_info_1 = 0;
2033         svm->vmcb->control.exit_info_2 = 0;
2034
2035         if (svm->nested.intercept & 1ULL) {
2036                 /*
2037                  * The #vmexit can't be emulated here directly because this
2038                  * code path runs with irqs and preemption disabled. A
2039                  * #vmexit emulation might sleep. Only signal request for
2040                  * the #vmexit here.
2041                  */
2042                 svm->nested.exit_required = true;
2043                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2044                 return false;
2045         }
2046
2047         return true;
2048 }
2049
2050 /* This function returns true if it is save to enable the nmi window */
2051 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2052 {
2053         if (!is_guest_mode(&svm->vcpu))
2054                 return true;
2055
2056         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2057                 return true;
2058
2059         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2060         svm->nested.exit_required = true;
2061
2062         return false;
2063 }
2064
2065 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2066 {
2067         struct page *page;
2068
2069         might_sleep();
2070
2071         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2072         if (is_error_page(page))
2073                 goto error;
2074
2075         *_page = page;
2076
2077         return kmap(page);
2078
2079 error:
2080         kvm_inject_gp(&svm->vcpu, 0);
2081
2082         return NULL;
2083 }
2084
2085 static void nested_svm_unmap(struct page *page)
2086 {
2087         kunmap(page);
2088         kvm_release_page_dirty(page);
2089 }
2090
2091 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2092 {
2093         unsigned port;
2094         u8 val, bit;
2095         u64 gpa;
2096
2097         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2098                 return NESTED_EXIT_HOST;
2099
2100         port = svm->vmcb->control.exit_info_1 >> 16;
2101         gpa  = svm->nested.vmcb_iopm + (port / 8);
2102         bit  = port % 8;
2103         val  = 0;
2104
2105         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2106                 val &= (1 << bit);
2107
2108         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2109 }
2110
2111 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2112 {
2113         u32 offset, msr, value;
2114         int write, mask;
2115
2116         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2117                 return NESTED_EXIT_HOST;
2118
2119         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2120         offset = svm_msrpm_offset(msr);
2121         write  = svm->vmcb->control.exit_info_1 & 1;
2122         mask   = 1 << ((2 * (msr & 0xf)) + write);
2123
2124         if (offset == MSR_INVALID)
2125                 return NESTED_EXIT_DONE;
2126
2127         /* Offset is in 32 bit units but need in 8 bit units */
2128         offset *= 4;
2129
2130         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2131                 return NESTED_EXIT_DONE;
2132
2133         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2134 }
2135
2136 static int nested_svm_exit_special(struct vcpu_svm *svm)
2137 {
2138         u32 exit_code = svm->vmcb->control.exit_code;
2139
2140         switch (exit_code) {
2141         case SVM_EXIT_INTR:
2142         case SVM_EXIT_NMI:
2143         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2144                 return NESTED_EXIT_HOST;
2145         case SVM_EXIT_NPF:
2146                 /* For now we are always handling NPFs when using them */
2147                 if (npt_enabled)
2148                         return NESTED_EXIT_HOST;
2149                 break;
2150         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2151                 /* When we're shadowing, trap PFs, but not async PF */
2152                 if (!npt_enabled && svm->apf_reason == 0)
2153                         return NESTED_EXIT_HOST;
2154                 break;
2155         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2156                 nm_interception(svm);
2157                 break;
2158         default:
2159                 break;
2160         }
2161
2162         return NESTED_EXIT_CONTINUE;
2163 }
2164
2165 /*
2166  * If this function returns true, this #vmexit was already handled
2167  */
2168 static int nested_svm_intercept(struct vcpu_svm *svm)
2169 {
2170         u32 exit_code = svm->vmcb->control.exit_code;
2171         int vmexit = NESTED_EXIT_HOST;
2172
2173         switch (exit_code) {
2174         case SVM_EXIT_MSR:
2175                 vmexit = nested_svm_exit_handled_msr(svm);
2176                 break;
2177         case SVM_EXIT_IOIO:
2178                 vmexit = nested_svm_intercept_ioio(svm);
2179                 break;
2180         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2181                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2182                 if (svm->nested.intercept_cr & bit)
2183                         vmexit = NESTED_EXIT_DONE;
2184                 break;
2185         }
2186         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2187                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2188                 if (svm->nested.intercept_dr & bit)
2189                         vmexit = NESTED_EXIT_DONE;
2190                 break;
2191         }
2192         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2193                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2194                 if (svm->nested.intercept_exceptions & excp_bits)
2195                         vmexit = NESTED_EXIT_DONE;
2196                 /* async page fault always cause vmexit */
2197                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2198                          svm->apf_reason != 0)
2199                         vmexit = NESTED_EXIT_DONE;
2200                 break;
2201         }
2202         case SVM_EXIT_ERR: {
2203                 vmexit = NESTED_EXIT_DONE;
2204                 break;
2205         }
2206         default: {
2207                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2208                 if (svm->nested.intercept & exit_bits)
2209                         vmexit = NESTED_EXIT_DONE;
2210         }
2211         }
2212
2213         return vmexit;
2214 }
2215
2216 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2217 {
2218         int vmexit;
2219
2220         vmexit = nested_svm_intercept(svm);
2221
2222         if (vmexit == NESTED_EXIT_DONE)
2223                 nested_svm_vmexit(svm);
2224
2225         return vmexit;
2226 }
2227
2228 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2229 {
2230         struct vmcb_control_area *dst  = &dst_vmcb->control;
2231         struct vmcb_control_area *from = &from_vmcb->control;
2232
2233         dst->intercept_cr         = from->intercept_cr;
2234         dst->intercept_dr         = from->intercept_dr;
2235         dst->intercept_exceptions = from->intercept_exceptions;
2236         dst->intercept            = from->intercept;
2237         dst->iopm_base_pa         = from->iopm_base_pa;
2238         dst->msrpm_base_pa        = from->msrpm_base_pa;
2239         dst->tsc_offset           = from->tsc_offset;
2240         dst->asid                 = from->asid;
2241         dst->tlb_ctl              = from->tlb_ctl;
2242         dst->int_ctl              = from->int_ctl;
2243         dst->int_vector           = from->int_vector;
2244         dst->int_state            = from->int_state;
2245         dst->exit_code            = from->exit_code;
2246         dst->exit_code_hi         = from->exit_code_hi;
2247         dst->exit_info_1          = from->exit_info_1;
2248         dst->exit_info_2          = from->exit_info_2;
2249         dst->exit_int_info        = from->exit_int_info;
2250         dst->exit_int_info_err    = from->exit_int_info_err;
2251         dst->nested_ctl           = from->nested_ctl;
2252         dst->event_inj            = from->event_inj;
2253         dst->event_inj_err        = from->event_inj_err;
2254         dst->nested_cr3           = from->nested_cr3;
2255         dst->lbr_ctl              = from->lbr_ctl;
2256 }
2257
2258 static int nested_svm_vmexit(struct vcpu_svm *svm)
2259 {
2260         struct vmcb *nested_vmcb;
2261         struct vmcb *hsave = svm->nested.hsave;
2262         struct vmcb *vmcb = svm->vmcb;
2263         struct page *page;
2264
2265         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2266                                        vmcb->control.exit_info_1,
2267                                        vmcb->control.exit_info_2,
2268                                        vmcb->control.exit_int_info,
2269                                        vmcb->control.exit_int_info_err,
2270                                        KVM_ISA_SVM);
2271
2272         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2273         if (!nested_vmcb)
2274                 return 1;
2275
2276         /* Exit Guest-Mode */
2277         leave_guest_mode(&svm->vcpu);
2278         svm->nested.vmcb = 0;
2279
2280         /* Give the current vmcb to the guest */
2281         disable_gif(svm);
2282
2283         nested_vmcb->save.es     = vmcb->save.es;
2284         nested_vmcb->save.cs     = vmcb->save.cs;
2285         nested_vmcb->save.ss     = vmcb->save.ss;
2286         nested_vmcb->save.ds     = vmcb->save.ds;
2287         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2288         nested_vmcb->save.idtr   = vmcb->save.idtr;
2289         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2290         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2291         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2292         nested_vmcb->save.cr2    = vmcb->save.cr2;
2293         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2294         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2295         nested_vmcb->save.rip    = vmcb->save.rip;
2296         nested_vmcb->save.rsp    = vmcb->save.rsp;
2297         nested_vmcb->save.rax    = vmcb->save.rax;
2298         nested_vmcb->save.dr7    = vmcb->save.dr7;
2299         nested_vmcb->save.dr6    = vmcb->save.dr6;
2300         nested_vmcb->save.cpl    = vmcb->save.cpl;
2301
2302         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2303         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2304         nested_vmcb->control.int_state         = vmcb->control.int_state;
2305         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2306         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2307         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2308         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2309         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2310         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2311         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2312
2313         /*
2314          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2315          * to make sure that we do not lose injected events. So check event_inj
2316          * here and copy it to exit_int_info if it is valid.
2317          * Exit_int_info and event_inj can't be both valid because the case
2318          * below only happens on a VMRUN instruction intercept which has
2319          * no valid exit_int_info set.
2320          */
2321         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2322                 struct vmcb_control_area *nc = &nested_vmcb->control;
2323
2324                 nc->exit_int_info     = vmcb->control.event_inj;
2325                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2326         }
2327
2328         nested_vmcb->control.tlb_ctl           = 0;
2329         nested_vmcb->control.event_inj         = 0;
2330         nested_vmcb->control.event_inj_err     = 0;
2331
2332         /* We always set V_INTR_MASKING and remember the old value in hflags */
2333         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2334                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2335
2336         /* Restore the original control entries */
2337         copy_vmcb_control_area(vmcb, hsave);
2338
2339         kvm_clear_exception_queue(&svm->vcpu);
2340         kvm_clear_interrupt_queue(&svm->vcpu);
2341
2342         svm->nested.nested_cr3 = 0;
2343
2344         /* Restore selected save entries */
2345         svm->vmcb->save.es = hsave->save.es;
2346         svm->vmcb->save.cs = hsave->save.cs;
2347         svm->vmcb->save.ss = hsave->save.ss;
2348         svm->vmcb->save.ds = hsave->save.ds;
2349         svm->vmcb->save.gdtr = hsave->save.gdtr;
2350         svm->vmcb->save.idtr = hsave->save.idtr;
2351         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2352         svm_set_efer(&svm->vcpu, hsave->save.efer);
2353         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2354         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2355         if (npt_enabled) {
2356                 svm->vmcb->save.cr3 = hsave->save.cr3;
2357                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2358         } else {
2359                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2360         }
2361         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2362         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2363         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2364         svm->vmcb->save.dr7 = 0;
2365         svm->vmcb->save.cpl = 0;
2366         svm->vmcb->control.exit_int_info = 0;
2367
2368         mark_all_dirty(svm->vmcb);
2369
2370         nested_svm_unmap(page);
2371
2372         nested_svm_uninit_mmu_context(&svm->vcpu);
2373         kvm_mmu_reset_context(&svm->vcpu);
2374         kvm_mmu_load(&svm->vcpu);
2375
2376         return 0;
2377 }
2378
2379 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2380 {
2381         /*
2382          * This function merges the msr permission bitmaps of kvm and the
2383          * nested vmcb. It is optimized in that it only merges the parts where
2384          * the kvm msr permission bitmap may contain zero bits
2385          */
2386         int i;
2387
2388         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2389                 return true;
2390
2391         for (i = 0; i < MSRPM_OFFSETS; i++) {
2392                 u32 value, p;
2393                 u64 offset;
2394
2395                 if (msrpm_offsets[i] == 0xffffffff)
2396                         break;
2397
2398                 p      = msrpm_offsets[i];
2399                 offset = svm->nested.vmcb_msrpm + (p * 4);
2400
2401                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2402                         return false;
2403
2404                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2405         }
2406
2407         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2408
2409         return true;
2410 }
2411
2412 static bool nested_vmcb_checks(struct vmcb *vmcb)
2413 {
2414         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2415                 return false;
2416
2417         if (vmcb->control.asid == 0)
2418                 return false;
2419
2420         if (vmcb->control.nested_ctl && !npt_enabled)
2421                 return false;
2422
2423         return true;
2424 }
2425
2426 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2427 {
2428         struct vmcb *nested_vmcb;
2429         struct vmcb *hsave = svm->nested.hsave;
2430         struct vmcb *vmcb = svm->vmcb;
2431         struct page *page;
2432         u64 vmcb_gpa;
2433
2434         vmcb_gpa = svm->vmcb->save.rax;
2435
2436         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2437         if (!nested_vmcb)
2438                 return false;
2439
2440         if (!nested_vmcb_checks(nested_vmcb)) {
2441                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2442                 nested_vmcb->control.exit_code_hi = 0;
2443                 nested_vmcb->control.exit_info_1  = 0;
2444                 nested_vmcb->control.exit_info_2  = 0;
2445
2446                 nested_svm_unmap(page);
2447
2448                 return false;
2449         }
2450
2451         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2452                                nested_vmcb->save.rip,
2453                                nested_vmcb->control.int_ctl,
2454                                nested_vmcb->control.event_inj,
2455                                nested_vmcb->control.nested_ctl);
2456
2457         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2458                                     nested_vmcb->control.intercept_cr >> 16,
2459                                     nested_vmcb->control.intercept_exceptions,
2460                                     nested_vmcb->control.intercept);
2461
2462         /* Clear internal status */
2463         kvm_clear_exception_queue(&svm->vcpu);
2464         kvm_clear_interrupt_queue(&svm->vcpu);
2465
2466         /*
2467          * Save the old vmcb, so we don't need to pick what we save, but can
2468          * restore everything when a VMEXIT occurs
2469          */
2470         hsave->save.es     = vmcb->save.es;
2471         hsave->save.cs     = vmcb->save.cs;
2472         hsave->save.ss     = vmcb->save.ss;
2473         hsave->save.ds     = vmcb->save.ds;
2474         hsave->save.gdtr   = vmcb->save.gdtr;
2475         hsave->save.idtr   = vmcb->save.idtr;
2476         hsave->save.efer   = svm->vcpu.arch.efer;
2477         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2478         hsave->save.cr4    = svm->vcpu.arch.cr4;
2479         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2480         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2481         hsave->save.rsp    = vmcb->save.rsp;
2482         hsave->save.rax    = vmcb->save.rax;
2483         if (npt_enabled)
2484                 hsave->save.cr3    = vmcb->save.cr3;
2485         else
2486                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2487
2488         copy_vmcb_control_area(hsave, vmcb);
2489
2490         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2491                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2492         else
2493                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2494
2495         if (nested_vmcb->control.nested_ctl) {
2496                 kvm_mmu_unload(&svm->vcpu);
2497                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2498                 nested_svm_init_mmu_context(&svm->vcpu);
2499         }
2500
2501         /* Load the nested guest state */
2502         svm->vmcb->save.es = nested_vmcb->save.es;
2503         svm->vmcb->save.cs = nested_vmcb->save.cs;
2504         svm->vmcb->save.ss = nested_vmcb->save.ss;
2505         svm->vmcb->save.ds = nested_vmcb->save.ds;
2506         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2507         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2508         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2509         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2510         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2511         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2512         if (npt_enabled) {
2513                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2514                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2515         } else
2516                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2517
2518         /* Guest paging mode is active - reset mmu */
2519         kvm_mmu_reset_context(&svm->vcpu);
2520
2521         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2522         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2523         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2524         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2525
2526         /* In case we don't even reach vcpu_run, the fields are not updated */
2527         svm->vmcb->save.rax = nested_vmcb->save.rax;
2528         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2529         svm->vmcb->save.rip = nested_vmcb->save.rip;
2530         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2531         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2532         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2533
2534         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2535         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2536
2537         /* cache intercepts */
2538         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2539         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2540         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2541         svm->nested.intercept            = nested_vmcb->control.intercept;
2542
2543         svm_flush_tlb(&svm->vcpu);
2544         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2545         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2546                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2547         else
2548                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2549
2550         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2551                 /* We only want the cr8 intercept bits of the guest */
2552                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2553                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2554         }
2555
2556         /* We don't want to see VMMCALLs from a nested guest */
2557         clr_intercept(svm, INTERCEPT_VMMCALL);
2558
2559         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2560         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2561         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2562         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2563         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2564         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2565
2566         nested_svm_unmap(page);
2567
2568         /* Enter Guest-Mode */
2569         enter_guest_mode(&svm->vcpu);
2570
2571         /*
2572          * Merge guest and host intercepts - must be called  with vcpu in
2573          * guest-mode to take affect here
2574          */
2575         recalc_intercepts(svm);
2576
2577         svm->nested.vmcb = vmcb_gpa;
2578
2579         enable_gif(svm);
2580
2581         mark_all_dirty(svm->vmcb);
2582
2583         return true;
2584 }
2585
2586 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2587 {
2588         to_vmcb->save.fs = from_vmcb->save.fs;
2589         to_vmcb->save.gs = from_vmcb->save.gs;
2590         to_vmcb->save.tr = from_vmcb->save.tr;
2591         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2592         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2593         to_vmcb->save.star = from_vmcb->save.star;
2594         to_vmcb->save.lstar = from_vmcb->save.lstar;
2595         to_vmcb->save.cstar = from_vmcb->save.cstar;
2596         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2597         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2598         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2599         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2600 }
2601
2602 static int vmload_interception(struct vcpu_svm *svm)
2603 {
2604         struct vmcb *nested_vmcb;
2605         struct page *page;
2606
2607         if (nested_svm_check_permissions(svm))
2608                 return 1;
2609
2610         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2611         if (!nested_vmcb)
2612                 return 1;
2613
2614         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2615         skip_emulated_instruction(&svm->vcpu);
2616
2617         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2618         nested_svm_unmap(page);
2619
2620         return 1;
2621 }
2622
2623 static int vmsave_interception(struct vcpu_svm *svm)
2624 {
2625         struct vmcb *nested_vmcb;
2626         struct page *page;
2627
2628         if (nested_svm_check_permissions(svm))
2629                 return 1;
2630
2631         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2632         if (!nested_vmcb)
2633                 return 1;
2634
2635         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2636         skip_emulated_instruction(&svm->vcpu);
2637
2638         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2639         nested_svm_unmap(page);
2640
2641         return 1;
2642 }
2643
2644 static int vmrun_interception(struct vcpu_svm *svm)
2645 {
2646         if (nested_svm_check_permissions(svm))
2647                 return 1;
2648
2649         /* Save rip after vmrun instruction */
2650         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2651
2652         if (!nested_svm_vmrun(svm))
2653                 return 1;
2654
2655         if (!nested_svm_vmrun_msrpm(svm))
2656                 goto failed;
2657
2658         return 1;
2659
2660 failed:
2661
2662         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2663         svm->vmcb->control.exit_code_hi = 0;
2664         svm->vmcb->control.exit_info_1  = 0;
2665         svm->vmcb->control.exit_info_2  = 0;
2666
2667         nested_svm_vmexit(svm);
2668
2669         return 1;
2670 }
2671
2672 static int stgi_interception(struct vcpu_svm *svm)
2673 {
2674         if (nested_svm_check_permissions(svm))
2675                 return 1;
2676
2677         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2678         skip_emulated_instruction(&svm->vcpu);
2679         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2680
2681         enable_gif(svm);
2682
2683         return 1;
2684 }
2685
2686 static int clgi_interception(struct vcpu_svm *svm)
2687 {
2688         if (nested_svm_check_permissions(svm))
2689                 return 1;
2690
2691         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2692         skip_emulated_instruction(&svm->vcpu);
2693
2694         disable_gif(svm);
2695
2696         /* After a CLGI no interrupts should come */
2697         svm_clear_vintr(svm);
2698         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2699
2700         mark_dirty(svm->vmcb, VMCB_INTR);
2701
2702         return 1;
2703 }
2704
2705 static int invlpga_interception(struct vcpu_svm *svm)
2706 {
2707         struct kvm_vcpu *vcpu = &svm->vcpu;
2708
2709         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2710                           vcpu->arch.regs[VCPU_REGS_RAX]);
2711
2712         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2713         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2714
2715         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2716         skip_emulated_instruction(&svm->vcpu);
2717         return 1;
2718 }
2719
2720 static int skinit_interception(struct vcpu_svm *svm)
2721 {
2722         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2723
2724         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2725         return 1;
2726 }
2727
2728 static int xsetbv_interception(struct vcpu_svm *svm)
2729 {
2730         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2731         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2732
2733         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2734                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2735                 skip_emulated_instruction(&svm->vcpu);
2736         }
2737
2738         return 1;
2739 }
2740
2741 static int invalid_op_interception(struct vcpu_svm *svm)
2742 {
2743         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2744         return 1;
2745 }
2746
2747 static int task_switch_interception(struct vcpu_svm *svm)
2748 {
2749         u16 tss_selector;
2750         int reason;
2751         int int_type = svm->vmcb->control.exit_int_info &
2752                 SVM_EXITINTINFO_TYPE_MASK;
2753         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2754         uint32_t type =
2755                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2756         uint32_t idt_v =
2757                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2758         bool has_error_code = false;
2759         u32 error_code = 0;
2760
2761         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2762
2763         if (svm->vmcb->control.exit_info_2 &
2764             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2765                 reason = TASK_SWITCH_IRET;
2766         else if (svm->vmcb->control.exit_info_2 &
2767                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2768                 reason = TASK_SWITCH_JMP;
2769         else if (idt_v)
2770                 reason = TASK_SWITCH_GATE;
2771         else
2772                 reason = TASK_SWITCH_CALL;
2773
2774         if (reason == TASK_SWITCH_GATE) {
2775                 switch (type) {
2776                 case SVM_EXITINTINFO_TYPE_NMI:
2777                         svm->vcpu.arch.nmi_injected = false;
2778                         break;
2779                 case SVM_EXITINTINFO_TYPE_EXEPT:
2780                         if (svm->vmcb->control.exit_info_2 &
2781                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2782                                 has_error_code = true;
2783                                 error_code =
2784                                         (u32)svm->vmcb->control.exit_info_2;
2785                         }
2786                         kvm_clear_exception_queue(&svm->vcpu);
2787                         break;
2788                 case SVM_EXITINTINFO_TYPE_INTR:
2789                         kvm_clear_interrupt_queue(&svm->vcpu);
2790                         break;
2791                 default:
2792                         break;
2793                 }
2794         }
2795
2796         if (reason != TASK_SWITCH_GATE ||
2797             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2798             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2799              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2800                 skip_emulated_instruction(&svm->vcpu);
2801
2802         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2803                 int_vec = -1;
2804
2805         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2806                                 has_error_code, error_code) == EMULATE_FAIL) {
2807                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2808                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2809                 svm->vcpu.run->internal.ndata = 0;
2810                 return 0;
2811         }
2812         return 1;
2813 }
2814
2815 static int cpuid_interception(struct vcpu_svm *svm)
2816 {
2817         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2818         kvm_emulate_cpuid(&svm->vcpu);
2819         return 1;
2820 }
2821
2822 static int iret_interception(struct vcpu_svm *svm)
2823 {
2824         ++svm->vcpu.stat.nmi_window_exits;
2825         clr_intercept(svm, INTERCEPT_IRET);
2826         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2827         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2828         return 1;
2829 }
2830
2831 static int invlpg_interception(struct vcpu_svm *svm)
2832 {
2833         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2834                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2835
2836         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2837         skip_emulated_instruction(&svm->vcpu);
2838         return 1;
2839 }
2840
2841 static int emulate_on_interception(struct vcpu_svm *svm)
2842 {
2843         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2844 }
2845
2846 static int rdpmc_interception(struct vcpu_svm *svm)
2847 {
2848         int err;
2849
2850         if (!static_cpu_has(X86_FEATURE_NRIPS))
2851                 return emulate_on_interception(svm);
2852
2853         err = kvm_rdpmc(&svm->vcpu);
2854         kvm_complete_insn_gp(&svm->vcpu, err);
2855
2856         return 1;
2857 }
2858
2859 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2860 {
2861         unsigned long cr0 = svm->vcpu.arch.cr0;
2862         bool ret = false;
2863         u64 intercept;
2864
2865         intercept = svm->nested.intercept;
2866
2867         if (!is_guest_mode(&svm->vcpu) ||
2868             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2869                 return false;
2870
2871         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2872         val &= ~SVM_CR0_SELECTIVE_MASK;
2873
2874         if (cr0 ^ val) {
2875                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2876                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2877         }
2878
2879         return ret;
2880 }
2881
2882 #define CR_VALID (1ULL << 63)
2883
2884 static int cr_interception(struct vcpu_svm *svm)
2885 {
2886         int reg, cr;
2887         unsigned long val;
2888         int err;
2889
2890         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2891                 return emulate_on_interception(svm);
2892
2893         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2894                 return emulate_on_interception(svm);
2895
2896         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2897         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2898
2899         err = 0;
2900         if (cr >= 16) { /* mov to cr */
2901                 cr -= 16;
2902                 val = kvm_register_read(&svm->vcpu, reg);
2903                 switch (cr) {
2904                 case 0:
2905                         if (!check_selective_cr0_intercepted(svm, val))
2906                                 err = kvm_set_cr0(&svm->vcpu, val);
2907                         else
2908                                 return 1;
2909
2910                         break;
2911                 case 3:
2912                         err = kvm_set_cr3(&svm->vcpu, val);
2913                         break;
2914                 case 4:
2915                         err = kvm_set_cr4(&svm->vcpu, val);
2916                         break;
2917                 case 8:
2918                         err = kvm_set_cr8(&svm->vcpu, val);
2919                         break;
2920                 default:
2921                         WARN(1, "unhandled write to CR%d", cr);
2922                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2923                         return 1;
2924                 }
2925         } else { /* mov from cr */
2926                 switch (cr) {
2927                 case 0:
2928                         val = kvm_read_cr0(&svm->vcpu);
2929                         break;
2930                 case 2:
2931                         val = svm->vcpu.arch.cr2;
2932                         break;
2933                 case 3:
2934                         val = kvm_read_cr3(&svm->vcpu);
2935                         break;
2936                 case 4:
2937                         val = kvm_read_cr4(&svm->vcpu);
2938                         break;
2939                 case 8:
2940                         val = kvm_get_cr8(&svm->vcpu);
2941                         break;
2942                 default:
2943                         WARN(1, "unhandled read from CR%d", cr);
2944                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2945                         return 1;
2946                 }
2947                 kvm_register_write(&svm->vcpu, reg, val);
2948         }
2949         kvm_complete_insn_gp(&svm->vcpu, err);
2950
2951         return 1;
2952 }
2953
2954 static int dr_interception(struct vcpu_svm *svm)
2955 {
2956         int reg, dr;
2957         unsigned long val;
2958         int err;
2959
2960         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2961                 return emulate_on_interception(svm);
2962
2963         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2964         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2965
2966         if (dr >= 16) { /* mov to DRn */
2967                 val = kvm_register_read(&svm->vcpu, reg);
2968                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2969         } else {
2970                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2971                 if (!err)
2972                         kvm_register_write(&svm->vcpu, reg, val);
2973         }
2974
2975         skip_emulated_instruction(&svm->vcpu);
2976
2977         return 1;
2978 }
2979
2980 static int cr8_write_interception(struct vcpu_svm *svm)
2981 {
2982         struct kvm_run *kvm_run = svm->vcpu.run;
2983         int r;
2984
2985         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2986         /* instruction emulation calls kvm_set_cr8() */
2987         r = cr_interception(svm);
2988         if (irqchip_in_kernel(svm->vcpu.kvm))
2989                 return r;
2990         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2991                 return r;
2992         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2993         return 0;
2994 }
2995
2996 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2997 {
2998         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2999         return vmcb->control.tsc_offset +
3000                 svm_scale_tsc(vcpu, host_tsc);
3001 }
3002
3003 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3004 {
3005         struct vcpu_svm *svm = to_svm(vcpu);
3006
3007         switch (ecx) {
3008         case MSR_IA32_TSC: {
3009                 *data = svm->vmcb->control.tsc_offset +
3010                         svm_scale_tsc(vcpu, native_read_tsc());
3011
3012                 break;
3013         }
3014         case MSR_STAR:
3015                 *data = svm->vmcb->save.star;
3016                 break;
3017 #ifdef CONFIG_X86_64
3018         case MSR_LSTAR:
3019                 *data = svm->vmcb->save.lstar;
3020                 break;
3021         case MSR_CSTAR:
3022                 *data = svm->vmcb->save.cstar;
3023                 break;
3024         case MSR_KERNEL_GS_BASE:
3025                 *data = svm->vmcb->save.kernel_gs_base;
3026                 break;
3027         case MSR_SYSCALL_MASK:
3028                 *data = svm->vmcb->save.sfmask;
3029                 break;
3030 #endif
3031         case MSR_IA32_SYSENTER_CS:
3032                 *data = svm->vmcb->save.sysenter_cs;
3033                 break;
3034         case MSR_IA32_SYSENTER_EIP:
3035                 *data = svm->sysenter_eip;
3036                 break;
3037         case MSR_IA32_SYSENTER_ESP:
3038                 *data = svm->sysenter_esp;
3039                 break;
3040         /*
3041          * Nobody will change the following 5 values in the VMCB so we can
3042          * safely return them on rdmsr. They will always be 0 until LBRV is
3043          * implemented.
3044          */
3045         case MSR_IA32_DEBUGCTLMSR:
3046                 *data = svm->vmcb->save.dbgctl;
3047                 break;
3048         case MSR_IA32_LASTBRANCHFROMIP:
3049                 *data = svm->vmcb->save.br_from;
3050                 break;
3051         case MSR_IA32_LASTBRANCHTOIP:
3052                 *data = svm->vmcb->save.br_to;
3053                 break;
3054         case MSR_IA32_LASTINTFROMIP:
3055                 *data = svm->vmcb->save.last_excp_from;
3056                 break;
3057         case MSR_IA32_LASTINTTOIP:
3058                 *data = svm->vmcb->save.last_excp_to;
3059                 break;
3060         case MSR_VM_HSAVE_PA:
3061                 *data = svm->nested.hsave_msr;
3062                 break;
3063         case MSR_VM_CR:
3064                 *data = svm->nested.vm_cr_msr;
3065                 break;
3066         case MSR_IA32_UCODE_REV:
3067                 *data = 0x01000065;
3068                 break;
3069         default:
3070                 return kvm_get_msr_common(vcpu, ecx, data);
3071         }
3072         return 0;
3073 }
3074
3075 static int rdmsr_interception(struct vcpu_svm *svm)
3076 {
3077         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3078         u64 data;
3079
3080         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3081                 trace_kvm_msr_read_ex(ecx);
3082                 kvm_inject_gp(&svm->vcpu, 0);
3083         } else {
3084                 trace_kvm_msr_read(ecx, data);
3085
3086                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3087                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3088                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3089                 skip_emulated_instruction(&svm->vcpu);
3090         }
3091         return 1;
3092 }
3093
3094 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3095 {
3096         struct vcpu_svm *svm = to_svm(vcpu);
3097         int svm_dis, chg_mask;
3098
3099         if (data & ~SVM_VM_CR_VALID_MASK)
3100                 return 1;
3101
3102         chg_mask = SVM_VM_CR_VALID_MASK;
3103
3104         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3105                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3106
3107         svm->nested.vm_cr_msr &= ~chg_mask;
3108         svm->nested.vm_cr_msr |= (data & chg_mask);
3109
3110         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3111
3112         /* check for svm_disable while efer.svme is set */
3113         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3114                 return 1;
3115
3116         return 0;
3117 }
3118
3119 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3120 {
3121         struct vcpu_svm *svm = to_svm(vcpu);
3122
3123         u32 ecx = msr->index;
3124         u64 data = msr->data;
3125         switch (ecx) {
3126         case MSR_IA32_TSC:
3127                 kvm_write_tsc(vcpu, msr);
3128                 break;
3129         case MSR_STAR:
3130                 svm->vmcb->save.star = data;
3131                 break;
3132 #ifdef CONFIG_X86_64
3133         case MSR_LSTAR:
3134                 svm->vmcb->save.lstar = data;
3135                 break;
3136         case MSR_CSTAR:
3137                 svm->vmcb->save.cstar = data;
3138                 break;
3139         case MSR_KERNEL_GS_BASE:
3140                 svm->vmcb->save.kernel_gs_base = data;
3141                 break;
3142         case MSR_SYSCALL_MASK:
3143                 svm->vmcb->save.sfmask = data;
3144                 break;
3145 #endif
3146         case MSR_IA32_SYSENTER_CS:
3147                 svm->vmcb->save.sysenter_cs = data;
3148                 break;
3149         case MSR_IA32_SYSENTER_EIP:
3150                 svm->sysenter_eip = data;
3151                 svm->vmcb->save.sysenter_eip = data;
3152                 break;
3153         case MSR_IA32_SYSENTER_ESP:
3154                 svm->sysenter_esp = data;
3155                 svm->vmcb->save.sysenter_esp = data;
3156                 break;
3157         case MSR_IA32_DEBUGCTLMSR:
3158                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3159                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3160                                     __func__, data);
3161                         break;
3162                 }
3163                 if (data & DEBUGCTL_RESERVED_BITS)
3164                         return 1;
3165
3166                 svm->vmcb->save.dbgctl = data;
3167                 mark_dirty(svm->vmcb, VMCB_LBR);
3168                 if (data & (1ULL<<0))
3169                         svm_enable_lbrv(svm);
3170                 else
3171                         svm_disable_lbrv(svm);
3172                 break;
3173         case MSR_VM_HSAVE_PA:
3174                 svm->nested.hsave_msr = data;
3175                 break;
3176         case MSR_VM_CR:
3177                 return svm_set_vm_cr(vcpu, data);
3178         case MSR_VM_IGNNE:
3179                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3180                 break;
3181         default:
3182                 return kvm_set_msr_common(vcpu, msr);
3183         }
3184         return 0;
3185 }
3186
3187 static int wrmsr_interception(struct vcpu_svm *svm)
3188 {
3189         struct msr_data msr;
3190         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3191         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3192                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3193
3194         msr.data = data;
3195         msr.index = ecx;
3196         msr.host_initiated = false;
3197
3198         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3199         if (svm_set_msr(&svm->vcpu, &msr)) {
3200                 trace_kvm_msr_write_ex(ecx, data);
3201                 kvm_inject_gp(&svm->vcpu, 0);
3202         } else {
3203                 trace_kvm_msr_write(ecx, data);
3204                 skip_emulated_instruction(&svm->vcpu);
3205         }
3206         return 1;
3207 }
3208
3209 static int msr_interception(struct vcpu_svm *svm)
3210 {
3211         if (svm->vmcb->control.exit_info_1)
3212                 return wrmsr_interception(svm);
3213         else
3214                 return rdmsr_interception(svm);
3215 }
3216
3217 static int interrupt_window_interception(struct vcpu_svm *svm)
3218 {
3219         struct kvm_run *kvm_run = svm->vcpu.run;
3220
3221         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3222         svm_clear_vintr(svm);
3223         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3224         mark_dirty(svm->vmcb, VMCB_INTR);
3225         ++svm->vcpu.stat.irq_window_exits;
3226         /*
3227          * If the user space waits to inject interrupts, exit as soon as
3228          * possible
3229          */
3230         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3231             kvm_run->request_interrupt_window &&
3232             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3233                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3234                 return 0;
3235         }
3236
3237         return 1;
3238 }
3239
3240 static int pause_interception(struct vcpu_svm *svm)
3241 {
3242         kvm_vcpu_on_spin(&(svm->vcpu));
3243         return 1;
3244 }
3245
3246 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3247         [SVM_EXIT_READ_CR0]                     = cr_interception,
3248         [SVM_EXIT_READ_CR3]                     = cr_interception,
3249         [SVM_EXIT_READ_CR4]                     = cr_interception,
3250         [SVM_EXIT_READ_CR8]                     = cr_interception,
3251         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3252         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3253         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3254         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3255         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3256         [SVM_EXIT_READ_DR0]                     = dr_interception,
3257         [SVM_EXIT_READ_DR1]                     = dr_interception,
3258         [SVM_EXIT_READ_DR2]                     = dr_interception,
3259         [SVM_EXIT_READ_DR3]                     = dr_interception,
3260         [SVM_EXIT_READ_DR4]                     = dr_interception,
3261         [SVM_EXIT_READ_DR5]                     = dr_interception,
3262         [SVM_EXIT_READ_DR6]                     = dr_interception,
3263         [SVM_EXIT_READ_DR7]                     = dr_interception,
3264         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3265         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3266         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3267         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3268         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3269         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3270         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3271         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3272         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3273         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3274         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3275         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3276         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3277         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3278         [SVM_EXIT_INTR]                         = intr_interception,
3279         [SVM_EXIT_NMI]                          = nmi_interception,
3280         [SVM_EXIT_SMI]                          = nop_on_interception,
3281         [SVM_EXIT_INIT]                         = nop_on_interception,
3282         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3283         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3284         [SVM_EXIT_CPUID]                        = cpuid_interception,
3285         [SVM_EXIT_IRET]                         = iret_interception,
3286         [SVM_EXIT_INVD]                         = emulate_on_interception,
3287         [SVM_EXIT_PAUSE]                        = pause_interception,
3288         [SVM_EXIT_HLT]                          = halt_interception,
3289         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3290         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3291         [SVM_EXIT_IOIO]                         = io_interception,
3292         [SVM_EXIT_MSR]                          = msr_interception,
3293         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3294         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3295         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3296         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3297         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3298         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3299         [SVM_EXIT_STGI]                         = stgi_interception,
3300         [SVM_EXIT_CLGI]                         = clgi_interception,
3301         [SVM_EXIT_SKINIT]                       = skinit_interception,
3302         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3303         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3304         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3305         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3306         [SVM_EXIT_NPF]                          = pf_interception,
3307 };
3308
3309 static void dump_vmcb(struct kvm_vcpu *vcpu)
3310 {
3311         struct vcpu_svm *svm = to_svm(vcpu);
3312         struct vmcb_control_area *control = &svm->vmcb->control;
3313         struct vmcb_save_area *save = &svm->vmcb->save;
3314
3315         pr_err("VMCB Control Area:\n");
3316         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3317         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3318         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3319         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3320         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3321         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3322         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3323         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3324         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3325         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3326         pr_err("%-20s%d\n", "asid:", control->asid);
3327         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3328         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3329         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3330         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3331         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3332         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3333         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3334         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3335         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3336         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3337         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3338         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3339         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3340         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3341         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3342         pr_err("VMCB State Save Area:\n");
3343         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3344                "es:",
3345                save->es.selector, save->es.attrib,
3346                save->es.limit, save->es.base);
3347         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3348                "cs:",
3349                save->cs.selector, save->cs.attrib,
3350                save->cs.limit, save->cs.base);
3351         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3352                "ss:",
3353                save->ss.selector, save->ss.attrib,
3354                save->ss.limit, save->ss.base);
3355         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3356                "ds:",
3357                save->ds.selector, save->ds.attrib,
3358                save->ds.limit, save->ds.base);
3359         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3360                "fs:",
3361                save->fs.selector, save->fs.attrib,
3362                save->fs.limit, save->fs.base);
3363         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3364                "gs:",
3365                save->gs.selector, save->gs.attrib,
3366                save->gs.limit, save->gs.base);
3367         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3368                "gdtr:",
3369                save->gdtr.selector, save->gdtr.attrib,
3370                save->gdtr.limit, save->gdtr.base);
3371         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3372                "ldtr:",
3373                save->ldtr.selector, save->ldtr.attrib,
3374                save->ldtr.limit, save->ldtr.base);
3375         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3376                "idtr:",
3377                save->idtr.selector, save->idtr.attrib,
3378                save->idtr.limit, save->idtr.base);
3379         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3380                "tr:",
3381                save->tr.selector, save->tr.attrib,
3382                save->tr.limit, save->tr.base);
3383         pr_err("cpl:            %d                efer:         %016llx\n",
3384                 save->cpl, save->efer);
3385         pr_err("%-15s %016llx %-13s %016llx\n",
3386                "cr0:", save->cr0, "cr2:", save->cr2);
3387         pr_err("%-15s %016llx %-13s %016llx\n",
3388                "cr3:", save->cr3, "cr4:", save->cr4);
3389         pr_err("%-15s %016llx %-13s %016llx\n",
3390                "dr6:", save->dr6, "dr7:", save->dr7);
3391         pr_err("%-15s %016llx %-13s %016llx\n",
3392                "rip:", save->rip, "rflags:", save->rflags);
3393         pr_err("%-15s %016llx %-13s %016llx\n",
3394                "rsp:", save->rsp, "rax:", save->rax);
3395         pr_err("%-15s %016llx %-13s %016llx\n",
3396                "star:", save->star, "lstar:", save->lstar);
3397         pr_err("%-15s %016llx %-13s %016llx\n",
3398                "cstar:", save->cstar, "sfmask:", save->sfmask);
3399         pr_err("%-15s %016llx %-13s %016llx\n",
3400                "kernel_gs_base:", save->kernel_gs_base,
3401                "sysenter_cs:", save->sysenter_cs);
3402         pr_err("%-15s %016llx %-13s %016llx\n",
3403                "sysenter_esp:", save->sysenter_esp,
3404                "sysenter_eip:", save->sysenter_eip);
3405         pr_err("%-15s %016llx %-13s %016llx\n",
3406                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3407         pr_err("%-15s %016llx %-13s %016llx\n",
3408                "br_from:", save->br_from, "br_to:", save->br_to);
3409         pr_err("%-15s %016llx %-13s %016llx\n",
3410                "excp_from:", save->last_excp_from,
3411                "excp_to:", save->last_excp_to);
3412 }
3413
3414 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3415 {
3416         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3417
3418         *info1 = control->exit_info_1;
3419         *info2 = control->exit_info_2;
3420 }
3421
3422 static int handle_exit(struct kvm_vcpu *vcpu)
3423 {
3424         struct vcpu_svm *svm = to_svm(vcpu);
3425         struct kvm_run *kvm_run = vcpu->run;
3426         u32 exit_code = svm->vmcb->control.exit_code;
3427
3428         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3429                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3430         if (npt_enabled)
3431                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3432
3433         if (unlikely(svm->nested.exit_required)) {
3434                 nested_svm_vmexit(svm);
3435                 svm->nested.exit_required = false;
3436
3437                 return 1;
3438         }
3439
3440         if (is_guest_mode(vcpu)) {
3441                 int vmexit;
3442
3443                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3444                                         svm->vmcb->control.exit_info_1,
3445                                         svm->vmcb->control.exit_info_2,
3446                                         svm->vmcb->control.exit_int_info,
3447                                         svm->vmcb->control.exit_int_info_err,
3448                                         KVM_ISA_SVM);
3449
3450                 vmexit = nested_svm_exit_special(svm);
3451
3452                 if (vmexit == NESTED_EXIT_CONTINUE)
3453                         vmexit = nested_svm_exit_handled(svm);
3454
3455                 if (vmexit == NESTED_EXIT_DONE)
3456                         return 1;
3457         }
3458
3459         svm_complete_interrupts(svm);
3460
3461         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3462                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3463                 kvm_run->fail_entry.hardware_entry_failure_reason
3464                         = svm->vmcb->control.exit_code;
3465                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3466                 dump_vmcb(vcpu);
3467                 return 0;
3468         }
3469
3470         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3471             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3472             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3473             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3474                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3475                        "exit_code 0x%x\n",
3476                        __func__, svm->vmcb->control.exit_int_info,
3477                        exit_code);
3478
3479         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3480             || !svm_exit_handlers[exit_code]) {
3481                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3482                 kvm_run->hw.hardware_exit_reason = exit_code;
3483                 return 0;
3484         }
3485
3486         return svm_exit_handlers[exit_code](svm);
3487 }
3488
3489 static void reload_tss(struct kvm_vcpu *vcpu)
3490 {
3491         int cpu = raw_smp_processor_id();
3492
3493         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3494         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3495         load_TR_desc();
3496 }
3497
3498 static void pre_svm_run(struct vcpu_svm *svm)
3499 {
3500         int cpu = raw_smp_processor_id();
3501
3502         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3503
3504         /* FIXME: handle wraparound of asid_generation */
3505         if (svm->asid_generation != sd->asid_generation)
3506                 new_asid(svm, sd);
3507 }
3508
3509 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3510 {
3511         struct vcpu_svm *svm = to_svm(vcpu);
3512
3513         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3514         vcpu->arch.hflags |= HF_NMI_MASK;
3515         set_intercept(svm, INTERCEPT_IRET);
3516         ++vcpu->stat.nmi_injections;
3517 }
3518
3519 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3520 {
3521         struct vmcb_control_area *control;
3522
3523         control = &svm->vmcb->control;
3524         control->int_vector = irq;
3525         control->int_ctl &= ~V_INTR_PRIO_MASK;
3526         control->int_ctl |= V_IRQ_MASK |
3527                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3528         mark_dirty(svm->vmcb, VMCB_INTR);
3529 }
3530
3531 static void svm_set_irq(struct kvm_vcpu *vcpu)
3532 {
3533         struct vcpu_svm *svm = to_svm(vcpu);
3534
3535         BUG_ON(!(gif_set(svm)));
3536
3537         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3538         ++vcpu->stat.irq_injections;
3539
3540         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3541                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3542 }
3543
3544 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3545 {
3546         struct vcpu_svm *svm = to_svm(vcpu);
3547
3548         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3549                 return;
3550
3551         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3552
3553         if (irr == -1)
3554                 return;
3555
3556         if (tpr >= irr)
3557                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3558 }
3559
3560 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3561 {
3562         return;
3563 }
3564
3565 static int svm_vm_has_apicv(struct kvm *kvm)
3566 {
3567         return 0;
3568 }
3569
3570 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3571 {
3572         return;
3573 }
3574
3575 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3576 {
3577         return;
3578 }
3579
3580 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3581 {
3582         return;
3583 }
3584
3585 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3586 {
3587         struct vcpu_svm *svm = to_svm(vcpu);
3588         struct vmcb *vmcb = svm->vmcb;
3589         int ret;
3590         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3591               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3592         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3593
3594         return ret;
3595 }
3596
3597 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3598 {
3599         struct vcpu_svm *svm = to_svm(vcpu);
3600
3601         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3602 }
3603
3604 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3605 {
3606         struct vcpu_svm *svm = to_svm(vcpu);
3607
3608         if (masked) {
3609                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3610                 set_intercept(svm, INTERCEPT_IRET);
3611         } else {
3612                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3613                 clr_intercept(svm, INTERCEPT_IRET);
3614         }
3615 }
3616
3617 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3618 {
3619         struct vcpu_svm *svm = to_svm(vcpu);
3620         struct vmcb *vmcb = svm->vmcb;
3621         int ret;
3622
3623         if (!gif_set(svm) ||
3624              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3625                 return 0;
3626
3627         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3628
3629         if (is_guest_mode(vcpu))
3630                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3631
3632         return ret;
3633 }
3634
3635 static int enable_irq_window(struct kvm_vcpu *vcpu)
3636 {
3637         struct vcpu_svm *svm = to_svm(vcpu);
3638
3639         /*
3640          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3641          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3642          * get that intercept, this function will be called again though and
3643          * we'll get the vintr intercept.
3644          */
3645         if (gif_set(svm) && nested_svm_intr(svm)) {
3646                 svm_set_vintr(svm);
3647                 svm_inject_irq(svm, 0x0);
3648         }
3649         return 0;
3650 }
3651
3652 static int enable_nmi_window(struct kvm_vcpu *vcpu)
3653 {
3654         struct vcpu_svm *svm = to_svm(vcpu);
3655
3656         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3657             == HF_NMI_MASK)
3658                 return 0; /* IRET will cause a vm exit */
3659
3660         /*
3661          * Something prevents NMI from been injected. Single step over possible
3662          * problem (IRET or exception injection or interrupt shadow)
3663          */
3664         svm->nmi_singlestep = true;
3665         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3666         update_db_bp_intercept(vcpu);
3667         return 0;
3668 }
3669
3670 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3671 {
3672         return 0;
3673 }
3674
3675 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3676 {
3677         struct vcpu_svm *svm = to_svm(vcpu);
3678
3679         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3680                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3681         else
3682                 svm->asid_generation--;
3683 }
3684
3685 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3686 {
3687 }
3688
3689 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3690 {
3691         struct vcpu_svm *svm = to_svm(vcpu);
3692
3693         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3694                 return;
3695
3696         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3697                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3698                 kvm_set_cr8(vcpu, cr8);
3699         }
3700 }
3701
3702 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3703 {
3704         struct vcpu_svm *svm = to_svm(vcpu);
3705         u64 cr8;
3706
3707         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3708                 return;
3709
3710         cr8 = kvm_get_cr8(vcpu);
3711         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3712         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3713 }
3714
3715 static void svm_complete_interrupts(struct vcpu_svm *svm)
3716 {
3717         u8 vector;
3718         int type;
3719         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3720         unsigned int3_injected = svm->int3_injected;
3721
3722         svm->int3_injected = 0;
3723
3724         /*
3725          * If we've made progress since setting HF_IRET_MASK, we've
3726          * executed an IRET and can allow NMI injection.
3727          */
3728         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3729             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3730                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3731                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3732         }
3733
3734         svm->vcpu.arch.nmi_injected = false;
3735         kvm_clear_exception_queue(&svm->vcpu);
3736         kvm_clear_interrupt_queue(&svm->vcpu);
3737
3738         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3739                 return;
3740
3741         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3742
3743         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3744         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3745
3746         switch (type) {
3747         case SVM_EXITINTINFO_TYPE_NMI:
3748                 svm->vcpu.arch.nmi_injected = true;
3749                 break;
3750         case SVM_EXITINTINFO_TYPE_EXEPT:
3751                 /*
3752                  * In case of software exceptions, do not reinject the vector,
3753                  * but re-execute the instruction instead. Rewind RIP first
3754                  * if we emulated INT3 before.
3755                  */
3756                 if (kvm_exception_is_soft(vector)) {
3757                         if (vector == BP_VECTOR && int3_injected &&
3758                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3759                                 kvm_rip_write(&svm->vcpu,
3760                                               kvm_rip_read(&svm->vcpu) -
3761                                               int3_injected);
3762                         break;
3763                 }
3764                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3765                         u32 err = svm->vmcb->control.exit_int_info_err;
3766                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3767
3768                 } else
3769                         kvm_requeue_exception(&svm->vcpu, vector);
3770                 break;
3771         case SVM_EXITINTINFO_TYPE_INTR:
3772                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3773                 break;
3774         default:
3775                 break;
3776         }
3777 }
3778
3779 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3780 {
3781         struct vcpu_svm *svm = to_svm(vcpu);
3782         struct vmcb_control_area *control = &svm->vmcb->control;
3783
3784         control->exit_int_info = control->event_inj;
3785         control->exit_int_info_err = control->event_inj_err;
3786         control->event_inj = 0;
3787         svm_complete_interrupts(svm);
3788 }
3789
3790 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3791 {
3792         struct vcpu_svm *svm = to_svm(vcpu);
3793
3794         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3795         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3796         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3797
3798         /*
3799          * A vmexit emulation is required before the vcpu can be executed
3800          * again.
3801          */
3802         if (unlikely(svm->nested.exit_required))
3803                 return;
3804
3805         pre_svm_run(svm);
3806
3807         sync_lapic_to_cr8(vcpu);
3808
3809         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3810
3811         clgi();
3812
3813         local_irq_enable();
3814
3815         asm volatile (
3816                 "push %%" _ASM_BP "; \n\t"
3817                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3818                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3819                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3820                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3821                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3822                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3823 #ifdef CONFIG_X86_64
3824                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3825                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3826                 "mov %c[r10](%[svm]), %%r10 \n\t"
3827                 "mov %c[r11](%[svm]), %%r11 \n\t"
3828                 "mov %c[r12](%[svm]), %%r12 \n\t"
3829                 "mov %c[r13](%[svm]), %%r13 \n\t"
3830                 "mov %c[r14](%[svm]), %%r14 \n\t"
3831                 "mov %c[r15](%[svm]), %%r15 \n\t"
3832 #endif
3833
3834                 /* Enter guest mode */
3835                 "push %%" _ASM_AX " \n\t"
3836                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3837                 __ex(SVM_VMLOAD) "\n\t"
3838                 __ex(SVM_VMRUN) "\n\t"
3839                 __ex(SVM_VMSAVE) "\n\t"
3840                 "pop %%" _ASM_AX " \n\t"
3841
3842                 /* Save guest registers, load host registers */
3843                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3844                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3845                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3846                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3847                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3848                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3849 #ifdef CONFIG_X86_64
3850                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3851                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3852                 "mov %%r10, %c[r10](%[svm]) \n\t"
3853                 "mov %%r11, %c[r11](%[svm]) \n\t"
3854                 "mov %%r12, %c[r12](%[svm]) \n\t"
3855                 "mov %%r13, %c[r13](%[svm]) \n\t"
3856                 "mov %%r14, %c[r14](%[svm]) \n\t"
3857                 "mov %%r15, %c[r15](%[svm]) \n\t"
3858 #endif
3859                 "pop %%" _ASM_BP
3860                 :
3861                 : [svm]"a"(svm),
3862                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3863                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3864                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3865                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3866                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3867                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3868                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3869 #ifdef CONFIG_X86_64
3870                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3871                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3872                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3873                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3874                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3875                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3876                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3877                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3878 #endif
3879                 : "cc", "memory"
3880 #ifdef CONFIG_X86_64
3881                 , "rbx", "rcx", "rdx", "rsi", "rdi"
3882                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3883 #else
3884                 , "ebx", "ecx", "edx", "esi", "edi"
3885 #endif
3886                 );
3887
3888 #ifdef CONFIG_X86_64
3889         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3890 #else
3891         loadsegment(fs, svm->host.fs);
3892 #ifndef CONFIG_X86_32_LAZY_GS
3893         loadsegment(gs, svm->host.gs);
3894 #endif
3895 #endif
3896
3897         reload_tss(vcpu);
3898
3899         local_irq_disable();
3900
3901         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3902         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3903         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3904         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3905
3906         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3907
3908         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3909                 kvm_before_handle_nmi(&svm->vcpu);
3910
3911         stgi();
3912
3913         /* Any pending NMI will happen here */
3914
3915         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3916                 kvm_after_handle_nmi(&svm->vcpu);
3917
3918         sync_cr8_to_lapic(vcpu);
3919
3920         svm->next_rip = 0;
3921
3922         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3923
3924         /* if exit due to PF check for async PF */
3925         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3926                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3927
3928         if (npt_enabled) {
3929                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3930                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3931         }
3932
3933         /*
3934          * We need to handle MC intercepts here before the vcpu has a chance to
3935          * change the physical cpu
3936          */
3937         if (unlikely(svm->vmcb->control.exit_code ==
3938                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3939                 svm_handle_mce(svm);
3940
3941         mark_all_clean(svm->vmcb);
3942 }
3943
3944 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3945 {
3946         struct vcpu_svm *svm = to_svm(vcpu);
3947
3948         svm->vmcb->save.cr3 = root;
3949         mark_dirty(svm->vmcb, VMCB_CR);
3950         svm_flush_tlb(vcpu);
3951 }
3952
3953 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3954 {
3955         struct vcpu_svm *svm = to_svm(vcpu);
3956
3957         svm->vmcb->control.nested_cr3 = root;
3958         mark_dirty(svm->vmcb, VMCB_NPT);
3959
3960         /* Also sync guest cr3 here in case we live migrate */
3961         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3962         mark_dirty(svm->vmcb, VMCB_CR);
3963
3964         svm_flush_tlb(vcpu);
3965 }
3966
3967 static int is_disabled(void)
3968 {
3969         u64 vm_cr;
3970
3971         rdmsrl(MSR_VM_CR, vm_cr);
3972         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3973                 return 1;
3974
3975         return 0;
3976 }
3977
3978 static void
3979 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3980 {
3981         /*
3982          * Patch in the VMMCALL instruction:
3983          */
3984         hypercall[0] = 0x0f;
3985         hypercall[1] = 0x01;
3986         hypercall[2] = 0xd9;
3987 }
3988
3989 static void svm_check_processor_compat(void *rtn)
3990 {
3991         *(int *)rtn = 0;
3992 }
3993
3994 static bool svm_cpu_has_accelerated_tpr(void)
3995 {
3996         return false;
3997 }
3998
3999 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4000 {
4001         return 0;
4002 }
4003
4004 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4005 {
4006 }
4007
4008 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4009 {
4010         switch (func) {
4011         case 0x80000001:
4012                 if (nested)
4013                         entry->ecx |= (1 << 2); /* Set SVM bit */
4014                 break;
4015         case 0x8000000A:
4016                 entry->eax = 1; /* SVM revision 1 */
4017                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4018                                    ASID emulation to nested SVM */
4019                 entry->ecx = 0; /* Reserved */
4020                 entry->edx = 0; /* Per default do not support any
4021                                    additional features */
4022
4023                 /* Support next_rip if host supports it */
4024                 if (boot_cpu_has(X86_FEATURE_NRIPS))
4025                         entry->edx |= SVM_FEATURE_NRIP;
4026
4027                 /* Support NPT for the guest if enabled */
4028                 if (npt_enabled)
4029                         entry->edx |= SVM_FEATURE_NPT;
4030
4031                 break;
4032         }
4033 }
4034
4035 static int svm_get_lpage_level(void)
4036 {
4037         return PT_PDPE_LEVEL;
4038 }
4039
4040 static bool svm_rdtscp_supported(void)
4041 {
4042         return false;
4043 }
4044
4045 static bool svm_invpcid_supported(void)
4046 {
4047         return false;
4048 }
4049
4050 static bool svm_has_wbinvd_exit(void)
4051 {
4052         return true;
4053 }
4054
4055 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4056 {
4057         struct vcpu_svm *svm = to_svm(vcpu);
4058
4059         set_exception_intercept(svm, NM_VECTOR);
4060         update_cr0_intercept(svm);
4061 }
4062
4063 #define PRE_EX(exit)  { .exit_code = (exit), \
4064                         .stage = X86_ICPT_PRE_EXCEPT, }
4065 #define POST_EX(exit) { .exit_code = (exit), \
4066                         .stage = X86_ICPT_POST_EXCEPT, }
4067 #define POST_MEM(exit) { .exit_code = (exit), \
4068                         .stage = X86_ICPT_POST_MEMACCESS, }
4069
4070 static const struct __x86_intercept {
4071         u32 exit_code;
4072         enum x86_intercept_stage stage;
4073 } x86_intercept_map[] = {
4074         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4075         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4076         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4077         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4078         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4079         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4080         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4081         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4082         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4083         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4084         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4085         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4086         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4087         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4088         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4089         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4090         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4091         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4092         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4093         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4094         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4095         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4096         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4097         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4098         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4099         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4100         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4101         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4102         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4103         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4104         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4105         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4106         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4107         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4108         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4109         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4110         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4111         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4112         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4113         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4114         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4115         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4116         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4117         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4118         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4119         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4120 };
4121
4122 #undef PRE_EX
4123 #undef POST_EX
4124 #undef POST_MEM
4125
4126 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4127                                struct x86_instruction_info *info,
4128                                enum x86_intercept_stage stage)
4129 {
4130         struct vcpu_svm *svm = to_svm(vcpu);
4131         int vmexit, ret = X86EMUL_CONTINUE;
4132         struct __x86_intercept icpt_info;
4133         struct vmcb *vmcb = svm->vmcb;
4134
4135         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4136                 goto out;
4137
4138         icpt_info = x86_intercept_map[info->intercept];
4139
4140         if (stage != icpt_info.stage)
4141                 goto out;
4142
4143         switch (icpt_info.exit_code) {
4144         case SVM_EXIT_READ_CR0:
4145                 if (info->intercept == x86_intercept_cr_read)
4146                         icpt_info.exit_code += info->modrm_reg;
4147                 break;
4148         case SVM_EXIT_WRITE_CR0: {
4149                 unsigned long cr0, val;
4150                 u64 intercept;
4151
4152                 if (info->intercept == x86_intercept_cr_write)
4153                         icpt_info.exit_code += info->modrm_reg;
4154
4155                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4156                         break;
4157
4158                 intercept = svm->nested.intercept;
4159
4160                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4161                         break;
4162
4163                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4164                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4165
4166                 if (info->intercept == x86_intercept_lmsw) {
4167                         cr0 &= 0xfUL;
4168                         val &= 0xfUL;
4169                         /* lmsw can't clear PE - catch this here */
4170                         if (cr0 & X86_CR0_PE)
4171                                 val |= X86_CR0_PE;
4172                 }
4173
4174                 if (cr0 ^ val)
4175                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4176
4177                 break;
4178         }
4179         case SVM_EXIT_READ_DR0:
4180         case SVM_EXIT_WRITE_DR0:
4181                 icpt_info.exit_code += info->modrm_reg;
4182                 break;
4183         case SVM_EXIT_MSR:
4184                 if (info->intercept == x86_intercept_wrmsr)
4185                         vmcb->control.exit_info_1 = 1;
4186                 else
4187                         vmcb->control.exit_info_1 = 0;
4188                 break;
4189         case SVM_EXIT_PAUSE:
4190                 /*
4191                  * We get this for NOP only, but pause
4192                  * is rep not, check this here
4193                  */
4194                 if (info->rep_prefix != REPE_PREFIX)
4195                         goto out;
4196         case SVM_EXIT_IOIO: {
4197                 u64 exit_info;
4198                 u32 bytes;
4199
4200                 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4201
4202                 if (info->intercept == x86_intercept_in ||
4203                     info->intercept == x86_intercept_ins) {
4204                         exit_info |= SVM_IOIO_TYPE_MASK;
4205                         bytes = info->src_bytes;
4206                 } else {
4207                         bytes = info->dst_bytes;
4208                 }
4209
4210                 if (info->intercept == x86_intercept_outs ||
4211                     info->intercept == x86_intercept_ins)
4212                         exit_info |= SVM_IOIO_STR_MASK;
4213
4214                 if (info->rep_prefix)
4215                         exit_info |= SVM_IOIO_REP_MASK;
4216
4217                 bytes = min(bytes, 4u);
4218
4219                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4220
4221                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4222
4223                 vmcb->control.exit_info_1 = exit_info;
4224                 vmcb->control.exit_info_2 = info->next_rip;
4225
4226                 break;
4227         }
4228         default:
4229                 break;
4230         }
4231
4232         vmcb->control.next_rip  = info->next_rip;
4233         vmcb->control.exit_code = icpt_info.exit_code;
4234         vmexit = nested_svm_exit_handled(svm);
4235
4236         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4237                                            : X86EMUL_CONTINUE;
4238
4239 out:
4240         return ret;
4241 }
4242
4243 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4244 {
4245         local_irq_enable();
4246 }
4247
4248 static struct kvm_x86_ops svm_x86_ops = {
4249         .cpu_has_kvm_support = has_svm,
4250         .disabled_by_bios = is_disabled,
4251         .hardware_setup = svm_hardware_setup,
4252         .hardware_unsetup = svm_hardware_unsetup,
4253         .check_processor_compatibility = svm_check_processor_compat,
4254         .hardware_enable = svm_hardware_enable,
4255         .hardware_disable = svm_hardware_disable,
4256         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4257
4258         .vcpu_create = svm_create_vcpu,
4259         .vcpu_free = svm_free_vcpu,
4260         .vcpu_reset = svm_vcpu_reset,
4261
4262         .prepare_guest_switch = svm_prepare_guest_switch,
4263         .vcpu_load = svm_vcpu_load,
4264         .vcpu_put = svm_vcpu_put,
4265
4266         .update_db_bp_intercept = update_db_bp_intercept,
4267         .get_msr = svm_get_msr,
4268         .set_msr = svm_set_msr,
4269         .get_segment_base = svm_get_segment_base,
4270         .get_segment = svm_get_segment,
4271         .set_segment = svm_set_segment,
4272         .get_cpl = svm_get_cpl,
4273         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4274         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4275         .decache_cr3 = svm_decache_cr3,
4276         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4277         .set_cr0 = svm_set_cr0,
4278         .set_cr3 = svm_set_cr3,
4279         .set_cr4 = svm_set_cr4,
4280         .set_efer = svm_set_efer,
4281         .get_idt = svm_get_idt,
4282         .set_idt = svm_set_idt,
4283         .get_gdt = svm_get_gdt,
4284         .set_gdt = svm_set_gdt,
4285         .set_dr7 = svm_set_dr7,
4286         .cache_reg = svm_cache_reg,
4287         .get_rflags = svm_get_rflags,
4288         .set_rflags = svm_set_rflags,
4289         .fpu_activate = svm_fpu_activate,
4290         .fpu_deactivate = svm_fpu_deactivate,
4291
4292         .tlb_flush = svm_flush_tlb,
4293
4294         .run = svm_vcpu_run,
4295         .handle_exit = handle_exit,
4296         .skip_emulated_instruction = skip_emulated_instruction,
4297         .set_interrupt_shadow = svm_set_interrupt_shadow,
4298         .get_interrupt_shadow = svm_get_interrupt_shadow,
4299         .patch_hypercall = svm_patch_hypercall,
4300         .set_irq = svm_set_irq,
4301         .set_nmi = svm_inject_nmi,
4302         .queue_exception = svm_queue_exception,
4303         .cancel_injection = svm_cancel_injection,
4304         .interrupt_allowed = svm_interrupt_allowed,
4305         .nmi_allowed = svm_nmi_allowed,
4306         .get_nmi_mask = svm_get_nmi_mask,
4307         .set_nmi_mask = svm_set_nmi_mask,
4308         .enable_nmi_window = enable_nmi_window,
4309         .enable_irq_window = enable_irq_window,
4310         .update_cr8_intercept = update_cr8_intercept,
4311         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4312         .vm_has_apicv = svm_vm_has_apicv,
4313         .load_eoi_exitmap = svm_load_eoi_exitmap,
4314         .hwapic_isr_update = svm_hwapic_isr_update,
4315         .sync_pir_to_irr = svm_sync_pir_to_irr,
4316
4317         .set_tss_addr = svm_set_tss_addr,
4318         .get_tdp_level = get_npt_level,
4319         .get_mt_mask = svm_get_mt_mask,
4320
4321         .get_exit_info = svm_get_exit_info,
4322
4323         .get_lpage_level = svm_get_lpage_level,
4324
4325         .cpuid_update = svm_cpuid_update,
4326
4327         .rdtscp_supported = svm_rdtscp_supported,
4328         .invpcid_supported = svm_invpcid_supported,
4329
4330         .set_supported_cpuid = svm_set_supported_cpuid,
4331
4332         .has_wbinvd_exit = svm_has_wbinvd_exit,
4333
4334         .set_tsc_khz = svm_set_tsc_khz,
4335         .read_tsc_offset = svm_read_tsc_offset,
4336         .write_tsc_offset = svm_write_tsc_offset,
4337         .adjust_tsc_offset = svm_adjust_tsc_offset,
4338         .compute_tsc_offset = svm_compute_tsc_offset,
4339         .read_l1_tsc = svm_read_l1_tsc,
4340
4341         .set_tdp_cr3 = set_tdp_cr3,
4342
4343         .check_intercept = svm_check_intercept,
4344         .handle_external_intr = svm_handle_external_intr,
4345 };
4346
4347 static int __init svm_init(void)
4348 {
4349         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4350                         __alignof__(struct vcpu_svm), THIS_MODULE);
4351 }
4352
4353 static void __exit svm_exit(void)
4354 {
4355         kvm_exit();
4356 }
4357
4358 module_init(svm_init)
4359 module_exit(svm_exit)