arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69 #define APIC_VECTORS_PER_REG            32
  70
  71 #define VEC_POS(v) ((v) & (32 - 1))
  72 #define REG_POS(v) (((v) >> 5) << 4)
  73
  74 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  75 {
  76         *((u32 *) (apic->regs + reg_off)) = val;
  77 }
  78
  79 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  80 {
  81         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  82 }
  83
  84 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  85 {
  86         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  87 }
  88
  89 static inline int apic_test_vector(int vec, void *bitmap)
  90 {
  91         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  92 }
  93
  94 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  95 {
  96         struct kvm_lapic *apic = vcpu->arch.apic;
  97
  98         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  99                 apic_test_vector(vector, apic->regs + APIC_IRR);
 100 }
 101
 102 static inline void apic_set_vector(int vec, void *bitmap)
 103 {
 104         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 105 }
 106
 107 static inline void apic_clear_vector(int vec, void *bitmap)
 108 {
 109         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 110 }
 111
 112 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 113 {
 114         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 115 }
 116
 117 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 118 {
 119         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 120 }
 121
 122 struct static_key_deferred apic_hw_disabled __read_mostly;
 123 struct static_key_deferred apic_sw_disabled __read_mostly;
 124
 125 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 126 {
 127         if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
 128                 if (val & APIC_SPIV_APIC_ENABLED)
 129                         static_key_slow_dec_deferred(&apic_sw_disabled);
 130                 else
 131                         static_key_slow_inc(&apic_sw_disabled.key);
 132         }
 133         apic_set_reg(apic, APIC_SPIV, val);
 134 }
 135
 136 static inline int apic_enabled(struct kvm_lapic *apic)
 137 {
 138         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 139 }
 140
 141 #define LVT_MASK        \
 142         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 143
 144 #define LINT_MASK       \
 145         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 146          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 147
 148 static inline int kvm_apic_id(struct kvm_lapic *apic)
 149 {
 150         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 151 }
 152
 153 #define KVM_X2APIC_CID_BITS 0
 154
 155 static void recalculate_apic_map(struct kvm *kvm)
 156 {
 157         struct kvm_apic_map *new, *old = NULL;
 158         struct kvm_vcpu *vcpu;
 159         int i;
 160
 161         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 162
 163         mutex_lock(&kvm->arch.apic_map_lock);
 164
 165         if (!new)
 166                 goto out;
 167
 168         new->ldr_bits = 8;
 169         /* flat mode is default */
 170         new->cid_shift = 8;
 171         new->cid_mask = 0;
 172         new->lid_mask = 0xff;
 173
 174         kvm_for_each_vcpu(i, vcpu, kvm) {
 175                 struct kvm_lapic *apic = vcpu->arch.apic;
 176                 u16 cid, lid;
 177                 u32 ldr;
 178
 179                 if (!kvm_apic_present(vcpu))
 180                         continue;
 181
 182                 /*
 183                  * All APICs have to be configured in the same mode by an OS.
 184                  * We take advatage of this while building logical id loockup
 185                  * table. After reset APICs are in xapic/flat mode, so if we
 186                  * find apic with different setting we assume this is the mode
 187                  * OS wants all apics to be in; build lookup table accordingly.
 188                  */
 189                 if (apic_x2apic_mode(apic)) {
 190                         new->ldr_bits = 32;
 191                         new->cid_shift = 16;
 192                         new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
 193                         new->lid_mask = 0xffff;
 194                 } else if (kvm_apic_sw_enabled(apic) &&
 195                                 !new->cid_mask /* flat mode */ &&
 196                                 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
 197                         new->cid_shift = 4;
 198                         new->cid_mask = 0xf;
 199                         new->lid_mask = 0xf;
 200                 }
 201
 202                 new->phys_map[kvm_apic_id(apic)] = apic;
 203
 204                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 205                 cid = apic_cluster_id(new, ldr);
 206                 lid = apic_logical_id(new, ldr);
 207
 208                 if (lid)
 209                         new->logical_map[cid][ffs(lid) - 1] = apic;
 210         }
 211 out:
 212         old = rcu_dereference_protected(kvm->arch.apic_map,
 213                         lockdep_is_held(&kvm->arch.apic_map_lock));
 214         rcu_assign_pointer(kvm->arch.apic_map, new);
 215         mutex_unlock(&kvm->arch.apic_map_lock);
 216
 217         if (old)
 218                 kfree_rcu(old, rcu);
 219
 220         kvm_vcpu_request_scan_ioapic(kvm);
 221 }
 222
 223 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 224 {
 225         apic_set_reg(apic, APIC_ID, id << 24);
 226         recalculate_apic_map(apic->vcpu->kvm);
 227 }
 228
 229 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 230 {
 231         apic_set_reg(apic, APIC_LDR, id);
 232         recalculate_apic_map(apic->vcpu->kvm);
 233 }
 234
 235 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 236 {
 237         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 238 }
 239
 240 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 241 {
 242         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 243 }
 244
 245 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 246 {
 247         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 248                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
 249 }
 250
 251 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 252 {
 253         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 254                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
 255 }
 256
 257 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 258 {
 259         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 260                 apic->lapic_timer.timer_mode_mask) ==
 261                         APIC_LVT_TIMER_TSCDEADLINE);
 262 }
 263
 264 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 265 {
 266         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 267 }
 268
 269 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 270 {
 271         struct kvm_lapic *apic = vcpu->arch.apic;
 272         struct kvm_cpuid_entry2 *feat;
 273         u32 v = APIC_VERSION;
 274
 275         if (!kvm_vcpu_has_lapic(vcpu))
 276                 return;
 277
 278         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 279         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 280                 v |= APIC_LVR_DIRECTED_EOI;
 281         apic_set_reg(apic, APIC_LVR, v);
 282 }
 283
 284 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 285         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 286         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 287         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 288         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 289         LVT_MASK                /* LVTERR */
 290 };
 291
 292 static int find_highest_vector(void *bitmap)
 293 {
 294         int vec;
 295         u32 *reg;
 296
 297         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 298              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 299                 reg = bitmap + REG_POS(vec);
 300                 if (*reg)
 301                         return fls(*reg) - 1 + vec;
 302         }
 303
 304         return -1;
 305 }
 306
 307 static u8 count_vectors(void *bitmap)
 308 {
 309         int vec;
 310         u32 *reg;
 311         u8 count = 0;
 312
 313         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 314                 reg = bitmap + REG_POS(vec);
 315                 count += hweight32(*reg);
 316         }
 317
 318         return count;
 319 }
 320
 321 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 322 {
 323         u32 i, pir_val;
 324         struct kvm_lapic *apic = vcpu->arch.apic;
 325
 326         for (i = 0; i <= 7; i++) {
 327                 pir_val = xchg(&pir[i], 0);
 328                 if (pir_val)
 329                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 330         }
 331 }
 332 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 333
 334 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 335 {
 336         apic->irr_pending = true;
 337         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 338 }
 339
 340 static inline int apic_search_irr(struct kvm_lapic *apic)
 341 {
 342         return find_highest_vector(apic->regs + APIC_IRR);
 343 }
 344
 345 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 346 {
 347         int result;
 348
 349         /*
 350          * Note that irr_pending is just a hint. It will be always
 351          * true with virtual interrupt delivery enabled.
 352          */
 353         if (!apic->irr_pending)
 354                 return -1;
 355
 356         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 357         result = apic_search_irr(apic);
 358         ASSERT(result == -1 || result >= 16);
 359
 360         return result;
 361 }
 362
 363 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 364 {
 365         apic->irr_pending = false;
 366         apic_clear_vector(vec, apic->regs + APIC_IRR);
 367         if (apic_search_irr(apic) != -1)
 368                 apic->irr_pending = true;
 369 }
 370
 371 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 372 {
 373         /* Note that we never get here with APIC virtualization enabled.  */
 374
 375         if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 376                 ++apic->isr_count;
 377         BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 378         /*
 379          * ISR (in service register) bit is set when injecting an interrupt.
 380          * The highest vector is injected. Thus the latest bit set matches
 381          * the highest bit in ISR.
 382          */
 383         apic->highest_isr_cache = vec;
 384 }
 385
 386 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 387 {
 388         int result;
 389
 390         /*
 391          * Note that isr_count is always 1, and highest_isr_cache
 392          * is always -1, with APIC virtualization enabled.
 393          */
 394         if (!apic->isr_count)
 395                 return -1;
 396         if (likely(apic->highest_isr_cache != -1))
 397                 return apic->highest_isr_cache;
 398
 399         result = find_highest_vector(apic->regs + APIC_ISR);
 400         ASSERT(result == -1 || result >= 16);
 401
 402         return result;
 403 }
 404
 405 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 406 {
 407         struct kvm_vcpu *vcpu;
 408         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 409                 return;
 410
 411         vcpu = apic->vcpu;
 412
 413         /*
 414          * We do get here for APIC virtualization enabled if the guest
 415          * uses the Hyper-V APIC enlightenment.  In this case we may need
 416          * to trigger a new interrupt delivery by writing the SVI field;
 417          * on the other hand isr_count and highest_isr_cache are unused
 418          * and must be left alone.
 419          */
 420         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 421                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 422                                                apic_find_highest_isr(apic));
 423         else {
 424                 --apic->isr_count;
 425                 BUG_ON(apic->isr_count < 0);
 426                 apic->highest_isr_cache = -1;
 427         }
 428 }
 429
 430 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 431 {
 432         int highest_irr;
 433
 434         /* This may race with setting of irr in __apic_accept_irq() and
 435          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 436          * will cause vmexit immediately and the value will be recalculated
 437          * on the next vmentry.
 438          */
 439         if (!kvm_vcpu_has_lapic(vcpu))
 440                 return 0;
 441         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 442
 443         return highest_irr;
 444 }
 445
 446 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 447                              int vector, int level, int trig_mode,
 448                              unsigned long *dest_map);
 449
 450 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 451                 unsigned long *dest_map)
 452 {
 453         struct kvm_lapic *apic = vcpu->arch.apic;
 454
 455         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 456                         irq->level, irq->trig_mode, dest_map);
 457 }
 458
 459 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 460 {
 461
 462         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 463                                       sizeof(val));
 464 }
 465
 466 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 467 {
 468
 469         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 470                                       sizeof(*val));
 471 }
 472
 473 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 474 {
 475         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 476 }
 477
 478 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 479 {
 480         u8 val;
 481         if (pv_eoi_get_user(vcpu, &val) < 0)
 482                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 483                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 484         return val & 0x1;
 485 }
 486
 487 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 488 {
 489         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 490                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 491                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 492                 return;
 493         }
 494         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 495 }
 496
 497 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 498 {
 499         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 500                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 501                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 502                 return;
 503         }
 504         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 505 }
 506
 507 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 508 {
 509         struct kvm_lapic *apic = vcpu->arch.apic;
 510         int i;
 511
 512         for (i = 0; i < 8; i++)
 513                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 514 }
 515
 516 static void apic_update_ppr(struct kvm_lapic *apic)
 517 {
 518         u32 tpr, isrv, ppr, old_ppr;
 519         int isr;
 520
 521         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 522         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 523         isr = apic_find_highest_isr(apic);
 524         isrv = (isr != -1) ? isr : 0;
 525
 526         if ((tpr & 0xf0) >= (isrv & 0xf0))
 527                 ppr = tpr & 0xff;
 528         else
 529                 ppr = isrv & 0xf0;
 530
 531         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 532                    apic, ppr, isr, isrv);
 533
 534         if (old_ppr != ppr) {
 535                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 536                 if (ppr < old_ppr)
 537                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 538         }
 539 }
 540
 541 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 542 {
 543         apic_set_reg(apic, APIC_TASKPRI, tpr);
 544         apic_update_ppr(apic);
 545 }
 546
 547 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 548 {
 549         return dest == 0xff || kvm_apic_id(apic) == dest;
 550 }
 551
 552 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 553 {
 554         int result = 0;
 555         u32 logical_id;
 556
 557         if (apic_x2apic_mode(apic)) {
 558                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 559                 return logical_id & mda;
 560         }
 561
 562         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
 563
 564         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 565         case APIC_DFR_FLAT:
 566                 if (logical_id & mda)
 567                         result = 1;
 568                 break;
 569         case APIC_DFR_CLUSTER:
 570                 if (((logical_id >> 4) == (mda >> 0x4))
 571                     && (logical_id & mda & 0xf))
 572                         result = 1;
 573                 break;
 574         default:
 575                 apic_debug("Bad DFR vcpu %d: %08x\n",
 576                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 577                 break;
 578         }
 579
 580         return result;
 581 }
 582
 583 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 584                            int short_hand, int dest, int dest_mode)
 585 {
 586         int result = 0;
 587         struct kvm_lapic *target = vcpu->arch.apic;
 588
 589         apic_debug("target %p, source %p, dest 0x%x, "
 590                    "dest_mode 0x%x, short_hand 0x%x\n",
 591                    target, source, dest, dest_mode, short_hand);
 592
 593         ASSERT(target);
 594         switch (short_hand) {
 595         case APIC_DEST_NOSHORT:
 596                 if (dest_mode == 0)
 597                         /* Physical mode. */
 598                         result = kvm_apic_match_physical_addr(target, dest);
 599                 else
 600                         /* Logical mode. */
 601                         result = kvm_apic_match_logical_addr(target, dest);
 602                 break;
 603         case APIC_DEST_SELF:
 604                 result = (target == source);
 605                 break;
 606         case APIC_DEST_ALLINC:
 607                 result = 1;
 608                 break;
 609         case APIC_DEST_ALLBUT:
 610                 result = (target != source);
 611                 break;
 612         default:
 613                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 614                            short_hand);
 615                 break;
 616         }
 617
 618         return result;
 619 }
 620
 621 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 622                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 623 {
 624         struct kvm_apic_map *map;
 625         unsigned long bitmap = 1;
 626         struct kvm_lapic **dst;
 627         int i;
 628         bool ret = false;
 629
 630         *r = -1;
 631
 632         if (irq->shorthand == APIC_DEST_SELF) {
 633                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 634                 return true;
 635         }
 636
 637         if (irq->shorthand)
 638                 return false;
 639
 640         rcu_read_lock();
 641         map = rcu_dereference(kvm->arch.apic_map);
 642
 643         if (!map)
 644                 goto out;
 645
 646         if (irq->dest_mode == 0) { /* physical mode */
 647                 if (irq->delivery_mode == APIC_DM_LOWEST ||
 648                                 irq->dest_id == 0xff)
 649                         goto out;
 650                 dst = &map->phys_map[irq->dest_id & 0xff];
 651         } else {
 652                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 653
 654                 dst = map->logical_map[apic_cluster_id(map, mda)];
 655
 656                 bitmap = apic_logical_id(map, mda);
 657
 658                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 659                         int l = -1;
 660                         for_each_set_bit(i, &bitmap, 16) {
 661                                 if (!dst[i])
 662                                         continue;
 663                                 if (l < 0)
 664                                         l = i;
 665                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 666                                         l = i;
 667                         }
 668
 669                         bitmap = (l >= 0) ? 1 << l : 0;
 670                 }
 671         }
 672
 673         for_each_set_bit(i, &bitmap, 16) {
 674                 if (!dst[i])
 675                         continue;
 676                 if (*r < 0)
 677                         *r = 0;
 678                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 679         }
 680
 681         ret = true;
 682 out:
 683         rcu_read_unlock();
 684         return ret;
 685 }
 686
 687 /*
 688  * Add a pending IRQ into lapic.
 689  * Return 1 if successfully added and 0 if discarded.
 690  */
 691 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 692                              int vector, int level, int trig_mode,
 693                              unsigned long *dest_map)
 694 {
 695         int result = 0;
 696         struct kvm_vcpu *vcpu = apic->vcpu;
 697
 698         switch (delivery_mode) {
 699         case APIC_DM_LOWEST:
 700                 vcpu->arch.apic_arb_prio++;
 701         case APIC_DM_FIXED:
 702                 /* FIXME add logic for vcpu on reset */
 703                 if (unlikely(!apic_enabled(apic)))
 704                         break;
 705
 706                 if (dest_map)
 707                         __set_bit(vcpu->vcpu_id, dest_map);
 708
 709                 if (kvm_x86_ops->deliver_posted_interrupt) {
 710                         result = 1;
 711                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 712                 } else {
 713                         result = !apic_test_and_set_irr(vector, apic);
 714
 715                         if (!result) {
 716                                 if (trig_mode)
 717                                         apic_debug("level trig mode repeatedly "
 718                                                 "for vector %d", vector);
 719                                 goto out;
 720                         }
 721
 722                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 723                         kvm_vcpu_kick(vcpu);
 724                 }
 725 out:
 726                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 727                                 trig_mode, vector, !result);
 728                 break;
 729
 730         case APIC_DM_REMRD:
 731                 apic_debug("Ignoring delivery mode 3\n");
 732                 break;
 733
 734         case APIC_DM_SMI:
 735                 apic_debug("Ignoring guest SMI\n");
 736                 break;
 737
 738         case APIC_DM_NMI:
 739                 result = 1;
 740                 kvm_inject_nmi(vcpu);
 741                 kvm_vcpu_kick(vcpu);
 742                 break;
 743
 744         case APIC_DM_INIT:
 745                 if (!trig_mode || level) {
 746                         result = 1;
 747                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 748                         apic->pending_events = (1UL << KVM_APIC_INIT);
 749                         /* make sure pending_events is visible before sending
 750                          * the request */
 751                         smp_wmb();
 752                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 753                         kvm_vcpu_kick(vcpu);
 754                 } else {
 755                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 756                                    vcpu->vcpu_id);
 757                 }
 758                 break;
 759
 760         case APIC_DM_STARTUP:
 761                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 762                            vcpu->vcpu_id, vector);
 763                 result = 1;
 764                 apic->sipi_vector = vector;
 765                 /* make sure sipi_vector is visible for the receiver */
 766                 smp_wmb();
 767                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 768                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 769                 kvm_vcpu_kick(vcpu);
 770                 break;
 771
 772         case APIC_DM_EXTINT:
 773                 /*
 774                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 775                  * before NMI watchdog was enabled. Already handled by
 776                  * kvm_apic_accept_pic_intr().
 777                  */
 778                 break;
 779
 780         default:
 781                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 782                        delivery_mode);
 783                 break;
 784         }
 785         return result;
 786 }
 787
 788 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 789 {
 790         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 791 }
 792
 793 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 794 {
 795         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 796             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 797                 int trigger_mode;
 798                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 799                         trigger_mode = IOAPIC_LEVEL_TRIG;
 800                 else
 801                         trigger_mode = IOAPIC_EDGE_TRIG;
 802                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 803         }
 804 }
 805
 806 static int apic_set_eoi(struct kvm_lapic *apic)
 807 {
 808         int vector = apic_find_highest_isr(apic);
 809
 810         trace_kvm_eoi(apic, vector);
 811
 812         /*
 813          * Not every write EOI will has corresponding ISR,
 814          * one example is when Kernel check timer on setup_IO_APIC
 815          */
 816         if (vector == -1)
 817                 return vector;
 818
 819         apic_clear_isr(vector, apic);
 820         apic_update_ppr(apic);
 821
 822         kvm_ioapic_send_eoi(apic, vector);
 823         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 824         return vector;
 825 }
 826
 827 /*
 828  * this interface assumes a trap-like exit, which has already finished
 829  * desired side effect including vISR and vPPR update.
 830  */
 831 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 832 {
 833         struct kvm_lapic *apic = vcpu->arch.apic;
 834
 835         trace_kvm_eoi(apic, vector);
 836
 837         kvm_ioapic_send_eoi(apic, vector);
 838         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 839 }
 840 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 841
 842 static void apic_send_ipi(struct kvm_lapic *apic)
 843 {
 844         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 845         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 846         struct kvm_lapic_irq irq;
 847
 848         irq.vector = icr_low & APIC_VECTOR_MASK;
 849         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 850         irq.dest_mode = icr_low & APIC_DEST_MASK;
 851         irq.level = icr_low & APIC_INT_ASSERT;
 852         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 853         irq.shorthand = icr_low & APIC_SHORT_MASK;
 854         if (apic_x2apic_mode(apic))
 855                 irq.dest_id = icr_high;
 856         else
 857                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 858
 859         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 860
 861         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 862                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 863                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 864                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 865                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 866                    irq.vector);
 867
 868         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 869 }
 870
 871 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 872 {
 873         ktime_t remaining;
 874         s64 ns;
 875         u32 tmcct;
 876
 877         ASSERT(apic != NULL);
 878
 879         /* if initial count is 0, current count should also be 0 */
 880         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 881                 apic->lapic_timer.period == 0)
 882                 return 0;
 883
 884         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 885         if (ktime_to_ns(remaining) < 0)
 886                 remaining = ktime_set(0, 0);
 887
 888         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 889         tmcct = div64_u64(ns,
 890                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 891
 892         return tmcct;
 893 }
 894
 895 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 896 {
 897         struct kvm_vcpu *vcpu = apic->vcpu;
 898         struct kvm_run *run = vcpu->run;
 899
 900         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 901         run->tpr_access.rip = kvm_rip_read(vcpu);
 902         run->tpr_access.is_write = write;
 903 }
 904
 905 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 906 {
 907         if (apic->vcpu->arch.tpr_access_reporting)
 908                 __report_tpr_access(apic, write);
 909 }
 910
 911 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 912 {
 913         u32 val = 0;
 914
 915         if (offset >= LAPIC_MMIO_LENGTH)
 916                 return 0;
 917
 918         switch (offset) {
 919         case APIC_ID:
 920                 if (apic_x2apic_mode(apic))
 921                         val = kvm_apic_id(apic);
 922                 else
 923                         val = kvm_apic_id(apic) << 24;
 924                 break;
 925         case APIC_ARBPRI:
 926                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 927                 break;
 928
 929         case APIC_TMCCT:        /* Timer CCR */
 930                 if (apic_lvtt_tscdeadline(apic))
 931                         return 0;
 932
 933                 val = apic_get_tmcct(apic);
 934                 break;
 935         case APIC_PROCPRI:
 936                 apic_update_ppr(apic);
 937                 val = kvm_apic_get_reg(apic, offset);
 938                 break;
 939         case APIC_TASKPRI:
 940                 report_tpr_access(apic, false);
 941                 /* fall thru */
 942         default:
 943                 val = kvm_apic_get_reg(apic, offset);
 944                 break;
 945         }
 946
 947         return val;
 948 }
 949
 950 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 951 {
 952         return container_of(dev, struct kvm_lapic, dev);
 953 }
 954
 955 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 956                 void *data)
 957 {
 958         unsigned char alignment = offset & 0xf;
 959         u32 result;
 960         /* this bitmask has a bit cleared for each reserved register */
 961         static const u64 rmask = 0x43ff01ffffffe70cULL;
 962
 963         if ((alignment + len) > 4) {
 964                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 965                            offset, len);
 966                 return 1;
 967         }
 968
 969         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 970                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 971                            offset);
 972                 return 1;
 973         }
 974
 975         result = __apic_read(apic, offset & ~0xf);
 976
 977         trace_kvm_apic_read(offset, result);
 978
 979         switch (len) {
 980         case 1:
 981         case 2:
 982         case 4:
 983                 memcpy(data, (char *)&result + alignment, len);
 984                 break;
 985         default:
 986                 printk(KERN_ERR "Local APIC read with len = %x, "
 987                        "should be 1,2, or 4 instead\n", len);
 988                 break;
 989         }
 990         return 0;
 991 }
 992
 993 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 994 {
 995         return kvm_apic_hw_enabled(apic) &&
 996             addr >= apic->base_address &&
 997             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 998 }
 999
1000 static int apic_mmio_read(struct kvm_io_device *this,
1001                            gpa_t address, int len, void *data)
1002 {
1003         struct kvm_lapic *apic = to_lapic(this);
1004         u32 offset = address - apic->base_address;
1005
1006         if (!apic_mmio_in_range(apic, address))
1007                 return -EOPNOTSUPP;
1008
1009         apic_reg_read(apic, offset, len, data);
1010
1011         return 0;
1012 }
1013
1014 static void update_divide_count(struct kvm_lapic *apic)
1015 {
1016         u32 tmp1, tmp2, tdcr;
1017
1018         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1019         tmp1 = tdcr & 0xf;
1020         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1021         apic->divide_count = 0x1 << (tmp2 & 0x7);
1022
1023         apic_debug("timer divide count is 0x%x\n",
1024                                    apic->divide_count);
1025 }
1026
1027 static void start_apic_timer(struct kvm_lapic *apic)
1028 {
1029         ktime_t now;
1030         atomic_set(&apic->lapic_timer.pending, 0);
1031
1032         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1033                 /* lapic timer in oneshot or periodic mode */
1034                 now = apic->lapic_timer.timer.base->get_time();
1035                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1036                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1037
1038                 if (!apic->lapic_timer.period)
1039                         return;
1040                 /*
1041                  * Do not allow the guest to program periodic timers with small
1042                  * interval, since the hrtimers are not throttled by the host
1043                  * scheduler.
1044                  */
1045                 if (apic_lvtt_period(apic)) {
1046                         s64 min_period = min_timer_period_us * 1000LL;
1047
1048                         if (apic->lapic_timer.period < min_period) {
1049                                 pr_info_ratelimited(
1050                                     "kvm: vcpu %i: requested %lld ns "
1051                                     "lapic timer period limited to %lld ns\n",
1052                                     apic->vcpu->vcpu_id,
1053                                     apic->lapic_timer.period, min_period);
1054                                 apic->lapic_timer.period = min_period;
1055                         }
1056                 }
1057
1058                 hrtimer_start(&apic->lapic_timer.timer,
1059                               ktime_add_ns(now, apic->lapic_timer.period),
1060                               HRTIMER_MODE_ABS);
1061
1062                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1063                            PRIx64 ", "
1064                            "timer initial count 0x%x, period %lldns, "
1065                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1066                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1067                            kvm_apic_get_reg(apic, APIC_TMICT),
1068                            apic->lapic_timer.period,
1069                            ktime_to_ns(ktime_add_ns(now,
1070                                         apic->lapic_timer.period)));
1071         } else if (apic_lvtt_tscdeadline(apic)) {
1072                 /* lapic timer in tsc deadline mode */
1073                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1074                 u64 ns = 0;
1075                 struct kvm_vcpu *vcpu = apic->vcpu;
1076                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1077                 unsigned long flags;
1078
1079                 if (unlikely(!tscdeadline || !this_tsc_khz))
1080                         return;
1081
1082                 local_irq_save(flags);
1083
1084                 now = apic->lapic_timer.timer.base->get_time();
1085                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1086                 if (likely(tscdeadline > guest_tsc)) {
1087                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1088                         do_div(ns, this_tsc_khz);
1089                 }
1090                 hrtimer_start(&apic->lapic_timer.timer,
1091                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1092
1093                 local_irq_restore(flags);
1094         }
1095 }
1096
1097 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1098 {
1099         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1100
1101         if (apic_lvt_nmi_mode(lvt0_val)) {
1102                 if (!nmi_wd_enabled) {
1103                         apic_debug("Receive NMI setting on APIC_LVT0 "
1104                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1105                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1106                 }
1107         } else if (nmi_wd_enabled)
1108                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1109 }
1110
1111 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1112 {
1113         int ret = 0;
1114
1115         trace_kvm_apic_write(reg, val);
1116
1117         switch (reg) {
1118         case APIC_ID:           /* Local APIC ID */
1119                 if (!apic_x2apic_mode(apic))
1120                         kvm_apic_set_id(apic, val >> 24);
1121                 else
1122                         ret = 1;
1123                 break;
1124
1125         case APIC_TASKPRI:
1126                 report_tpr_access(apic, true);
1127                 apic_set_tpr(apic, val & 0xff);
1128                 break;
1129
1130         case APIC_EOI:
1131                 apic_set_eoi(apic);
1132                 break;
1133
1134         case APIC_LDR:
1135                 if (!apic_x2apic_mode(apic))
1136                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1137                 else
1138                         ret = 1;
1139                 break;
1140
1141         case APIC_DFR:
1142                 if (!apic_x2apic_mode(apic)) {
1143                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1144                         recalculate_apic_map(apic->vcpu->kvm);
1145                 } else
1146                         ret = 1;
1147                 break;
1148
1149         case APIC_SPIV: {
1150                 u32 mask = 0x3ff;
1151                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1152                         mask |= APIC_SPIV_DIRECTED_EOI;
1153                 apic_set_spiv(apic, val & mask);
1154                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1155                         int i;
1156                         u32 lvt_val;
1157
1158                         for (i = 0; i < APIC_LVT_NUM; i++) {
1159                                 lvt_val = kvm_apic_get_reg(apic,
1160                                                        APIC_LVTT + 0x10 * i);
1161                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1162                                              lvt_val | APIC_LVT_MASKED);
1163                         }
1164                         atomic_set(&apic->lapic_timer.pending, 0);
1165
1166                 }
1167                 break;
1168         }
1169         case APIC_ICR:
1170                 /* No delay here, so we always clear the pending bit */
1171                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1172                 apic_send_ipi(apic);
1173                 break;
1174
1175         case APIC_ICR2:
1176                 if (!apic_x2apic_mode(apic))
1177                         val &= 0xff000000;
1178                 apic_set_reg(apic, APIC_ICR2, val);
1179                 break;
1180
1181         case APIC_LVT0:
1182                 apic_manage_nmi_watchdog(apic, val);
1183         case APIC_LVTTHMR:
1184         case APIC_LVTPC:
1185         case APIC_LVT1:
1186         case APIC_LVTERR:
1187                 /* TODO: Check vector */
1188                 if (!kvm_apic_sw_enabled(apic))
1189                         val |= APIC_LVT_MASKED;
1190
1191                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1192                 apic_set_reg(apic, reg, val);
1193
1194                 break;
1195
1196         case APIC_LVTT:
1197                 if ((kvm_apic_get_reg(apic, APIC_LVTT) &
1198                     apic->lapic_timer.timer_mode_mask) !=
1199                    (val & apic->lapic_timer.timer_mode_mask))
1200                         hrtimer_cancel(&apic->lapic_timer.timer);
1201
1202                 if (!kvm_apic_sw_enabled(apic))
1203                         val |= APIC_LVT_MASKED;
1204                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1205                 apic_set_reg(apic, APIC_LVTT, val);
1206                 break;
1207
1208         case APIC_TMICT:
1209                 if (apic_lvtt_tscdeadline(apic))
1210                         break;
1211
1212                 hrtimer_cancel(&apic->lapic_timer.timer);
1213                 apic_set_reg(apic, APIC_TMICT, val);
1214                 start_apic_timer(apic);
1215                 break;
1216
1217         case APIC_TDCR:
1218                 if (val & 4)
1219                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1220                 apic_set_reg(apic, APIC_TDCR, val);
1221                 update_divide_count(apic);
1222                 break;
1223
1224         case APIC_ESR:
1225                 if (apic_x2apic_mode(apic) && val != 0) {
1226                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1227                         ret = 1;
1228                 }
1229                 break;
1230
1231         case APIC_SELF_IPI:
1232                 if (apic_x2apic_mode(apic)) {
1233                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1234                 } else
1235                         ret = 1;
1236                 break;
1237         default:
1238                 ret = 1;
1239                 break;
1240         }
1241         if (ret)
1242                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1243         return ret;
1244 }
1245
1246 static int apic_mmio_write(struct kvm_io_device *this,
1247                             gpa_t address, int len, const void *data)
1248 {
1249         struct kvm_lapic *apic = to_lapic(this);
1250         unsigned int offset = address - apic->base_address;
1251         u32 val;
1252
1253         if (!apic_mmio_in_range(apic, address))
1254                 return -EOPNOTSUPP;
1255
1256         /*
1257          * APIC register must be aligned on 128-bits boundary.
1258          * 32/64/128 bits registers must be accessed thru 32 bits.
1259          * Refer SDM 8.4.1
1260          */
1261         if (len != 4 || (offset & 0xf)) {
1262                 /* Don't shout loud, $infamous_os would cause only noise. */
1263                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1264                 return 0;
1265         }
1266
1267         val = *(u32*)data;
1268
1269         /* too common printing */
1270         if (offset != APIC_EOI)
1271                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1272                            "0x%x\n", __func__, offset, len, val);
1273
1274         apic_reg_write(apic, offset & 0xff0, val);
1275
1276         return 0;
1277 }
1278
1279 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1280 {
1281         if (kvm_vcpu_has_lapic(vcpu))
1282                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1283 }
1284 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1285
1286 /* emulate APIC access in a trap manner */
1287 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1288 {
1289         u32 val = 0;
1290
1291         /* hw has done the conditional check and inst decode */
1292         offset &= 0xff0;
1293
1294         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1295
1296         /* TODO: optimize to just emulate side effect w/o one more write */
1297         apic_reg_write(vcpu->arch.apic, offset, val);
1298 }
1299 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1300
1301 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1302 {
1303         struct kvm_lapic *apic = vcpu->arch.apic;
1304
1305         if (!vcpu->arch.apic)
1306                 return;
1307
1308         hrtimer_cancel(&apic->lapic_timer.timer);
1309
1310         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1311                 static_key_slow_dec_deferred(&apic_hw_disabled);
1312
1313         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
1314                 static_key_slow_dec_deferred(&apic_sw_disabled);
1315
1316         if (apic->regs)
1317                 free_page((unsigned long)apic->regs);
1318
1319         kfree(apic);
1320 }
1321
1322 /*
1323  *----------------------------------------------------------------------
1324  * LAPIC interface
1325  *----------------------------------------------------------------------
1326  */
1327
1328 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1329 {
1330         struct kvm_lapic *apic = vcpu->arch.apic;
1331
1332         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1333                         apic_lvtt_period(apic))
1334                 return 0;
1335
1336         return apic->lapic_timer.tscdeadline;
1337 }
1338
1339 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1340 {
1341         struct kvm_lapic *apic = vcpu->arch.apic;
1342
1343         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1344                         apic_lvtt_period(apic))
1345                 return;
1346
1347         hrtimer_cancel(&apic->lapic_timer.timer);
1348         apic->lapic_timer.tscdeadline = data;
1349         start_apic_timer(apic);
1350 }
1351
1352 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1353 {
1354         struct kvm_lapic *apic = vcpu->arch.apic;
1355
1356         if (!kvm_vcpu_has_lapic(vcpu))
1357                 return;
1358
1359         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1360                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1361 }
1362
1363 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1364 {
1365         u64 tpr;
1366
1367         if (!kvm_vcpu_has_lapic(vcpu))
1368                 return 0;
1369
1370         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1371
1372         return (tpr & 0xf0) >> 4;
1373 }
1374
1375 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1376 {
1377         u64 old_value = vcpu->arch.apic_base;
1378         struct kvm_lapic *apic = vcpu->arch.apic;
1379
1380         if (!apic) {
1381                 value |= MSR_IA32_APICBASE_BSP;
1382                 vcpu->arch.apic_base = value;
1383                 return;
1384         }
1385
1386         if (!kvm_vcpu_is_bsp(apic->vcpu))
1387                 value &= ~MSR_IA32_APICBASE_BSP;
1388         vcpu->arch.apic_base = value;
1389
1390         /* update jump label if enable bit changes */
1391         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1392                 if (value & MSR_IA32_APICBASE_ENABLE)
1393                         static_key_slow_dec_deferred(&apic_hw_disabled);
1394                 else
1395                         static_key_slow_inc(&apic_hw_disabled.key);
1396                 recalculate_apic_map(vcpu->kvm);
1397         }
1398
1399         if ((old_value ^ value) & X2APIC_ENABLE) {
1400                 if (value & X2APIC_ENABLE) {
1401                         u32 id = kvm_apic_id(apic);
1402                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1403                         kvm_apic_set_ldr(apic, ldr);
1404                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1405                 } else
1406                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1407         }
1408
1409         apic->base_address = apic->vcpu->arch.apic_base &
1410                              MSR_IA32_APICBASE_BASE;
1411
1412         /* with FSB delivery interrupt, we can restart APIC functionality */
1413         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1414                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1415
1416 }
1417
1418 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1419 {
1420         struct kvm_lapic *apic;
1421         int i;
1422
1423         apic_debug("%s\n", __func__);
1424
1425         ASSERT(vcpu);
1426         apic = vcpu->arch.apic;
1427         ASSERT(apic != NULL);
1428
1429         /* Stop the timer in case it's a reset to an active apic */
1430         hrtimer_cancel(&apic->lapic_timer.timer);
1431
1432         kvm_apic_set_id(apic, vcpu->vcpu_id);
1433         kvm_apic_set_version(apic->vcpu);
1434
1435         for (i = 0; i < APIC_LVT_NUM; i++)
1436                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1437         apic_set_reg(apic, APIC_LVT0,
1438                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1439
1440         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1441         apic_set_spiv(apic, 0xff);
1442         apic_set_reg(apic, APIC_TASKPRI, 0);
1443         kvm_apic_set_ldr(apic, 0);
1444         apic_set_reg(apic, APIC_ESR, 0);
1445         apic_set_reg(apic, APIC_ICR, 0);
1446         apic_set_reg(apic, APIC_ICR2, 0);
1447         apic_set_reg(apic, APIC_TDCR, 0);
1448         apic_set_reg(apic, APIC_TMICT, 0);
1449         for (i = 0; i < 8; i++) {
1450                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1451                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1452                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1453         }
1454         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1455         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1456         apic->highest_isr_cache = -1;
1457         update_divide_count(apic);
1458         atomic_set(&apic->lapic_timer.pending, 0);
1459         if (kvm_vcpu_is_bsp(vcpu))
1460                 kvm_lapic_set_base(vcpu,
1461                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1462         vcpu->arch.pv_eoi.msr_val = 0;
1463         apic_update_ppr(apic);
1464
1465         vcpu->arch.apic_arb_prio = 0;
1466         vcpu->arch.apic_attention = 0;
1467
1468         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1469                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1470                    vcpu, kvm_apic_id(apic),
1471                    vcpu->arch.apic_base, apic->base_address);
1472 }
1473
1474 /*
1475  *----------------------------------------------------------------------
1476  * timer interface
1477  *----------------------------------------------------------------------
1478  */
1479
1480 static bool lapic_is_periodic(struct kvm_lapic *apic)
1481 {
1482         return apic_lvtt_period(apic);
1483 }
1484
1485 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1486 {
1487         struct kvm_lapic *apic = vcpu->arch.apic;
1488
1489         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1490                         apic_lvt_enabled(apic, APIC_LVTT))
1491                 return atomic_read(&apic->lapic_timer.pending);
1492
1493         return 0;
1494 }
1495
1496 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1497 {
1498         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1499         int vector, mode, trig_mode;
1500
1501         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1502                 vector = reg & APIC_VECTOR_MASK;
1503                 mode = reg & APIC_MODE_MASK;
1504                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1505                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1506                                         NULL);
1507         }
1508         return 0;
1509 }
1510
1511 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1512 {
1513         struct kvm_lapic *apic = vcpu->arch.apic;
1514
1515         if (apic)
1516                 kvm_apic_local_deliver(apic, APIC_LVT0);
1517 }
1518
1519 static const struct kvm_io_device_ops apic_mmio_ops = {
1520         .read     = apic_mmio_read,
1521         .write    = apic_mmio_write,
1522 };
1523
1524 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1525 {
1526         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1527         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1528         struct kvm_vcpu *vcpu = apic->vcpu;
1529         wait_queue_head_t *q = &vcpu->wq;
1530
1531         /*
1532          * There is a race window between reading and incrementing, but we do
1533          * not care about potentially losing timer events in the !reinject
1534          * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1535          * in vcpu_enter_guest.
1536          */
1537         if (!atomic_read(&ktimer->pending)) {
1538                 atomic_inc(&ktimer->pending);
1539                 /* FIXME: this code should not know anything about vcpus */
1540                 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1541         }
1542
1543         if (waitqueue_active(q))
1544                 wake_up_interruptible(q);
1545
1546         if (lapic_is_periodic(apic)) {
1547                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1548                 return HRTIMER_RESTART;
1549         } else
1550                 return HRTIMER_NORESTART;
1551 }
1552
1553 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1554 {
1555         struct kvm_lapic *apic;
1556
1557         ASSERT(vcpu != NULL);
1558         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1559
1560         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1561         if (!apic)
1562                 goto nomem;
1563
1564         vcpu->arch.apic = apic;
1565
1566         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1567         if (!apic->regs) {
1568                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1569                        vcpu->vcpu_id);
1570                 goto nomem_free_apic;
1571         }
1572         apic->vcpu = vcpu;
1573
1574         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1575                      HRTIMER_MODE_ABS);
1576         apic->lapic_timer.timer.function = apic_timer_fn;
1577
1578         /*
1579          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1580          * thinking that APIC satet has changed.
1581          */
1582         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1583         kvm_lapic_set_base(vcpu,
1584                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1585
1586         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1587         kvm_lapic_reset(vcpu);
1588         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1589
1590         return 0;
1591 nomem_free_apic:
1592         kfree(apic);
1593 nomem:
1594         return -ENOMEM;
1595 }
1596
1597 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1598 {
1599         struct kvm_lapic *apic = vcpu->arch.apic;
1600         int highest_irr;
1601
1602         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1603                 return -1;
1604
1605         apic_update_ppr(apic);
1606         highest_irr = apic_find_highest_irr(apic);
1607         if ((highest_irr == -1) ||
1608             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1609                 return -1;
1610         return highest_irr;
1611 }
1612
1613 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1614 {
1615         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1616         int r = 0;
1617
1618         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1619                 r = 1;
1620         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1621             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1622                 r = 1;
1623         return r;
1624 }
1625
1626 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1627 {
1628         struct kvm_lapic *apic = vcpu->arch.apic;
1629
1630         if (!kvm_vcpu_has_lapic(vcpu))
1631                 return;
1632
1633         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1634                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1635                         atomic_dec(&apic->lapic_timer.pending);
1636         }
1637 }
1638
1639 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1640 {
1641         int vector = kvm_apic_has_interrupt(vcpu);
1642         struct kvm_lapic *apic = vcpu->arch.apic;
1643
1644         /* Note that we never get here with APIC virtualization enabled.  */
1645
1646         if (vector == -1)
1647                 return -1;
1648
1649         apic_set_isr(vector, apic);
1650         apic_update_ppr(apic);
1651         apic_clear_irr(vector, apic);
1652         return vector;
1653 }
1654
1655 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1656                 struct kvm_lapic_state *s)
1657 {
1658         struct kvm_lapic *apic = vcpu->arch.apic;
1659
1660         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1661         /* set SPIV separately to get count of SW disabled APICs right */
1662         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1663         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1664         /* call kvm_apic_set_id() to put apic into apic_map */
1665         kvm_apic_set_id(apic, kvm_apic_id(apic));
1666         kvm_apic_set_version(vcpu);
1667
1668         apic_update_ppr(apic);
1669         hrtimer_cancel(&apic->lapic_timer.timer);
1670         update_divide_count(apic);
1671         start_apic_timer(apic);
1672         apic->irr_pending = true;
1673         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1674                                 1 : count_vectors(apic->regs + APIC_ISR);
1675         apic->highest_isr_cache = -1;
1676         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1677         kvm_make_request(KVM_REQ_EVENT, vcpu);
1678         kvm_rtc_eoi_tracking_restore_one(vcpu);
1679 }
1680
1681 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1682 {
1683         struct hrtimer *timer;
1684
1685         if (!kvm_vcpu_has_lapic(vcpu))
1686                 return;
1687
1688         timer = &vcpu->arch.apic->lapic_timer.timer;
1689         if (hrtimer_cancel(timer))
1690                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1691 }
1692
1693 /*
1694  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1695  *
1696  * Detect whether guest triggered PV EOI since the
1697  * last entry. If yes, set EOI on guests's behalf.
1698  * Clear PV EOI in guest memory in any case.
1699  */
1700 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1701                                         struct kvm_lapic *apic)
1702 {
1703         bool pending;
1704         int vector;
1705         /*
1706          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1707          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1708          *
1709          * KVM_APIC_PV_EOI_PENDING is unset:
1710          *      -> host disabled PV EOI.
1711          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1712          *      -> host enabled PV EOI, guest did not execute EOI yet.
1713          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1714          *      -> host enabled PV EOI, guest executed EOI.
1715          */
1716         BUG_ON(!pv_eoi_enabled(vcpu));
1717         pending = pv_eoi_get_pending(vcpu);
1718         /*
1719          * Clear pending bit in any case: it will be set again on vmentry.
1720          * While this might not be ideal from performance point of view,
1721          * this makes sure pv eoi is only enabled when we know it's safe.
1722          */
1723         pv_eoi_clr_pending(vcpu);
1724         if (pending)
1725                 return;
1726         vector = apic_set_eoi(apic);
1727         trace_kvm_pv_eoi(apic, vector);
1728 }
1729
1730 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1731 {
1732         u32 data;
1733
1734         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1735                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1736
1737         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1738                 return;
1739
1740         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1741                                 sizeof(u32));
1742
1743         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1744 }
1745
1746 /*
1747  * apic_sync_pv_eoi_to_guest - called before vmentry
1748  *
1749  * Detect whether it's safe to enable PV EOI and
1750  * if yes do so.
1751  */
1752 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1753                                         struct kvm_lapic *apic)
1754 {
1755         if (!pv_eoi_enabled(vcpu) ||
1756             /* IRR set or many bits in ISR: could be nested. */
1757             apic->irr_pending ||
1758             /* Cache not set: could be safe but we don't bother. */
1759             apic->highest_isr_cache == -1 ||
1760             /* Need EOI to update ioapic. */
1761             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1762                 /*
1763                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1764                  * so we need not do anything here.
1765                  */
1766                 return;
1767         }
1768
1769         pv_eoi_set_pending(apic->vcpu);
1770 }
1771
1772 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1773 {
1774         u32 data, tpr;
1775         int max_irr, max_isr;
1776         struct kvm_lapic *apic = vcpu->arch.apic;
1777
1778         apic_sync_pv_eoi_to_guest(vcpu, apic);
1779
1780         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1781                 return;
1782
1783         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1784         max_irr = apic_find_highest_irr(apic);
1785         if (max_irr < 0)
1786                 max_irr = 0;
1787         max_isr = apic_find_highest_isr(apic);
1788         if (max_isr < 0)
1789                 max_isr = 0;
1790         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1791
1792         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1793                                 sizeof(u32));
1794 }
1795
1796 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1797 {
1798         if (vapic_addr) {
1799                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1800                                         &vcpu->arch.apic->vapic_cache,
1801                                         vapic_addr, sizeof(u32)))
1802                         return -EINVAL;
1803                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1804         } else {
1805                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1806         }
1807
1808         vcpu->arch.apic->vapic_addr = vapic_addr;
1809         return 0;
1810 }
1811
1812 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1813 {
1814         struct kvm_lapic *apic = vcpu->arch.apic;
1815         u32 reg = (msr - APIC_BASE_MSR) << 4;
1816
1817         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1818                 return 1;
1819
1820         /* if this is ICR write vector before command */
1821         if (msr == 0x830)
1822                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1823         return apic_reg_write(apic, reg, (u32)data);
1824 }
1825
1826 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1827 {
1828         struct kvm_lapic *apic = vcpu->arch.apic;
1829         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1830
1831         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1832                 return 1;
1833
1834         if (apic_reg_read(apic, reg, 4, &low))
1835                 return 1;
1836         if (msr == 0x830)
1837                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1838
1839         *data = (((u64)high) << 32) | low;
1840
1841         return 0;
1842 }
1843
1844 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1845 {
1846         struct kvm_lapic *apic = vcpu->arch.apic;
1847
1848         if (!kvm_vcpu_has_lapic(vcpu))
1849                 return 1;
1850
1851         /* if this is ICR write vector before command */
1852         if (reg == APIC_ICR)
1853                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1854         return apic_reg_write(apic, reg, (u32)data);
1855 }
1856
1857 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1858 {
1859         struct kvm_lapic *apic = vcpu->arch.apic;
1860         u32 low, high = 0;
1861
1862         if (!kvm_vcpu_has_lapic(vcpu))
1863                 return 1;
1864
1865         if (apic_reg_read(apic, reg, 4, &low))
1866                 return 1;
1867         if (reg == APIC_ICR)
1868                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1869
1870         *data = (((u64)high) << 32) | low;
1871
1872         return 0;
1873 }
1874
1875 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1876 {
1877         u64 addr = data & ~KVM_MSR_ENABLED;
1878         if (!IS_ALIGNED(addr, 4))
1879                 return 1;
1880
1881         vcpu->arch.pv_eoi.msr_val = data;
1882         if (!pv_eoi_enabled(vcpu))
1883                 return 0;
1884         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1885                                          addr, sizeof(u8));
1886 }
1887
1888 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1889 {
1890         struct kvm_lapic *apic = vcpu->arch.apic;
1891         unsigned int sipi_vector;
1892         unsigned long pe;
1893
1894         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1895                 return;
1896
1897         pe = xchg(&apic->pending_events, 0);
1898
1899         if (test_bit(KVM_APIC_INIT, &pe)) {
1900                 kvm_lapic_reset(vcpu);
1901                 kvm_vcpu_reset(vcpu);
1902                 if (kvm_vcpu_is_bsp(apic->vcpu))
1903                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1904                 else
1905                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1906         }
1907         if (test_bit(KVM_APIC_SIPI, &pe) &&
1908             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1909                 /* evaluate pending_events before reading the vector */
1910                 smp_rmb();
1911                 sipi_vector = apic->sipi_vector;
1912                 pr_debug("vcpu %d received sipi with vector # %x\n",
1913                          vcpu->vcpu_id, sipi_vector);
1914                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1915                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1916         }
1917 }
1918
1919 void kvm_lapic_init(void)
1920 {
1921         /* do not patch jump label more than once per second */
1922         jump_label_rate_limit(&apic_hw_disabled, HZ);
1923         jump_label_rate_limit(&apic_sw_disabled, HZ);
1924 }