arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/crash_dump.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <linux/iommu-helper.h>
  40
  41 #include <asm/iommu.h>
  42 #include <asm/calgary.h>
  43 #include <asm/tce.h>
  44 #include <asm/pci-direct.h>
  45 #include <asm/system.h>
  46 #include <asm/dma.h>
  47 #include <asm/rio.h>
  48 #include <asm/bios_ebda.h>
  49
  50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  51 int use_calgary __read_mostly = 1;
  52 #else
  53 int use_calgary __read_mostly = 0;
  54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  55
  56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  58
  59 /* register offsets inside the host bridge space */
  60 #define CALGARY_CONFIG_REG      0x0108
  61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  62 #define PHB_PLSSR_OFFSET        0x0120
  63 #define PHB_CONFIG_RW_OFFSET    0x0160
  64 #define PHB_IOBASE_BAR_LOW      0x0170
  65 #define PHB_IOBASE_BAR_HIGH     0x0180
  66 #define PHB_MEM_1_LOW           0x0190
  67 #define PHB_MEM_1_HIGH          0x01A0
  68 #define PHB_IO_ADDR_SIZE        0x01B0
  69 #define PHB_MEM_1_SIZE          0x01C0
  70 #define PHB_MEM_ST_OFFSET       0x01D0
  71 #define PHB_AER_OFFSET          0x0200
  72 #define PHB_CONFIG_0_HIGH       0x0220
  73 #define PHB_CONFIG_0_LOW        0x0230
  74 #define PHB_CONFIG_0_END        0x0240
  75 #define PHB_MEM_2_LOW           0x02B0
  76 #define PHB_MEM_2_HIGH          0x02C0
  77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  78 #define PHB_MEM_2_SIZE_LOW      0x02E0
  79 #define PHB_DOSHOLE_OFFSET      0x08E0
  80
  81 /* CalIOC2 specific */
  82 #define PHB_SAVIOR_L2           0x0DB0
  83 #define PHB_PAGE_MIG_CTRL       0x0DA8
  84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  86
  87 /* PHB_CONFIG_RW */
  88 #define PHB_TCE_ENABLE          0x20000000
  89 #define PHB_SLOT_DISABLE        0x1C000000
  90 #define PHB_DAC_DISABLE         0x01000000
  91 #define PHB_MEM2_ENABLE         0x00400000
  92 #define PHB_MCSR_ENABLE         0x00100000
  93 /* TAR (Table Address Register) */
  94 #define TAR_SW_BITS             0x0000ffffffff800fUL
  95 #define TAR_VALID               0x0000000000000008UL
  96 /* CSR (Channel/DMA Status Register) */
  97 #define CSR_AGENT_MASK          0xffe0ffff
  98 /* CCR (Calgary Configuration Register) */
  99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 101 #define PMR_SOFTSTOP            0x80000000
 102 #define PMR_SOFTSTOPFAULT       0x40000000
 103 #define PMR_HARDSTOP            0x20000000
 104
 105 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 106 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 107 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 108 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 109 #define PHBS_PER_CALGARY        4
 110
 111 /* register offsets in Calgary's internal register space */
 112 static const unsigned long tar_offsets[] = {
 113         0x0580 /* TAR0 */,
 114         0x0588 /* TAR1 */,
 115         0x0590 /* TAR2 */,
 116         0x0598 /* TAR3 */
 117 };
 118
 119 static const unsigned long split_queue_offsets[] = {
 120         0x4870 /* SPLIT QUEUE 0 */,
 121         0x5870 /* SPLIT QUEUE 1 */,
 122         0x6870 /* SPLIT QUEUE 2 */,
 123         0x7870 /* SPLIT QUEUE 3 */
 124 };
 125
 126 static const unsigned long phb_offsets[] = {
 127         0x8000 /* PHB0 */,
 128         0x9000 /* PHB1 */,
 129         0xA000 /* PHB2 */,
 130         0xB000 /* PHB3 */
 131 };
 132
 133 /* PHB debug registers */
 134
 135 static const unsigned long phb_debug_offsets[] = {
 136         0x4000  /* PHB 0 DEBUG */,
 137         0x5000  /* PHB 1 DEBUG */,
 138         0x6000  /* PHB 2 DEBUG */,
 139         0x7000  /* PHB 3 DEBUG */
 140 };
 141
 142 /*
 143  * STUFF register for each debug PHB,
 144  * byte 1 = start bus number, byte 2 = end bus number
 145  */
 146
 147 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 148
 149 #define EMERGENCY_PAGES 32 /* = 128KB */
 150
 151 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 152 static int translate_empty_slots __read_mostly = 0;
 153 static int calgary_detected __read_mostly = 0;
 154
 155 static struct rio_table_hdr     *rio_table_hdr __initdata;
 156 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 157 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 158
 159 struct calgary_bus_info {
 160         void *tce_space;
 161         unsigned char translation_disabled;
 162         signed char phbid;
 163         void __iomem *bbar;
 164 };
 165
 166 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 167 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 168 static void calgary_dump_error_regs(struct iommu_table *tbl);
 169 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 170 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 171 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 172 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 173 static void get_tce_space_from_tar(void);
 174
 175 static struct cal_chipset_ops calgary_chip_ops = {
 176         .handle_quirks = calgary_handle_quirks,
 177         .tce_cache_blast = calgary_tce_cache_blast,
 178         .dump_error_regs = calgary_dump_error_regs
 179 };
 180
 181 static struct cal_chipset_ops calioc2_chip_ops = {
 182         .handle_quirks = calioc2_handle_quirks,
 183         .tce_cache_blast = calioc2_tce_cache_blast,
 184         .dump_error_regs = calioc2_dump_error_regs
 185 };
 186
 187 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 188
 189 static inline int translation_enabled(struct iommu_table *tbl)
 190 {
 191         /* only PHBs with translation enabled have an IOMMU table */
 192         return (tbl != NULL);
 193 }
 194
 195 static void iommu_range_reserve(struct iommu_table *tbl,
 196         unsigned long start_addr, unsigned int npages)
 197 {
 198         unsigned long index;
 199         unsigned long end;
 200         unsigned long flags;
 201
 202         index = start_addr >> PAGE_SHIFT;
 203
 204         /* bail out if we're asked to reserve a region we don't cover */
 205         if (index >= tbl->it_size)
 206                 return;
 207
 208         end = index + npages;
 209         if (end > tbl->it_size) /* don't go off the table */
 210                 end = tbl->it_size;
 211
 212         spin_lock_irqsave(&tbl->it_lock, flags);
 213
 214         iommu_area_reserve(tbl->it_map, index, npages);
 215
 216         spin_unlock_irqrestore(&tbl->it_lock, flags);
 217 }
 218
 219 static unsigned long iommu_range_alloc(struct device *dev,
 220                                        struct iommu_table *tbl,
 221                                        unsigned int npages)
 222 {
 223         unsigned long flags;
 224         unsigned long offset;
 225         unsigned long boundary_size;
 226
 227         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 228                               PAGE_SIZE) >> PAGE_SHIFT;
 229
 230         BUG_ON(npages == 0);
 231
 232         spin_lock_irqsave(&tbl->it_lock, flags);
 233
 234         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 235                                   npages, 0, boundary_size, 0);
 236         if (offset == ~0UL) {
 237                 tbl->chip_ops->tce_cache_blast(tbl);
 238
 239                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 240                                           npages, 0, boundary_size, 0);
 241                 if (offset == ~0UL) {
 242                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 243                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 244                         if (panic_on_overflow)
 245                                 panic("Calgary: fix the allocator.\n");
 246                         else
 247                                 return bad_dma_address;
 248                 }
 249         }
 250
 251         tbl->it_hint = offset + npages;
 252         BUG_ON(tbl->it_hint > tbl->it_size);
 253
 254         spin_unlock_irqrestore(&tbl->it_lock, flags);
 255
 256         return offset;
 257 }
 258
 259 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 260                               void *vaddr, unsigned int npages, int direction)
 261 {
 262         unsigned long entry;
 263         dma_addr_t ret = bad_dma_address;
 264
 265         entry = iommu_range_alloc(dev, tbl, npages);
 266
 267         if (unlikely(entry == bad_dma_address))
 268                 goto error;
 269
 270         /* set the return dma address */
 271         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 272
 273         /* put the TCEs in the HW table */
 274         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 275                   direction);
 276
 277         return ret;
 278
 279 error:
 280         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 281                "iommu %p\n", npages, tbl);
 282         return bad_dma_address;
 283 }
 284
 285 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 286         unsigned int npages)
 287 {
 288         unsigned long entry;
 289         unsigned long badend;
 290         unsigned long flags;
 291
 292         /* were we called with bad_dma_address? */
 293         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 294         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 295                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 296                        "address 0x%Lx\n", dma_addr);
 297                 return;
 298         }
 299
 300         entry = dma_addr >> PAGE_SHIFT;
 301
 302         BUG_ON(entry + npages > tbl->it_size);
 303
 304         tce_free(tbl, entry, npages);
 305
 306         spin_lock_irqsave(&tbl->it_lock, flags);
 307
 308         iommu_area_free(tbl->it_map, entry, npages);
 309
 310         spin_unlock_irqrestore(&tbl->it_lock, flags);
 311 }
 312
 313 static inline struct iommu_table *find_iommu_table(struct device *dev)
 314 {
 315         struct pci_dev *pdev;
 316         struct pci_bus *pbus;
 317         struct iommu_table *tbl;
 318
 319         pdev = to_pci_dev(dev);
 320
 321         /* search up the device tree for an iommu */
 322         pbus = pdev->bus;
 323         do {
 324                 tbl = pci_iommu(pbus);
 325                 if (tbl && tbl->it_busno == pbus->number)
 326                         break;
 327                 tbl = NULL;
 328                 pbus = pbus->parent;
 329         } while (pbus);
 330
 331         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 332
 333         return tbl;
 334 }
 335
 336 static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 337                              int nelems,enum dma_data_direction dir,
 338                              struct dma_attrs *attrs)
 339 {
 340         struct iommu_table *tbl = find_iommu_table(dev);
 341         struct scatterlist *s;
 342         int i;
 343
 344         if (!translation_enabled(tbl))
 345                 return;
 346
 347         for_each_sg(sglist, s, nelems, i) {
 348                 unsigned int npages;
 349                 dma_addr_t dma = s->dma_address;
 350                 unsigned int dmalen = s->dma_length;
 351
 352                 if (dmalen == 0)
 353                         break;
 354
 355                 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
 356                 iommu_free(tbl, dma, npages);
 357         }
 358 }
 359
 360 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 361                           int nelems, enum dma_data_direction dir,
 362                           struct dma_attrs *attrs)
 363 {
 364         struct iommu_table *tbl = find_iommu_table(dev);
 365         struct scatterlist *s;
 366         unsigned long vaddr;
 367         unsigned int npages;
 368         unsigned long entry;
 369         int i;
 370
 371         for_each_sg(sg, s, nelems, i) {
 372                 BUG_ON(!sg_page(s));
 373
 374                 vaddr = (unsigned long) sg_virt(s);
 375                 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
 376
 377                 entry = iommu_range_alloc(dev, tbl, npages);
 378                 if (entry == bad_dma_address) {
 379                         /* makes sure unmap knows to stop */
 380                         s->dma_length = 0;
 381                         goto error;
 382                 }
 383
 384                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 385
 386                 /* insert into HW table */
 387                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
 388
 389                 s->dma_length = s->length;
 390         }
 391
 392         return nelems;
 393 error:
 394         calgary_unmap_sg(dev, sg, nelems, dir, NULL);
 395         for_each_sg(sg, s, nelems, i) {
 396                 sg->dma_address = bad_dma_address;
 397                 sg->dma_length = 0;
 398         }
 399         return 0;
 400 }
 401
 402 static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
 403                                    unsigned long offset, size_t size,
 404                                    enum dma_data_direction dir,
 405                                    struct dma_attrs *attrs)
 406 {
 407         void *vaddr = page_address(page) + offset;
 408         unsigned long uaddr;
 409         unsigned int npages;
 410         struct iommu_table *tbl = find_iommu_table(dev);
 411
 412         uaddr = (unsigned long)vaddr;
 413         npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
 414
 415         return iommu_alloc(dev, tbl, vaddr, npages, dir);
 416 }
 417
 418 static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
 419                                size_t size, enum dma_data_direction dir,
 420                                struct dma_attrs *attrs)
 421 {
 422         struct iommu_table *tbl = find_iommu_table(dev);
 423         unsigned int npages;
 424
 425         npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
 426         iommu_free(tbl, dma_addr, npages);
 427 }
 428
 429 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 430         dma_addr_t *dma_handle, gfp_t flag)
 431 {
 432         void *ret = NULL;
 433         dma_addr_t mapping;
 434         unsigned int npages, order;
 435         struct iommu_table *tbl = find_iommu_table(dev);
 436
 437         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 438         npages = size >> PAGE_SHIFT;
 439         order = get_order(size);
 440
 441         flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
 442
 443         /* alloc enough pages (and possibly more) */
 444         ret = (void *)__get_free_pages(flag, order);
 445         if (!ret)
 446                 goto error;
 447         memset(ret, 0, size);
 448
 449         /* set up tces to cover the allocated range */
 450         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 451         if (mapping == bad_dma_address)
 452                 goto free;
 453         *dma_handle = mapping;
 454         return ret;
 455 free:
 456         free_pages((unsigned long)ret, get_order(size));
 457         ret = NULL;
 458 error:
 459         return ret;
 460 }
 461
 462 static void calgary_free_coherent(struct device *dev, size_t size,
 463                                   void *vaddr, dma_addr_t dma_handle)
 464 {
 465         unsigned int npages;
 466         struct iommu_table *tbl = find_iommu_table(dev);
 467
 468         size = PAGE_ALIGN(size);
 469         npages = size >> PAGE_SHIFT;
 470
 471         iommu_free(tbl, dma_handle, npages);
 472         free_pages((unsigned long)vaddr, get_order(size));
 473 }
 474
 475 static struct dma_map_ops calgary_dma_ops = {
 476         .alloc_coherent = calgary_alloc_coherent,
 477         .free_coherent = calgary_free_coherent,
 478         .map_sg = calgary_map_sg,
 479         .unmap_sg = calgary_unmap_sg,
 480         .map_page = calgary_map_page,
 481         .unmap_page = calgary_unmap_page,
 482 };
 483
 484 static inline void __iomem * busno_to_bbar(unsigned char num)
 485 {
 486         return bus_info[num].bbar;
 487 }
 488
 489 static inline int busno_to_phbid(unsigned char num)
 490 {
 491         return bus_info[num].phbid;
 492 }
 493
 494 static inline unsigned long split_queue_offset(unsigned char num)
 495 {
 496         size_t idx = busno_to_phbid(num);
 497
 498         return split_queue_offsets[idx];
 499 }
 500
 501 static inline unsigned long tar_offset(unsigned char num)
 502 {
 503         size_t idx = busno_to_phbid(num);
 504
 505         return tar_offsets[idx];
 506 }
 507
 508 static inline unsigned long phb_offset(unsigned char num)
 509 {
 510         size_t idx = busno_to_phbid(num);
 511
 512         return phb_offsets[idx];
 513 }
 514
 515 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 516 {
 517         unsigned long target = ((unsigned long)bar) | offset;
 518         return (void __iomem*)target;
 519 }
 520
 521 static inline int is_calioc2(unsigned short device)
 522 {
 523         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 524 }
 525
 526 static inline int is_calgary(unsigned short device)
 527 {
 528         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 529 }
 530
 531 static inline int is_cal_pci_dev(unsigned short device)
 532 {
 533         return (is_calgary(device) || is_calioc2(device));
 534 }
 535
 536 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 537 {
 538         u64 val;
 539         u32 aer;
 540         int i = 0;
 541         void __iomem *bbar = tbl->bbar;
 542         void __iomem *target;
 543
 544         /* disable arbitration on the bus */
 545         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 546         aer = readl(target);
 547         writel(0, target);
 548
 549         /* read plssr to ensure it got there */
 550         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 551         val = readl(target);
 552
 553         /* poll split queues until all DMA activity is done */
 554         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 555         do {
 556                 val = readq(target);
 557                 i++;
 558         } while ((val & 0xff) != 0xff && i < 100);
 559         if (i == 100)
 560                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 561                        "continuing anyway\n");
 562
 563         /* invalidate TCE cache */
 564         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 565         writeq(tbl->tar_val, target);
 566
 567         /* enable arbitration */
 568         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 569         writel(aer, target);
 570         (void)readl(target); /* flush */
 571 }
 572
 573 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 574 {
 575         void __iomem *bbar = tbl->bbar;
 576         void __iomem *target;
 577         u64 val64;
 578         u32 val;
 579         int i = 0;
 580         int count = 1;
 581         unsigned char bus = tbl->it_busno;
 582
 583 begin:
 584         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 585                "sequence - count %d\n", bus, count);
 586
 587         /* 1. using the Page Migration Control reg set SoftStop */
 588         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 589         val = be32_to_cpu(readl(target));
 590         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 591         val |= PMR_SOFTSTOP;
 592         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 593         writel(cpu_to_be32(val), target);
 594
 595         /* 2. poll split queues until all DMA activity is done */
 596         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 597         target = calgary_reg(bbar, split_queue_offset(bus));
 598         do {
 599                 val64 = readq(target);
 600                 i++;
 601         } while ((val64 & 0xff) != 0xff && i < 100);
 602         if (i == 100)
 603                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 604                        "continuing anyway\n");
 605
 606         /* 3. poll Page Migration DEBUG for SoftStopFault */
 607         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 608         val = be32_to_cpu(readl(target));
 609         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 610
 611         /* 4. if SoftStopFault - goto (1) */
 612         if (val & PMR_SOFTSTOPFAULT) {
 613                 if (++count < 100)
 614                         goto begin;
 615                 else {
 616                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 617                                "aborting TCE cache flush sequence!\n");
 618                         return; /* pray for the best */
 619                 }
 620         }
 621
 622         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 623         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 624         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 625         val = be32_to_cpu(readl(target));
 626         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 627         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 628         val = be32_to_cpu(readl(target));
 629         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 630
 631         /* 6. invalidate TCE cache */
 632         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 633         target = calgary_reg(bbar, tar_offset(bus));
 634         writeq(tbl->tar_val, target);
 635
 636         /* 7. Re-read PMCR */
 637         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 638         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 639         val = be32_to_cpu(readl(target));
 640         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 641
 642         /* 8. Remove HardStop */
 643         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 644         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 645         val = 0;
 646         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 647         writel(cpu_to_be32(val), target);
 648         val = be32_to_cpu(readl(target));
 649         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 650 }
 651
 652 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 653         u64 limit)
 654 {
 655         unsigned int numpages;
 656
 657         limit = limit | 0xfffff;
 658         limit++;
 659
 660         numpages = ((limit - start) >> PAGE_SHIFT);
 661         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 662 }
 663
 664 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 665 {
 666         void __iomem *target;
 667         u64 low, high, sizelow;
 668         u64 start, limit;
 669         struct iommu_table *tbl = pci_iommu(dev->bus);
 670         unsigned char busnum = dev->bus->number;
 671         void __iomem *bbar = tbl->bbar;
 672
 673         /* peripheral MEM_1 region */
 674         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 675         low = be32_to_cpu(readl(target));
 676         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 677         high = be32_to_cpu(readl(target));
 678         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 679         sizelow = be32_to_cpu(readl(target));
 680
 681         start = (high << 32) | low;
 682         limit = sizelow;
 683
 684         calgary_reserve_mem_region(dev, start, limit);
 685 }
 686
 687 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 688 {
 689         void __iomem *target;
 690         u32 val32;
 691         u64 low, high, sizelow, sizehigh;
 692         u64 start, limit;
 693         struct iommu_table *tbl = pci_iommu(dev->bus);
 694         unsigned char busnum = dev->bus->number;
 695         void __iomem *bbar = tbl->bbar;
 696
 697         /* is it enabled? */
 698         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 699         val32 = be32_to_cpu(readl(target));
 700         if (!(val32 & PHB_MEM2_ENABLE))
 701                 return;
 702
 703         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 704         low = be32_to_cpu(readl(target));
 705         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 706         high = be32_to_cpu(readl(target));
 707         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 708         sizelow = be32_to_cpu(readl(target));
 709         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 710         sizehigh = be32_to_cpu(readl(target));
 711
 712         start = (high << 32) | low;
 713         limit = (sizehigh << 32) | sizelow;
 714
 715         calgary_reserve_mem_region(dev, start, limit);
 716 }
 717
 718 /*
 719  * some regions of the IO address space do not get translated, so we
 720  * must not give devices IO addresses in those regions. The regions
 721  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 722  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 723  * later.
 724  */
 725 static void __init calgary_reserve_regions(struct pci_dev *dev)
 726 {
 727         unsigned int npages;
 728         u64 start;
 729         struct iommu_table *tbl = pci_iommu(dev->bus);
 730
 731         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 732         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 733
 734         /* avoid the BIOS/VGA first 640KB-1MB region */
 735         /* for CalIOC2 - avoid the entire first MB */
 736         if (is_calgary(dev->device)) {
 737                 start = (640 * 1024);
 738                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 739         } else { /* calioc2 */
 740                 start = 0;
 741                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 742         }
 743         iommu_range_reserve(tbl, start, npages);
 744
 745         /* reserve the two PCI peripheral memory regions in IO space */
 746         calgary_reserve_peripheral_mem_1(dev);
 747         calgary_reserve_peripheral_mem_2(dev);
 748 }
 749
 750 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 751 {
 752         u64 val64;
 753         u64 table_phys;
 754         void __iomem *target;
 755         int ret;
 756         struct iommu_table *tbl;
 757
 758         /* build TCE tables for each PHB */
 759         ret = build_tce_table(dev, bbar);
 760         if (ret)
 761                 return ret;
 762
 763         tbl = pci_iommu(dev->bus);
 764         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 765
 766         if (is_kdump_kernel())
 767                 calgary_init_bitmap_from_tce_table(tbl);
 768         else
 769                 tce_free(tbl, 0, tbl->it_size);
 770
 771         if (is_calgary(dev->device))
 772                 tbl->chip_ops = &calgary_chip_ops;
 773         else if (is_calioc2(dev->device))
 774                 tbl->chip_ops = &calioc2_chip_ops;
 775         else
 776                 BUG();
 777
 778         calgary_reserve_regions(dev);
 779
 780         /* set TARs for each PHB */
 781         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 782         val64 = be64_to_cpu(readq(target));
 783
 784         /* zero out all TAR bits under sw control */
 785         val64 &= ~TAR_SW_BITS;
 786         table_phys = (u64)__pa(tbl->it_base);
 787
 788         val64 |= table_phys;
 789
 790         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 791         val64 |= (u64) specified_table_size;
 792
 793         tbl->tar_val = cpu_to_be64(val64);
 794
 795         writeq(tbl->tar_val, target);
 796         readq(target); /* flush */
 797
 798         return 0;
 799 }
 800
 801 static void __init calgary_free_bus(struct pci_dev *dev)
 802 {
 803         u64 val64;
 804         struct iommu_table *tbl = pci_iommu(dev->bus);
 805         void __iomem *target;
 806         unsigned int bitmapsz;
 807
 808         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 809         val64 = be64_to_cpu(readq(target));
 810         val64 &= ~TAR_SW_BITS;
 811         writeq(cpu_to_be64(val64), target);
 812         readq(target); /* flush */
 813
 814         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 815         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 816         tbl->it_map = NULL;
 817
 818         kfree(tbl);
 819
 820         set_pci_iommu(dev->bus, NULL);
 821
 822         /* Can't free bootmem allocated memory after system is up :-( */
 823         bus_info[dev->bus->number].tce_space = NULL;
 824 }
 825
 826 static void calgary_dump_error_regs(struct iommu_table *tbl)
 827 {
 828         void __iomem *bbar = tbl->bbar;
 829         void __iomem *target;
 830         u32 csr, plssr;
 831
 832         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 833         csr = be32_to_cpu(readl(target));
 834
 835         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 836         plssr = be32_to_cpu(readl(target));
 837
 838         /* If no error, the agent ID in the CSR is not valid */
 839         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 840                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 841 }
 842
 843 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 844 {
 845         void __iomem *bbar = tbl->bbar;
 846         u32 csr, csmr, plssr, mck, rcstat;
 847         void __iomem *target;
 848         unsigned long phboff = phb_offset(tbl->it_busno);
 849         unsigned long erroff;
 850         u32 errregs[7];
 851         int i;
 852
 853         /* dump CSR */
 854         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 855         csr = be32_to_cpu(readl(target));
 856         /* dump PLSSR */
 857         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 858         plssr = be32_to_cpu(readl(target));
 859         /* dump CSMR */
 860         target = calgary_reg(bbar, phboff | 0x290);
 861         csmr = be32_to_cpu(readl(target));
 862         /* dump mck */
 863         target = calgary_reg(bbar, phboff | 0x800);
 864         mck = be32_to_cpu(readl(target));
 865
 866         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 867                tbl->it_busno);
 868
 869         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 870                csr, plssr, csmr, mck);
 871
 872         /* dump rest of error regs */
 873         printk(KERN_EMERG "Calgary: ");
 874         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 875                 /* err regs are at 0x810 - 0x870 */
 876                 erroff = (0x810 + (i * 0x10));
 877                 target = calgary_reg(bbar, phboff | erroff);
 878                 errregs[i] = be32_to_cpu(readl(target));
 879                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 880         }
 881         printk("\n");
 882
 883         /* root complex status */
 884         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 885         rcstat = be32_to_cpu(readl(target));
 886         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 887                PHB_ROOT_COMPLEX_STATUS);
 888 }
 889
 890 static void calgary_watchdog(unsigned long data)
 891 {
 892         struct pci_dev *dev = (struct pci_dev *)data;
 893         struct iommu_table *tbl = pci_iommu(dev->bus);
 894         void __iomem *bbar = tbl->bbar;
 895         u32 val32;
 896         void __iomem *target;
 897
 898         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 899         val32 = be32_to_cpu(readl(target));
 900
 901         /* If no error, the agent ID in the CSR is not valid */
 902         if (val32 & CSR_AGENT_MASK) {
 903                 tbl->chip_ops->dump_error_regs(tbl);
 904
 905                 /* reset error */
 906                 writel(0, target);
 907
 908                 /* Disable bus that caused the error */
 909                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 910                                      PHB_CONFIG_RW_OFFSET);
 911                 val32 = be32_to_cpu(readl(target));
 912                 val32 |= PHB_SLOT_DISABLE;
 913                 writel(cpu_to_be32(val32), target);
 914                 readl(target); /* flush */
 915         } else {
 916                 /* Reset the timer */
 917                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 918         }
 919 }
 920
 921 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 922         unsigned char busnum, unsigned long timeout)
 923 {
 924         u64 val64;
 925         void __iomem *target;
 926         unsigned int phb_shift = ~0; /* silence gcc */
 927         u64 mask;
 928
 929         switch (busno_to_phbid(busnum)) {
 930         case 0: phb_shift = (63 - 19);
 931                 break;
 932         case 1: phb_shift = (63 - 23);
 933                 break;
 934         case 2: phb_shift = (63 - 27);
 935                 break;
 936         case 3: phb_shift = (63 - 35);
 937                 break;
 938         default:
 939                 BUG_ON(busno_to_phbid(busnum));
 940         }
 941
 942         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 943         val64 = be64_to_cpu(readq(target));
 944
 945         /* zero out this PHB's timer bits */
 946         mask = ~(0xFUL << phb_shift);
 947         val64 &= mask;
 948         val64 |= (timeout << phb_shift);
 949         writeq(cpu_to_be64(val64), target);
 950         readq(target); /* flush */
 951 }
 952
 953 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 954 {
 955         unsigned char busnum = dev->bus->number;
 956         void __iomem *bbar = tbl->bbar;
 957         void __iomem *target;
 958         u32 val;
 959
 960         /*
 961          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
 962          */
 963         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
 964         val = cpu_to_be32(readl(target));
 965         val |= 0x00800000;
 966         writel(cpu_to_be32(val), target);
 967 }
 968
 969 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 970 {
 971         unsigned char busnum = dev->bus->number;
 972
 973         /*
 974          * Give split completion a longer timeout on bus 1 for aic94xx
 975          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
 976          */
 977         if (is_calgary(dev->device) && (busnum == 1))
 978                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
 979                                                      CCR_2SEC_TIMEOUT);
 980 }
 981
 982 static void __init calgary_enable_translation(struct pci_dev *dev)
 983 {
 984         u32 val32;
 985         unsigned char busnum;
 986         void __iomem *target;
 987         void __iomem *bbar;
 988         struct iommu_table *tbl;
 989
 990         busnum = dev->bus->number;
 991         tbl = pci_iommu(dev->bus);
 992         bbar = tbl->bbar;
 993
 994         /* enable TCE in PHB Config Register */
 995         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 996         val32 = be32_to_cpu(readl(target));
 997         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 998
 999         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1000                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1001                "Calgary" : "CalIOC2", busnum);
1002         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1003                "bus.\n");
1004
1005         writel(cpu_to_be32(val32), target);
1006         readl(target); /* flush */
1007
1008         init_timer(&tbl->watchdog_timer);
1009         tbl->watchdog_timer.function = &calgary_watchdog;
1010         tbl->watchdog_timer.data = (unsigned long)dev;
1011         mod_timer(&tbl->watchdog_timer, jiffies);
1012 }
1013
1014 static void __init calgary_disable_translation(struct pci_dev *dev)
1015 {
1016         u32 val32;
1017         unsigned char busnum;
1018         void __iomem *target;
1019         void __iomem *bbar;
1020         struct iommu_table *tbl;
1021
1022         busnum = dev->bus->number;
1023         tbl = pci_iommu(dev->bus);
1024         bbar = tbl->bbar;
1025
1026         /* disable TCE in PHB Config Register */
1027         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1028         val32 = be32_to_cpu(readl(target));
1029         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1030
1031         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1032         writel(cpu_to_be32(val32), target);
1033         readl(target); /* flush */
1034
1035         del_timer_sync(&tbl->watchdog_timer);
1036 }
1037
1038 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1039 {
1040         pci_dev_get(dev);
1041         set_pci_iommu(dev->bus, NULL);
1042
1043         /* is the device behind a bridge? */
1044         if (dev->bus->parent)
1045                 dev->bus->parent->self = dev;
1046         else
1047                 dev->bus->self = dev;
1048 }
1049
1050 static int __init calgary_init_one(struct pci_dev *dev)
1051 {
1052         void __iomem *bbar;
1053         struct iommu_table *tbl;
1054         int ret;
1055
1056         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1057
1058         bbar = busno_to_bbar(dev->bus->number);
1059         ret = calgary_setup_tar(dev, bbar);
1060         if (ret)
1061                 goto done;
1062
1063         pci_dev_get(dev);
1064
1065         if (dev->bus->parent) {
1066                 if (dev->bus->parent->self)
1067                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1068                                "bus->parent->self!\n", dev);
1069                 dev->bus->parent->self = dev;
1070         } else
1071                 dev->bus->self = dev;
1072
1073         tbl = pci_iommu(dev->bus);
1074         tbl->chip_ops->handle_quirks(tbl, dev);
1075
1076         calgary_enable_translation(dev);
1077
1078         return 0;
1079
1080 done:
1081         return ret;
1082 }
1083
1084 static int __init calgary_locate_bbars(void)
1085 {
1086         int ret;
1087         int rioidx, phb, bus;
1088         void __iomem *bbar;
1089         void __iomem *target;
1090         unsigned long offset;
1091         u8 start_bus, end_bus;
1092         u32 val;
1093
1094         ret = -ENODATA;
1095         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1096                 struct rio_detail *rio = rio_devs[rioidx];
1097
1098                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1099                         continue;
1100
1101                 /* map entire 1MB of Calgary config space */
1102                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1103                 if (!bbar)
1104                         goto error;
1105
1106                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1107                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1108                         target = calgary_reg(bbar, offset);
1109
1110                         val = be32_to_cpu(readl(target));
1111
1112                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1113                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1114
1115                         if (end_bus) {
1116                                 for (bus = start_bus; bus <= end_bus; bus++) {
1117                                         bus_info[bus].bbar = bbar;
1118                                         bus_info[bus].phbid = phb;
1119                                 }
1120                         } else {
1121                                 bus_info[start_bus].bbar = bbar;
1122                                 bus_info[start_bus].phbid = phb;
1123                         }
1124                 }
1125         }
1126
1127         return 0;
1128
1129 error:
1130         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1131         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1132                 if (bus_info[bus].bbar)
1133                         iounmap(bus_info[bus].bbar);
1134
1135         return ret;
1136 }
1137
1138 static int __init calgary_init(void)
1139 {
1140         int ret;
1141         struct pci_dev *dev = NULL;
1142         struct calgary_bus_info *info;
1143
1144         ret = calgary_locate_bbars();
1145         if (ret)
1146                 return ret;
1147
1148         /* Purely for kdump kernel case */
1149         if (is_kdump_kernel())
1150                 get_tce_space_from_tar();
1151
1152         do {
1153                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1154                 if (!dev)
1155                         break;
1156                 if (!is_cal_pci_dev(dev->device))
1157                         continue;
1158
1159                 info = &bus_info[dev->bus->number];
1160                 if (info->translation_disabled) {
1161                         calgary_init_one_nontraslated(dev);
1162                         continue;
1163                 }
1164
1165                 if (!info->tce_space && !translate_empty_slots)
1166                         continue;
1167
1168                 ret = calgary_init_one(dev);
1169                 if (ret)
1170                         goto error;
1171         } while (1);
1172
1173         dev = NULL;
1174         for_each_pci_dev(dev) {
1175                 struct iommu_table *tbl;
1176
1177                 tbl = find_iommu_table(&dev->dev);
1178
1179                 if (translation_enabled(tbl))
1180                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1181         }
1182
1183         return ret;
1184
1185 error:
1186         do {
1187                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1188                 if (!dev)
1189                         break;
1190                 if (!is_cal_pci_dev(dev->device))
1191                         continue;
1192
1193                 info = &bus_info[dev->bus->number];
1194                 if (info->translation_disabled) {
1195                         pci_dev_put(dev);
1196                         continue;
1197                 }
1198                 if (!info->tce_space && !translate_empty_slots)
1199                         continue;
1200
1201                 calgary_disable_translation(dev);
1202                 calgary_free_bus(dev);
1203                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1204                 dev->dev.archdata.dma_ops = NULL;
1205         } while (1);
1206
1207         return ret;
1208 }
1209
1210 static inline int __init determine_tce_table_size(u64 ram)
1211 {
1212         int ret;
1213
1214         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1215                 return specified_table_size;
1216
1217         /*
1218          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1219          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1220          * larger table size has twice as many entries, so shift the
1221          * max ram address by 13 to divide by 8K and then look at the
1222          * order of the result to choose between 0-7.
1223          */
1224         ret = get_order(ram >> 13);
1225         if (ret > TCE_TABLE_SIZE_8M)
1226                 ret = TCE_TABLE_SIZE_8M;
1227
1228         return ret;
1229 }
1230
1231 static int __init build_detail_arrays(void)
1232 {
1233         unsigned long ptr;
1234         unsigned numnodes, i;
1235         int scal_detail_size, rio_detail_size;
1236
1237         numnodes = rio_table_hdr->num_scal_dev;
1238         if (numnodes > MAX_NUMNODES){
1239                 printk(KERN_WARNING
1240                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1241                         "but system has %d nodes.\n",
1242                         MAX_NUMNODES, numnodes);
1243                 return -ENODEV;
1244         }
1245
1246         switch (rio_table_hdr->version){
1247         case 2:
1248                 scal_detail_size = 11;
1249                 rio_detail_size = 13;
1250                 break;
1251         case 3:
1252                 scal_detail_size = 12;
1253                 rio_detail_size = 15;
1254                 break;
1255         default:
1256                 printk(KERN_WARNING
1257                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1258                        rio_table_hdr->version);
1259                 return -EPROTO;
1260         }
1261
1262         ptr = ((unsigned long)rio_table_hdr) + 3;
1263         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1264                 scal_devs[i] = (struct scal_detail *)ptr;
1265
1266         for (i = 0; i < rio_table_hdr->num_rio_dev;
1267                     i++, ptr += rio_detail_size)
1268                 rio_devs[i] = (struct rio_detail *)ptr;
1269
1270         return 0;
1271 }
1272
1273 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1274 {
1275         int dev;
1276         u32 val;
1277
1278         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1279                 /*
1280                  * FIXME: properly scan for devices accross the
1281                  * PCI-to-PCI bridge on every CalIOC2 port.
1282                  */
1283                 return 1;
1284         }
1285
1286         for (dev = 1; dev < 8; dev++) {
1287                 val = read_pci_config(bus, dev, 0, 0);
1288                 if (val != 0xffffffff)
1289                         break;
1290         }
1291         return (val != 0xffffffff);
1292 }
1293
1294 /*
1295  * calgary_init_bitmap_from_tce_table():
1296  * Funtion for kdump case. In the second/kdump kernel initialize
1297  * the bitmap based on the tce table entries obtained from first kernel
1298  */
1299 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1300 {
1301         u64 *tp;
1302         unsigned int index;
1303         tp = ((u64 *)tbl->it_base);
1304         for (index = 0 ; index < tbl->it_size; index++) {
1305                 if (*tp != 0x0)
1306                         set_bit(index, tbl->it_map);
1307                 tp++;
1308         }
1309 }
1310
1311 /*
1312  * get_tce_space_from_tar():
1313  * Function for kdump case. Get the tce tables from first kernel
1314  * by reading the contents of the base adress register of calgary iommu
1315  */
1316 static void __init get_tce_space_from_tar(void)
1317 {
1318         int bus;
1319         void __iomem *target;
1320         unsigned long tce_space;
1321
1322         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1323                 struct calgary_bus_info *info = &bus_info[bus];
1324                 unsigned short pci_device;
1325                 u32 val;
1326
1327                 val = read_pci_config(bus, 0, 0, 0);
1328                 pci_device = (val & 0xFFFF0000) >> 16;
1329
1330                 if (!is_cal_pci_dev(pci_device))
1331                         continue;
1332                 if (info->translation_disabled)
1333                         continue;
1334
1335                 if (calgary_bus_has_devices(bus, pci_device) ||
1336                                                 translate_empty_slots) {
1337                         target = calgary_reg(bus_info[bus].bbar,
1338                                                 tar_offset(bus));
1339                         tce_space = be64_to_cpu(readq(target));
1340                         tce_space = tce_space & TAR_SW_BITS;
1341
1342                         tce_space = tce_space & (~specified_table_size);
1343                         info->tce_space = (u64 *)__va(tce_space);
1344                 }
1345         }
1346         return;
1347 }
1348
1349 void __init detect_calgary(void)
1350 {
1351         int bus;
1352         void *tbl;
1353         int calgary_found = 0;
1354         unsigned long ptr;
1355         unsigned int offset, prev_offset;
1356         int ret;
1357
1358         /*
1359          * if the user specified iommu=off or iommu=soft or we found
1360          * another HW IOMMU already, bail out.
1361          */
1362         if (swiotlb || no_iommu || iommu_detected)
1363                 return;
1364
1365         if (!use_calgary)
1366                 return;
1367
1368         if (!early_pci_allowed())
1369                 return;
1370
1371         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1372
1373         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1374
1375         rio_table_hdr = NULL;
1376         prev_offset = 0;
1377         offset = 0x180;
1378         /*
1379          * The next offset is stored in the 1st word.
1380          * Only parse up until the offset increases:
1381          */
1382         while (offset > prev_offset) {
1383                 /* The block id is stored in the 2nd word */
1384                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1385                         /* set the pointer past the offset & block id */
1386                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1387                         break;
1388                 }
1389                 prev_offset = offset;
1390                 offset = *((unsigned short *)(ptr + offset));
1391         }
1392         if (!rio_table_hdr) {
1393                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1394                        "in EBDA - bailing!\n");
1395                 return;
1396         }
1397
1398         ret = build_detail_arrays();
1399         if (ret) {
1400                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1401                 return;
1402         }
1403
1404         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1405                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1406
1407         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1408                 struct calgary_bus_info *info = &bus_info[bus];
1409                 unsigned short pci_device;
1410                 u32 val;
1411
1412                 val = read_pci_config(bus, 0, 0, 0);
1413                 pci_device = (val & 0xFFFF0000) >> 16;
1414
1415                 if (!is_cal_pci_dev(pci_device))
1416                         continue;
1417
1418                 if (info->translation_disabled)
1419                         continue;
1420
1421                 if (calgary_bus_has_devices(bus, pci_device) ||
1422                     translate_empty_slots) {
1423                         /*
1424                          * If it is kdump kernel, find and use tce tables
1425                          * from first kernel, else allocate tce tables here
1426                          */
1427                         if (!is_kdump_kernel()) {
1428                                 tbl = alloc_tce_table();
1429                                 if (!tbl)
1430                                         goto cleanup;
1431                                 info->tce_space = tbl;
1432                         }
1433                         calgary_found = 1;
1434                 }
1435         }
1436
1437         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1438                calgary_found ? "found" : "not found");
1439
1440         if (calgary_found) {
1441                 iommu_detected = 1;
1442                 calgary_detected = 1;
1443                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1444                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1445                        specified_table_size);
1446
1447                 /* swiotlb for devices that aren't behind the Calgary. */
1448                 if (max_pfn > MAX_DMA32_PFN)
1449                         swiotlb = 1;
1450         }
1451         return;
1452
1453 cleanup:
1454         for (--bus; bus >= 0; --bus) {
1455                 struct calgary_bus_info *info = &bus_info[bus];
1456
1457                 if (info->tce_space)
1458                         free_tce_table(info->tce_space);
1459         }
1460 }
1461
1462 int __init calgary_iommu_init(void)
1463 {
1464         int ret;
1465
1466         if (no_iommu || (swiotlb && !calgary_detected))
1467                 return -ENODEV;
1468
1469         if (!calgary_detected)
1470                 return -ENODEV;
1471
1472         /* ok, we're trying to use Calgary - let's roll */
1473         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1474
1475         ret = calgary_init();
1476         if (ret) {
1477                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1478                        "falling back to no_iommu\n", ret);
1479                 return ret;
1480         }
1481
1482         force_iommu = 1;
1483         bad_dma_address = 0x0;
1484         /* dma_ops is set to swiotlb or nommu */
1485         if (!dma_ops)
1486                 dma_ops = &nommu_dma_ops;
1487
1488         return 0;
1489 }
1490
1491 static int __init calgary_parse_options(char *p)
1492 {
1493         unsigned int bridge;
1494         size_t len;
1495         char* endp;
1496
1497         while (*p) {
1498                 if (!strncmp(p, "64k", 3))
1499                         specified_table_size = TCE_TABLE_SIZE_64K;
1500                 else if (!strncmp(p, "128k", 4))
1501                         specified_table_size = TCE_TABLE_SIZE_128K;
1502                 else if (!strncmp(p, "256k", 4))
1503                         specified_table_size = TCE_TABLE_SIZE_256K;
1504                 else if (!strncmp(p, "512k", 4))
1505                         specified_table_size = TCE_TABLE_SIZE_512K;
1506                 else if (!strncmp(p, "1M", 2))
1507                         specified_table_size = TCE_TABLE_SIZE_1M;
1508                 else if (!strncmp(p, "2M", 2))
1509                         specified_table_size = TCE_TABLE_SIZE_2M;
1510                 else if (!strncmp(p, "4M", 2))
1511                         specified_table_size = TCE_TABLE_SIZE_4M;
1512                 else if (!strncmp(p, "8M", 2))
1513                         specified_table_size = TCE_TABLE_SIZE_8M;
1514
1515                 len = strlen("translate_empty_slots");
1516                 if (!strncmp(p, "translate_empty_slots", len))
1517                         translate_empty_slots = 1;
1518
1519                 len = strlen("disable");
1520                 if (!strncmp(p, "disable", len)) {
1521                         p += len;
1522                         if (*p == '=')
1523                                 ++p;
1524                         if (*p == '\0')
1525                                 break;
1526                         bridge = simple_strtoul(p, &endp, 0);
1527                         if (p == endp)
1528                                 break;
1529
1530                         if (bridge < MAX_PHB_BUS_NUM) {
1531                                 printk(KERN_INFO "Calgary: disabling "
1532                                        "translation for PHB %#x\n", bridge);
1533                                 bus_info[bridge].translation_disabled = 1;
1534                         }
1535                 }
1536
1537                 p = strpbrk(p, ",");
1538                 if (!p)
1539                         break;
1540
1541                 p++; /* skip ',' */
1542         }
1543         return 1;
1544 }
1545 __setup("calgary=", calgary_parse_options);
1546
1547 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1548 {
1549         struct iommu_table *tbl;
1550         unsigned int npages;
1551         int i;
1552
1553         tbl = pci_iommu(dev->bus);
1554
1555         for (i = 0; i < 4; i++) {
1556                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1557
1558                 /* Don't give out TCEs that map MEM resources */
1559                 if (!(r->flags & IORESOURCE_MEM))
1560                         continue;
1561
1562                 /* 0-based? we reserve the whole 1st MB anyway */
1563                 if (!r->start)
1564                         continue;
1565
1566                 /* cover the whole region */
1567                 npages = (r->end - r->start) >> PAGE_SHIFT;
1568                 npages++;
1569
1570                 iommu_range_reserve(tbl, r->start, npages);
1571         }
1572 }
1573
1574 static int __init calgary_fixup_tce_spaces(void)
1575 {
1576         struct pci_dev *dev = NULL;
1577         struct calgary_bus_info *info;
1578
1579         if (no_iommu || swiotlb || !calgary_detected)
1580                 return -ENODEV;
1581
1582         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1583
1584         do {
1585                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1586                 if (!dev)
1587                         break;
1588                 if (!is_cal_pci_dev(dev->device))
1589                         continue;
1590
1591                 info = &bus_info[dev->bus->number];
1592                 if (info->translation_disabled)
1593                         continue;
1594
1595                 if (!info->tce_space)
1596                         continue;
1597
1598                 calgary_fixup_one_tce_space(dev);
1599
1600         } while (1);
1601
1602         return 0;
1603 }
1604
1605 /*
1606  * We need to be call after pcibios_assign_resources (fs_initcall level)
1607  * and before device_initcall.
1608  */
1609 rootfs_initcall(calgary_fixup_tce_spaces);