arch/x86/kernel/cpu/perf_event_intel_uncore.c

   1 #include "perf_event_intel_uncore.h"
   2
   3 static struct intel_uncore_type *empty_uncore[] = { NULL, };
   4 static struct intel_uncore_type **msr_uncores = empty_uncore;
   5 static struct intel_uncore_type **pci_uncores = empty_uncore;
   6 /* pci bus to socket mapping */
   7 static int pcibus_to_physid[256] = { [0 ... 255] = -1, };
   8
   9 static DEFINE_RAW_SPINLOCK(uncore_box_lock);
  10
  11 /* mask of cpus that collect uncore events */
  12 static cpumask_t uncore_cpu_mask;
  13
  14 /* constraint for the fixed counter */
  15 static struct event_constraint constraint_fixed =
  16         EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
  17 static struct event_constraint constraint_empty =
  18         EVENT_CONSTRAINT(0, 0, 0);
  19
  20 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
  21 DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
  22 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
  23 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
  24 DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
  25 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
  26 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
  27 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
  28 DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
  29 DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
  30 DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
  31 DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
  32 DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
  33 DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
  34 DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
  35 DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
  36 DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
  37 DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
  38 DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
  39 DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
  40 DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31");
  41
  42 static u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
  43 {
  44         u64 count;
  45
  46         rdmsrl(event->hw.event_base, count);
  47
  48         return count;
  49 }
  50
  51 /*
  52  * generic get constraint function for shared match/mask registers.
  53  */
  54 static struct event_constraint *
  55 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
  56 {
  57         struct intel_uncore_extra_reg *er;
  58         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
  59         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
  60         unsigned long flags;
  61         bool ok = false;
  62
  63         /*
  64          * reg->alloc can be set due to existing state, so for fake box we
  65          * need to ignore this, otherwise we might fail to allocate proper
  66          * fake state for this extra reg constraint.
  67          */
  68         if (reg1->idx == EXTRA_REG_NONE ||
  69             (!uncore_box_is_fake(box) && reg1->alloc))
  70                 return NULL;
  71
  72         er = &box->shared_regs[reg1->idx];
  73         raw_spin_lock_irqsave(&er->lock, flags);
  74         if (!atomic_read(&er->ref) ||
  75             (er->config1 == reg1->config && er->config2 == reg2->config)) {
  76                 atomic_inc(&er->ref);
  77                 er->config1 = reg1->config;
  78                 er->config2 = reg2->config;
  79                 ok = true;
  80         }
  81         raw_spin_unlock_irqrestore(&er->lock, flags);
  82
  83         if (ok) {
  84                 if (!uncore_box_is_fake(box))
  85                         reg1->alloc = 1;
  86                 return NULL;
  87         }
  88
  89         return &constraint_empty;
  90 }
  91
  92 static void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
  93 {
  94         struct intel_uncore_extra_reg *er;
  95         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
  96
  97         /*
  98          * Only put constraint if extra reg was actually allocated. Also
  99          * takes care of event which do not use an extra shared reg.
 100          *
 101          * Also, if this is a fake box we shouldn't touch any event state
 102          * (reg->alloc) and we don't care about leaving inconsistent box
 103          * state either since it will be thrown out.
 104          */
 105         if (uncore_box_is_fake(box) || !reg1->alloc)
 106                 return;
 107
 108         er = &box->shared_regs[reg1->idx];
 109         atomic_dec(&er->ref);
 110         reg1->alloc = 0;
 111 }
 112
 113 /* Sandy Bridge-EP uncore support */
 114 static struct intel_uncore_type snbep_uncore_cbox;
 115 static struct intel_uncore_type snbep_uncore_pcu;
 116
 117 static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
 118 {
 119         struct pci_dev *pdev = box->pci_dev;
 120         int box_ctl = uncore_pci_box_ctl(box);
 121         u32 config;
 122
 123         pci_read_config_dword(pdev, box_ctl, &config);
 124         config |= SNBEP_PMON_BOX_CTL_FRZ;
 125         pci_write_config_dword(pdev, box_ctl, config);
 126 }
 127
 128 static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
 129 {
 130         struct pci_dev *pdev = box->pci_dev;
 131         int box_ctl = uncore_pci_box_ctl(box);
 132         u32 config;
 133
 134         pci_read_config_dword(pdev, box_ctl, &config);
 135         config &= ~SNBEP_PMON_BOX_CTL_FRZ;
 136         pci_write_config_dword(pdev, box_ctl, config);
 137 }
 138
 139 static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 140 {
 141         struct pci_dev *pdev = box->pci_dev;
 142         struct hw_perf_event *hwc = &event->hw;
 143
 144         pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
 145 }
 146
 147 static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event)
 148 {
 149         struct pci_dev *pdev = box->pci_dev;
 150         struct hw_perf_event *hwc = &event->hw;
 151
 152         pci_write_config_dword(pdev, hwc->config_base, hwc->config);
 153 }
 154
 155 static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event)
 156 {
 157         struct pci_dev *pdev = box->pci_dev;
 158         struct hw_perf_event *hwc = &event->hw;
 159         u64 count;
 160
 161         pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
 162         pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
 163
 164         return count;
 165 }
 166
 167 static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
 168 {
 169         struct pci_dev *pdev = box->pci_dev;
 170
 171         pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, SNBEP_PMON_BOX_CTL_INT);
 172 }
 173
 174 static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
 175 {
 176         u64 config;
 177         unsigned msr;
 178
 179         msr = uncore_msr_box_ctl(box);
 180         if (msr) {
 181                 rdmsrl(msr, config);
 182                 config |= SNBEP_PMON_BOX_CTL_FRZ;
 183                 wrmsrl(msr, config);
 184         }
 185 }
 186
 187 static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
 188 {
 189         u64 config;
 190         unsigned msr;
 191
 192         msr = uncore_msr_box_ctl(box);
 193         if (msr) {
 194                 rdmsrl(msr, config);
 195                 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
 196                 wrmsrl(msr, config);
 197         }
 198 }
 199
 200 static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 201 {
 202         struct hw_perf_event *hwc = &event->hw;
 203         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
 204
 205         if (reg1->idx != EXTRA_REG_NONE)
 206                 wrmsrl(reg1->reg, reg1->config);
 207
 208         wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
 209 }
 210
 211 static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
 212                                         struct perf_event *event)
 213 {
 214         struct hw_perf_event *hwc = &event->hw;
 215
 216         wrmsrl(hwc->config_base, hwc->config);
 217 }
 218
 219 static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
 220 {
 221         unsigned msr = uncore_msr_box_ctl(box);
 222
 223         if (msr)
 224                 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
 225 }
 226
 227 static int snbep_uncore_hw_config(struct intel_uncore_box *box, struct perf_event *event)
 228 {
 229         struct hw_perf_event *hwc = &event->hw;
 230         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
 231
 232         if (box->pmu->type == &snbep_uncore_cbox) {
 233                 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
 234                         SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
 235                 reg1->config = event->attr.config1 &
 236                         SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK;
 237         } else {
 238                 if (box->pmu->type == &snbep_uncore_pcu) {
 239                         reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
 240                         reg1->config = event->attr.config1 & SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK;
 241                 } else {
 242                         return 0;
 243                 }
 244         }
 245         reg1->idx = 0;
 246
 247         return 0;
 248 }
 249
 250 static struct attribute *snbep_uncore_formats_attr[] = {
 251         &format_attr_event.attr,
 252         &format_attr_umask.attr,
 253         &format_attr_edge.attr,
 254         &format_attr_inv.attr,
 255         &format_attr_thresh8.attr,
 256         NULL,
 257 };
 258
 259 static struct attribute *snbep_uncore_ubox_formats_attr[] = {
 260         &format_attr_event.attr,
 261         &format_attr_umask.attr,
 262         &format_attr_edge.attr,
 263         &format_attr_inv.attr,
 264         &format_attr_thresh5.attr,
 265         NULL,
 266 };
 267
 268 static struct attribute *snbep_uncore_cbox_formats_attr[] = {
 269         &format_attr_event.attr,
 270         &format_attr_umask.attr,
 271         &format_attr_edge.attr,
 272         &format_attr_tid_en.attr,
 273         &format_attr_inv.attr,
 274         &format_attr_thresh8.attr,
 275         &format_attr_filter_tid.attr,
 276         &format_attr_filter_nid.attr,
 277         &format_attr_filter_state.attr,
 278         &format_attr_filter_opc.attr,
 279         NULL,
 280 };
 281
 282 static struct attribute *snbep_uncore_pcu_formats_attr[] = {
 283         &format_attr_event.attr,
 284         &format_attr_occ_sel.attr,
 285         &format_attr_edge.attr,
 286         &format_attr_inv.attr,
 287         &format_attr_thresh5.attr,
 288         &format_attr_occ_invert.attr,
 289         &format_attr_occ_edge.attr,
 290         &format_attr_filter_band0.attr,
 291         &format_attr_filter_band1.attr,
 292         &format_attr_filter_band2.attr,
 293         &format_attr_filter_band3.attr,
 294         NULL,
 295 };
 296
 297 static struct attribute *snbep_uncore_qpi_formats_attr[] = {
 298         &format_attr_event_ext.attr,
 299         &format_attr_umask.attr,
 300         &format_attr_edge.attr,
 301         &format_attr_inv.attr,
 302         &format_attr_thresh8.attr,
 303         NULL,
 304 };
 305
 306 static struct uncore_event_desc snbep_uncore_imc_events[] = {
 307         INTEL_UNCORE_EVENT_DESC(clockticks,      "event=0xff,umask=0x00"),
 308         INTEL_UNCORE_EVENT_DESC(cas_count_read,  "event=0x04,umask=0x03"),
 309         INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
 310         { /* end: all zeroes */ },
 311 };
 312
 313 static struct uncore_event_desc snbep_uncore_qpi_events[] = {
 314         INTEL_UNCORE_EVENT_DESC(clockticks,       "event=0x14"),
 315         INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"),
 316         INTEL_UNCORE_EVENT_DESC(drs_data,         "event=0x02,umask=0x08"),
 317         INTEL_UNCORE_EVENT_DESC(ncb_data,         "event=0x03,umask=0x04"),
 318         { /* end: all zeroes */ },
 319 };
 320
 321 static struct attribute_group snbep_uncore_format_group = {
 322         .name = "format",
 323         .attrs = snbep_uncore_formats_attr,
 324 };
 325
 326 static struct attribute_group snbep_uncore_ubox_format_group = {
 327         .name = "format",
 328         .attrs = snbep_uncore_ubox_formats_attr,
 329 };
 330
 331 static struct attribute_group snbep_uncore_cbox_format_group = {
 332         .name = "format",
 333         .attrs = snbep_uncore_cbox_formats_attr,
 334 };
 335
 336 static struct attribute_group snbep_uncore_pcu_format_group = {
 337         .name = "format",
 338         .attrs = snbep_uncore_pcu_formats_attr,
 339 };
 340
 341 static struct attribute_group snbep_uncore_qpi_format_group = {
 342         .name = "format",
 343         .attrs = snbep_uncore_qpi_formats_attr,
 344 };
 345
 346 static struct intel_uncore_ops snbep_uncore_msr_ops = {
 347         .init_box       = snbep_uncore_msr_init_box,
 348         .disable_box    = snbep_uncore_msr_disable_box,
 349         .enable_box     = snbep_uncore_msr_enable_box,
 350         .disable_event  = snbep_uncore_msr_disable_event,
 351         .enable_event   = snbep_uncore_msr_enable_event,
 352         .read_counter   = uncore_msr_read_counter,
 353         .get_constraint = uncore_get_constraint,
 354         .put_constraint = uncore_put_constraint,
 355         .hw_config      = snbep_uncore_hw_config,
 356 };
 357
 358 static struct intel_uncore_ops snbep_uncore_pci_ops = {
 359         .init_box       = snbep_uncore_pci_init_box,
 360         .disable_box    = snbep_uncore_pci_disable_box,
 361         .enable_box     = snbep_uncore_pci_enable_box,
 362         .disable_event  = snbep_uncore_pci_disable_event,
 363         .enable_event   = snbep_uncore_pci_enable_event,
 364         .read_counter   = snbep_uncore_pci_read_counter,
 365 };
 366
 367 static struct event_constraint snbep_uncore_cbox_constraints[] = {
 368         UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
 369         UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
 370         UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
 371         UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
 372         UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
 373         UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
 374         UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
 375         UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
 376         UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
 377         UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
 378         UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
 379         UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
 380         EVENT_CONSTRAINT_OVERLAP(0x1f, 0xe, 0xff),
 381         UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
 382         UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
 383         UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
 384         UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
 385         UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
 386         UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
 387         UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
 388         UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
 389         UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
 390         UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
 391         UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
 392         UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
 393         EVENT_CONSTRAINT_END
 394 };
 395
 396 static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
 397         UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
 398         UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
 399         UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
 400         UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
 401         UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
 402         UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
 403         UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
 404         UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
 405         UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
 406         UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
 407         EVENT_CONSTRAINT_END
 408 };
 409
 410 static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
 411         UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
 412         UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
 413         UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
 414         UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
 415         UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
 416         UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
 417         UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
 418         UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
 419         UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
 420         UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
 421         UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
 422         UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
 423         UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
 424         UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
 425         UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
 426         UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
 427         UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
 428         UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
 429         EVENT_CONSTRAINT_END
 430 };
 431
 432 static struct intel_uncore_type snbep_uncore_ubox = {
 433         .name           = "ubox",
 434         .num_counters   = 2,
 435         .num_boxes      = 1,
 436         .perf_ctr_bits  = 44,
 437         .fixed_ctr_bits = 48,
 438         .perf_ctr       = SNBEP_U_MSR_PMON_CTR0,
 439         .event_ctl      = SNBEP_U_MSR_PMON_CTL0,
 440         .event_mask     = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
 441         .fixed_ctr      = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
 442         .fixed_ctl      = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
 443         .ops            = &snbep_uncore_msr_ops,
 444         .format_group   = &snbep_uncore_ubox_format_group,
 445 };
 446
 447 static struct intel_uncore_type snbep_uncore_cbox = {
 448         .name                   = "cbox",
 449         .num_counters           = 4,
 450         .num_boxes              = 8,
 451         .perf_ctr_bits          = 44,
 452         .event_ctl              = SNBEP_C0_MSR_PMON_CTL0,
 453         .perf_ctr               = SNBEP_C0_MSR_PMON_CTR0,
 454         .event_mask             = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
 455         .box_ctl                = SNBEP_C0_MSR_PMON_BOX_CTL,
 456         .msr_offset             = SNBEP_CBO_MSR_OFFSET,
 457         .num_shared_regs        = 1,
 458         .constraints            = snbep_uncore_cbox_constraints,
 459         .ops                    = &snbep_uncore_msr_ops,
 460         .format_group           = &snbep_uncore_cbox_format_group,
 461 };
 462
 463 static struct intel_uncore_type snbep_uncore_pcu = {
 464         .name                   = "pcu",
 465         .num_counters           = 4,
 466         .num_boxes              = 1,
 467         .perf_ctr_bits          = 48,
 468         .perf_ctr               = SNBEP_PCU_MSR_PMON_CTR0,
 469         .event_ctl              = SNBEP_PCU_MSR_PMON_CTL0,
 470         .event_mask             = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
 471         .box_ctl                = SNBEP_PCU_MSR_PMON_BOX_CTL,
 472         .num_shared_regs        = 1,
 473         .ops                    = &snbep_uncore_msr_ops,
 474         .format_group           = &snbep_uncore_pcu_format_group,
 475 };
 476
 477 static struct intel_uncore_type *snbep_msr_uncores[] = {
 478         &snbep_uncore_ubox,
 479         &snbep_uncore_cbox,
 480         &snbep_uncore_pcu,
 481         NULL,
 482 };
 483
 484 #define SNBEP_UNCORE_PCI_COMMON_INIT()                          \
 485         .perf_ctr       = SNBEP_PCI_PMON_CTR0,                  \
 486         .event_ctl      = SNBEP_PCI_PMON_CTL0,                  \
 487         .event_mask     = SNBEP_PMON_RAW_EVENT_MASK,            \
 488         .box_ctl        = SNBEP_PCI_PMON_BOX_CTL,               \
 489         .ops            = &snbep_uncore_pci_ops,                \
 490         .format_group   = &snbep_uncore_format_group
 491
 492 static struct intel_uncore_type snbep_uncore_ha = {
 493         .name           = "ha",
 494         .num_counters   = 4,
 495         .num_boxes      = 1,
 496         .perf_ctr_bits  = 48,
 497         SNBEP_UNCORE_PCI_COMMON_INIT(),
 498 };
 499
 500 static struct intel_uncore_type snbep_uncore_imc = {
 501         .name           = "imc",
 502         .num_counters   = 4,
 503         .num_boxes      = 4,
 504         .perf_ctr_bits  = 48,
 505         .fixed_ctr_bits = 48,
 506         .fixed_ctr      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
 507         .fixed_ctl      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
 508         .event_descs    = snbep_uncore_imc_events,
 509         SNBEP_UNCORE_PCI_COMMON_INIT(),
 510 };
 511
 512 static struct intel_uncore_type snbep_uncore_qpi = {
 513         .name           = "qpi",
 514         .num_counters   = 4,
 515         .num_boxes      = 2,
 516         .perf_ctr_bits  = 48,
 517         .perf_ctr       = SNBEP_PCI_PMON_CTR0,
 518         .event_ctl      = SNBEP_PCI_PMON_CTL0,
 519         .event_mask     = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
 520         .box_ctl        = SNBEP_PCI_PMON_BOX_CTL,
 521         .ops            = &snbep_uncore_pci_ops,
 522         .event_descs    = snbep_uncore_qpi_events,
 523         .format_group   = &snbep_uncore_qpi_format_group,
 524 };
 525
 526
 527 static struct intel_uncore_type snbep_uncore_r2pcie = {
 528         .name           = "r2pcie",
 529         .num_counters   = 4,
 530         .num_boxes      = 1,
 531         .perf_ctr_bits  = 44,
 532         .constraints    = snbep_uncore_r2pcie_constraints,
 533         SNBEP_UNCORE_PCI_COMMON_INIT(),
 534 };
 535
 536 static struct intel_uncore_type snbep_uncore_r3qpi = {
 537         .name           = "r3qpi",
 538         .num_counters   = 3,
 539         .num_boxes      = 2,
 540         .perf_ctr_bits  = 44,
 541         .constraints    = snbep_uncore_r3qpi_constraints,
 542         SNBEP_UNCORE_PCI_COMMON_INIT(),
 543 };
 544
 545 static struct intel_uncore_type *snbep_pci_uncores[] = {
 546         &snbep_uncore_ha,
 547         &snbep_uncore_imc,
 548         &snbep_uncore_qpi,
 549         &snbep_uncore_r2pcie,
 550         &snbep_uncore_r3qpi,
 551         NULL,
 552 };
 553
 554 static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
 555         { /* Home Agent */
 556                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
 557                 .driver_data = (unsigned long)&snbep_uncore_ha,
 558         },
 559         { /* MC Channel 0 */
 560                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
 561                 .driver_data = (unsigned long)&snbep_uncore_imc,
 562         },
 563         { /* MC Channel 1 */
 564                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
 565                 .driver_data = (unsigned long)&snbep_uncore_imc,
 566         },
 567         { /* MC Channel 2 */
 568                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
 569                 .driver_data = (unsigned long)&snbep_uncore_imc,
 570         },
 571         { /* MC Channel 3 */
 572                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
 573                 .driver_data = (unsigned long)&snbep_uncore_imc,
 574         },
 575         { /* QPI Port 0 */
 576                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
 577                 .driver_data = (unsigned long)&snbep_uncore_qpi,
 578         },
 579         { /* QPI Port 1 */
 580                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
 581                 .driver_data = (unsigned long)&snbep_uncore_qpi,
 582         },
 583         { /* P2PCIe */
 584                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
 585                 .driver_data = (unsigned long)&snbep_uncore_r2pcie,
 586         },
 587         { /* R3QPI Link 0 */
 588                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
 589                 .driver_data = (unsigned long)&snbep_uncore_r3qpi,
 590         },
 591         { /* R3QPI Link 1 */
 592                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
 593                 .driver_data = (unsigned long)&snbep_uncore_r3qpi,
 594         },
 595         { /* end: all zeroes */ }
 596 };
 597
 598 static struct pci_driver snbep_uncore_pci_driver = {
 599         .name           = "snbep_uncore",
 600         .id_table       = snbep_uncore_pci_ids,
 601 };
 602
 603 /*
 604  * build pci bus to socket mapping
 605  */
 606 static void snbep_pci2phy_map_init(void)
 607 {
 608         struct pci_dev *ubox_dev = NULL;
 609         int i, bus, nodeid;
 610         u32 config;
 611
 612         while (1) {
 613                 /* find the UBOX device */
 614                 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
 615                                         PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX,
 616                                         ubox_dev);
 617                 if (!ubox_dev)
 618                         break;
 619                 bus = ubox_dev->bus->number;
 620                 /* get the Node ID of the local register */
 621                 pci_read_config_dword(ubox_dev, 0x40, &config);
 622                 nodeid = config;
 623                 /* get the Node ID mapping */
 624                 pci_read_config_dword(ubox_dev, 0x54, &config);
 625                 /*
 626                  * every three bits in the Node ID mapping register maps
 627                  * to a particular node.
 628                  */
 629                 for (i = 0; i < 8; i++) {
 630                         if (nodeid == ((config >> (3 * i)) & 0x7)) {
 631                                 pcibus_to_physid[bus] = i;
 632                                 break;
 633                         }
 634                 }
 635         };
 636         return;
 637 }
 638 /* end of Sandy Bridge-EP uncore support */
 639
 640 /* Sandy Bridge uncore support */
 641 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 642 {
 643         struct hw_perf_event *hwc = &event->hw;
 644
 645         if (hwc->idx < UNCORE_PMC_IDX_FIXED)
 646                 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
 647         else
 648                 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
 649 }
 650
 651 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
 652 {
 653         wrmsrl(event->hw.config_base, 0);
 654 }
 655
 656 static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
 657 {
 658         if (box->pmu->pmu_idx == 0) {
 659                 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
 660                         SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
 661         }
 662 }
 663
 664 static struct attribute *snb_uncore_formats_attr[] = {
 665         &format_attr_event.attr,
 666         &format_attr_umask.attr,
 667         &format_attr_edge.attr,
 668         &format_attr_inv.attr,
 669         &format_attr_cmask5.attr,
 670         NULL,
 671 };
 672
 673 static struct attribute_group snb_uncore_format_group = {
 674         .name           = "format",
 675         .attrs          = snb_uncore_formats_attr,
 676 };
 677
 678 static struct intel_uncore_ops snb_uncore_msr_ops = {
 679         .init_box       = snb_uncore_msr_init_box,
 680         .disable_event  = snb_uncore_msr_disable_event,
 681         .enable_event   = snb_uncore_msr_enable_event,
 682         .read_counter   = uncore_msr_read_counter,
 683 };
 684
 685 static struct event_constraint snb_uncore_cbox_constraints[] = {
 686         UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
 687         UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
 688         EVENT_CONSTRAINT_END
 689 };
 690
 691 static struct intel_uncore_type snb_uncore_cbox = {
 692         .name           = "cbox",
 693         .num_counters   = 2,
 694         .num_boxes      = 4,
 695         .perf_ctr_bits  = 44,
 696         .fixed_ctr_bits = 48,
 697         .perf_ctr       = SNB_UNC_CBO_0_PER_CTR0,
 698         .event_ctl      = SNB_UNC_CBO_0_PERFEVTSEL0,
 699         .fixed_ctr      = SNB_UNC_FIXED_CTR,
 700         .fixed_ctl      = SNB_UNC_FIXED_CTR_CTRL,
 701         .single_fixed   = 1,
 702         .event_mask     = SNB_UNC_RAW_EVENT_MASK,
 703         .msr_offset     = SNB_UNC_CBO_MSR_OFFSET,
 704         .constraints    = snb_uncore_cbox_constraints,
 705         .ops            = &snb_uncore_msr_ops,
 706         .format_group   = &snb_uncore_format_group,
 707 };
 708
 709 static struct intel_uncore_type *snb_msr_uncores[] = {
 710         &snb_uncore_cbox,
 711         NULL,
 712 };
 713 /* end of Sandy Bridge uncore support */
 714
 715 /* Nehalem uncore support */
 716 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
 717 {
 718         wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
 719 }
 720
 721 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
 722 {
 723         wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
 724 }
 725
 726 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 727 {
 728         struct hw_perf_event *hwc = &event->hw;
 729
 730         if (hwc->idx < UNCORE_PMC_IDX_FIXED)
 731                 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
 732         else
 733                 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
 734 }
 735
 736 static struct attribute *nhm_uncore_formats_attr[] = {
 737         &format_attr_event.attr,
 738         &format_attr_umask.attr,
 739         &format_attr_edge.attr,
 740         &format_attr_inv.attr,
 741         &format_attr_cmask8.attr,
 742         NULL,
 743 };
 744
 745 static struct attribute_group nhm_uncore_format_group = {
 746         .name = "format",
 747         .attrs = nhm_uncore_formats_attr,
 748 };
 749
 750 static struct uncore_event_desc nhm_uncore_events[] = {
 751         INTEL_UNCORE_EVENT_DESC(clockticks,                "event=0xff,umask=0x00"),
 752         INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any,       "event=0x2f,umask=0x0f"),
 753         INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any,      "event=0x2c,umask=0x0f"),
 754         INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads,     "event=0x20,umask=0x01"),
 755         INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes,    "event=0x20,umask=0x02"),
 756         INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads,  "event=0x20,umask=0x04"),
 757         INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
 758         INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads,   "event=0x20,umask=0x10"),
 759         INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes,  "event=0x20,umask=0x20"),
 760         { /* end: all zeroes */ },
 761 };
 762
 763 static struct intel_uncore_ops nhm_uncore_msr_ops = {
 764         .disable_box    = nhm_uncore_msr_disable_box,
 765         .enable_box     = nhm_uncore_msr_enable_box,
 766         .disable_event  = snb_uncore_msr_disable_event,
 767         .enable_event   = nhm_uncore_msr_enable_event,
 768         .read_counter   = uncore_msr_read_counter,
 769 };
 770
 771 static struct intel_uncore_type nhm_uncore = {
 772         .name           = "",
 773         .num_counters   = 8,
 774         .num_boxes      = 1,
 775         .perf_ctr_bits  = 48,
 776         .fixed_ctr_bits = 48,
 777         .event_ctl      = NHM_UNC_PERFEVTSEL0,
 778         .perf_ctr       = NHM_UNC_UNCORE_PMC0,
 779         .fixed_ctr      = NHM_UNC_FIXED_CTR,
 780         .fixed_ctl      = NHM_UNC_FIXED_CTR_CTRL,
 781         .event_mask     = NHM_UNC_RAW_EVENT_MASK,
 782         .event_descs    = nhm_uncore_events,
 783         .ops            = &nhm_uncore_msr_ops,
 784         .format_group   = &nhm_uncore_format_group,
 785 };
 786
 787 static struct intel_uncore_type *nhm_msr_uncores[] = {
 788         &nhm_uncore,
 789         NULL,
 790 };
 791 /* end of Nehalem uncore support */
 792
 793 /* Nehalem-EX uncore support */
 794 #define __BITS_VALUE(x, i, n)  ((typeof(x))(((x) >> ((i) * (n))) & \
 795                                 ((1ULL << (n)) - 1)))
 796
 797 DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
 798 DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
 799 DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
 800 DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
 801
 802 static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box)
 803 {
 804         wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL);
 805 }
 806
 807 static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)
 808 {
 809         unsigned msr = uncore_msr_box_ctl(box);
 810         u64 config;
 811
 812         if (msr) {
 813                 rdmsrl(msr, config);
 814                 config &= ~((1ULL << uncore_num_counters(box)) - 1);
 815                 /* WBox has a fixed counter */
 816                 if (uncore_msr_fixed_ctl(box))
 817                         config &= ~NHMEX_W_PMON_GLOBAL_FIXED_EN;
 818                 wrmsrl(msr, config);
 819         }
 820 }
 821
 822 static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)
 823 {
 824         unsigned msr = uncore_msr_box_ctl(box);
 825         u64 config;
 826
 827         if (msr) {
 828                 rdmsrl(msr, config);
 829                 config |= (1ULL << uncore_num_counters(box)) - 1;
 830                 /* WBox has a fixed counter */
 831                 if (uncore_msr_fixed_ctl(box))
 832                         config |= NHMEX_W_PMON_GLOBAL_FIXED_EN;
 833                 wrmsrl(msr, config);
 834         }
 835 }
 836
 837 static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
 838 {
 839         wrmsrl(event->hw.config_base, 0);
 840 }
 841
 842 static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 843 {
 844         struct hw_perf_event *hwc = &event->hw;
 845
 846         if (hwc->idx >= UNCORE_PMC_IDX_FIXED)
 847                 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0);
 848         else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0)
 849                 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
 850         else
 851                 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
 852 }
 853
 854 #define NHMEX_UNCORE_OPS_COMMON_INIT()                          \
 855         .init_box       = nhmex_uncore_msr_init_box,            \
 856         .disable_box    = nhmex_uncore_msr_disable_box,         \
 857         .enable_box     = nhmex_uncore_msr_enable_box,          \
 858         .disable_event  = nhmex_uncore_msr_disable_event,       \
 859         .read_counter   = uncore_msr_read_counter
 860
 861 static struct intel_uncore_ops nhmex_uncore_ops = {
 862         NHMEX_UNCORE_OPS_COMMON_INIT(),
 863         .enable_event   = nhmex_uncore_msr_enable_event,
 864 };
 865
 866 static struct attribute *nhmex_uncore_ubox_formats_attr[] = {
 867         &format_attr_event.attr,
 868         &format_attr_edge.attr,
 869         NULL,
 870 };
 871
 872 static struct attribute_group nhmex_uncore_ubox_format_group = {
 873         .name           = "format",
 874         .attrs          = nhmex_uncore_ubox_formats_attr,
 875 };
 876
 877 static struct intel_uncore_type nhmex_uncore_ubox = {
 878         .name           = "ubox",
 879         .num_counters   = 1,
 880         .num_boxes      = 1,
 881         .perf_ctr_bits  = 48,
 882         .event_ctl      = NHMEX_U_MSR_PMON_EV_SEL,
 883         .perf_ctr       = NHMEX_U_MSR_PMON_CTR,
 884         .event_mask     = NHMEX_U_PMON_RAW_EVENT_MASK,
 885         .box_ctl        = NHMEX_U_MSR_PMON_GLOBAL_CTL,
 886         .ops            = &nhmex_uncore_ops,
 887         .format_group   = &nhmex_uncore_ubox_format_group
 888 };
 889
 890 static struct attribute *nhmex_uncore_cbox_formats_attr[] = {
 891         &format_attr_event.attr,
 892         &format_attr_umask.attr,
 893         &format_attr_edge.attr,
 894         &format_attr_inv.attr,
 895         &format_attr_thresh8.attr,
 896         NULL,
 897 };
 898
 899 static struct attribute_group nhmex_uncore_cbox_format_group = {
 900         .name = "format",
 901         .attrs = nhmex_uncore_cbox_formats_attr,
 902 };
 903
 904 /* msr offset for each instance of cbox */
 905 static unsigned nhmex_cbox_msr_offsets[] = {
 906         0x0, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x240, 0x2c0,
 907 };
 908
 909 static struct intel_uncore_type nhmex_uncore_cbox = {
 910         .name                   = "cbox",
 911         .num_counters           = 6,
 912         .num_boxes              = 10,
 913         .perf_ctr_bits          = 48,
 914         .event_ctl              = NHMEX_C0_MSR_PMON_EV_SEL0,
 915         .perf_ctr               = NHMEX_C0_MSR_PMON_CTR0,
 916         .event_mask             = NHMEX_PMON_RAW_EVENT_MASK,
 917         .box_ctl                = NHMEX_C0_MSR_PMON_GLOBAL_CTL,
 918         .msr_offsets            = nhmex_cbox_msr_offsets,
 919         .pair_ctr_ctl           = 1,
 920         .ops                    = &nhmex_uncore_ops,
 921         .format_group           = &nhmex_uncore_cbox_format_group
 922 };
 923
 924 static struct uncore_event_desc nhmex_uncore_wbox_events[] = {
 925         INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0"),
 926         { /* end: all zeroes */ },
 927 };
 928
 929 static struct intel_uncore_type nhmex_uncore_wbox = {
 930         .name                   = "wbox",
 931         .num_counters           = 4,
 932         .num_boxes              = 1,
 933         .perf_ctr_bits          = 48,
 934         .event_ctl              = NHMEX_W_MSR_PMON_CNT0,
 935         .perf_ctr               = NHMEX_W_MSR_PMON_EVT_SEL0,
 936         .fixed_ctr              = NHMEX_W_MSR_PMON_FIXED_CTR,
 937         .fixed_ctl              = NHMEX_W_MSR_PMON_FIXED_CTL,
 938         .event_mask             = NHMEX_PMON_RAW_EVENT_MASK,
 939         .box_ctl                = NHMEX_W_MSR_GLOBAL_CTL,
 940         .pair_ctr_ctl           = 1,
 941         .event_descs            = nhmex_uncore_wbox_events,
 942         .ops                    = &nhmex_uncore_ops,
 943         .format_group           = &nhmex_uncore_cbox_format_group
 944 };
 945
 946 static int nhmex_bbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
 947 {
 948         struct hw_perf_event *hwc = &event->hw;
 949         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
 950         struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
 951         int ctr, ev_sel;
 952
 953         ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >>
 954                 NHMEX_B_PMON_CTR_SHIFT;
 955         ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >>
 956                   NHMEX_B_PMON_CTL_EV_SEL_SHIFT;
 957
 958         /* events that do not use the match/mask registers */
 959         if ((ctr == 0 && ev_sel > 0x3) || (ctr == 1 && ev_sel > 0x6) ||
 960             (ctr == 2 && ev_sel != 0x4) || ctr == 3)
 961                 return 0;
 962
 963         if (box->pmu->pmu_idx == 0)
 964                 reg1->reg = NHMEX_B0_MSR_MATCH;
 965         else
 966                 reg1->reg = NHMEX_B1_MSR_MATCH;
 967         reg1->idx = 0;
 968         reg1->config = event->attr.config1;
 969         reg2->config = event->attr.config2;
 970         return 0;
 971 }
 972
 973 static void nhmex_bbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 974 {
 975         struct hw_perf_event *hwc = &event->hw;
 976         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
 977         struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
 978
 979         if (reg1->idx != EXTRA_REG_NONE) {
 980                 wrmsrl(reg1->reg, reg1->config);
 981                 wrmsrl(reg1->reg + 1, reg2->config);
 982         }
 983         wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
 984                 (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK));
 985 }
 986
 987 /*
 988  * The Bbox has 4 counters, but each counter monitors different events.
 989  * Use bits 6-7 in the event config to select counter.
 990  */
 991 static struct event_constraint nhmex_uncore_bbox_constraints[] = {
 992         EVENT_CONSTRAINT(0 , 1, 0xc0),
 993         EVENT_CONSTRAINT(0x40, 2, 0xc0),
 994         EVENT_CONSTRAINT(0x80, 4, 0xc0),
 995         EVENT_CONSTRAINT(0xc0, 8, 0xc0),
 996         EVENT_CONSTRAINT_END,
 997 };
 998
 999 static struct attribute *nhmex_uncore_bbox_formats_attr[] = {
1000         &format_attr_event5.attr,
1001         &format_attr_counter.attr,
1002         &format_attr_match.attr,
1003         &format_attr_mask.attr,
1004         NULL,
1005 };
1006
1007 static struct attribute_group nhmex_uncore_bbox_format_group = {
1008         .name = "format",
1009         .attrs = nhmex_uncore_bbox_formats_attr,
1010 };
1011
1012 static struct intel_uncore_ops nhmex_uncore_bbox_ops = {
1013         NHMEX_UNCORE_OPS_COMMON_INIT(),
1014         .enable_event           = nhmex_bbox_msr_enable_event,
1015         .hw_config              = nhmex_bbox_hw_config,
1016         .get_constraint         = uncore_get_constraint,
1017         .put_constraint         = uncore_put_constraint,
1018 };
1019
1020 static struct intel_uncore_type nhmex_uncore_bbox = {
1021         .name                   = "bbox",
1022         .num_counters           = 4,
1023         .num_boxes              = 2,
1024         .perf_ctr_bits          = 48,
1025         .event_ctl              = NHMEX_B0_MSR_PMON_CTL0,
1026         .perf_ctr               = NHMEX_B0_MSR_PMON_CTR0,
1027         .event_mask             = NHMEX_B_PMON_RAW_EVENT_MASK,
1028         .box_ctl                = NHMEX_B0_MSR_PMON_GLOBAL_CTL,
1029         .msr_offset             = NHMEX_B_MSR_OFFSET,
1030         .pair_ctr_ctl           = 1,
1031         .num_shared_regs        = 1,
1032         .constraints            = nhmex_uncore_bbox_constraints,
1033         .ops                    = &nhmex_uncore_bbox_ops,
1034         .format_group           = &nhmex_uncore_bbox_format_group
1035 };
1036
1037 static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1038 {
1039         struct hw_perf_event *hwc = &event->hw;
1040         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1041         struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1042
1043         /* only TO_R_PROG_EV event uses the match/mask register */
1044         if ((hwc->config & NHMEX_PMON_CTL_EV_SEL_MASK) !=
1045             NHMEX_S_EVENT_TO_R_PROG_EV)
1046                 return 0;
1047
1048         if (box->pmu->pmu_idx == 0)
1049                 reg1->reg = NHMEX_S0_MSR_MM_CFG;
1050         else
1051                 reg1->reg = NHMEX_S1_MSR_MM_CFG;
1052         reg1->idx = 0;
1053         reg1->config = event->attr.config1;
1054         reg2->config = event->attr.config2;
1055         return 0;
1056 }
1057
1058 static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1059 {
1060         struct hw_perf_event *hwc = &event->hw;
1061         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1062         struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1063
1064         if (reg1->idx != EXTRA_REG_NONE) {
1065                 wrmsrl(reg1->reg, 0);
1066                 wrmsrl(reg1->reg + 1, reg1->config);
1067                 wrmsrl(reg1->reg + 2, reg2->config);
1068                 wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
1069         }
1070         wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
1071 }
1072
1073 static struct attribute *nhmex_uncore_sbox_formats_attr[] = {
1074         &format_attr_event.attr,
1075         &format_attr_umask.attr,
1076         &format_attr_edge.attr,
1077         &format_attr_inv.attr,
1078         &format_attr_thresh8.attr,
1079         &format_attr_match.attr,
1080         &format_attr_mask.attr,
1081         NULL,
1082 };
1083
1084 static struct attribute_group nhmex_uncore_sbox_format_group = {
1085         .name                   = "format",
1086         .attrs                  = nhmex_uncore_sbox_formats_attr,
1087 };
1088
1089 static struct intel_uncore_ops nhmex_uncore_sbox_ops = {
1090         NHMEX_UNCORE_OPS_COMMON_INIT(),
1091         .enable_event           = nhmex_sbox_msr_enable_event,
1092         .hw_config              = nhmex_sbox_hw_config,
1093         .get_constraint         = uncore_get_constraint,
1094         .put_constraint         = uncore_put_constraint,
1095 };
1096
1097 static struct intel_uncore_type nhmex_uncore_sbox = {
1098         .name                   = "sbox",
1099         .num_counters           = 4,
1100         .num_boxes              = 2,
1101         .perf_ctr_bits          = 48,
1102         .event_ctl              = NHMEX_S0_MSR_PMON_CTL0,
1103         .perf_ctr               = NHMEX_S0_MSR_PMON_CTR0,
1104         .event_mask             = NHMEX_PMON_RAW_EVENT_MASK,
1105         .box_ctl                = NHMEX_S0_MSR_PMON_GLOBAL_CTL,
1106         .msr_offset             = NHMEX_S_MSR_OFFSET,
1107         .pair_ctr_ctl           = 1,
1108         .num_shared_regs        = 1,
1109         .ops                    = &nhmex_uncore_sbox_ops,
1110         .format_group           = &nhmex_uncore_sbox_format_group
1111 };
1112
1113 enum {
1114         EXTRA_REG_NHMEX_M_FILTER,
1115         EXTRA_REG_NHMEX_M_DSP,
1116         EXTRA_REG_NHMEX_M_ISS,
1117         EXTRA_REG_NHMEX_M_MAP,
1118         EXTRA_REG_NHMEX_M_MSC_THR,
1119         EXTRA_REG_NHMEX_M_PGT,
1120         EXTRA_REG_NHMEX_M_PLD,
1121         EXTRA_REG_NHMEX_M_ZDP_CTL_FVC,
1122 };
1123
1124 static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
1125         MBOX_INC_SEL_EXTAR_REG(0x0, DSP),
1126         MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR),
1127         MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR),
1128         MBOX_INC_SEL_EXTAR_REG(0x9, ISS),
1129         /* event 0xa uses two extra registers */
1130         MBOX_INC_SEL_EXTAR_REG(0xa, ISS),
1131         MBOX_INC_SEL_EXTAR_REG(0xa, PLD),
1132         MBOX_INC_SEL_EXTAR_REG(0xb, PLD),
1133         /* events 0xd ~ 0x10 use the same extra register */
1134         MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC),
1135         MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC),
1136         MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC),
1137         MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC),
1138         MBOX_INC_SEL_EXTAR_REG(0x16, PGT),
1139         MBOX_SET_FLAG_SEL_EXTRA_REG(0x0, DSP),
1140         MBOX_SET_FLAG_SEL_EXTRA_REG(0x1, ISS),
1141         MBOX_SET_FLAG_SEL_EXTRA_REG(0x5, PGT),
1142         MBOX_SET_FLAG_SEL_EXTRA_REG(0x6, MAP),
1143         EVENT_EXTRA_END
1144 };
1145
1146 /* Nehalem-EX or Westmere-EX ? */
1147 bool uncore_nhmex;
1148
1149 static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)
1150 {
1151         struct intel_uncore_extra_reg *er;
1152         unsigned long flags;
1153         bool ret = false;
1154         u64 mask;
1155
1156         if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
1157                 er = &box->shared_regs[idx];
1158                 raw_spin_lock_irqsave(&er->lock, flags);
1159                 if (!atomic_read(&er->ref) || er->config == config) {
1160                         atomic_inc(&er->ref);
1161                         er->config = config;
1162                         ret = true;
1163                 }
1164                 raw_spin_unlock_irqrestore(&er->lock, flags);
1165
1166                 return ret;
1167         }
1168         /*
1169          * The ZDP_CTL_FVC MSR has 4 fields which are used to control
1170          * events 0xd ~ 0x10. Besides these 4 fields, there are additional
1171          * fields which are shared.
1172          */
1173         idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1174         if (WARN_ON_ONCE(idx >= 4))
1175                 return false;
1176
1177         /* mask of the shared fields */
1178         if (uncore_nhmex)
1179                 mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK;
1180         else
1181                 mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK;
1182         er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
1183
1184         raw_spin_lock_irqsave(&er->lock, flags);
1185         /* add mask of the non-shared field if it's in use */
1186         if (__BITS_VALUE(atomic_read(&er->ref), idx, 8)) {
1187                 if (uncore_nhmex)
1188                         mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1189                 else
1190                         mask |= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1191         }
1192
1193         if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) {
1194                 atomic_add(1 << (idx * 8), &er->ref);
1195                 if (uncore_nhmex)
1196                         mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK |
1197                                 NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1198                 else
1199                         mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK |
1200                                 WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1201                 er->config &= ~mask;
1202                 er->config |= (config & mask);
1203                 ret = true;
1204         }
1205         raw_spin_unlock_irqrestore(&er->lock, flags);
1206
1207         return ret;
1208 }
1209
1210 static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)
1211 {
1212         struct intel_uncore_extra_reg *er;
1213
1214         if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
1215                 er = &box->shared_regs[idx];
1216                 atomic_dec(&er->ref);
1217                 return;
1218         }
1219
1220         idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1221         er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
1222         atomic_sub(1 << (idx * 8), &er->ref);
1223 }
1224
1225 u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
1226 {
1227         struct hw_perf_event *hwc = &event->hw;
1228         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1229         int idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
1230         u64 config = reg1->config;
1231
1232         /* get the non-shared control bits and shift them */
1233         idx = orig_idx - EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1234         if (uncore_nhmex)
1235                 config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1236         else
1237                 config &= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1238         if (new_idx > orig_idx) {
1239                 idx = new_idx - orig_idx;
1240                 config <<= 3 * idx;
1241         } else {
1242                 idx = orig_idx - new_idx;
1243                 config >>= 3 * idx;
1244         }
1245
1246         /* add the shared control bits back */
1247         if (uncore_nhmex)
1248                 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
1249         else
1250                 config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
1251         config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
1252         if (modify) {
1253                 /* adjust the main event selector */
1254                 if (new_idx > orig_idx)
1255                         hwc->config += idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
1256                 else
1257                         hwc->config -= idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
1258                 reg1->config = config;
1259                 reg1->idx = ~0xff | new_idx;
1260         }
1261         return config;
1262 }
1263
1264 static struct event_constraint *
1265 nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1266 {
1267         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1268         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1269         int i, idx[2], alloc = 0;
1270         u64 config1 = reg1->config;
1271
1272         idx[0] = __BITS_VALUE(reg1->idx, 0, 8);
1273         idx[1] = __BITS_VALUE(reg1->idx, 1, 8);
1274 again:
1275         for (i = 0; i < 2; i++) {
1276                 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
1277                         idx[i] = 0xff;
1278
1279                 if (idx[i] == 0xff)
1280                         continue;
1281
1282                 if (!nhmex_mbox_get_shared_reg(box, idx[i],
1283                                 __BITS_VALUE(config1, i, 32)))
1284                         goto fail;
1285                 alloc |= (0x1 << i);
1286         }
1287
1288         /* for the match/mask registers */
1289         if (reg2->idx != EXTRA_REG_NONE &&
1290             (uncore_box_is_fake(box) || !reg2->alloc) &&
1291             !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))
1292                 goto fail;
1293
1294         /*
1295          * If it's a fake box -- as per validate_{group,event}() we
1296          * shouldn't touch event state and we can avoid doing so
1297          * since both will only call get_event_constraints() once
1298          * on each event, this avoids the need for reg->alloc.
1299          */
1300         if (!uncore_box_is_fake(box)) {
1301                 if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))
1302                         nhmex_mbox_alter_er(event, idx[0], true);
1303                 reg1->alloc |= alloc;
1304                 if (reg2->idx != EXTRA_REG_NONE)
1305                         reg2->alloc = 1;
1306         }
1307         return NULL;
1308 fail:
1309         if (idx[0] != 0xff && !(alloc & 0x1) &&
1310             idx[0] >= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
1311                 /*
1312                  * events 0xd ~ 0x10 are functional identical, but are
1313                  * controlled by different fields in the ZDP_CTL_FVC
1314                  * register. If we failed to take one field, try the
1315                  * rest 3 choices.
1316                  */
1317                 BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff);
1318                 idx[0] -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1319                 idx[0] = (idx[0] + 1) % 4;
1320                 idx[0] += EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1321                 if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) {
1322                         config1 = nhmex_mbox_alter_er(event, idx[0], false);
1323                         goto again;
1324                 }
1325         }
1326
1327         if (alloc & 0x1)
1328                 nhmex_mbox_put_shared_reg(box, idx[0]);
1329         if (alloc & 0x2)
1330                 nhmex_mbox_put_shared_reg(box, idx[1]);
1331         return &constraint_empty;
1332 }
1333
1334 static void nhmex_mbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
1335 {
1336         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1337         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1338
1339         if (uncore_box_is_fake(box))
1340                 return;
1341
1342         if (reg1->alloc & 0x1)
1343                 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));
1344         if (reg1->alloc & 0x2)
1345                 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));
1346         reg1->alloc = 0;
1347
1348         if (reg2->alloc) {
1349                 nhmex_mbox_put_shared_reg(box, reg2->idx);
1350                 reg2->alloc = 0;
1351         }
1352 }
1353
1354 static int nhmex_mbox_extra_reg_idx(struct extra_reg *er)
1355 {
1356         if (er->idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
1357                 return er->idx;
1358         return er->idx + (er->event >> NHMEX_M_PMON_CTL_INC_SEL_SHIFT) - 0xd;
1359 }
1360
1361 static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1362 {
1363         struct intel_uncore_type *type = box->pmu->type;
1364         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1365         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1366         struct extra_reg *er;
1367         unsigned msr;
1368         int reg_idx = 0;
1369         /*
1370          * The mbox events may require 2 extra MSRs at the most. But only
1371          * the lower 32 bits in these MSRs are significant, so we can use
1372          * config1 to pass two MSRs' config.
1373          */
1374         for (er = nhmex_uncore_mbox_extra_regs; er->msr; er++) {
1375                 if (er->event != (event->hw.config & er->config_mask))
1376                         continue;
1377                 if (event->attr.config1 & ~er->valid_mask)
1378                         return -EINVAL;
1379
1380                 msr = er->msr + type->msr_offset * box->pmu->pmu_idx;
1381                 if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
1382                         return -EINVAL;
1383
1384                 /* always use the 32~63 bits to pass the PLD config */
1385                 if (er->idx == EXTRA_REG_NHMEX_M_PLD)
1386                         reg_idx = 1;
1387                 else if (WARN_ON_ONCE(reg_idx > 0))
1388                         return -EINVAL;
1389
1390                 reg1->idx &= ~(0xff << (reg_idx * 8));
1391                 reg1->reg &= ~(0xffff << (reg_idx * 16));
1392                 reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);
1393                 reg1->reg |= msr << (reg_idx * 16);
1394                 reg1->config = event->attr.config1;
1395                 reg_idx++;
1396         }
1397         /*
1398          * The mbox only provides ability to perform address matching
1399          * for the PLD events.
1400          */
1401         if (reg_idx == 2) {
1402                 reg2->idx = EXTRA_REG_NHMEX_M_FILTER;
1403                 if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)
1404                         reg2->config = event->attr.config2;
1405                 else
1406                         reg2->config = ~0ULL;
1407                 if (box->pmu->pmu_idx == 0)
1408                         reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;
1409                 else
1410                         reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;
1411         }
1412         return 0;
1413 }
1414
1415 static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx)
1416 {
1417         struct intel_uncore_extra_reg *er;
1418         unsigned long flags;
1419         u64 config;
1420
1421         if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
1422                 return box->shared_regs[idx].config;
1423
1424         er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
1425         raw_spin_lock_irqsave(&er->lock, flags);
1426         config = er->config;
1427         raw_spin_unlock_irqrestore(&er->lock, flags);
1428         return config;
1429 }
1430
1431 static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1432 {
1433         struct hw_perf_event *hwc = &event->hw;
1434         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1435         struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1436         int idx;
1437
1438         idx = __BITS_VALUE(reg1->idx, 0, 8);
1439         if (idx != 0xff)
1440                 wrmsrl(__BITS_VALUE(reg1->reg, 0, 16),
1441                         nhmex_mbox_shared_reg_config(box, idx));
1442         idx = __BITS_VALUE(reg1->idx, 1, 8);
1443         if (idx != 0xff)
1444                 wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),
1445                         nhmex_mbox_shared_reg_config(box, idx));
1446
1447         if (reg2->idx != EXTRA_REG_NONE) {
1448                 wrmsrl(reg2->reg, 0);
1449                 if (reg2->config != ~0ULL) {
1450                         wrmsrl(reg2->reg + 1,
1451                                 reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK);
1452                         wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &
1453                                 (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));
1454                         wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);
1455                 }
1456         }
1457
1458         wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
1459 }
1460
1461 DEFINE_UNCORE_FORMAT_ATTR(count_mode,           count_mode,     "config:2-3");
1462 DEFINE_UNCORE_FORMAT_ATTR(storage_mode,         storage_mode,   "config:4-5");
1463 DEFINE_UNCORE_FORMAT_ATTR(wrap_mode,            wrap_mode,      "config:6");
1464 DEFINE_UNCORE_FORMAT_ATTR(flag_mode,            flag_mode,      "config:7");
1465 DEFINE_UNCORE_FORMAT_ATTR(inc_sel,              inc_sel,        "config:9-13");
1466 DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel,         set_flag_sel,   "config:19-21");
1467 DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en,        filter_cfg_en,  "config2:63");
1468 DEFINE_UNCORE_FORMAT_ATTR(filter_match,         filter_match,   "config2:0-33");
1469 DEFINE_UNCORE_FORMAT_ATTR(filter_mask,          filter_mask,    "config2:34-61");
1470 DEFINE_UNCORE_FORMAT_ATTR(dsp,                  dsp,            "config1:0-31");
1471 DEFINE_UNCORE_FORMAT_ATTR(thr,                  thr,            "config1:0-31");
1472 DEFINE_UNCORE_FORMAT_ATTR(fvc,                  fvc,            "config1:0-31");
1473 DEFINE_UNCORE_FORMAT_ATTR(pgt,                  pgt,            "config1:0-31");
1474 DEFINE_UNCORE_FORMAT_ATTR(map,                  map,            "config1:0-31");
1475 DEFINE_UNCORE_FORMAT_ATTR(iss,                  iss,            "config1:0-31");
1476 DEFINE_UNCORE_FORMAT_ATTR(pld,                  pld,            "config1:32-63");
1477
1478 static struct attribute *nhmex_uncore_mbox_formats_attr[] = {
1479         &format_attr_count_mode.attr,
1480         &format_attr_storage_mode.attr,
1481         &format_attr_wrap_mode.attr,
1482         &format_attr_flag_mode.attr,
1483         &format_attr_inc_sel.attr,
1484         &format_attr_set_flag_sel.attr,
1485         &format_attr_filter_cfg_en.attr,
1486         &format_attr_filter_match.attr,
1487         &format_attr_filter_mask.attr,
1488         &format_attr_dsp.attr,
1489         &format_attr_thr.attr,
1490         &format_attr_fvc.attr,
1491         &format_attr_pgt.attr,
1492         &format_attr_map.attr,
1493         &format_attr_iss.attr,
1494         &format_attr_pld.attr,
1495         NULL,
1496 };
1497
1498 static struct attribute_group nhmex_uncore_mbox_format_group = {
1499         .name           = "format",
1500         .attrs          = nhmex_uncore_mbox_formats_attr,
1501 };
1502
1503 static struct uncore_event_desc nhmex_uncore_mbox_events[] = {
1504         INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x2800"),
1505         INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x2820"),
1506         { /* end: all zeroes */ },
1507 };
1508
1509 static struct uncore_event_desc wsmex_uncore_mbox_events[] = {
1510         INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x5000"),
1511         INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x5040"),
1512         { /* end: all zeroes */ },
1513 };
1514
1515 static struct intel_uncore_ops nhmex_uncore_mbox_ops = {
1516         NHMEX_UNCORE_OPS_COMMON_INIT(),
1517         .enable_event   = nhmex_mbox_msr_enable_event,
1518         .hw_config      = nhmex_mbox_hw_config,
1519         .get_constraint = nhmex_mbox_get_constraint,
1520         .put_constraint = nhmex_mbox_put_constraint,
1521 };
1522
1523 static struct intel_uncore_type nhmex_uncore_mbox = {
1524         .name                   = "mbox",
1525         .num_counters           = 6,
1526         .num_boxes              = 2,
1527         .perf_ctr_bits          = 48,
1528         .event_ctl              = NHMEX_M0_MSR_PMU_CTL0,
1529         .perf_ctr               = NHMEX_M0_MSR_PMU_CNT0,
1530         .event_mask             = NHMEX_M_PMON_RAW_EVENT_MASK,
1531         .box_ctl                = NHMEX_M0_MSR_GLOBAL_CTL,
1532         .msr_offset             = NHMEX_M_MSR_OFFSET,
1533         .pair_ctr_ctl           = 1,
1534         .num_shared_regs        = 8,
1535         .event_descs            = nhmex_uncore_mbox_events,
1536         .ops                    = &nhmex_uncore_mbox_ops,
1537         .format_group           = &nhmex_uncore_mbox_format_group,
1538 };
1539
1540 void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
1541 {
1542         struct hw_perf_event *hwc = &event->hw;
1543         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1544         int port;
1545
1546         /* adjust the main event selector and extra register index */
1547         if (reg1->idx % 2) {
1548                 reg1->idx--;
1549                 hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
1550         } else {
1551                 reg1->idx++;
1552                 hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
1553         }
1554
1555         /* adjust extra register config */
1556         port = reg1->idx / 6 + box->pmu->pmu_idx * 4;
1557         switch (reg1->idx % 6) {
1558         case 2:
1559                 /* shift the 8~15 bits to the 0~7 bits */
1560                 reg1->config >>= 8;
1561                 break;
1562         case 3:
1563                 /* shift the 0~7 bits to the 8~15 bits */
1564                 reg1->config <<= 8;
1565                 break;
1566         };
1567 }
1568
1569 /*
1570  * Each rbox has 4 event set which monitor PQI port 0~3 or 4~7.
1571  * An event set consists of 6 events, the 3rd and 4th events in
1572  * an event set use the same extra register. So an event set uses
1573  * 5 extra registers.
1574  */
1575 static struct event_constraint *
1576 nhmex_rbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1577 {
1578         struct hw_perf_event *hwc = &event->hw;
1579         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1580         struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1581         struct intel_uncore_extra_reg *er;
1582         unsigned long flags;
1583         int idx, er_idx;
1584         u64 config1;
1585         bool ok = false;
1586
1587         if (!uncore_box_is_fake(box) && reg1->alloc)
1588                 return NULL;
1589
1590         idx = reg1->idx % 6;
1591         config1 = reg1->config;
1592 again:
1593         er_idx = idx;
1594         /* the 3rd and 4th events use the same extra register */
1595         if (er_idx > 2)
1596                 er_idx--;
1597         er_idx += (reg1->idx / 6) * 5;
1598
1599         er = &box->shared_regs[er_idx];
1600         raw_spin_lock_irqsave(&er->lock, flags);
1601         if (idx < 2) {
1602                 if (!atomic_read(&er->ref) || er->config == reg1->config) {
1603                         atomic_inc(&er->ref);
1604                         er->config = reg1->config;
1605                         ok = true;
1606                 }
1607         } else if (idx == 2 || idx == 3) {
1608                 /*
1609                  * these two events use different fields in a extra register,
1610                  * the 0~7 bits and the 8~15 bits respectively.
1611                  */
1612                 u64 mask = 0xff << ((idx - 2) * 8);
1613                 if (!__BITS_VALUE(atomic_read(&er->ref), idx - 2, 8) ||
1614                                 !((er->config ^ config1) & mask)) {
1615                         atomic_add(1 << ((idx - 2) * 8), &er->ref);
1616                         er->config &= ~mask;
1617                         er->config |= config1 & mask;
1618                         ok = true;
1619                 }
1620         } else {
1621                 if (!atomic_read(&er->ref) ||
1622                                 (er->config == (hwc->config >> 32) &&
1623                                  er->config1 == reg1->config &&
1624                                  er->config2 == reg2->config)) {
1625                         atomic_inc(&er->ref);
1626                         er->config = (hwc->config >> 32);
1627                         er->config1 = reg1->config;
1628                         er->config2 = reg2->config;
1629                         ok = true;
1630                 }
1631         }
1632         raw_spin_unlock_irqrestore(&er->lock, flags);
1633
1634         if (!ok) {
1635                 /*
1636                  * The Rbox events are always in pairs. The paired
1637                  * events are functional identical, but use different
1638                  * extra registers. If we failed to take an extra
1639                  * register, try the alternative.
1640                  */
1641                 if (idx % 2)
1642                         idx--;
1643                 else
1644                         idx++;
1645                 if (idx != reg1->idx % 6) {
1646                         if (idx == 2)
1647                                 config1 >>= 8;
1648                         else if (idx == 3)
1649                                 config1 <<= 8;
1650                         goto again;
1651                 }
1652         } else {
1653                 if (!uncore_box_is_fake(box)) {
1654                         if (idx != reg1->idx % 6)
1655                                 nhmex_rbox_alter_er(box, event);
1656                         reg1->alloc = 1;
1657                 }
1658                 return NULL;
1659         }
1660         return &constraint_empty;
1661 }
1662
1663 static void nhmex_rbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
1664 {
1665         struct intel_uncore_extra_reg *er;
1666         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1667         int idx, er_idx;
1668
1669         if (uncore_box_is_fake(box) || !reg1->alloc)
1670                 return;
1671
1672         idx = reg1->idx % 6;
1673         er_idx = idx;
1674         if (er_idx > 2)
1675                 er_idx--;
1676         er_idx += (reg1->idx / 6) * 5;
1677
1678         er = &box->shared_regs[er_idx];
1679         if (idx == 2 || idx == 3)
1680                 atomic_sub(1 << ((idx - 2) * 8), &er->ref);
1681         else
1682                 atomic_dec(&er->ref);
1683
1684         reg1->alloc = 0;
1685 }
1686
1687 static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1688 {
1689         struct hw_perf_event *hwc = &event->hw;
1690         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1691         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1692         int idx;
1693
1694         idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>
1695                 NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
1696         if (idx >= 0x18)
1697                 return -EINVAL;
1698
1699         reg1->idx = idx;
1700         reg1->config = event->attr.config1;
1701
1702         switch (idx % 6) {
1703         case 4:
1704         case 5:
1705                 hwc->config |= event->attr.config & (~0ULL << 32);
1706                 reg2->config = event->attr.config2;
1707                 break;
1708         };
1709         return 0;
1710 }
1711
1712 static u64 nhmex_rbox_shared_reg_config(struct intel_uncore_box *box, int idx)
1713 {
1714         struct intel_uncore_extra_reg *er;
1715         unsigned long flags;
1716         u64 config;
1717
1718         er = &box->shared_regs[idx];
1719
1720         raw_spin_lock_irqsave(&er->lock, flags);
1721         config = er->config;
1722         raw_spin_unlock_irqrestore(&er->lock, flags);
1723
1724         return config;
1725 }
1726
1727 static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1728 {
1729         struct hw_perf_event *hwc = &event->hw;
1730         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1731         struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1732         int idx, port;
1733
1734         idx = reg1->idx;
1735         port = idx / 6 + box->pmu->pmu_idx * 4;
1736
1737         switch (idx % 6) {
1738         case 0:
1739                 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);
1740                 break;
1741         case 1:
1742                 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);
1743                 break;
1744         case 2:
1745         case 3:
1746                 wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),
1747                         nhmex_rbox_shared_reg_config(box, 2 + (idx / 6) * 5));
1748                 break;
1749         case 4:
1750                 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),
1751                         hwc->config >> 32);
1752                 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);
1753                 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config);
1754                 break;
1755         case 5:
1756                 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port),
1757                         hwc->config >> 32);
1758                 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
1759                 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
1760                 break;
1761         };
1762
1763         wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
1764                 (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
1765 }
1766
1767 DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config:32-63");
1768 DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config1:0-63");
1769 DEFINE_UNCORE_FORMAT_ATTR(xbr_mask, xbr_mask, "config2:0-63");
1770 DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg, qlx_cfg, "config1:0-15");
1771 DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg, iperf_cfg, "config1:0-31");
1772
1773 static struct attribute *nhmex_uncore_rbox_formats_attr[] = {
1774         &format_attr_event5.attr,
1775         &format_attr_xbr_mm_cfg.attr,
1776         &format_attr_xbr_match.attr,
1777         &format_attr_xbr_mask.attr,
1778         &format_attr_qlx_cfg.attr,
1779         &format_attr_iperf_cfg.attr,
1780         NULL,
1781 };
1782
1783 static struct attribute_group nhmex_uncore_rbox_format_group = {
1784         .name = "format",
1785         .attrs = nhmex_uncore_rbox_formats_attr,
1786 };
1787
1788 static struct uncore_event_desc nhmex_uncore_rbox_events[] = {
1789         INTEL_UNCORE_EVENT_DESC(qpi0_flit_send,         "event=0x0,iperf_cfg=0x80000000"),
1790         INTEL_UNCORE_EVENT_DESC(qpi1_filt_send,         "event=0x6,iperf_cfg=0x80000000"),
1791         INTEL_UNCORE_EVENT_DESC(qpi0_idle_filt,         "event=0x0,iperf_cfg=0x40000000"),
1792         INTEL_UNCORE_EVENT_DESC(qpi1_idle_filt,         "event=0x6,iperf_cfg=0x40000000"),
1793         INTEL_UNCORE_EVENT_DESC(qpi0_date_response,     "event=0x0,iperf_cfg=0xc4"),
1794         INTEL_UNCORE_EVENT_DESC(qpi1_date_response,     "event=0x6,iperf_cfg=0xc4"),
1795         { /* end: all zeroes */ },
1796 };
1797
1798 static struct intel_uncore_ops nhmex_uncore_rbox_ops = {
1799         NHMEX_UNCORE_OPS_COMMON_INIT(),
1800         .enable_event           = nhmex_rbox_msr_enable_event,
1801         .hw_config              = nhmex_rbox_hw_config,
1802         .get_constraint         = nhmex_rbox_get_constraint,
1803         .put_constraint         = nhmex_rbox_put_constraint,
1804 };
1805
1806 static struct intel_uncore_type nhmex_uncore_rbox = {
1807         .name                   = "rbox",
1808         .num_counters           = 8,
1809         .num_boxes              = 2,
1810         .perf_ctr_bits          = 48,
1811         .event_ctl              = NHMEX_R_MSR_PMON_CTL0,
1812         .perf_ctr               = NHMEX_R_MSR_PMON_CNT0,
1813         .event_mask             = NHMEX_R_PMON_RAW_EVENT_MASK,
1814         .box_ctl                = NHMEX_R_MSR_GLOBAL_CTL,
1815         .msr_offset             = NHMEX_R_MSR_OFFSET,
1816         .pair_ctr_ctl           = 1,
1817         .num_shared_regs        = 20,
1818         .event_descs            = nhmex_uncore_rbox_events,
1819         .ops                    = &nhmex_uncore_rbox_ops,
1820         .format_group           = &nhmex_uncore_rbox_format_group
1821 };
1822
1823 static struct intel_uncore_type *nhmex_msr_uncores[] = {
1824         &nhmex_uncore_ubox,
1825         &nhmex_uncore_cbox,
1826         &nhmex_uncore_bbox,
1827         &nhmex_uncore_sbox,
1828         &nhmex_uncore_mbox,
1829         &nhmex_uncore_rbox,
1830         &nhmex_uncore_wbox,
1831         NULL,
1832 };
1833 /* end of Nehalem-EX uncore support */
1834
1835 static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
1836 {
1837         struct hw_perf_event *hwc = &event->hw;
1838
1839         hwc->idx = idx;
1840         hwc->last_tag = ++box->tags[idx];
1841
1842         if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
1843                 hwc->event_base = uncore_fixed_ctr(box);
1844                 hwc->config_base = uncore_fixed_ctl(box);
1845                 return;
1846         }
1847
1848         hwc->config_base = uncore_event_ctl(box, hwc->idx);
1849         hwc->event_base  = uncore_perf_ctr(box, hwc->idx);
1850 }
1851
1852 static void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
1853 {
1854         u64 prev_count, new_count, delta;
1855         int shift;
1856
1857         if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
1858                 shift = 64 - uncore_fixed_ctr_bits(box);
1859         else
1860                 shift = 64 - uncore_perf_ctr_bits(box);
1861
1862         /* the hrtimer might modify the previous event value */
1863 again:
1864         prev_count = local64_read(&event->hw.prev_count);
1865         new_count = uncore_read_counter(box, event);
1866         if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
1867                 goto again;
1868
1869         delta = (new_count << shift) - (prev_count << shift);
1870         delta >>= shift;
1871
1872         local64_add(delta, &event->count);
1873 }
1874
1875 /*
1876  * The overflow interrupt is unavailable for SandyBridge-EP, is broken
1877  * for SandyBridge. So we use hrtimer to periodically poll the counter
1878  * to avoid overflow.
1879  */
1880 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
1881 {
1882         struct intel_uncore_box *box;
1883         unsigned long flags;
1884         int bit;
1885
1886         box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
1887         if (!box->n_active || box->cpu != smp_processor_id())
1888                 return HRTIMER_NORESTART;
1889         /*
1890          * disable local interrupt to prevent uncore_pmu_event_start/stop
1891          * to interrupt the update process
1892          */
1893         local_irq_save(flags);
1894
1895         for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
1896                 uncore_perf_event_update(box, box->events[bit]);
1897
1898         local_irq_restore(flags);
1899
1900         hrtimer_forward_now(hrtimer, ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL));
1901         return HRTIMER_RESTART;
1902 }
1903
1904 static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
1905 {
1906         __hrtimer_start_range_ns(&box->hrtimer,
1907                         ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL), 0,
1908                         HRTIMER_MODE_REL_PINNED, 0);
1909 }
1910
1911 static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
1912 {
1913         hrtimer_cancel(&box->hrtimer);
1914 }
1915
1916 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
1917 {
1918         hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1919         box->hrtimer.function = uncore_pmu_hrtimer;
1920 }
1921
1922 struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int cpu)
1923 {
1924         struct intel_uncore_box *box;
1925         int i, size;
1926
1927         size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
1928
1929         box = kmalloc_node(size, GFP_KERNEL | __GFP_ZERO, cpu_to_node(cpu));
1930         if (!box)
1931                 return NULL;
1932
1933         for (i = 0; i < type->num_shared_regs; i++)
1934                 raw_spin_lock_init(&box->shared_regs[i].lock);
1935
1936         uncore_pmu_init_hrtimer(box);
1937         atomic_set(&box->refcnt, 1);
1938         box->cpu = -1;
1939         box->phys_id = -1;
1940
1941         return box;
1942 }
1943
1944 static struct intel_uncore_box *
1945 uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
1946 {
1947         static struct intel_uncore_box *box;
1948
1949         box = *per_cpu_ptr(pmu->box, cpu);
1950         if (box)
1951                 return box;
1952
1953         raw_spin_lock(&uncore_box_lock);
1954         list_for_each_entry(box, &pmu->box_list, list) {
1955                 if (box->phys_id == topology_physical_package_id(cpu)) {
1956                         atomic_inc(&box->refcnt);
1957                         *per_cpu_ptr(pmu->box, cpu) = box;
1958                         break;
1959                 }
1960         }
1961         raw_spin_unlock(&uncore_box_lock);
1962
1963         return *per_cpu_ptr(pmu->box, cpu);
1964 }
1965
1966 static struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
1967 {
1968         return container_of(event->pmu, struct intel_uncore_pmu, pmu);
1969 }
1970
1971 static struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
1972 {
1973         /*
1974          * perf core schedules event on the basis of cpu, uncore events are
1975          * collected by one of the cpus inside a physical package.
1976          */
1977         return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
1978 }
1979
1980 static int
1981 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
1982 {
1983         struct perf_event *event;
1984         int n, max_count;
1985
1986         max_count = box->pmu->type->num_counters;
1987         if (box->pmu->type->fixed_ctl)
1988                 max_count++;
1989
1990         if (box->n_events >= max_count)
1991                 return -EINVAL;
1992
1993         n = box->n_events;
1994         box->event_list[n] = leader;
1995         n++;
1996         if (!dogrp)
1997                 return n;
1998
1999         list_for_each_entry(event, &leader->sibling_list, group_entry) {
2000                 if (event->state <= PERF_EVENT_STATE_OFF)
2001                         continue;
2002
2003                 if (n >= max_count)
2004                         return -EINVAL;
2005
2006                 box->event_list[n] = event;
2007                 n++;
2008         }
2009         return n;
2010 }
2011
2012 static struct event_constraint *
2013 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
2014 {
2015         struct intel_uncore_type *type = box->pmu->type;
2016         struct event_constraint *c;
2017
2018         if (type->ops->get_constraint) {
2019                 c = type->ops->get_constraint(box, event);
2020                 if (c)
2021                         return c;
2022         }
2023
2024         if (event->hw.config == ~0ULL)
2025                 return &constraint_fixed;
2026
2027         if (type->constraints) {
2028                 for_each_event_constraint(c, type->constraints) {
2029                         if ((event->hw.config & c->cmask) == c->code)
2030                                 return c;
2031                 }
2032         }
2033
2034         return &type->unconstrainted;
2035 }
2036
2037 static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
2038 {
2039         if (box->pmu->type->ops->put_constraint)
2040                 box->pmu->type->ops->put_constraint(box, event);
2041 }
2042
2043 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
2044 {
2045         unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
2046         struct event_constraint *c, *constraints[UNCORE_PMC_IDX_MAX];
2047         int i, wmin, wmax, ret = 0;
2048         struct hw_perf_event *hwc;
2049
2050         bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
2051
2052         for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
2053                 c = uncore_get_event_constraint(box, box->event_list[i]);
2054                 constraints[i] = c;
2055                 wmin = min(wmin, c->weight);
2056                 wmax = max(wmax, c->weight);
2057         }
2058
2059         /* fastpath, try to reuse previous register */
2060         for (i = 0; i < n; i++) {
2061                 hwc = &box->event_list[i]->hw;
2062                 c = constraints[i];
2063
2064                 /* never assigned */
2065                 if (hwc->idx == -1)
2066                         break;
2067
2068                 /* constraint still honored */
2069                 if (!test_bit(hwc->idx, c->idxmsk))
2070                         break;
2071
2072                 /* not already used */
2073                 if (test_bit(hwc->idx, used_mask))
2074                         break;
2075
2076                 __set_bit(hwc->idx, used_mask);
2077                 if (assign)
2078                         assign[i] = hwc->idx;
2079         }
2080         /* slow path */
2081         if (i != n)
2082                 ret = perf_assign_events(constraints, n, wmin, wmax, assign);
2083
2084         if (!assign || ret) {
2085                 for (i = 0; i < n; i++)
2086                         uncore_put_event_constraint(box, box->event_list[i]);
2087         }
2088         return ret ? -EINVAL : 0;
2089 }
2090
2091 static void uncore_pmu_event_start(struct perf_event *event, int flags)
2092 {
2093         struct intel_uncore_box *box = uncore_event_to_box(event);
2094         int idx = event->hw.idx;
2095
2096         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
2097                 return;
2098
2099         if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
2100                 return;
2101
2102         event->hw.state = 0;
2103         box->events[idx] = event;
2104         box->n_active++;
2105         __set_bit(idx, box->active_mask);
2106
2107         local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
2108         uncore_enable_event(box, event);
2109
2110         if (box->n_active == 1) {
2111                 uncore_enable_box(box);
2112                 uncore_pmu_start_hrtimer(box);
2113         }
2114 }
2115
2116 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
2117 {
2118         struct intel_uncore_box *box = uncore_event_to_box(event);
2119         struct hw_perf_event *hwc = &event->hw;
2120
2121         if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
2122                 uncore_disable_event(box, event);
2123                 box->n_active--;
2124                 box->events[hwc->idx] = NULL;
2125                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
2126                 hwc->state |= PERF_HES_STOPPED;
2127
2128                 if (box->n_active == 0) {
2129                         uncore_disable_box(box);
2130                         uncore_pmu_cancel_hrtimer(box);
2131                 }
2132         }
2133
2134         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
2135                 /*
2136                  * Drain the remaining delta count out of a event
2137                  * that we are disabling:
2138                  */
2139                 uncore_perf_event_update(box, event);
2140                 hwc->state |= PERF_HES_UPTODATE;
2141         }
2142 }
2143
2144 static int uncore_pmu_event_add(struct perf_event *event, int flags)
2145 {
2146         struct intel_uncore_box *box = uncore_event_to_box(event);
2147         struct hw_perf_event *hwc = &event->hw;
2148         int assign[UNCORE_PMC_IDX_MAX];
2149         int i, n, ret;
2150
2151         if (!box)
2152                 return -ENODEV;
2153
2154         ret = n = uncore_collect_events(box, event, false);
2155         if (ret < 0)
2156                 return ret;
2157
2158         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
2159         if (!(flags & PERF_EF_START))
2160                 hwc->state |= PERF_HES_ARCH;
2161
2162         ret = uncore_assign_events(box, assign, n);
2163         if (ret)
2164                 return ret;
2165
2166         /* save events moving to new counters */
2167         for (i = 0; i < box->n_events; i++) {
2168                 event = box->event_list[i];
2169                 hwc = &event->hw;
2170
2171                 if (hwc->idx == assign[i] &&
2172                         hwc->last_tag == box->tags[assign[i]])
2173                         continue;
2174                 /*
2175                  * Ensure we don't accidentally enable a stopped
2176                  * counter simply because we rescheduled.
2177                  */
2178                 if (hwc->state & PERF_HES_STOPPED)
2179                         hwc->state |= PERF_HES_ARCH;
2180
2181                 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
2182         }
2183
2184         /* reprogram moved events into new counters */
2185         for (i = 0; i < n; i++) {
2186                 event = box->event_list[i];
2187                 hwc = &event->hw;
2188
2189                 if (hwc->idx != assign[i] ||
2190                         hwc->last_tag != box->tags[assign[i]])
2191                         uncore_assign_hw_event(box, event, assign[i]);
2192                 else if (i < box->n_events)
2193                         continue;
2194
2195                 if (hwc->state & PERF_HES_ARCH)
2196                         continue;
2197
2198                 uncore_pmu_event_start(event, 0);
2199         }
2200         box->n_events = n;
2201
2202         return 0;
2203 }
2204
2205 static void uncore_pmu_event_del(struct perf_event *event, int flags)
2206 {
2207         struct intel_uncore_box *box = uncore_event_to_box(event);
2208         int i;
2209
2210         uncore_pmu_event_stop(event, PERF_EF_UPDATE);
2211
2212         for (i = 0; i < box->n_events; i++) {
2213                 if (event == box->event_list[i]) {
2214                         uncore_put_event_constraint(box, event);
2215
2216                         while (++i < box->n_events)
2217                                 box->event_list[i - 1] = box->event_list[i];
2218
2219                         --box->n_events;
2220                         break;
2221                 }
2222         }
2223
2224         event->hw.idx = -1;
2225         event->hw.last_tag = ~0ULL;
2226 }
2227
2228 static void uncore_pmu_event_read(struct perf_event *event)
2229 {
2230         struct intel_uncore_box *box = uncore_event_to_box(event);
2231         uncore_perf_event_update(box, event);
2232 }
2233
2234 /*
2235  * validation ensures the group can be loaded onto the
2236  * PMU if it was the only group available.
2237  */
2238 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
2239                                 struct perf_event *event)
2240 {
2241         struct perf_event *leader = event->group_leader;
2242         struct intel_uncore_box *fake_box;
2243         int ret = -EINVAL, n;
2244
2245         fake_box = uncore_alloc_box(pmu->type, smp_processor_id());
2246         if (!fake_box)
2247                 return -ENOMEM;
2248
2249         fake_box->pmu = pmu;
2250         /*
2251          * the event is not yet connected with its
2252          * siblings therefore we must first collect
2253          * existing siblings, then add the new event
2254          * before we can simulate the scheduling
2255          */
2256         n = uncore_collect_events(fake_box, leader, true);
2257         if (n < 0)
2258                 goto out;
2259
2260         fake_box->n_events = n;
2261         n = uncore_collect_events(fake_box, event, false);
2262         if (n < 0)
2263                 goto out;
2264
2265         fake_box->n_events = n;
2266
2267         ret = uncore_assign_events(fake_box, NULL, n);
2268 out:
2269         kfree(fake_box);
2270         return ret;
2271 }
2272
2273 int uncore_pmu_event_init(struct perf_event *event)
2274 {
2275         struct intel_uncore_pmu *pmu;
2276         struct intel_uncore_box *box;
2277         struct hw_perf_event *hwc = &event->hw;
2278         int ret;
2279
2280         if (event->attr.type != event->pmu->type)
2281                 return -ENOENT;
2282
2283         pmu = uncore_event_to_pmu(event);
2284         /* no device found for this pmu */
2285         if (pmu->func_id < 0)
2286                 return -ENOENT;
2287
2288         /*
2289          * Uncore PMU does measure at all privilege level all the time.
2290          * So it doesn't make sense to specify any exclude bits.
2291          */
2292         if (event->attr.exclude_user || event->attr.exclude_kernel ||
2293                         event->attr.exclude_hv || event->attr.exclude_idle)
2294                 return -EINVAL;
2295
2296         /* Sampling not supported yet */
2297         if (hwc->sample_period)
2298                 return -EINVAL;
2299
2300         /*
2301          * Place all uncore events for a particular physical package
2302          * onto a single cpu
2303          */
2304         if (event->cpu < 0)
2305                 return -EINVAL;
2306         box = uncore_pmu_to_box(pmu, event->cpu);
2307         if (!box || box->cpu < 0)
2308                 return -EINVAL;
2309         event->cpu = box->cpu;
2310
2311         event->hw.idx = -1;
2312         event->hw.last_tag = ~0ULL;
2313         event->hw.extra_reg.idx = EXTRA_REG_NONE;
2314         event->hw.branch_reg.idx = EXTRA_REG_NONE;
2315
2316         if (event->attr.config == UNCORE_FIXED_EVENT) {
2317                 /* no fixed counter */
2318                 if (!pmu->type->fixed_ctl)
2319                         return -EINVAL;
2320                 /*
2321                  * if there is only one fixed counter, only the first pmu
2322                  * can access the fixed counter
2323                  */
2324                 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
2325                         return -EINVAL;
2326                 hwc->config = ~0ULL;
2327         } else {
2328                 hwc->config = event->attr.config & pmu->type->event_mask;
2329                 if (pmu->type->ops->hw_config) {
2330                         ret = pmu->type->ops->hw_config(box, event);
2331                         if (ret)
2332                                 return ret;
2333                 }
2334         }
2335
2336         if (event->group_leader != event)
2337                 ret = uncore_validate_group(pmu, event);
2338         else
2339                 ret = 0;
2340
2341         return ret;
2342 }
2343
2344 static int __init uncore_pmu_register(struct intel_uncore_pmu *pmu)
2345 {
2346         int ret;
2347
2348         pmu->pmu = (struct pmu) {
2349                 .attr_groups    = pmu->type->attr_groups,
2350                 .task_ctx_nr    = perf_invalid_context,
2351                 .event_init     = uncore_pmu_event_init,
2352                 .add            = uncore_pmu_event_add,
2353                 .del            = uncore_pmu_event_del,
2354                 .start          = uncore_pmu_event_start,
2355                 .stop           = uncore_pmu_event_stop,
2356                 .read           = uncore_pmu_event_read,
2357         };
2358
2359         if (pmu->type->num_boxes == 1) {
2360                 if (strlen(pmu->type->name) > 0)
2361                         sprintf(pmu->name, "uncore_%s", pmu->type->name);
2362                 else
2363                         sprintf(pmu->name, "uncore");
2364         } else {
2365                 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
2366                         pmu->pmu_idx);
2367         }
2368
2369         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
2370         return ret;
2371 }
2372
2373 static void __init uncore_type_exit(struct intel_uncore_type *type)
2374 {
2375         int i;
2376
2377         for (i = 0; i < type->num_boxes; i++)
2378                 free_percpu(type->pmus[i].box);
2379         kfree(type->pmus);
2380         type->pmus = NULL;
2381         kfree(type->attr_groups[1]);
2382         type->attr_groups[1] = NULL;
2383 }
2384
2385 static void __init uncore_types_exit(struct intel_uncore_type **types)
2386 {
2387         int i;
2388         for (i = 0; types[i]; i++)
2389                 uncore_type_exit(types[i]);
2390 }
2391
2392 static int __init uncore_type_init(struct intel_uncore_type *type)
2393 {
2394         struct intel_uncore_pmu *pmus;
2395         struct attribute_group *events_group;
2396         struct attribute **attrs;
2397         int i, j;
2398
2399         pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
2400         if (!pmus)
2401                 return -ENOMEM;
2402
2403         type->unconstrainted = (struct event_constraint)
2404                 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
2405                                 0, type->num_counters, 0);
2406
2407         for (i = 0; i < type->num_boxes; i++) {
2408                 pmus[i].func_id = -1;
2409                 pmus[i].pmu_idx = i;
2410                 pmus[i].type = type;
2411                 INIT_LIST_HEAD(&pmus[i].box_list);
2412                 pmus[i].box = alloc_percpu(struct intel_uncore_box *);
2413                 if (!pmus[i].box)
2414                         goto fail;
2415         }
2416
2417         if (type->event_descs) {
2418                 i = 0;
2419                 while (type->event_descs[i].attr.attr.name)
2420                         i++;
2421
2422                 events_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
2423                                         sizeof(*events_group), GFP_KERNEL);
2424                 if (!events_group)
2425                         goto fail;
2426
2427                 attrs = (struct attribute **)(events_group + 1);
2428                 events_group->name = "events";
2429                 events_group->attrs = attrs;
2430
2431                 for (j = 0; j < i; j++)
2432                         attrs[j] = &type->event_descs[j].attr.attr;
2433
2434                 type->attr_groups[1] = events_group;
2435         }
2436
2437         type->pmus = pmus;
2438         return 0;
2439 fail:
2440         uncore_type_exit(type);
2441         return -ENOMEM;
2442 }
2443
2444 static int __init uncore_types_init(struct intel_uncore_type **types)
2445 {
2446         int i, ret;
2447
2448         for (i = 0; types[i]; i++) {
2449                 ret = uncore_type_init(types[i]);
2450                 if (ret)
2451                         goto fail;
2452         }
2453         return 0;
2454 fail:
2455         while (--i >= 0)
2456                 uncore_type_exit(types[i]);
2457         return ret;
2458 }
2459
2460 static struct pci_driver *uncore_pci_driver;
2461 static bool pcidrv_registered;
2462
2463 /*
2464  * add a pci uncore device
2465  */
2466 static int __devinit uncore_pci_add(struct intel_uncore_type *type, struct pci_dev *pdev)
2467 {
2468         struct intel_uncore_pmu *pmu;
2469         struct intel_uncore_box *box;
2470         int i, phys_id;
2471
2472         phys_id = pcibus_to_physid[pdev->bus->number];
2473         if (phys_id < 0)
2474                 return -ENODEV;
2475
2476         box = uncore_alloc_box(type, 0);
2477         if (!box)
2478                 return -ENOMEM;
2479
2480         /*
2481          * for performance monitoring unit with multiple boxes,
2482          * each box has a different function id.
2483          */
2484         for (i = 0; i < type->num_boxes; i++) {
2485                 pmu = &type->pmus[i];
2486                 if (pmu->func_id == pdev->devfn)
2487                         break;
2488                 if (pmu->func_id < 0) {
2489                         pmu->func_id = pdev->devfn;
2490                         break;
2491                 }
2492                 pmu = NULL;
2493         }
2494
2495         if (!pmu) {
2496                 kfree(box);
2497                 return -EINVAL;
2498         }
2499
2500         box->phys_id = phys_id;
2501         box->pci_dev = pdev;
2502         box->pmu = pmu;
2503         uncore_box_init(box);
2504         pci_set_drvdata(pdev, box);
2505
2506         raw_spin_lock(&uncore_box_lock);
2507         list_add_tail(&box->list, &pmu->box_list);
2508         raw_spin_unlock(&uncore_box_lock);
2509
2510         return 0;
2511 }
2512
2513 static void uncore_pci_remove(struct pci_dev *pdev)
2514 {
2515         struct intel_uncore_box *box = pci_get_drvdata(pdev);
2516         struct intel_uncore_pmu *pmu = box->pmu;
2517         int cpu, phys_id = pcibus_to_physid[pdev->bus->number];
2518
2519         if (WARN_ON_ONCE(phys_id != box->phys_id))
2520                 return;
2521
2522         raw_spin_lock(&uncore_box_lock);
2523         list_del(&box->list);
2524         raw_spin_unlock(&uncore_box_lock);
2525
2526         for_each_possible_cpu(cpu) {
2527                 if (*per_cpu_ptr(pmu->box, cpu) == box) {
2528                         *per_cpu_ptr(pmu->box, cpu) = NULL;
2529                         atomic_dec(&box->refcnt);
2530                 }
2531         }
2532
2533         WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
2534         kfree(box);
2535 }
2536
2537 static int __devinit uncore_pci_probe(struct pci_dev *pdev,
2538                                 const struct pci_device_id *id)
2539 {
2540         struct intel_uncore_type *type;
2541
2542         type = (struct intel_uncore_type *)id->driver_data;
2543
2544         return uncore_pci_add(type, pdev);
2545 }
2546
2547 static int __init uncore_pci_init(void)
2548 {
2549         int ret;
2550
2551         switch (boot_cpu_data.x86_model) {
2552         case 45: /* Sandy Bridge-EP */
2553                 pci_uncores = snbep_pci_uncores;
2554                 uncore_pci_driver = &snbep_uncore_pci_driver;
2555                 snbep_pci2phy_map_init();
2556                 break;
2557         default:
2558                 return 0;
2559         }
2560
2561         ret = uncore_types_init(pci_uncores);
2562         if (ret)
2563                 return ret;
2564
2565         uncore_pci_driver->probe = uncore_pci_probe;
2566         uncore_pci_driver->remove = uncore_pci_remove;
2567
2568         ret = pci_register_driver(uncore_pci_driver);
2569         if (ret == 0)
2570                 pcidrv_registered = true;
2571         else
2572                 uncore_types_exit(pci_uncores);
2573
2574         return ret;
2575 }
2576
2577 static void __init uncore_pci_exit(void)
2578 {
2579         if (pcidrv_registered) {
2580                 pcidrv_registered = false;
2581                 pci_unregister_driver(uncore_pci_driver);
2582                 uncore_types_exit(pci_uncores);
2583         }
2584 }
2585
2586 static void __cpuinit uncore_cpu_dying(int cpu)
2587 {
2588         struct intel_uncore_type *type;
2589         struct intel_uncore_pmu *pmu;
2590         struct intel_uncore_box *box;
2591         int i, j;
2592
2593         for (i = 0; msr_uncores[i]; i++) {
2594                 type = msr_uncores[i];
2595                 for (j = 0; j < type->num_boxes; j++) {
2596                         pmu = &type->pmus[j];
2597                         box = *per_cpu_ptr(pmu->box, cpu);
2598                         *per_cpu_ptr(pmu->box, cpu) = NULL;
2599                         if (box && atomic_dec_and_test(&box->refcnt))
2600                                 kfree(box);
2601                 }
2602         }
2603 }
2604
2605 static int __cpuinit uncore_cpu_starting(int cpu)
2606 {
2607         struct intel_uncore_type *type;
2608         struct intel_uncore_pmu *pmu;
2609         struct intel_uncore_box *box, *exist;
2610         int i, j, k, phys_id;
2611
2612         phys_id = topology_physical_package_id(cpu);
2613
2614         for (i = 0; msr_uncores[i]; i++) {
2615                 type = msr_uncores[i];
2616                 for (j = 0; j < type->num_boxes; j++) {
2617                         pmu = &type->pmus[j];
2618                         box = *per_cpu_ptr(pmu->box, cpu);
2619                         /* called by uncore_cpu_init? */
2620                         if (box && box->phys_id >= 0) {
2621                                 uncore_box_init(box);
2622                                 continue;
2623                         }
2624
2625                         for_each_online_cpu(k) {
2626                                 exist = *per_cpu_ptr(pmu->box, k);
2627                                 if (exist && exist->phys_id == phys_id) {
2628                                         atomic_inc(&exist->refcnt);
2629                                         *per_cpu_ptr(pmu->box, cpu) = exist;
2630                                         kfree(box);
2631                                         box = NULL;
2632                                         break;
2633                                 }
2634                         }
2635
2636                         if (box) {
2637                                 box->phys_id = phys_id;
2638                                 uncore_box_init(box);
2639                         }
2640                 }
2641         }
2642         return 0;
2643 }
2644
2645 static int __cpuinit uncore_cpu_prepare(int cpu, int phys_id)
2646 {
2647         struct intel_uncore_type *type;
2648         struct intel_uncore_pmu *pmu;
2649         struct intel_uncore_box *box;
2650         int i, j;
2651
2652         for (i = 0; msr_uncores[i]; i++) {
2653                 type = msr_uncores[i];
2654                 for (j = 0; j < type->num_boxes; j++) {
2655                         pmu = &type->pmus[j];
2656                         if (pmu->func_id < 0)
2657                                 pmu->func_id = j;
2658
2659                         box = uncore_alloc_box(type, cpu);
2660                         if (!box)
2661                                 return -ENOMEM;
2662
2663                         box->pmu = pmu;
2664                         box->phys_id = phys_id;
2665                         *per_cpu_ptr(pmu->box, cpu) = box;
2666                 }
2667         }
2668         return 0;
2669 }
2670
2671 static void __cpuinit
2672 uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
2673 {
2674         struct intel_uncore_type *type;
2675         struct intel_uncore_pmu *pmu;
2676         struct intel_uncore_box *box;
2677         int i, j;
2678
2679         for (i = 0; uncores[i]; i++) {
2680                 type = uncores[i];
2681                 for (j = 0; j < type->num_boxes; j++) {
2682                         pmu = &type->pmus[j];
2683                         if (old_cpu < 0)
2684                                 box = uncore_pmu_to_box(pmu, new_cpu);
2685                         else
2686                                 box = uncore_pmu_to_box(pmu, old_cpu);
2687                         if (!box)
2688                                 continue;
2689
2690                         if (old_cpu < 0) {
2691                                 WARN_ON_ONCE(box->cpu != -1);
2692                                 box->cpu = new_cpu;
2693                                 continue;
2694                         }
2695
2696                         WARN_ON_ONCE(box->cpu != old_cpu);
2697                         if (new_cpu >= 0) {
2698                                 uncore_pmu_cancel_hrtimer(box);
2699                                 perf_pmu_migrate_context(&pmu->pmu,
2700                                                 old_cpu, new_cpu);
2701                                 box->cpu = new_cpu;
2702                         } else {
2703                                 box->cpu = -1;
2704                         }
2705                 }
2706         }
2707 }
2708
2709 static void __cpuinit uncore_event_exit_cpu(int cpu)
2710 {
2711         int i, phys_id, target;
2712
2713         /* if exiting cpu is used for collecting uncore events */
2714         if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
2715                 return;
2716
2717         /* find a new cpu to collect uncore events */
2718         phys_id = topology_physical_package_id(cpu);
2719         target = -1;
2720         for_each_online_cpu(i) {
2721                 if (i == cpu)
2722                         continue;
2723                 if (phys_id == topology_physical_package_id(i)) {
2724                         target = i;
2725                         break;
2726                 }
2727         }
2728
2729         /* migrate uncore events to the new cpu */
2730         if (target >= 0)
2731                 cpumask_set_cpu(target, &uncore_cpu_mask);
2732
2733         uncore_change_context(msr_uncores, cpu, target);
2734         uncore_change_context(pci_uncores, cpu, target);
2735 }
2736
2737 static void __cpuinit uncore_event_init_cpu(int cpu)
2738 {
2739         int i, phys_id;
2740
2741         phys_id = topology_physical_package_id(cpu);
2742         for_each_cpu(i, &uncore_cpu_mask) {
2743                 if (phys_id == topology_physical_package_id(i))
2744                         return;
2745         }
2746
2747         cpumask_set_cpu(cpu, &uncore_cpu_mask);
2748
2749         uncore_change_context(msr_uncores, -1, cpu);
2750         uncore_change_context(pci_uncores, -1, cpu);
2751 }
2752
2753 static int
2754  __cpuinit uncore_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
2755 {
2756         unsigned int cpu = (long)hcpu;
2757
2758         /* allocate/free data structure for uncore box */
2759         switch (action & ~CPU_TASKS_FROZEN) {
2760         case CPU_UP_PREPARE:
2761                 uncore_cpu_prepare(cpu, -1);
2762                 break;
2763         case CPU_STARTING:
2764                 uncore_cpu_starting(cpu);
2765                 break;
2766         case CPU_UP_CANCELED:
2767         case CPU_DYING:
2768                 uncore_cpu_dying(cpu);
2769                 break;
2770         default:
2771                 break;
2772         }
2773
2774         /* select the cpu that collects uncore events */
2775         switch (action & ~CPU_TASKS_FROZEN) {
2776         case CPU_DOWN_FAILED:
2777         case CPU_STARTING:
2778                 uncore_event_init_cpu(cpu);
2779                 break;
2780         case CPU_DOWN_PREPARE:
2781                 uncore_event_exit_cpu(cpu);
2782                 break;
2783         default:
2784                 break;
2785         }
2786
2787         return NOTIFY_OK;
2788 }
2789
2790 static struct notifier_block uncore_cpu_nb __cpuinitdata = {
2791         .notifier_call  = uncore_cpu_notifier,
2792         /*
2793          * to migrate uncore events, our notifier should be executed
2794          * before perf core's notifier.
2795          */
2796         .priority       = CPU_PRI_PERF + 1,
2797 };
2798
2799 static void __init uncore_cpu_setup(void *dummy)
2800 {
2801         uncore_cpu_starting(smp_processor_id());
2802 }
2803
2804 static int __init uncore_cpu_init(void)
2805 {
2806         int ret, cpu, max_cores;
2807
2808         max_cores = boot_cpu_data.x86_max_cores;
2809         switch (boot_cpu_data.x86_model) {
2810         case 26: /* Nehalem */
2811         case 30:
2812         case 37: /* Westmere */
2813         case 44:
2814                 msr_uncores = nhm_msr_uncores;
2815                 break;
2816         case 42: /* Sandy Bridge */
2817                 if (snb_uncore_cbox.num_boxes > max_cores)
2818                         snb_uncore_cbox.num_boxes = max_cores;
2819                 msr_uncores = snb_msr_uncores;
2820                 break;
2821         case 45: /* Sandy Birdge-EP */
2822                 if (snbep_uncore_cbox.num_boxes > max_cores)
2823                         snbep_uncore_cbox.num_boxes = max_cores;
2824                 msr_uncores = snbep_msr_uncores;
2825                 break;
2826         case 46: /* Nehalem-EX */
2827                 uncore_nhmex = true;
2828         case 47: /* Westmere-EX aka. Xeon E7 */
2829                 if (!uncore_nhmex)
2830                         nhmex_uncore_mbox.event_descs = wsmex_uncore_mbox_events;
2831                 if (nhmex_uncore_cbox.num_boxes > max_cores)
2832                         nhmex_uncore_cbox.num_boxes = max_cores;
2833                 msr_uncores = nhmex_msr_uncores;
2834                 break;
2835         default:
2836                 return 0;
2837         }
2838
2839         ret = uncore_types_init(msr_uncores);
2840         if (ret)
2841                 return ret;
2842
2843         get_online_cpus();
2844
2845         for_each_online_cpu(cpu) {
2846                 int i, phys_id = topology_physical_package_id(cpu);
2847
2848                 for_each_cpu(i, &uncore_cpu_mask) {
2849                         if (phys_id == topology_physical_package_id(i)) {
2850                                 phys_id = -1;
2851                                 break;
2852                         }
2853                 }
2854                 if (phys_id < 0)
2855                         continue;
2856
2857                 uncore_cpu_prepare(cpu, phys_id);
2858                 uncore_event_init_cpu(cpu);
2859         }
2860         on_each_cpu(uncore_cpu_setup, NULL, 1);
2861
2862         register_cpu_notifier(&uncore_cpu_nb);
2863
2864         put_online_cpus();
2865
2866         return 0;
2867 }
2868
2869 static int __init uncore_pmus_register(void)
2870 {
2871         struct intel_uncore_pmu *pmu;
2872         struct intel_uncore_type *type;
2873         int i, j;
2874
2875         for (i = 0; msr_uncores[i]; i++) {
2876                 type = msr_uncores[i];
2877                 for (j = 0; j < type->num_boxes; j++) {
2878                         pmu = &type->pmus[j];
2879                         uncore_pmu_register(pmu);
2880                 }
2881         }
2882
2883         for (i = 0; pci_uncores[i]; i++) {
2884                 type = pci_uncores[i];
2885                 for (j = 0; j < type->num_boxes; j++) {
2886                         pmu = &type->pmus[j];
2887                         uncore_pmu_register(pmu);
2888                 }
2889         }
2890
2891         return 0;
2892 }
2893
2894 static int __init intel_uncore_init(void)
2895 {
2896         int ret;
2897
2898         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2899                 return -ENODEV;
2900
2901         ret = uncore_pci_init();
2902         if (ret)
2903                 goto fail;
2904         ret = uncore_cpu_init();
2905         if (ret) {
2906                 uncore_pci_exit();
2907                 goto fail;
2908         }
2909
2910         uncore_pmus_register();
2911         return 0;
2912 fail:
2913         return ret;
2914 }
2915 device_initcall(intel_uncore_init);