1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
34 * We handle most unaligned accesses in hardware. On the other hand
35 * unaligned DMA can be quite expensive on some Nehalem processors.
37 * Based on this we disable the IP header alignment in network drivers.
39 #define NET_IP_ALIGN 0
43 * Default implementation of macro that returns current
44 * instruction pointer ("program counter").
46 static inline void *current_text_addr(void)
50 asm volatile("mov $1f, %0; 1:":"=r" (pc));
55 #ifdef CONFIG_X86_VSMP
56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
59 # define ARCH_MIN_TASKALIGN 16
60 # define ARCH_MIN_MMSTRUCT_ALIGN 0
68 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
69 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
70 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
71 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
72 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
73 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
75 extern s8 __read_mostly tlb_flushall_shift;
78 * CPU type and hardware bug flags. Kept separately for each CPU.
79 * Members of this structure are referenced in head.S, so think twice
80 * before touching them. [mj]
84 __u8 x86; /* CPU family */
85 __u8 x86_vendor; /* CPU vendor */
89 char wp_works_ok; /* It doesn't on 386's */
91 /* Problems on some 486Dx4's and old 386's: */
96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
101 /* CPUID returned core id bits: */
102 __u8 x86_coreid_bits;
103 /* Max extended CPUID function supported: */
104 __u32 extended_cpuid_level;
105 /* Maximum supported CPUID level, -1=no CPUID: */
107 __u32 x86_capability[NCAPINTS + NBUGINTS];
108 char x86_vendor_id[16];
109 char x86_model_id[64];
110 /* in KB - valid for CPUS which support this call: */
112 int x86_cache_alignment; /* In bytes */
114 unsigned long loops_per_jiffy;
115 /* cpuid returned max cores value: */
119 u16 x86_clflush_size;
120 /* number of cores as seen by the OS: */
122 /* Physical processor id: */
126 /* Compute unit id */
128 /* Index into per_cpu list: */
131 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
133 #define X86_VENDOR_INTEL 0
134 #define X86_VENDOR_CYRIX 1
135 #define X86_VENDOR_AMD 2
136 #define X86_VENDOR_UMC 3
137 #define X86_VENDOR_CENTAUR 5
138 #define X86_VENDOR_TRANSMETA 7
139 #define X86_VENDOR_NSC 8
140 #define X86_VENDOR_NUM 9
142 #define X86_VENDOR_UNKNOWN 0xff
145 * capabilities of CPUs
147 extern struct cpuinfo_x86 boot_cpu_data;
148 extern struct cpuinfo_x86 new_cpu_data;
150 extern struct tss_struct doublefault_tss;
151 extern __u32 cpu_caps_cleared[NCAPINTS];
152 extern __u32 cpu_caps_set[NCAPINTS];
155 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
156 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
158 #define cpu_info boot_cpu_data
159 #define cpu_data(cpu) boot_cpu_data
162 extern const struct seq_operations cpuinfo_op;
164 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
166 extern void cpu_detect(struct cpuinfo_x86 *c);
167 extern void fpu_detect(struct cpuinfo_x86 *c);
169 extern void early_cpu_init(void);
170 extern void identify_boot_cpu(void);
171 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
172 extern void print_cpu_info(struct cpuinfo_x86 *);
173 void print_cpu_msr(struct cpuinfo_x86 *);
174 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
175 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
176 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
178 extern void detect_extended_topology(struct cpuinfo_x86 *c);
179 extern void detect_ht(struct cpuinfo_x86 *c);
182 extern int have_cpuid_p(void);
184 static inline int have_cpuid_p(void)
189 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
190 unsigned int *ecx, unsigned int *edx)
192 /* ecx is often an input as well as an output. */
198 : "0" (*eax), "2" (*ecx)
202 static inline void load_cr3(pgd_t *pgdir)
204 write_cr3(__pa(pgdir));
208 /* This is the TSS defined by the hardware. */
210 unsigned short back_link, __blh;
212 unsigned short ss0, __ss0h;
214 /* ss1 caches MSR_IA32_SYSENTER_CS: */
215 unsigned short ss1, __ss1h;
217 unsigned short ss2, __ss2h;
229 unsigned short es, __esh;
230 unsigned short cs, __csh;
231 unsigned short ss, __ssh;
232 unsigned short ds, __dsh;
233 unsigned short fs, __fsh;
234 unsigned short gs, __gsh;
235 unsigned short ldt, __ldth;
236 unsigned short trace;
237 unsigned short io_bitmap_base;
239 } __attribute__((packed));
253 } __attribute__((packed)) ____cacheline_aligned;
259 #define IO_BITMAP_BITS 65536
260 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
261 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
262 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
263 #define INVALID_IO_BITMAP_OFFSET 0x8000
267 * The hardware state:
269 struct x86_hw_tss x86_tss;
272 * The extra 1 is there because the CPU will access an
273 * additional byte beyond the end of the IO permission
274 * bitmap. The extra byte must be all 1 bits, and must
275 * be within the limit.
277 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
280 * .. and then another 0x100 bytes for the emergency kernel stack:
282 unsigned long stack[64];
284 } ____cacheline_aligned;
286 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
289 * Save the original ist values for checking stack pointers during debugging
292 unsigned long ist[7];
295 #define MXCSR_DEFAULT 0x1f80
297 struct i387_fsave_struct {
298 u32 cwd; /* FPU Control Word */
299 u32 swd; /* FPU Status Word */
300 u32 twd; /* FPU Tag Word */
301 u32 fip; /* FPU IP Offset */
302 u32 fcs; /* FPU IP Selector */
303 u32 foo; /* FPU Operand Pointer Offset */
304 u32 fos; /* FPU Operand Pointer Selector */
306 /* 8*10 bytes for each FP-reg = 80 bytes: */
309 /* Software status information [not touched by FSAVE ]: */
313 struct i387_fxsave_struct {
314 u16 cwd; /* Control Word */
315 u16 swd; /* Status Word */
316 u16 twd; /* Tag Word */
317 u16 fop; /* Last Instruction Opcode */
320 u64 rip; /* Instruction Pointer */
321 u64 rdp; /* Data Pointer */
324 u32 fip; /* FPU IP Offset */
325 u32 fcs; /* FPU IP Selector */
326 u32 foo; /* FPU Operand Offset */
327 u32 fos; /* FPU Operand Selector */
330 u32 mxcsr; /* MXCSR Register State */
331 u32 mxcsr_mask; /* MXCSR Mask */
333 /* 8*16 bytes for each FP-reg = 128 bytes: */
336 /* 16*16 bytes for each XMM-reg = 256 bytes: */
346 } __attribute__((aligned(16)));
348 struct i387_soft_struct {
356 /* 8*10 bytes for each FP-reg = 80 bytes: */
364 struct math_emu_info *info;
369 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
373 /* We don't support LWP yet: */
378 struct bndregs_struct {
382 struct bndcsr_struct {
387 struct xsave_hdr_struct {
391 } __attribute__((packed));
393 struct xsave_struct {
394 struct i387_fxsave_struct i387;
395 struct xsave_hdr_struct xsave_hdr;
396 struct ymmh_struct ymmh;
397 struct lwp_struct lwp;
398 struct bndregs_struct bndregs;
399 struct bndcsr_struct bndcsr;
400 /* new processor state extensions will go here */
401 } __attribute__ ((packed, aligned (64)));
403 union thread_xstate {
404 struct i387_fsave_struct fsave;
405 struct i387_fxsave_struct fxsave;
406 struct i387_soft_struct soft;
407 struct xsave_struct xsave;
411 unsigned int last_cpu;
412 unsigned int has_fpu;
413 union thread_xstate *state;
417 DECLARE_PER_CPU(struct orig_ist, orig_ist);
419 union irq_stack_union {
420 char irq_stack[IRQ_STACK_SIZE];
422 * GCC hardcodes the stack canary as %gs:40. Since the
423 * irq_stack is the object at %gs:0, we reserve the bottom
424 * 48 bytes of the irq stack for the canary.
428 unsigned long stack_canary;
432 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
433 DECLARE_INIT_PER_CPU(irq_stack_union);
435 DECLARE_PER_CPU(char *, irq_stack_ptr);
436 DECLARE_PER_CPU(unsigned int, irq_count);
437 extern asmlinkage void ignore_sysret(void);
439 #ifdef CONFIG_CC_STACKPROTECTOR
441 * Make sure stack canary segment base is cached-aligned:
442 * "For Intel Atom processors, avoid non zero segment base address
443 * that is not aligned to cache line boundary at all cost."
444 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
446 struct stack_canary {
447 char __pad[20]; /* canary at %gs:20 */
448 unsigned long canary;
450 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
453 * per-CPU IRQ handling stacks
456 u32 stack[THREAD_SIZE/sizeof(u32)];
457 } __aligned(THREAD_SIZE);
459 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
460 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
463 extern unsigned int xstate_size;
464 extern void free_thread_xstate(struct task_struct *);
465 extern struct kmem_cache *task_xstate_cachep;
469 struct thread_struct {
470 /* Cached TLS descriptors: */
471 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
475 unsigned long sysenter_cs;
477 unsigned long usersp; /* Copy from PDA */
480 unsigned short fsindex;
481 unsigned short gsindex;
490 /* Save middle states of ptrace breakpoints */
491 struct perf_event *ptrace_bps[HBP_NUM];
492 /* Debug status used for traps, single steps, etc... */
493 unsigned long debugreg6;
494 /* Keep track of the exact dr7 value set by the user */
495 unsigned long ptrace_dr7;
498 unsigned long trap_nr;
499 unsigned long error_code;
500 /* floating point and extended processor state */
503 /* Virtual 86 mode info */
504 struct vm86_struct __user *vm86_info;
505 unsigned long screen_bitmap;
506 unsigned long v86flags;
507 unsigned long v86mask;
508 unsigned long saved_sp0;
509 unsigned int saved_fs;
510 unsigned int saved_gs;
512 /* IO permissions: */
513 unsigned long *io_bitmap_ptr;
515 /* Max allowed port in the bitmap, in bytes: */
516 unsigned io_bitmap_max;
518 * fpu_counter contains the number of consecutive context switches
519 * that the FPU is used. If this is over a threshold, the lazy fpu
520 * saving becomes unlazy to save the trap. This is an unsigned char
521 * so that after 256 times the counter wraps and the behavior turns
522 * lazy again; this to deal with bursty apps that only use FPU for
525 unsigned char fpu_counter;
529 * Set IOPL bits in EFLAGS from given mask
531 static inline void native_set_iopl_mask(unsigned mask)
536 asm volatile ("pushfl;"
543 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
548 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
550 tss->x86_tss.sp0 = thread->sp0;
552 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
553 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
554 tss->x86_tss.ss1 = thread->sysenter_cs;
555 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
560 static inline void native_swapgs(void)
563 asm volatile("swapgs" ::: "memory");
567 #ifdef CONFIG_PARAVIRT
568 #include <asm/paravirt.h>
570 #define __cpuid native_cpuid
571 #define paravirt_enabled() 0
573 static inline void load_sp0(struct tss_struct *tss,
574 struct thread_struct *thread)
576 native_load_sp0(tss, thread);
579 #define set_iopl_mask native_set_iopl_mask
580 #endif /* CONFIG_PARAVIRT */
583 * Save the cr4 feature set we're using (ie
584 * Pentium 4MB enable and PPro Global page
585 * enable), so that any CPU's that boot up
586 * after us can get the correct flags.
588 extern unsigned long mmu_cr4_features;
589 extern u32 *trampoline_cr4_features;
591 static inline void set_in_cr4(unsigned long mask)
595 mmu_cr4_features |= mask;
596 if (trampoline_cr4_features)
597 *trampoline_cr4_features = mmu_cr4_features;
603 static inline void clear_in_cr4(unsigned long mask)
607 mmu_cr4_features &= ~mask;
608 if (trampoline_cr4_features)
609 *trampoline_cr4_features = mmu_cr4_features;
620 /* Free all resources held by a thread. */
621 extern void release_thread(struct task_struct *);
623 unsigned long get_wchan(struct task_struct *p);
626 * Generic CPUID function
627 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
628 * resulting in stale register contents being returned.
630 static inline void cpuid(unsigned int op,
631 unsigned int *eax, unsigned int *ebx,
632 unsigned int *ecx, unsigned int *edx)
636 __cpuid(eax, ebx, ecx, edx);
639 /* Some CPUID calls want 'count' to be placed in ecx */
640 static inline void cpuid_count(unsigned int op, int count,
641 unsigned int *eax, unsigned int *ebx,
642 unsigned int *ecx, unsigned int *edx)
646 __cpuid(eax, ebx, ecx, edx);
650 * CPUID functions returning a single datum
652 static inline unsigned int cpuid_eax(unsigned int op)
654 unsigned int eax, ebx, ecx, edx;
656 cpuid(op, &eax, &ebx, &ecx, &edx);
661 static inline unsigned int cpuid_ebx(unsigned int op)
663 unsigned int eax, ebx, ecx, edx;
665 cpuid(op, &eax, &ebx, &ecx, &edx);
670 static inline unsigned int cpuid_ecx(unsigned int op)
672 unsigned int eax, ebx, ecx, edx;
674 cpuid(op, &eax, &ebx, &ecx, &edx);
679 static inline unsigned int cpuid_edx(unsigned int op)
681 unsigned int eax, ebx, ecx, edx;
683 cpuid(op, &eax, &ebx, &ecx, &edx);
688 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
689 static inline void rep_nop(void)
691 asm volatile("rep; nop" ::: "memory");
694 static inline void cpu_relax(void)
699 /* Stop speculative execution and prefetching of modified code. */
700 static inline void sync_core(void)
706 * Do a CPUID if available, otherwise do a jump. The jump
707 * can conveniently enough be the jump around CPUID.
709 asm volatile("cmpl %2,%1\n\t"
714 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
715 : "ebx", "ecx", "edx", "memory");
718 * CPUID is a barrier to speculative execution.
719 * Prefetched instructions are automatically
720 * invalidated when modified.
725 : "ebx", "ecx", "edx", "memory");
729 extern void select_idle_routine(const struct cpuinfo_x86 *c);
730 extern void init_amd_e400_c1e_mask(void);
732 extern unsigned long boot_option_idle_override;
733 extern bool amd_e400_c1e_detected;
735 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
738 extern void enable_sep_cpu(void);
739 extern int sysenter_setup(void);
741 extern void early_trap_init(void);
742 void early_trap_pf_init(void);
744 /* Defined in head.S */
745 extern struct desc_ptr early_gdt_descr;
747 extern void cpu_set_gdt(int);
748 extern void switch_to_new_gdt(int);
749 extern void load_percpu_segment(int);
750 extern void cpu_init(void);
752 static inline unsigned long get_debugctlmsr(void)
754 unsigned long debugctlmsr = 0;
756 #ifndef CONFIG_X86_DEBUGCTLMSR
757 if (boot_cpu_data.x86 < 6)
760 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
765 static inline void update_debugctlmsr(unsigned long debugctlmsr)
767 #ifndef CONFIG_X86_DEBUGCTLMSR
768 if (boot_cpu_data.x86 < 6)
771 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
774 extern void set_task_blockstep(struct task_struct *task, bool on);
777 * from system description table in BIOS. Mostly for MCA use, but
778 * others may find it useful:
780 extern unsigned int machine_id;
781 extern unsigned int machine_submodel_id;
782 extern unsigned int BIOS_revision;
784 /* Boot loader type from the setup header: */
785 extern int bootloader_type;
786 extern int bootloader_version;
788 extern char ignore_fpu_irq;
790 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
791 #define ARCH_HAS_PREFETCHW
792 #define ARCH_HAS_SPINLOCK_PREFETCH
795 # define BASE_PREFETCH ASM_NOP4
796 # define ARCH_HAS_PREFETCH
798 # define BASE_PREFETCH "prefetcht0 (%1)"
802 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
804 * It's not worth to care about 3dnow prefetches for the K6
805 * because they are microcoded there and very slow.
807 static inline void prefetch(const void *x)
809 alternative_input(BASE_PREFETCH,
816 * 3dnow prefetch to get an exclusive cache line.
817 * Useful for spinlocks to avoid one state transition in the
818 * cache coherency protocol:
820 static inline void prefetchw(const void *x)
822 alternative_input(BASE_PREFETCH,
828 static inline void spin_lock_prefetch(const void *x)
835 * User space process size: 3GB (default).
837 #define TASK_SIZE PAGE_OFFSET
838 #define TASK_SIZE_MAX TASK_SIZE
839 #define STACK_TOP TASK_SIZE
840 #define STACK_TOP_MAX STACK_TOP
842 #define INIT_THREAD { \
843 .sp0 = sizeof(init_stack) + (long)&init_stack, \
845 .sysenter_cs = __KERNEL_CS, \
846 .io_bitmap_ptr = NULL, \
850 * Note that the .io_bitmap member must be extra-big. This is because
851 * the CPU will access an additional byte beyond the end of the IO
852 * permission bitmap. The extra byte must be all 1 bits, and must
853 * be within the limit.
857 .sp0 = sizeof(init_stack) + (long)&init_stack, \
858 .ss0 = __KERNEL_DS, \
859 .ss1 = __KERNEL_CS, \
860 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
862 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
865 extern unsigned long thread_saved_pc(struct task_struct *tsk);
867 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
868 #define KSTK_TOP(info) \
870 unsigned long *__ptr = (unsigned long *)(info); \
871 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
875 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
876 * This is necessary to guarantee that the entire "struct pt_regs"
877 * is accessible even if the CPU haven't stored the SS/ESP registers
878 * on the stack (interrupt gate does not save these registers
879 * when switching to the same priv ring).
880 * Therefore beware: accessing the ss/esp fields of the
881 * "struct pt_regs" is possible, but they may contain the
882 * completely wrong values.
884 #define task_pt_regs(task) \
886 struct pt_regs *__regs__; \
887 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
891 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
895 * User space process size. 47bits minus one guard page.
897 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
899 /* This decides where the kernel will search for a free chunk of vm
900 * space during mmap's.
902 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
903 0xc0000000 : 0xFFFFe000)
905 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
906 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
907 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
908 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
910 #define STACK_TOP TASK_SIZE
911 #define STACK_TOP_MAX TASK_SIZE_MAX
913 #define INIT_THREAD { \
914 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
918 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
922 * Return saved PC of a blocked thread.
923 * What is this good for? it will be always the scheduler or ret_from_fork.
925 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
927 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
928 extern unsigned long KSTK_ESP(struct task_struct *task);
931 * User space RSP while inside the SYSCALL fast path
933 DECLARE_PER_CPU(unsigned long, old_rsp);
935 #endif /* CONFIG_X86_64 */
937 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
938 unsigned long new_sp);
941 * This decides where the kernel will search for a free chunk of vm
942 * space during mmap's.
944 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
946 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
948 /* Get/set a process' ability to use the timestamp counter instruction */
949 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
950 #define SET_TSC_CTL(val) set_tsc_mode((val))
952 extern int get_tsc_mode(unsigned long adr);
953 extern int set_tsc_mode(unsigned int val);
955 extern u16 amd_get_nb_id(int cpu);
957 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
959 uint32_t base, eax, signature[3];
961 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
962 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
964 if (!memcmp(sig, signature, 12) &&
965 (leaves == 0 || ((eax - base) >= leaves)))
972 extern unsigned long arch_align_stack(unsigned long sp);
973 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
975 void default_idle(void);
977 bool xen_set_default_idle(void);
979 #define xen_set_default_idle 0
982 void stop_this_cpu(void *dummy);
983 void df_debug(struct pt_regs *regs, long error_code);
984 #endif /* _ASM_X86_PROCESSOR_H */