2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
14 * Linux interrupt vectors.
17 #include <linux/linkage.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/init.h>
21 #include <asm/ptrace.h>
22 #include <asm/thread_info.h>
23 #include <asm/irqflags.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/types.h>
26 #include <asm/traps.h>
27 #include <asm/signal.h>
28 #include <hv/hypervisor.h>
30 #include <arch/interrupts.h>
31 #include <arch/spr_def.h>
33 #define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
35 #define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
37 #if CONFIG_KERNEL_PL == 1 || CONFIG_KERNEL_PL == 2
39 * Set "result" non-zero if ex1 holds the PL of the kernel
40 * (with or without ICS being set). Note this works only
41 * because we never find the PL at level 3.
43 # define IS_KERNEL_EX1(result, ex1) andi result, ex1, CONFIG_KERNEL_PL
45 # error Recode IS_KERNEL_EX1 for CONFIG_KERNEL_PL
48 .macro push_reg reg, ptr=sp, delta=-8
51 addli \ptr, \ptr, \delta
55 .macro pop_reg reg, ptr=sp, delta=8
58 addli \ptr, \ptr, \delta
62 .macro pop_reg_zero reg, zreg, ptr=sp, delta=8
66 addi \ptr, \ptr, \delta
70 .macro push_extra_callee_saves reg
71 PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
89 push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
93 .pushsection .rodata, "a"
98 moveli r0, hw2_last(1b)
101 shl16insli r0, r0, hw1(1b)
104 shl16insli r0, r0, hw0(1b)
110 * Unalign data exception fast handling: In order to handle
111 * unaligned data access, a fast JIT version is generated and stored
112 * in a specific area in user space. We first need to do a quick poke
113 * to see if the JIT is available. We use certain bits in the fault
114 * PC (3 to 9 is used for 16KB page size) as index to address the JIT
115 * code area. The first 64bit word is the fault PC, and the 2nd one is
116 * the fault bundle itself. If these 2 words both match, then we
117 * directly "iret" to JIT code. If not, a slow path is invoked to
118 * generate new JIT code. Note: the current JIT code WILL be
119 * overwritten if it existed. So, ideally we can handle 128 unalign
120 * fixups via JIT. For lookup efficiency and to effectively support
121 * tight loops with multiple unaligned reference, a simple
122 * direct-mapped cache is used.
124 * SPR_EX_CONTEXT_K_0 is modified to return to JIT code.
125 * SPR_EX_CONTEXT_K_1 has ICS set.
126 * SPR_EX_CONTEXT_0_0 is setup to user program's next PC.
127 * SPR_EX_CONTEXT_0_1 = 0.
129 .macro int_hand_unalign_fast vecnum, vecname
132 /* Put r3 in SPR_SYSTEM_SAVE_K_1. */
133 mtspr SPR_SYSTEM_SAVE_K_1, r3
135 mfspr r3, SPR_EX_CONTEXT_K_1
137 * Examine if exception comes from user without ICS set.
138 * If not, just go directly to the slow path.
140 bnez r3, hand_unalign_slow_nonuser
142 mfspr r3, SPR_SYSTEM_SAVE_K_0
144 /* Get &thread_info->unalign_jit_tmp[0] in r3. */
145 bfexts r3, r3, 0, CPU_SHIFT-1
146 mm r3, zero, LOG2_THREAD_SIZE, 63
147 addli r3, r3, THREAD_INFO_UNALIGN_JIT_TMP_OFFSET
150 * Save r0, r1, r2 into thread_info array r3 points to
151 * from low to high memory in order.
160 /* Save stored r3 value so we can revert it on a page fault. */
161 mfspr r1, SPR_SYSTEM_SAVE_K_1
165 /* Generate a SIGBUS if sp is not 8-byte aligned. */
166 bnez r2, hand_unalign_slow_badsp
170 * Get the thread_info in r0; load r1 with pc. Set the low bit of sp
171 * as an indicator to the page fault code in case we fault.
175 mfspr r1, SPR_EX_CONTEXT_K_0
178 /* Add the jit_info offset in thread_info; extract r1 [3:9] into r2. */
180 addli r0, r3, THREAD_INFO_UNALIGN_JIT_BASE_OFFSET - \
181 (THREAD_INFO_UNALIGN_JIT_TMP_OFFSET + (3 * 8))
182 bfextu r2, r1, 3, (2 + PAGE_SHIFT - UNALIGN_JIT_SHIFT)
185 /* Load the jit_info; multiply r2 by 128. */
188 shli r2, r2, UNALIGN_JIT_SHIFT
192 * If r0 is NULL, the JIT page is not mapped, so go to slow path;
193 * add offset r2 to r0 at the same time.
196 beqz r0, hand_unalign_slow
201 * We are loading from userspace (both the JIT info PC and
202 * instruction word, and the instruction word we executed)
203 * and since either could fault while holding the interrupt
204 * critical section, we must tag this region and check it in
205 * do_page_fault() to handle it properly.
207 ENTRY(__start_unalign_asm_code)
209 /* Load first word of JIT in r0 and increment r2 by 8. */
213 * Compare the PC with the 1st word in JIT; load the fault bundle
221 /* Go to slow path if PC doesn't match. */
222 beqz r0, hand_unalign_slow
225 * Load the 2nd word of JIT, which is supposed to be the fault
226 * bundle for a cache hit. Increment r2; after this bundle r2 will
227 * point to the potential start of the JIT code we want to run.
231 /* No further accesses to userspace are done after this point. */
232 ENTRY(__end_unalign_asm_code)
234 /* Compare the real bundle with what is saved in the JIT area. */
237 mtspr SPR_EX_CONTEXT_0_1, zero
240 /* Go to slow path if the fault bundle does not match. */
241 beqz r0, hand_unalign_slow
244 * A cache hit is found.
245 * r2 points to start of JIT code (3rd word).
246 * r0 is the fault pc.
247 * r1 is the fault bundle.
248 * Reset the low bit of sp.
251 mfspr r0, SPR_EX_CONTEXT_K_0
255 /* Write r2 into EX_CONTEXT_K_0 and increment PC. */
257 mtspr SPR_EX_CONTEXT_K_0, r2
262 * Set ICS on kernel EX_CONTEXT_K_1 in order to "iret" to
263 * user with ICS set. This way, if the JIT fixup causes another
264 * unalign exception (which shouldn't be possible) the user
265 * process will be terminated with SIGBUS. Also, our fixup will
266 * run without interleaving with external interrupts.
267 * Each fixup is at most 14 bundles, so it won't hold ICS for long.
270 movei r1, PL_ICS_EX1(USER_PL, 1)
271 mtspr SPR_EX_CONTEXT_0_0, r0
275 mtspr SPR_EX_CONTEXT_K_1, r1
276 addi r3, r3, -(3 * 8)
279 /* Restore r0..r3. */
286 ENDPROC(intvec_\vecname)
289 #ifdef __COLLECT_LINKER_FEEDBACK__
290 .pushsection .text.intvec_feedback,"ax"
296 * Default interrupt handler.
298 * vecnum is where we'll put this code.
299 * c_routine is the C routine we'll call.
301 * The C routine is passed two arguments:
302 * - A pointer to the pt_regs state.
303 * - The interrupt vector number.
305 * The "processing" argument specifies the code for processing
306 * the interrupt. Defaults to "handle_interrupt".
308 .macro __int_hand vecnum, vecname, c_routine,processing=handle_interrupt
310 /* Temporarily save a register so we have somewhere to work. */
312 mtspr SPR_SYSTEM_SAVE_K_1, r0
313 mfspr r0, SPR_EX_CONTEXT_K_1
316 * The unalign data fastpath code sets the low bit in sp to
317 * force us to reset it here on fault.
321 IS_KERNEL_EX1(r0, r0)
324 .ifc \vecnum, INT_DOUBLE_FAULT
326 * For double-faults from user-space, fall through to the normal
327 * register save and stack setup path. Otherwise, it's the
328 * hypervisor giving us one last chance to dump diagnostics, and we
329 * branch to the kernel_double_fault routine to do so.
332 j _kernel_double_fault
336 * If we're coming from user-space, then set sp to the top of
337 * the kernel stack. Otherwise, assume sp is already valid.
345 .ifc \c_routine, do_page_fault
347 * The page_fault handler may be downcalled directly by the
348 * hypervisor even when Linux is running and has ICS set.
350 * In this case the contents of EX_CONTEXT_K_1 reflect the
351 * previous fault and can't be relied on to choose whether or
352 * not to reinitialize the stack pointer. So we add a test
353 * to see whether SYSTEM_SAVE_K_2 has the high bit set,
354 * and if so we don't reinitialize sp, since we must be coming
355 * from Linux. (In fact the precise case is !(val & ~1),
356 * but any Linux PC has to have the high bit set.)
358 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
359 * any path that turns into a downcall to one of our TLB handlers.
361 * FIXME: if we end up never using this path, perhaps we should
362 * prevent the hypervisor from generating downcalls in this case.
363 * The advantage of getting a downcall is we can panic in Linux.
365 mfspr r0, SPR_SYSTEM_SAVE_K_2
367 bltz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
374 * SYSTEM_SAVE_K_0 holds the cpu number in the high bits, and
375 * the current stack top in the lower bits. So we recover
376 * our starting stack value by sign-extending the low bits, then
377 * point sp at the top aligned address on the actual stack page.
379 mfspr r0, SPR_SYSTEM_SAVE_K_0
380 bfexts r0, r0, 0, CPU_SHIFT-1
384 * Align the stack mod 64 so we can properly predict what
385 * cache lines we need to write-hint to reduce memory fetch
386 * latency as we enter the kernel. The layout of memory is
387 * as follows, with cache line 0 at the lowest VA, and cache
388 * line 8 just below the r0 value this "andi" computes.
389 * Note that we never write to cache line 8, and we skip
390 * cache lines 1-3 for syscalls.
392 * cache line 8: ptregs padding (two words)
393 * cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch
394 * cache line 6: r46...r53 (tp)
395 * cache line 5: r38...r45
396 * cache line 4: r30...r37
397 * cache line 3: r22...r29
398 * cache line 2: r14...r21
399 * cache line 1: r6...r13
400 * cache line 0: 2 x frame, r0..r5
402 #if STACK_TOP_DELTA != 64
403 #error STACK_TOP_DELTA must be 64 for assumptions here and in task_pt_regs()
408 * Push the first four registers on the stack, so that we can set
409 * them to vector-unique values before we jump to the common code.
411 * Registers are pushed on the stack as a struct pt_regs,
412 * with the sp initially just above the struct, and when we're
413 * done, sp points to the base of the struct, minus
414 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
416 * This routine saves just the first four registers, plus the
417 * stack context so we can do proper backtracing right away,
418 * and defers to handle_interrupt to save the rest.
419 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum,
420 * and needs sp set to its final location at the bottom of
423 addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
424 wh64 r0 /* cache line 7 */
427 addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
431 addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
433 wh64 sp /* cache line 6 */
436 addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
438 wh64 sp /* cache line 0 */
441 addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
445 addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
449 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
451 mfspr r0, SPR_EX_CONTEXT_K_0
452 .ifc \processing,handle_syscall
454 * Bump the saved PC by one bundle so that when we return, we won't
455 * execute the same swint instruction again. We need to do this while
456 * we're in the critical section.
462 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
464 mfspr r0, SPR_EX_CONTEXT_K_1
467 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
469 * Use r0 for syscalls so it's a temporary; use r1 for interrupts
470 * so that it gets passed through unchanged to the handler routine.
471 * Note that the .if conditional confusingly spans bundles.
473 .ifc \processing,handle_syscall
484 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
486 mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
489 addi sp, sp, -PTREGS_OFFSET_REG(0) - 8
492 st sp, zero /* write zero into "Next SP" frame pointer */
493 addi sp, sp, -8 /* leave SP pointing at bottom of frame */
495 .ifc \processing,handle_syscall
498 /* Capture per-interrupt SPR context to registers. */
499 .ifc \c_routine, do_page_fault
500 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
501 mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
503 .ifc \vecnum, INT_ILL_TRANS
506 .ifc \vecnum, INT_DOUBLE_FAULT
507 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
509 .ifc \c_routine, do_trap
512 .ifc \c_routine, op_handle_perf_interrupt
513 mfspr r2, PERF_COUNT_STS
514 #if CHIP_HAS_AUX_PERF_COUNTERS()
516 .ifc \c_routine, op_handle_aux_perf_interrupt
517 mfspr r2, AUX_PERF_COUNT_STS
525 /* Put function pointer in r0 */
526 moveli r0, hw2_last(\c_routine)
527 shl16insli r0, r0, hw1(\c_routine)
529 shl16insli r0, r0, hw0(\c_routine)
533 ENDPROC(intvec_\vecname)
535 #ifdef __COLLECT_LINKER_FEEDBACK__
536 .pushsection .text.intvec_feedback,"ax"
538 FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
547 * Save the rest of the registers that we didn't save in the actual
548 * vector itself. We can't use r0-r10 inclusive here.
550 .macro finish_interrupt_save, function
552 /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
553 PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
555 .ifc \function,handle_syscall
560 PTREGS_PTR(r52, PTREGS_OFFSET_TP)
564 mfspr tp, CMPEXCH_VALUE
565 PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH)
569 * For ordinary syscalls, we save neither caller- nor callee-
570 * save registers, since the syscall invoker doesn't expect the
571 * caller-saves to be saved, and the called kernel functions will
572 * take care of saving the callee-saves for us.
574 * For interrupts we save just the caller-save registers. Saving
575 * them is required (since the "caller" can't save them). Again,
576 * the called kernel functions will restore the callee-save
577 * registers for us appropriately.
579 * On return, we normally restore nothing special for syscalls,
580 * and just the caller-save registers for interrupts.
582 * However, there are some important caveats to all this:
584 * - We always save a few callee-save registers to give us
585 * some scratchpad registers to carry across function calls.
587 * - fork/vfork/etc require us to save all the callee-save
588 * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
590 * - We always save r0..r5 and r10 for syscalls, since we need
591 * to reload them a bit later for the actual kernel call, and
592 * since we might need them for -ERESTARTNOINTR, etc.
594 * - Before invoking a signal handler, we save the unsaved
595 * callee-save registers so they are visible to the
596 * signal handler or any ptracer.
598 * - If the unsaved callee-save registers are modified, we set
599 * a bit in pt_regs so we know to reload them from pt_regs
600 * and not just rely on the kernel function unwinding.
601 * (Done for ptrace register writes and SA_SIGINFO handler.)
605 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
607 wh64 r52 /* cache line 4 */
611 .ifc \function,handle_syscall
612 push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
613 push_reg TREG_SYSCALL_NR_NAME, r52, \
614 PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
617 push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
618 wh64 r52 /* cache line 3 */
627 wh64 r52 /* cache line 2 */
636 wh64 r52 /* cache line 1 */
652 * If we will be returning to the kernel, we will need to
653 * reset the interrupt masks to the state they had before.
654 * Set DISABLE_IRQ in flags iff we came from kernel pl with
657 mfspr r32, SPR_EX_CONTEXT_K_1
659 IS_KERNEL_EX1(r22, r22)
660 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
662 beqzt r32, 1f /* zero if from user space */
663 IRQS_DISABLED(r32) /* zero if irqs enabled */
664 #if PT_FLAGS_DISABLE_IRQ != 1
665 # error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
668 .ifnc \function,handle_syscall
669 /* Record the fact that we saved the caller-save registers above. */
670 ori r32, r32, PT_FLAGS_CALLER_SAVES
675 * we've captured enough state to the stack (including in
676 * particular our EX_CONTEXT state) that we can now release
677 * the interrupt critical section and replace it with our
678 * standard "interrupts disabled" mask value. This allows
679 * synchronous interrupts (and profile interrupts) to punch
680 * through from this point onwards.
682 * It's important that no code before this point touch memory
683 * other than our own stack (to keep the invariant that this
684 * is all that gets touched under ICS), and that no code after
685 * this point reference any interrupt-specific SPR, in particular
686 * the EX_CONTEXT_K_ values.
688 .ifc \function,handle_nmi
691 IRQ_DISABLE(r20, r21)
693 mtspr INTERRUPT_CRITICAL_SECTION, zero
695 /* Load tp with our per-cpu offset. */
698 mfspr r20, SPR_SYSTEM_SAVE_K_0
699 moveli r21, hw2_last(__per_cpu_offset)
702 shl16insli r21, r21, hw1(__per_cpu_offset)
703 bfextu r20, r20, CPU_SHIFT, 63
705 shl16insli r21, r21, hw0(__per_cpu_offset)
706 shl3add r20, r20, r21
712 #ifdef __COLLECT_LINKER_FEEDBACK__
714 * Notify the feedback routines that we were in the
715 * appropriate fixed interrupt vector area. Note that we
716 * still have ICS set at this point, so we can't invoke any
717 * atomic operations or we will panic. The feedback
718 * routines internally preserve r0..r10 and r30 up.
720 .ifnc \function,handle_syscall
723 moveli r20, INT_SWINT_1 << 5
725 moveli r21, hw2_last(intvec_feedback)
726 shl16insli r21, r21, hw1(intvec_feedback)
727 shl16insli r21, r21, hw0(intvec_feedback)
731 /* And now notify the feedback routines that we are here. */
732 FEEDBACK_ENTER(\function)
736 * Prepare the first 256 stack bytes to be rapidly accessible
737 * without having to fetch the background data.
754 #ifdef CONFIG_TRACE_IRQFLAGS
755 .ifnc \function,handle_nmi
757 * We finally have enough state set up to notify the irq
758 * tracing code that irqs were disabled on entry to the handler.
759 * The TRACE_IRQS_OFF call clobbers registers r0-r29.
760 * For syscalls, we already have the register state saved away
761 * on the stack, so we don't bother to do any register saves here,
762 * and later we pop the registers back off the kernel stack.
763 * For interrupt handlers, save r0-r3 in callee-saved registers.
765 .ifnc \function,handle_syscall
766 { move r30, r0; move r31, r1 }
767 { move r32, r2; move r33, r3 }
770 .ifnc \function,handle_syscall
771 { move r0, r30; move r1, r31 }
772 { move r2, r32; move r3, r33 }
780 * Redispatch a downcall.
782 .macro dc_dispatch vecnum, vecname
785 j _hv_downcall_dispatch
786 ENDPROC(intvec_\vecname)
790 * Common code for most interrupts. The C function we're eventually
791 * going to is in r0, and the faultnum is in r1; the original
792 * values for those registers are on the stack.
794 .pushsection .text.handle_interrupt,"ax"
796 finish_interrupt_save handle_interrupt
798 /* Jump to the C routine; it should enable irqs as soon as possible. */
801 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
803 FEEDBACK_REENTER(handle_interrupt)
805 movei r30, 0 /* not an NMI */
808 STD_ENDPROC(handle_interrupt)
811 * This routine takes a boolean in r30 indicating if this is an NMI.
812 * If so, we also expect a boolean in r31 indicating whether to
813 * re-enable the oprofile interrupts.
815 * Note that .Lresume_userspace is jumped to directly in several
816 * places, and we need to make sure r30 is set correctly in those
819 STD_ENTRY(interrupt_return)
820 /* If we're resuming to kernel space, don't check thread flags. */
822 bnez r30, .Lrestore_all /* NMIs don't special-case user-space */
823 PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
826 IS_KERNEL_EX1(r29, r29)
828 beqzt r29, .Lresume_userspace
832 #ifdef CONFIG_PREEMPT
833 /* Returning to kernel space. Check if we need preemption. */
834 EXTRACT_THREAD_INFO(r29)
835 addli r28, r29, THREAD_INFO_FLAGS_OFFSET
838 addli r29, r29, THREAD_INFO_PREEMPT_COUNT_OFFSET
841 andi r28, r28, _TIF_NEED_RESCHED
846 jal preempt_schedule_irq
847 FEEDBACK_REENTER(interrupt_return)
851 /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
853 moveli r27, hw2_last(_cpu_idle_nap)
854 PTREGS_PTR(r29, PTREGS_OFFSET_PC)
858 shl16insli r27, r27, hw1(_cpu_idle_nap)
861 shl16insli r27, r27, hw0(_cpu_idle_nap)
867 blbc r27, .Lrestore_all
874 FEEDBACK_REENTER(interrupt_return)
877 * Use r33 to hold whether we have already loaded the callee-saves
878 * into ptregs. We don't want to do it twice in this loop, since
879 * then we'd clobber whatever changes are made by ptrace, etc.
886 /* Get base of stack in r32. */
887 EXTRACT_THREAD_INFO(r32)
889 .Lretry_work_pending:
891 * Disable interrupts so as to make sure we don't
892 * miss an interrupt that sets any of the thread flags (like
893 * need_resched or sigpending) between sampling and the iret.
894 * Routines like schedule() or do_signal() may re-enable
895 * interrupts before returning.
897 IRQ_DISABLE(r20, r21)
898 TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */
901 /* Check to see if there is any work to do before returning to user. */
903 addi r29, r32, THREAD_INFO_FLAGS_OFFSET
904 moveli r1, hw1_last(_TIF_ALLWORK_MASK)
908 shl16insli r1, r1, hw0(_TIF_ALLWORK_MASK)
911 beqzt r1, .Lrestore_all
914 * Make sure we have all the registers saved for signal
915 * handling or notify-resume. Call out to C code to figure out
916 * exactly what we need to do for each flag bit, then if
917 * necessary, reload the flags and recheck.
920 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
923 push_extra_callee_saves r0
925 1: jal do_work_pending
926 bnez r0, .Lretry_work_pending
930 * omit the call to single_process_check_nohz, which normally checks
931 * to see if we should start or stop the scheduler tick, because
932 * we can't call arbitrary Linux code from an NMI context.
933 * We always call the homecache TLB deferral code to re-trigger
934 * the deferral mechanism.
936 * The other chunk of responsibility this code has is to reset the
937 * interrupt masks appropriately to reset irqs and NMIs. We have
938 * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
939 * lockdep-type stuff, but we can't set ICS until afterwards, since
940 * ICS can only be used in very tight chunks of code to avoid
941 * tripping over various assertions that it is off.
944 PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
947 PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
950 IS_KERNEL_EX1(r0, r0)
955 #if PT_FLAGS_DISABLE_IRQ != 1
956 # error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below
962 mtspr INTERRUPT_CRITICAL_SECTION, r0
963 beqzt r30, .Lrestore_regs
966 IRQ_ENABLE_LOAD(r20, r21)
968 mtspr INTERRUPT_CRITICAL_SECTION, r0
969 IRQ_ENABLE_APPLY(r20, r21)
970 beqzt r30, .Lrestore_regs
975 * We now commit to returning from this interrupt, since we will be
976 * doing things like setting EX_CONTEXT SPRs and unwinding the stack
977 * frame. No calls should be made to any other code after this point.
978 * This code should only be entered with ICS set.
979 * r32 must still be set to ptregs.flags.
980 * We launch loads to each cache line separately first, so we can
981 * get some parallelism out of the memory subsystem.
982 * We start zeroing caller-saved registers throughout, since
983 * that will save some cycles if this turns out to be a syscall.
988 * Rotate so we have one high bit and one low bit to test.
989 * - low bit says whether to restore all the callee-saved registers,
990 * or just r30-r33, and r52 up.
991 * - high bit (i.e. sign bit) says whether to restore all the
992 * caller-saved registers, or just r0.
994 #if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
995 # error Rotate trick does not work :-)
999 PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
1003 * Load cache lines 0, 4, 6 and 7, in that order, then use
1004 * the last loaded value, which makes it likely that the other
1005 * cache lines have also loaded, at which point we should be
1006 * able to safely read all the remaining words on those cache
1007 * lines without waiting for the memory subsystem.
1009 pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
1010 pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30)
1011 pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52)
1012 pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH
1013 pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1
1015 mtspr CMPEXCH_VALUE, r21
1018 pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
1020 mtspr SPR_EX_CONTEXT_K_1, lr
1021 IS_KERNEL_EX1(lr, lr)
1024 mtspr SPR_EX_CONTEXT_K_0, r21
1028 /* Restore callee-saveds that we actually use. */
1029 pop_reg_zero r31, r6
1030 pop_reg_zero r32, r7
1031 pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
1034 * If we modified other callee-saveds, restore them now.
1035 * This is rare, but could be via ptrace or signal handler.
1039 blbs r20, .Lrestore_callees
1041 .Lcontinue_restore_regs:
1043 /* Check if we're returning from a syscall. */
1046 bltzt r20, 1f /* no, so go restore callee-save registers */
1050 * Check if we're returning to userspace.
1051 * Note that if we're not, we don't worry about zeroing everything.
1054 addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
1055 bnez lr, .Lkernel_return
1059 * On return from syscall, we've restored r0 from pt_regs, but we
1060 * clear the remainder of the caller-saved registers. We could
1061 * restore the syscall arguments, but there's not much point,
1062 * and it ensures user programs aren't trying to use the
1063 * caller-saves if we clear them, as well as avoiding leaking
1064 * kernel pointers into userspace.
1066 pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
1067 pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
1073 { move r15, zero; move r16, zero }
1074 { move r17, zero; move r18, zero }
1075 { move r19, zero; move r20, zero }
1076 { move r21, zero; move r22, zero }
1077 { move r23, zero; move r24, zero }
1078 { move r25, zero; move r26, zero }
1080 /* Set r1 to errno if we are returning an error, otherwise zero. */
1096 * Not a syscall, so restore caller-saved registers.
1097 * First kick off loads for cache lines 1-3, which we're touching
1098 * for the first time here.
1101 1: pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29)
1102 pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21)
1103 pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13)
1116 /* r13 already restored above */
1124 /* r21 already restored above */
1131 pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
1132 /* r29 already restored above */
1133 bnez lr, .Lkernel_return
1134 pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
1135 pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
1140 * We can't restore tp when in kernel mode, since a thread might
1141 * have migrated from another cpu and brought a stale tp value.
1144 pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
1148 /* Restore callee-saved registers from r34 to r51. */
1150 addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
1168 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
1169 j .Lcontinue_restore_regs
1170 STD_ENDPROC(interrupt_return)
1173 * "NMI" interrupts mask ALL interrupts before calling the
1174 * handler, and don't check thread flags, etc., on the way
1175 * back out. In general, the only things we do here for NMIs
1176 * are register save/restore and dataplane kernel-TLB management.
1177 * We don't (for example) deal with start/stop of the sched tick.
1179 .pushsection .text.handle_nmi,"ax"
1181 finish_interrupt_save handle_nmi
1184 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1186 FEEDBACK_REENTER(handle_nmi)
1192 STD_ENDPROC(handle_nmi)
1195 * Parallel code for syscalls to handle_interrupt.
1197 .pushsection .text.handle_syscall,"ax"
1199 finish_interrupt_save handle_syscall
1203 IRQ_ENABLE(r20, r21)
1205 /* Bump the counter for syscalls made on this tile. */
1206 moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1207 shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1208 shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1217 EXTRACT_THREAD_INFO(r31)
1220 /* Trace syscalls, if requested. */
1221 addi r31, r31, THREAD_INFO_FLAGS_OFFSET
1224 moveli r32, _TIF_SYSCALL_ENTRY_WORK
1228 addi r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
1229 beqzt r30, .Lrestore_syscall_regs
1232 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1233 jal do_syscall_trace_enter
1235 FEEDBACK_REENTER(handle_syscall)
1238 * We always reload our registers from the stack at this
1239 * point. They might be valid, if we didn't build with
1240 * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
1241 * doing syscall tracing, but there are enough cases now that it
1242 * seems simplest just to do the reload unconditionally.
1244 .Lrestore_syscall_regs:
1247 PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
1254 pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
1256 ld TREG_SYSCALL_NR_NAME, r11
1257 moveli r21, __NR_syscalls
1260 /* Ensure that the syscall number is within the legal range. */
1262 moveli r20, hw2(sys_call_table)
1263 #ifdef CONFIG_COMPAT
1264 blbs r30, .Lcompat_syscall
1268 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1269 shl16insli r20, r20, hw1(sys_call_table)
1272 blbc r21, .Linvalid_syscall
1273 shl16insli r20, r20, hw0(sys_call_table)
1275 .Lload_syscall_pointer:
1276 shl3add r20, TREG_SYSCALL_NR_NAME, r20
1279 /* Jump to syscall handler. */
1281 .Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
1284 * Write our r0 onto the stack so it gets restored instead
1285 * of whatever the user had there before.
1286 * In compat mode, sign-extend r0 before storing it.
1289 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1295 .Lsyscall_sigreturn_skip:
1296 FEEDBACK_REENTER(handle_syscall)
1298 /* Do syscall trace again, if requested. */
1301 moveli r32, _TIF_SYSCALL_EXIT_WORK
1305 andi r0, r30, _TIF_SINGLESTEP
1309 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1310 jal do_syscall_trace_exit
1312 FEEDBACK_REENTER(handle_syscall)
1313 andi r0, r30, _TIF_SINGLESTEP
1317 /* Single stepping -- notify ptrace. */
1322 FEEDBACK_REENTER(handle_syscall)
1325 movei r30, 0 /* not an NMI */
1326 j .Lresume_userspace /* jump into middle of interrupt_return */
1329 #ifdef CONFIG_COMPAT
1332 * Load the base of the compat syscall table in r20, and
1333 * range-check the syscall number (duplicated from 64-bit path).
1334 * Sign-extend all the user's passed arguments to make them consistent.
1335 * Also save the original "r(n)" values away in "r(11+n)" in
1336 * case the syscall table entry wants to validate them.
1338 moveli r20, hw2(compat_sys_call_table)
1340 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1341 shl16insli r20, r20, hw1(compat_sys_call_table)
1344 blbc r21, .Linvalid_syscall
1345 shl16insli r20, r20, hw0(compat_sys_call_table)
1347 { move r11, r0; addxi r0, r0, 0 }
1348 { move r12, r1; addxi r1, r1, 0 }
1349 { move r13, r2; addxi r2, r2, 0 }
1350 { move r14, r3; addxi r3, r3, 0 }
1351 { move r15, r4; addxi r4, r4, 0 }
1352 { move r16, r5; addxi r5, r5, 0 }
1353 j .Lload_syscall_pointer
1357 /* Report an invalid syscall back to the user program */
1359 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1364 movei r30, 0 /* not an NMI */
1365 j .Lresume_userspace /* jump into middle of interrupt_return */
1367 STD_ENDPROC(handle_syscall)
1369 /* Return the address for oprofile to suppress in backtraces. */
1370 STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
1373 addli r0, r0, .Lhandle_syscall_link - .
1376 STD_ENDPROC(handle_syscall_link_address)
1378 STD_ENTRY(ret_from_fork)
1381 FEEDBACK_REENTER(ret_from_fork)
1383 movei r30, 0 /* not an NMI */
1384 j .Lresume_userspace /* jump into middle of interrupt_return */
1386 STD_ENDPROC(ret_from_fork)
1388 STD_ENTRY(ret_from_kernel_thread)
1391 FEEDBACK_REENTER(ret_from_fork)
1396 FEEDBACK_REENTER(ret_from_kernel_thread)
1398 movei r30, 0 /* not an NMI */
1399 j .Lresume_userspace /* jump into middle of interrupt_return */
1401 STD_ENDPROC(ret_from_kernel_thread)
1403 /* Various stub interrupt handlers and syscall handlers */
1405 STD_ENTRY_LOCAL(_kernel_double_fault)
1406 mfspr r1, SPR_EX_CONTEXT_K_0
1410 addi sp, sp, -C_ABI_SAVE_AREA_SIZE
1411 j kernel_double_fault
1412 STD_ENDPROC(_kernel_double_fault)
1414 STD_ENTRY_LOCAL(bad_intr)
1415 mfspr r2, SPR_EX_CONTEXT_K_0
1416 panic "Unhandled interrupt %#x: PC %#lx"
1417 STD_ENDPROC(bad_intr)
1420 * Special-case sigreturn to not write r0 to the stack on return.
1421 * This is technically more efficient, but it also avoids difficulties
1422 * in the 64-bit OS when handling 32-bit compat code, since we must not
1423 * sign-extend r0 for the sigreturn return-value case.
1425 #define PTREGS_SYSCALL_SIGRETURN(x, reg) \
1427 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
1429 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1434 PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
1435 #ifdef CONFIG_COMPAT
1436 PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0)
1439 /* Save additional callee-saves to pt_regs and jump to standard function. */
1440 STD_ENTRY(_sys_clone)
1441 push_extra_callee_saves r4
1443 STD_ENDPROC(_sys_clone)
1446 * Recover r3, r2, r1 and r0 here saved by unalign fast vector.
1447 * The vector area limit is 32 bundles, so we handle the reload here.
1448 * r0, r1, r2 are in thread_info from low to high memory in order.
1449 * r3 points to location the original r3 was saved.
1450 * We put this code in the __HEAD section so it can be reached
1451 * via a conditional branch from the fast path.
1456 hand_unalign_slow_badsp:
1457 addi r3, r3, -(3 * 8)
1461 hand_unalign_slow_nonuser:
1462 mfspr r3, SPR_SYSTEM_SAVE_K_1
1463 __int_hand INT_UNALIGN_DATA, UNALIGN_DATA_SLOW, int_unalign
1465 /* The unaligned data support needs to read all the registers. */
1467 push_extra_callee_saves r0
1469 ENDPROC(hand_unalign_slow)
1471 /* Fill the return address stack with nonzero entries. */
1472 STD_ENTRY(fill_ra_stack)
1481 STD_ENDPROC(fill_ra_stack)
1483 .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt
1485 __int_hand \vecnum, \vecname, \c_routine, \processing
1488 /* Include .intrpt1 array of interrupt vectors */
1489 .section ".intrpt1", "ax"
1491 #define op_handle_perf_interrupt bad_intr
1492 #define op_handle_aux_perf_interrupt bad_intr
1494 #ifndef CONFIG_HARDWALL
1495 #define do_hardwall_trap bad_intr
1498 int_hand INT_MEM_ERROR, MEM_ERROR, do_trap
1499 int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr
1500 #if CONFIG_KERNEL_PL == 2
1501 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle
1502 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr
1504 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr
1505 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle
1507 int_hand INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr
1508 int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
1509 int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
1510 int_hand INT_ITLB_MISS, ITLB_MISS, do_page_fault
1511 int_hand INT_ILL, ILL, do_trap
1512 int_hand INT_GPV, GPV, do_trap
1513 int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap
1514 int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap
1515 int_hand INT_SWINT_3, SWINT_3, do_trap
1516 int_hand INT_SWINT_2, SWINT_2, do_trap
1517 int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
1518 int_hand INT_SWINT_0, SWINT_0, do_trap
1519 int_hand INT_ILL_TRANS, ILL_TRANS, do_trap
1520 int_hand_unalign_fast INT_UNALIGN_DATA, UNALIGN_DATA
1521 int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault
1522 int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
1523 int_hand INT_IDN_FIREWALL, IDN_FIREWALL, do_hardwall_trap
1524 int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
1525 int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
1526 int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr
1527 int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr
1528 int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
1529 int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
1530 int_hand INT_IPI_3, IPI_3, bad_intr
1531 #if CONFIG_KERNEL_PL == 2
1532 int_hand INT_IPI_2, IPI_2, tile_dev_intr
1533 int_hand INT_IPI_1, IPI_1, bad_intr
1535 int_hand INT_IPI_2, IPI_2, bad_intr
1536 int_hand INT_IPI_1, IPI_1, tile_dev_intr
1538 int_hand INT_IPI_0, IPI_0, bad_intr
1539 int_hand INT_PERF_COUNT, PERF_COUNT, \
1540 op_handle_perf_interrupt, handle_nmi
1541 int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
1542 op_handle_perf_interrupt, handle_nmi
1543 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
1544 #if CONFIG_KERNEL_PL == 2
1545 dc_dispatch INT_INTCTRL_2, INTCTRL_2
1546 int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
1548 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
1549 dc_dispatch INT_INTCTRL_1, INTCTRL_1
1551 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
1552 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
1554 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr
1555 int_hand INT_I_ASID, I_ASID, bad_intr
1556 int_hand INT_D_ASID, D_ASID, bad_intr
1557 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
1559 /* Synthetic interrupt delivered only by the simulator */
1560 int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint