arch/sh/kernel/cpu/sh4/setup-sh4-202.c

   1 /*
   2  * SH4-202 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2009  Magnus Damm
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17
  18 static struct plat_sci_port sci_platform_data[] = {
  19         {
  20                 .mapbase        = 0xffe80000,
  21                 .flags          = UPF_BOOT_AUTOCONF,
  22                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  23                 .scbrr_algo_id  = SCBRR_ALGO_2,
  24                 .type           = PORT_SCIF,
  25                 .irqs           = { 40, 41, 43, 42 },
  26         }, {
  27                 .flags = 0,
  28         }
  29 };
  30
  31 static struct platform_device sci_device = {
  32         .name           = "sh-sci",
  33         .id             = -1,
  34         .dev            = {
  35                 .platform_data  = sci_platform_data,
  36         },
  37 };
  38
  39 static struct sh_timer_config tmu0_platform_data = {
  40         .name = "TMU0",
  41         .channel_offset = 0x04,
  42         .timer_bit = 0,
  43         .clk = "peripheral_clk",
  44         .clockevent_rating = 200,
  45 };
  46
  47 static struct resource tmu0_resources[] = {
  48         [0] = {
  49                 .name   = "TMU0",
  50                 .start  = 0xffd80008,
  51                 .end    = 0xffd80013,
  52                 .flags  = IORESOURCE_MEM,
  53         },
  54         [1] = {
  55                 .start  = 16,
  56                 .flags  = IORESOURCE_IRQ,
  57         },
  58 };
  59
  60 static struct platform_device tmu0_device = {
  61         .name           = "sh_tmu",
  62         .id             = 0,
  63         .dev = {
  64                 .platform_data  = &tmu0_platform_data,
  65         },
  66         .resource       = tmu0_resources,
  67         .num_resources  = ARRAY_SIZE(tmu0_resources),
  68 };
  69
  70 static struct sh_timer_config tmu1_platform_data = {
  71         .name = "TMU1",
  72         .channel_offset = 0x10,
  73         .timer_bit = 1,
  74         .clk = "peripheral_clk",
  75         .clocksource_rating = 200,
  76 };
  77
  78 static struct resource tmu1_resources[] = {
  79         [0] = {
  80                 .name   = "TMU1",
  81                 .start  = 0xffd80014,
  82                 .end    = 0xffd8001f,
  83                 .flags  = IORESOURCE_MEM,
  84         },
  85         [1] = {
  86                 .start  = 17,
  87                 .flags  = IORESOURCE_IRQ,
  88         },
  89 };
  90
  91 static struct platform_device tmu1_device = {
  92         .name           = "sh_tmu",
  93         .id             = 1,
  94         .dev = {
  95                 .platform_data  = &tmu1_platform_data,
  96         },
  97         .resource       = tmu1_resources,
  98         .num_resources  = ARRAY_SIZE(tmu1_resources),
  99 };
 100
 101 static struct sh_timer_config tmu2_platform_data = {
 102         .name = "TMU2",
 103         .channel_offset = 0x1c,
 104         .timer_bit = 2,
 105         .clk = "peripheral_clk",
 106 };
 107
 108 static struct resource tmu2_resources[] = {
 109         [0] = {
 110                 .name   = "TMU2",
 111                 .start  = 0xffd80020,
 112                 .end    = 0xffd8002f,
 113                 .flags  = IORESOURCE_MEM,
 114         },
 115         [1] = {
 116                 .start  = 18,
 117                 .flags  = IORESOURCE_IRQ,
 118         },
 119 };
 120
 121 static struct platform_device tmu2_device = {
 122         .name           = "sh_tmu",
 123         .id             = 2,
 124         .dev = {
 125                 .platform_data  = &tmu2_platform_data,
 126         },
 127         .resource       = tmu2_resources,
 128         .num_resources  = ARRAY_SIZE(tmu2_resources),
 129 };
 130
 131 static struct platform_device *sh4202_devices[] __initdata = {
 132         &sci_device,
 133         &tmu0_device,
 134         &tmu1_device,
 135         &tmu2_device,
 136 };
 137
 138 static int __init sh4202_devices_setup(void)
 139 {
 140         return platform_add_devices(sh4202_devices,
 141                                     ARRAY_SIZE(sh4202_devices));
 142 }
 143 __initcall(sh4202_devices_setup);
 144
 145 static struct platform_device *sh4202_early_devices[] __initdata = {
 146         &tmu0_device,
 147         &tmu1_device,
 148         &tmu2_device,
 149 };
 150
 151 void __init plat_early_device_setup(void)
 152 {
 153         early_platform_add_devices(sh4202_early_devices,
 154                                    ARRAY_SIZE(sh4202_early_devices));
 155 }
 156
 157 enum {
 158         UNUSED = 0,
 159
 160         /* interrupt sources */
 161         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 162         HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
 163 };
 164
 165 static struct intc_vect vectors[] __initdata = {
 166         INTC_VECT(HUDI, 0x600),
 167         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 168         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 169         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 170         INTC_VECT(RTC, 0x4c0),
 171         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 172         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 173         INTC_VECT(WDT, 0x560),
 174 };
 175
 176 static struct intc_prio_reg prio_registers[] __initdata = {
 177         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 178         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
 179         { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
 180         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 181 };
 182
 183 static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
 184                          NULL, prio_registers, NULL);
 185
 186 static struct intc_vect vectors_irlm[] __initdata = {
 187         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 188         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 189 };
 190
 191 static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
 192                          NULL, prio_registers, NULL);
 193
 194 void __init plat_irq_setup(void)
 195 {
 196         register_intc_controller(&intc_desc);
 197 }
 198
 199 #define INTC_ICR        0xffd00000UL
 200 #define INTC_ICR_IRLM   (1<<7)
 201
 202 void __init plat_irq_setup_pins(int mode)
 203 {
 204         switch (mode) {
 205         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 206                 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 207                 register_intc_controller(&intc_desc_irlm);
 208                 break;
 209         default:
 210                 BUG();
 211         }
 212 }