arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41
  42 #include <asm/pgtable.h>
  43 #include <asm/io.h>
  44 #include <asm/processor.h>
  45 #include <asm/mmu.h>
  46 #include <asm/prom.h>
  47 #include <asm/machdep.h>
  48 #include <asm/time.h>
  49 #include <asm/runlatch.h>
  50 #include <asm/syscalls.h>
  51 #include <asm/switch_to.h>
  52 #include <asm/tm.h>
  53 #include <asm/debug.h>
  54 #ifdef CONFIG_PPC64
  55 #include <asm/firmware.h>
  56 #endif
  57 #include <asm/code-patching.h>
  58 #include <linux/kprobes.h>
  59 #include <linux/kdebug.h>
  60
  61 /* Transactional Memory debug */
  62 #ifdef TM_DEBUG_SW
  63 #define TM_DEBUG(x...) printk(KERN_INFO x)
  64 #else
  65 #define TM_DEBUG(x...) do { } while(0)
  66 #endif
  67
  68 extern unsigned long _get_SP(void);
  69
  70 #ifndef CONFIG_SMP
  71 struct task_struct *last_task_used_math = NULL;
  72 struct task_struct *last_task_used_altivec = NULL;
  73 struct task_struct *last_task_used_vsx = NULL;
  74 struct task_struct *last_task_used_spe = NULL;
  75 #endif
  76
  77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  78 void giveup_fpu_maybe_transactional(struct task_struct *tsk)
  79 {
  80         /*
  81          * If we are saving the current thread's registers, and the
  82          * thread is in a transactional state, set the TIF_RESTORE_TM
  83          * bit so that we know to restore the registers before
  84          * returning to userspace.
  85          */
  86         if (tsk == current && tsk->thread.regs &&
  87             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  88             !test_thread_flag(TIF_RESTORE_TM)) {
  89                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  90                 set_thread_flag(TIF_RESTORE_TM);
  91         }
  92
  93         giveup_fpu(tsk);
  94 }
  95
  96 void giveup_altivec_maybe_transactional(struct task_struct *tsk)
  97 {
  98         /*
  99          * If we are saving the current thread's registers, and the
 100          * thread is in a transactional state, set the TIF_RESTORE_TM
 101          * bit so that we know to restore the registers before
 102          * returning to userspace.
 103          */
 104         if (tsk == current && tsk->thread.regs &&
 105             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 106             !test_thread_flag(TIF_RESTORE_TM)) {
 107                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
 108                 set_thread_flag(TIF_RESTORE_TM);
 109         }
 110
 111         giveup_altivec(tsk);
 112 }
 113
 114 #else
 115 #define giveup_fpu_maybe_transactional(tsk)     giveup_fpu(tsk)
 116 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
 117 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 118
 119 #ifdef CONFIG_PPC_FPU
 120 /*
 121  * Make sure the floating-point register state in the
 122  * the thread_struct is up to date for task tsk.
 123  */
 124 void flush_fp_to_thread(struct task_struct *tsk)
 125 {
 126         if (tsk->thread.regs) {
 127                 /*
 128                  * We need to disable preemption here because if we didn't,
 129                  * another process could get scheduled after the regs->msr
 130                  * test but before we have finished saving the FP registers
 131                  * to the thread_struct.  That process could take over the
 132                  * FPU, and then when we get scheduled again we would store
 133                  * bogus values for the remaining FP registers.
 134                  */
 135                 preempt_disable();
 136                 if (tsk->thread.regs->msr & MSR_FP) {
 137 #ifdef CONFIG_SMP
 138                         /*
 139                          * This should only ever be called for current or
 140                          * for a stopped child process.  Since we save away
 141                          * the FP register state on context switch on SMP,
 142                          * there is something wrong if a stopped child appears
 143                          * to still have its FP state in the CPU registers.
 144                          */
 145                         BUG_ON(tsk != current);
 146 #endif
 147                         giveup_fpu_maybe_transactional(tsk);
 148                 }
 149                 preempt_enable();
 150         }
 151 }
 152 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 153 #endif /* CONFIG_PPC_FPU */
 154
 155 void enable_kernel_fp(void)
 156 {
 157         WARN_ON(preemptible());
 158
 159 #ifdef CONFIG_SMP
 160         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
 161                 giveup_fpu_maybe_transactional(current);
 162         else
 163                 giveup_fpu(NULL);       /* just enables FP for kernel */
 164 #else
 165         giveup_fpu_maybe_transactional(last_task_used_math);
 166 #endif /* CONFIG_SMP */
 167 }
 168 EXPORT_SYMBOL(enable_kernel_fp);
 169
 170 #ifdef CONFIG_ALTIVEC
 171 void enable_kernel_altivec(void)
 172 {
 173         WARN_ON(preemptible());
 174
 175 #ifdef CONFIG_SMP
 176         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
 177                 giveup_altivec_maybe_transactional(current);
 178         else
 179                 giveup_altivec_notask();
 180 #else
 181         giveup_altivec_maybe_transactional(last_task_used_altivec);
 182 #endif /* CONFIG_SMP */
 183 }
 184 EXPORT_SYMBOL(enable_kernel_altivec);
 185
 186 /*
 187  * Make sure the VMX/Altivec register state in the
 188  * the thread_struct is up to date for task tsk.
 189  */
 190 void flush_altivec_to_thread(struct task_struct *tsk)
 191 {
 192         if (tsk->thread.regs) {
 193                 preempt_disable();
 194                 if (tsk->thread.regs->msr & MSR_VEC) {
 195 #ifdef CONFIG_SMP
 196                         BUG_ON(tsk != current);
 197 #endif
 198                         giveup_altivec_maybe_transactional(tsk);
 199                 }
 200                 preempt_enable();
 201         }
 202 }
 203 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 204 #endif /* CONFIG_ALTIVEC */
 205
 206 #ifdef CONFIG_VSX
 207 void enable_kernel_vsx(void)
 208 {
 209         WARN_ON(preemptible());
 210
 211 #ifdef CONFIG_SMP
 212         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
 213                 giveup_vsx(current);
 214         else
 215                 giveup_vsx(NULL);       /* just enable vsx for kernel - force */
 216 #else
 217         giveup_vsx(last_task_used_vsx);
 218 #endif /* CONFIG_SMP */
 219 }
 220 EXPORT_SYMBOL(enable_kernel_vsx);
 221
 222 void giveup_vsx(struct task_struct *tsk)
 223 {
 224         giveup_fpu_maybe_transactional(tsk);
 225         giveup_altivec_maybe_transactional(tsk);
 226         __giveup_vsx(tsk);
 227 }
 228 EXPORT_SYMBOL(giveup_vsx);
 229
 230 void flush_vsx_to_thread(struct task_struct *tsk)
 231 {
 232         if (tsk->thread.regs) {
 233                 preempt_disable();
 234                 if (tsk->thread.regs->msr & MSR_VSX) {
 235 #ifdef CONFIG_SMP
 236                         BUG_ON(tsk != current);
 237 #endif
 238                         giveup_vsx(tsk);
 239                 }
 240                 preempt_enable();
 241         }
 242 }
 243 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 244 #endif /* CONFIG_VSX */
 245
 246 #ifdef CONFIG_SPE
 247
 248 void enable_kernel_spe(void)
 249 {
 250         WARN_ON(preemptible());
 251
 252 #ifdef CONFIG_SMP
 253         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
 254                 giveup_spe(current);
 255         else
 256                 giveup_spe(NULL);       /* just enable SPE for kernel - force */
 257 #else
 258         giveup_spe(last_task_used_spe);
 259 #endif /* __SMP __ */
 260 }
 261 EXPORT_SYMBOL(enable_kernel_spe);
 262
 263 void flush_spe_to_thread(struct task_struct *tsk)
 264 {
 265         if (tsk->thread.regs) {
 266                 preempt_disable();
 267                 if (tsk->thread.regs->msr & MSR_SPE) {
 268 #ifdef CONFIG_SMP
 269                         BUG_ON(tsk != current);
 270 #endif
 271                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 272                         giveup_spe(tsk);
 273                 }
 274                 preempt_enable();
 275         }
 276 }
 277 #endif /* CONFIG_SPE */
 278
 279 #ifndef CONFIG_SMP
 280 /*
 281  * If we are doing lazy switching of CPU state (FP, altivec or SPE),
 282  * and the current task has some state, discard it.
 283  */
 284 void discard_lazy_cpu_state(void)
 285 {
 286         preempt_disable();
 287         if (last_task_used_math == current)
 288                 last_task_used_math = NULL;
 289 #ifdef CONFIG_ALTIVEC
 290         if (last_task_used_altivec == current)
 291                 last_task_used_altivec = NULL;
 292 #endif /* CONFIG_ALTIVEC */
 293 #ifdef CONFIG_VSX
 294         if (last_task_used_vsx == current)
 295                 last_task_used_vsx = NULL;
 296 #endif /* CONFIG_VSX */
 297 #ifdef CONFIG_SPE
 298         if (last_task_used_spe == current)
 299                 last_task_used_spe = NULL;
 300 #endif
 301         preempt_enable();
 302 }
 303 #endif /* CONFIG_SMP */
 304
 305 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 306 void do_send_trap(struct pt_regs *regs, unsigned long address,
 307                   unsigned long error_code, int signal_code, int breakpt)
 308 {
 309         siginfo_t info;
 310
 311         current->thread.trap_nr = signal_code;
 312         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 313                         11, SIGSEGV) == NOTIFY_STOP)
 314                 return;
 315
 316         /* Deliver the signal to userspace */
 317         info.si_signo = SIGTRAP;
 318         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 319         info.si_code = signal_code;
 320         info.si_addr = (void __user *)address;
 321         force_sig_info(SIGTRAP, &info, current);
 322 }
 323 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 324 void do_break (struct pt_regs *regs, unsigned long address,
 325                     unsigned long error_code)
 326 {
 327         siginfo_t info;
 328
 329         current->thread.trap_nr = TRAP_HWBKPT;
 330         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 331                         11, SIGSEGV) == NOTIFY_STOP)
 332                 return;
 333
 334         if (debugger_break_match(regs))
 335                 return;
 336
 337         /* Clear the breakpoint */
 338         hw_breakpoint_disable();
 339
 340         /* Deliver the signal to userspace */
 341         info.si_signo = SIGTRAP;
 342         info.si_errno = 0;
 343         info.si_code = TRAP_HWBKPT;
 344         info.si_addr = (void __user *)address;
 345         force_sig_info(SIGTRAP, &info, current);
 346 }
 347 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 348
 349 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 350
 351 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 352 /*
 353  * Set the debug registers back to their default "safe" values.
 354  */
 355 static void set_debug_reg_defaults(struct thread_struct *thread)
 356 {
 357         thread->debug.iac1 = thread->debug.iac2 = 0;
 358 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 359         thread->debug.iac3 = thread->debug.iac4 = 0;
 360 #endif
 361         thread->debug.dac1 = thread->debug.dac2 = 0;
 362 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 363         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 364 #endif
 365         thread->debug.dbcr0 = 0;
 366 #ifdef CONFIG_BOOKE
 367         /*
 368          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 369          */
 370         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 371                         DBCR1_IAC3US | DBCR1_IAC4US;
 372         /*
 373          * Force Data Address Compare User/Supervisor bits to be User-only
 374          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 375          */
 376         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 377 #else
 378         thread->debug.dbcr1 = 0;
 379 #endif
 380 }
 381
 382 static void prime_debug_regs(struct debug_reg *debug)
 383 {
 384         /*
 385          * We could have inherited MSR_DE from userspace, since
 386          * it doesn't get cleared on exception entry.  Make sure
 387          * MSR_DE is clear before we enable any debug events.
 388          */
 389         mtmsr(mfmsr() & ~MSR_DE);
 390
 391         mtspr(SPRN_IAC1, debug->iac1);
 392         mtspr(SPRN_IAC2, debug->iac2);
 393 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 394         mtspr(SPRN_IAC3, debug->iac3);
 395         mtspr(SPRN_IAC4, debug->iac4);
 396 #endif
 397         mtspr(SPRN_DAC1, debug->dac1);
 398         mtspr(SPRN_DAC2, debug->dac2);
 399 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 400         mtspr(SPRN_DVC1, debug->dvc1);
 401         mtspr(SPRN_DVC2, debug->dvc2);
 402 #endif
 403         mtspr(SPRN_DBCR0, debug->dbcr0);
 404         mtspr(SPRN_DBCR1, debug->dbcr1);
 405 #ifdef CONFIG_BOOKE
 406         mtspr(SPRN_DBCR2, debug->dbcr2);
 407 #endif
 408 }
 409 /*
 410  * Unless neither the old or new thread are making use of the
 411  * debug registers, set the debug registers from the values
 412  * stored in the new thread.
 413  */
 414 void switch_booke_debug_regs(struct debug_reg *new_debug)
 415 {
 416         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 417                 || (new_debug->dbcr0 & DBCR0_IDM))
 418                         prime_debug_regs(new_debug);
 419 }
 420 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 421 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 422 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 423 static void set_debug_reg_defaults(struct thread_struct *thread)
 424 {
 425         thread->hw_brk.address = 0;
 426         thread->hw_brk.type = 0;
 427         set_breakpoint(&thread->hw_brk);
 428 }
 429 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 430 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 431
 432 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 433 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 434 {
 435         mtspr(SPRN_DAC1, dabr);
 436 #ifdef CONFIG_PPC_47x
 437         isync();
 438 #endif
 439         return 0;
 440 }
 441 #elif defined(CONFIG_PPC_BOOK3S)
 442 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 443 {
 444         mtspr(SPRN_DABR, dabr);
 445         if (cpu_has_feature(CPU_FTR_DABRX))
 446                 mtspr(SPRN_DABRX, dabrx);
 447         return 0;
 448 }
 449 #else
 450 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 451 {
 452         return -EINVAL;
 453 }
 454 #endif
 455
 456 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 457 {
 458         unsigned long dabr, dabrx;
 459
 460         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 461         dabrx = ((brk->type >> 3) & 0x7);
 462
 463         if (ppc_md.set_dabr)
 464                 return ppc_md.set_dabr(dabr, dabrx);
 465
 466         return __set_dabr(dabr, dabrx);
 467 }
 468
 469 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 470 {
 471         unsigned long dawr, dawrx, mrd;
 472
 473         dawr = brk->address;
 474
 475         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 476                                    << (63 - 58); //* read/write bits */
 477         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 478                                    << (63 - 59); //* translate */
 479         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 480                                    >> 3; //* PRIM bits */
 481         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 482            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 483            0b111111=64DW.
 484            brk->len is in bytes.
 485            This aligns up to double word size, shifts and does the bias.
 486         */
 487         mrd = ((brk->len + 7) >> 3) - 1;
 488         dawrx |= (mrd & 0x3f) << (63 - 53);
 489
 490         if (ppc_md.set_dawr)
 491                 return ppc_md.set_dawr(dawr, dawrx);
 492         mtspr(SPRN_DAWR, dawr);
 493         mtspr(SPRN_DAWRX, dawrx);
 494         return 0;
 495 }
 496
 497 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 498 {
 499         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 500
 501         if (cpu_has_feature(CPU_FTR_DAWR))
 502                 set_dawr(brk);
 503         else
 504                 set_dabr(brk);
 505 }
 506
 507 void set_breakpoint(struct arch_hw_breakpoint *brk)
 508 {
 509         preempt_disable();
 510         __set_breakpoint(brk);
 511         preempt_enable();
 512 }
 513
 514 #ifdef CONFIG_PPC64
 515 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 516 #endif
 517
 518 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 519                               struct arch_hw_breakpoint *b)
 520 {
 521         if (a->address != b->address)
 522                 return false;
 523         if (a->type != b->type)
 524                 return false;
 525         if (a->len != b->len)
 526                 return false;
 527         return true;
 528 }
 529
 530 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 531 static void tm_reclaim_thread(struct thread_struct *thr,
 532                               struct thread_info *ti, uint8_t cause)
 533 {
 534         unsigned long msr_diff = 0;
 535
 536         /*
 537          * If FP/VSX registers have been already saved to the
 538          * thread_struct, move them to the transact_fp array.
 539          * We clear the TIF_RESTORE_TM bit since after the reclaim
 540          * the thread will no longer be transactional.
 541          */
 542         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 543                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 544                 if (msr_diff & MSR_FP)
 545                         memcpy(&thr->transact_fp, &thr->fp_state,
 546                                sizeof(struct thread_fp_state));
 547                 if (msr_diff & MSR_VEC)
 548                         memcpy(&thr->transact_vr, &thr->vr_state,
 549                                sizeof(struct thread_vr_state));
 550                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 551                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 552         }
 553
 554         tm_reclaim(thr, thr->regs->msr, cause);
 555
 556         /* Having done the reclaim, we now have the checkpointed
 557          * FP/VSX values in the registers.  These might be valid
 558          * even if we have previously called enable_kernel_fp() or
 559          * flush_fp_to_thread(), so update thr->regs->msr to
 560          * indicate their current validity.
 561          */
 562         thr->regs->msr |= msr_diff;
 563 }
 564
 565 void tm_reclaim_current(uint8_t cause)
 566 {
 567         tm_enable();
 568         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 569 }
 570
 571 static inline void tm_reclaim_task(struct task_struct *tsk)
 572 {
 573         /* We have to work out if we're switching from/to a task that's in the
 574          * middle of a transaction.
 575          *
 576          * In switching we need to maintain a 2nd register state as
 577          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 578          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 579          * (current) FPRs into oldtask->thread.transact_fpr[].
 580          *
 581          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 582          */
 583         struct thread_struct *thr = &tsk->thread;
 584
 585         if (!thr->regs)
 586                 return;
 587
 588         if (!MSR_TM_ACTIVE(thr->regs->msr))
 589                 goto out_and_saveregs;
 590
 591         /* Stash the original thread MSR, as giveup_fpu et al will
 592          * modify it.  We hold onto it to see whether the task used
 593          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 594          * ckpt_regs.msr is already set.
 595          */
 596         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 597                 thr->ckpt_regs.msr = thr->regs->msr;
 598
 599         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 600                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 601                  tsk->pid, thr->regs->nip,
 602                  thr->regs->ccr, thr->regs->msr,
 603                  thr->regs->trap);
 604
 605         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 606
 607         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 608                  tsk->pid);
 609
 610 out_and_saveregs:
 611         /* Always save the regs here, even if a transaction's not active.
 612          * This context-switches a thread's TM info SPRs.  We do it here to
 613          * be consistent with the restore path (in recheckpoint) which
 614          * cannot happen later in _switch().
 615          */
 616         tm_save_sprs(thr);
 617 }
 618
 619 extern void __tm_recheckpoint(struct thread_struct *thread,
 620                               unsigned long orig_msr);
 621
 622 void tm_recheckpoint(struct thread_struct *thread,
 623                      unsigned long orig_msr)
 624 {
 625         unsigned long flags;
 626
 627         /* We really can't be interrupted here as the TEXASR registers can't
 628          * change and later in the trecheckpoint code, we have a userspace R1.
 629          * So let's hard disable over this region.
 630          */
 631         local_irq_save(flags);
 632         hard_irq_disable();
 633
 634         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 635          * before the trecheckpoint and no explosion occurs.
 636          */
 637         tm_restore_sprs(thread);
 638
 639         __tm_recheckpoint(thread, orig_msr);
 640
 641         local_irq_restore(flags);
 642 }
 643
 644 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 645 {
 646         unsigned long msr;
 647
 648         if (!cpu_has_feature(CPU_FTR_TM))
 649                 return;
 650
 651         /* Recheckpoint the registers of the thread we're about to switch to.
 652          *
 653          * If the task was using FP, we non-lazily reload both the original and
 654          * the speculative FP register states.  This is because the kernel
 655          * doesn't see if/when a TM rollback occurs, so if we take an FP
 656          * unavoidable later, we are unable to determine which set of FP regs
 657          * need to be restored.
 658          */
 659         if (!new->thread.regs)
 660                 return;
 661
 662         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 663                 tm_restore_sprs(&new->thread);
 664                 return;
 665         }
 666         msr = new->thread.ckpt_regs.msr;
 667         /* Recheckpoint to restore original checkpointed register state. */
 668         TM_DEBUG("*** tm_recheckpoint of pid %d "
 669                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 670                  new->pid, new->thread.regs->msr, msr);
 671
 672         /* This loads the checkpointed FP/VEC state, if used */
 673         tm_recheckpoint(&new->thread, msr);
 674
 675         /* This loads the speculative FP/VEC state, if used */
 676         if (msr & MSR_FP) {
 677                 do_load_up_transact_fpu(&new->thread);
 678                 new->thread.regs->msr |=
 679                         (MSR_FP | new->thread.fpexc_mode);
 680         }
 681 #ifdef CONFIG_ALTIVEC
 682         if (msr & MSR_VEC) {
 683                 do_load_up_transact_altivec(&new->thread);
 684                 new->thread.regs->msr |= MSR_VEC;
 685         }
 686 #endif
 687         /* We may as well turn on VSX too since all the state is restored now */
 688         if (msr & MSR_VSX)
 689                 new->thread.regs->msr |= MSR_VSX;
 690
 691         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 692                  "(kernel msr 0x%lx)\n",
 693                  new->pid, mfmsr());
 694 }
 695
 696 static inline void __switch_to_tm(struct task_struct *prev)
 697 {
 698         if (cpu_has_feature(CPU_FTR_TM)) {
 699                 tm_enable();
 700                 tm_reclaim_task(prev);
 701         }
 702 }
 703
 704 /*
 705  * This is called if we are on the way out to userspace and the
 706  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 707  * FP and/or vector state and does so if necessary.
 708  * If userspace is inside a transaction (whether active or
 709  * suspended) and FP/VMX/VSX instructions have ever been enabled
 710  * inside that transaction, then we have to keep them enabled
 711  * and keep the FP/VMX/VSX state loaded while ever the transaction
 712  * continues.  The reason is that if we didn't, and subsequently
 713  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 714  * we don't know whether it's the same transaction, and thus we
 715  * don't know which of the checkpointed state and the transactional
 716  * state to use.
 717  */
 718 void restore_tm_state(struct pt_regs *regs)
 719 {
 720         unsigned long msr_diff;
 721
 722         clear_thread_flag(TIF_RESTORE_TM);
 723         if (!MSR_TM_ACTIVE(regs->msr))
 724                 return;
 725
 726         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 727         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 728         if (msr_diff & MSR_FP) {
 729                 fp_enable();
 730                 load_fp_state(&current->thread.fp_state);
 731                 regs->msr |= current->thread.fpexc_mode;
 732         }
 733         if (msr_diff & MSR_VEC) {
 734                 vec_enable();
 735                 load_vr_state(&current->thread.vr_state);
 736         }
 737         regs->msr |= msr_diff;
 738 }
 739
 740 #else
 741 #define tm_recheckpoint_new_task(new)
 742 #define __switch_to_tm(prev)
 743 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 744
 745 struct task_struct *__switch_to(struct task_struct *prev,
 746         struct task_struct *new)
 747 {
 748         struct thread_struct *new_thread, *old_thread;
 749         struct task_struct *last;
 750 #ifdef CONFIG_PPC_BOOK3S_64
 751         struct ppc64_tlb_batch *batch;
 752 #endif
 753
 754         WARN_ON(!irqs_disabled());
 755
 756         /* Back up the TAR and DSCR across context switches.
 757          * Note that the TAR is not available for use in the kernel.  (To
 758          * provide this, the TAR should be backed up/restored on exception
 759          * entry/exit instead, and be in pt_regs.  FIXME, this should be in
 760          * pt_regs anyway (for debug).)
 761          * Save the TAR and DSCR here before we do treclaim/trecheckpoint as
 762          * these will change them.
 763          */
 764         save_early_sprs(&prev->thread);
 765
 766         __switch_to_tm(prev);
 767
 768 #ifdef CONFIG_SMP
 769         /* avoid complexity of lazy save/restore of fpu
 770          * by just saving it every time we switch out if
 771          * this task used the fpu during the last quantum.
 772          *
 773          * If it tries to use the fpu again, it'll trap and
 774          * reload its fp regs.  So we don't have to do a restore
 775          * every switch, just a save.
 776          *  -- Cort
 777          */
 778         if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
 779                 giveup_fpu(prev);
 780 #ifdef CONFIG_ALTIVEC
 781         /*
 782          * If the previous thread used altivec in the last quantum
 783          * (thus changing altivec regs) then save them.
 784          * We used to check the VRSAVE register but not all apps
 785          * set it, so we don't rely on it now (and in fact we need
 786          * to save & restore VSCR even if VRSAVE == 0).  -- paulus
 787          *
 788          * On SMP we always save/restore altivec regs just to avoid the
 789          * complexity of changing processors.
 790          *  -- Cort
 791          */
 792         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
 793                 giveup_altivec(prev);
 794 #endif /* CONFIG_ALTIVEC */
 795 #ifdef CONFIG_VSX
 796         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
 797                 /* VMX and FPU registers are already save here */
 798                 __giveup_vsx(prev);
 799 #endif /* CONFIG_VSX */
 800 #ifdef CONFIG_SPE
 801         /*
 802          * If the previous thread used spe in the last quantum
 803          * (thus changing spe regs) then save them.
 804          *
 805          * On SMP we always save/restore spe regs just to avoid the
 806          * complexity of changing processors.
 807          */
 808         if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
 809                 giveup_spe(prev);
 810 #endif /* CONFIG_SPE */
 811
 812 #else  /* CONFIG_SMP */
 813 #ifdef CONFIG_ALTIVEC
 814         /* Avoid the trap.  On smp this this never happens since
 815          * we don't set last_task_used_altivec -- Cort
 816          */
 817         if (new->thread.regs && last_task_used_altivec == new)
 818                 new->thread.regs->msr |= MSR_VEC;
 819 #endif /* CONFIG_ALTIVEC */
 820 #ifdef CONFIG_VSX
 821         if (new->thread.regs && last_task_used_vsx == new)
 822                 new->thread.regs->msr |= MSR_VSX;
 823 #endif /* CONFIG_VSX */
 824 #ifdef CONFIG_SPE
 825         /* Avoid the trap.  On smp this this never happens since
 826          * we don't set last_task_used_spe
 827          */
 828         if (new->thread.regs && last_task_used_spe == new)
 829                 new->thread.regs->msr |= MSR_SPE;
 830 #endif /* CONFIG_SPE */
 831
 832 #endif /* CONFIG_SMP */
 833
 834 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 835         switch_booke_debug_regs(&new->thread.debug);
 836 #else
 837 /*
 838  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
 839  * schedule DABR
 840  */
 841 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 842         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
 843                 __set_breakpoint(&new->thread.hw_brk);
 844 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 845 #endif
 846
 847
 848         new_thread = &new->thread;
 849         old_thread = &current->thread;
 850
 851 #ifdef CONFIG_PPC64
 852         /*
 853          * Collect processor utilization data per process
 854          */
 855         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
 856                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
 857                 long unsigned start_tb, current_tb;
 858                 start_tb = old_thread->start_tb;
 859                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
 860                 old_thread->accum_tb += (current_tb - start_tb);
 861                 new_thread->start_tb = current_tb;
 862         }
 863 #endif /* CONFIG_PPC64 */
 864
 865 #ifdef CONFIG_PPC_BOOK3S_64
 866         batch = this_cpu_ptr(&ppc64_tlb_batch);
 867         if (batch->active) {
 868                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
 869                 if (batch->index)
 870                         __flush_tlb_pending(batch);
 871                 batch->active = 0;
 872         }
 873 #endif /* CONFIG_PPC_BOOK3S_64 */
 874
 875         /*
 876          * We can't take a PMU exception inside _switch() since there is a
 877          * window where the kernel stack SLB and the kernel stack are out
 878          * of sync. Hard disable here.
 879          */
 880         hard_irq_disable();
 881
 882         tm_recheckpoint_new_task(new);
 883
 884         last = _switch(old_thread, new_thread);
 885
 886 #ifdef CONFIG_PPC_BOOK3S_64
 887         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
 888                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
 889                 batch = this_cpu_ptr(&ppc64_tlb_batch);
 890                 batch->active = 1;
 891         }
 892 #endif /* CONFIG_PPC_BOOK3S_64 */
 893
 894         return last;
 895 }
 896
 897 static int instructions_to_print = 16;
 898
 899 static void show_instructions(struct pt_regs *regs)
 900 {
 901         int i;
 902         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
 903                         sizeof(int));
 904
 905         printk("Instruction dump:");
 906
 907         for (i = 0; i < instructions_to_print; i++) {
 908                 int instr;
 909
 910                 if (!(i % 8))
 911                         printk("\n");
 912
 913 #if !defined(CONFIG_BOOKE)
 914                 /* If executing with the IMMU off, adjust pc rather
 915                  * than print XXXXXXXX.
 916                  */
 917                 if (!(regs->msr & MSR_IR))
 918                         pc = (unsigned long)phys_to_virt(pc);
 919 #endif
 920
 921                 if (!__kernel_text_address(pc) ||
 922                      probe_kernel_address((unsigned int __user *)pc, instr)) {
 923                         printk(KERN_CONT "XXXXXXXX ");
 924                 } else {
 925                         if (regs->nip == pc)
 926                                 printk(KERN_CONT "<%08x> ", instr);
 927                         else
 928                                 printk(KERN_CONT "%08x ", instr);
 929                 }
 930
 931                 pc += sizeof(int);
 932         }
 933
 934         printk("\n");
 935 }
 936
 937 static struct regbit {
 938         unsigned long bit;
 939         const char *name;
 940 } msr_bits[] = {
 941 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
 942         {MSR_SF,        "SF"},
 943         {MSR_HV,        "HV"},
 944 #endif
 945         {MSR_VEC,       "VEC"},
 946         {MSR_VSX,       "VSX"},
 947 #ifdef CONFIG_BOOKE
 948         {MSR_CE,        "CE"},
 949 #endif
 950         {MSR_EE,        "EE"},
 951         {MSR_PR,        "PR"},
 952         {MSR_FP,        "FP"},
 953         {MSR_ME,        "ME"},
 954 #ifdef CONFIG_BOOKE
 955         {MSR_DE,        "DE"},
 956 #else
 957         {MSR_SE,        "SE"},
 958         {MSR_BE,        "BE"},
 959 #endif
 960         {MSR_IR,        "IR"},
 961         {MSR_DR,        "DR"},
 962         {MSR_PMM,       "PMM"},
 963 #ifndef CONFIG_BOOKE
 964         {MSR_RI,        "RI"},
 965         {MSR_LE,        "LE"},
 966 #endif
 967         {0,             NULL}
 968 };
 969
 970 static void printbits(unsigned long val, struct regbit *bits)
 971 {
 972         const char *sep = "";
 973
 974         printk("<");
 975         for (; bits->bit; ++bits)
 976                 if (val & bits->bit) {
 977                         printk("%s%s", sep, bits->name);
 978                         sep = ",";
 979                 }
 980         printk(">");
 981 }
 982
 983 #ifdef CONFIG_PPC64
 984 #define REG             "%016lx"
 985 #define REGS_PER_LINE   4
 986 #define LAST_VOLATILE   13
 987 #else
 988 #define REG             "%08lx"
 989 #define REGS_PER_LINE   8
 990 #define LAST_VOLATILE   12
 991 #endif
 992
 993 void show_regs(struct pt_regs * regs)
 994 {
 995         int i, trap;
 996
 997         show_regs_print_info(KERN_DEFAULT);
 998
 999         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1000                regs->nip, regs->link, regs->ctr);
1001         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1002                regs, regs->trap, print_tainted(), init_utsname()->release);
1003         printk("MSR: "REG" ", regs->msr);
1004         printbits(regs->msr, msr_bits);
1005         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1006         trap = TRAP(regs);
1007         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1008                 printk("CFAR: "REG" ", regs->orig_gpr3);
1009         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1010 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1011                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1012 #else
1013                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1014 #endif
1015 #ifdef CONFIG_PPC64
1016         printk("SOFTE: %ld ", regs->softe);
1017 #endif
1018 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1019         if (MSR_TM_ACTIVE(regs->msr))
1020                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1021 #endif
1022
1023         for (i = 0;  i < 32;  i++) {
1024                 if ((i % REGS_PER_LINE) == 0)
1025                         printk("\nGPR%02d: ", i);
1026                 printk(REG " ", regs->gpr[i]);
1027                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1028                         break;
1029         }
1030         printk("\n");
1031 #ifdef CONFIG_KALLSYMS
1032         /*
1033          * Lookup NIP late so we have the best change of getting the
1034          * above info out without failing
1035          */
1036         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1037         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1038 #endif
1039         show_stack(current, (unsigned long *) regs->gpr[1]);
1040         if (!user_mode(regs))
1041                 show_instructions(regs);
1042 }
1043
1044 void exit_thread(void)
1045 {
1046         discard_lazy_cpu_state();
1047 }
1048
1049 void flush_thread(void)
1050 {
1051         discard_lazy_cpu_state();
1052
1053 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1054         flush_ptrace_hw_breakpoint(current);
1055 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1056         set_debug_reg_defaults(&current->thread);
1057 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1058 }
1059
1060 void
1061 release_thread(struct task_struct *t)
1062 {
1063 }
1064
1065 /*
1066  * this gets called so that we can store coprocessor state into memory and
1067  * copy the current task into the new thread.
1068  */
1069 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1070 {
1071         flush_fp_to_thread(src);
1072         flush_altivec_to_thread(src);
1073         flush_vsx_to_thread(src);
1074         flush_spe_to_thread(src);
1075         /*
1076          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1077          * flush but it removes the checkpointed state from the current CPU and
1078          * transitions the CPU out of TM mode.  Hence we need to call
1079          * tm_recheckpoint_new_task() (on the same task) to restore the
1080          * checkpointed state back and the TM mode.
1081          */
1082         __switch_to_tm(src);
1083         tm_recheckpoint_new_task(src);
1084
1085         *dst = *src;
1086
1087         clear_task_ebb(dst);
1088
1089         return 0;
1090 }
1091
1092 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1093 {
1094 #ifdef CONFIG_PPC_STD_MMU_64
1095         unsigned long sp_vsid;
1096         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1097
1098         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1099                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1100                         << SLB_VSID_SHIFT_1T;
1101         else
1102                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1103                         << SLB_VSID_SHIFT;
1104         sp_vsid |= SLB_VSID_KERNEL | llp;
1105         p->thread.ksp_vsid = sp_vsid;
1106 #endif
1107 }
1108
1109 /*
1110  * Copy a thread..
1111  */
1112
1113 /*
1114  * Copy architecture-specific thread state
1115  */
1116 int copy_thread(unsigned long clone_flags, unsigned long usp,
1117                 unsigned long kthread_arg, struct task_struct *p)
1118 {
1119         struct pt_regs *childregs, *kregs;
1120         extern void ret_from_fork(void);
1121         extern void ret_from_kernel_thread(void);
1122         void (*f)(void);
1123         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1124
1125         /* Copy registers */
1126         sp -= sizeof(struct pt_regs);
1127         childregs = (struct pt_regs *) sp;
1128         if (unlikely(p->flags & PF_KTHREAD)) {
1129                 /* kernel thread */
1130                 struct thread_info *ti = (void *)task_stack_page(p);
1131                 memset(childregs, 0, sizeof(struct pt_regs));
1132                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1133                 /* function */
1134                 if (usp)
1135                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1136 #ifdef CONFIG_PPC64
1137                 clear_tsk_thread_flag(p, TIF_32BIT);
1138                 childregs->softe = 1;
1139 #endif
1140                 childregs->gpr[15] = kthread_arg;
1141                 p->thread.regs = NULL;  /* no user register state */
1142                 ti->flags |= _TIF_RESTOREALL;
1143                 f = ret_from_kernel_thread;
1144         } else {
1145                 /* user thread */
1146                 struct pt_regs *regs = current_pt_regs();
1147                 CHECK_FULL_REGS(regs);
1148                 *childregs = *regs;
1149                 if (usp)
1150                         childregs->gpr[1] = usp;
1151                 p->thread.regs = childregs;
1152                 childregs->gpr[3] = 0;  /* Result from fork() */
1153                 if (clone_flags & CLONE_SETTLS) {
1154 #ifdef CONFIG_PPC64
1155                         if (!is_32bit_task())
1156                                 childregs->gpr[13] = childregs->gpr[6];
1157                         else
1158 #endif
1159                                 childregs->gpr[2] = childregs->gpr[6];
1160                 }
1161
1162                 f = ret_from_fork;
1163         }
1164         sp -= STACK_FRAME_OVERHEAD;
1165
1166         /*
1167          * The way this works is that at some point in the future
1168          * some task will call _switch to switch to the new task.
1169          * That will pop off the stack frame created below and start
1170          * the new task running at ret_from_fork.  The new task will
1171          * do some house keeping and then return from the fork or clone
1172          * system call, using the stack frame created above.
1173          */
1174         ((unsigned long *)sp)[0] = 0;
1175         sp -= sizeof(struct pt_regs);
1176         kregs = (struct pt_regs *) sp;
1177         sp -= STACK_FRAME_OVERHEAD;
1178         p->thread.ksp = sp;
1179 #ifdef CONFIG_PPC32
1180         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1181                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1182 #endif
1183 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1184         p->thread.ptrace_bps[0] = NULL;
1185 #endif
1186
1187         p->thread.fp_save_area = NULL;
1188 #ifdef CONFIG_ALTIVEC
1189         p->thread.vr_save_area = NULL;
1190 #endif
1191
1192         setup_ksp_vsid(p, sp);
1193
1194 #ifdef CONFIG_PPC64
1195         if (cpu_has_feature(CPU_FTR_DSCR)) {
1196                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1197                 p->thread.dscr = current->thread.dscr;
1198         }
1199         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1200                 p->thread.ppr = INIT_PPR;
1201 #endif
1202         kregs->nip = ppc_function_entry(f);
1203         return 0;
1204 }
1205
1206 /*
1207  * Set up a thread for executing a new program
1208  */
1209 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1210 {
1211 #ifdef CONFIG_PPC64
1212         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1213 #endif
1214
1215         /*
1216          * If we exec out of a kernel thread then thread.regs will not be
1217          * set.  Do it now.
1218          */
1219         if (!current->thread.regs) {
1220                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1221                 current->thread.regs = regs - 1;
1222         }
1223
1224         memset(regs->gpr, 0, sizeof(regs->gpr));
1225         regs->ctr = 0;
1226         regs->link = 0;
1227         regs->xer = 0;
1228         regs->ccr = 0;
1229         regs->gpr[1] = sp;
1230
1231         /*
1232          * We have just cleared all the nonvolatile GPRs, so make
1233          * FULL_REGS(regs) return true.  This is necessary to allow
1234          * ptrace to examine the thread immediately after exec.
1235          */
1236         regs->trap &= ~1UL;
1237
1238 #ifdef CONFIG_PPC32
1239         regs->mq = 0;
1240         regs->nip = start;
1241         regs->msr = MSR_USER;
1242 #else
1243         if (!is_32bit_task()) {
1244                 unsigned long entry;
1245
1246                 if (is_elf2_task()) {
1247                         /* Look ma, no function descriptors! */
1248                         entry = start;
1249
1250                         /*
1251                          * Ulrich says:
1252                          *   The latest iteration of the ABI requires that when
1253                          *   calling a function (at its global entry point),
1254                          *   the caller must ensure r12 holds the entry point
1255                          *   address (so that the function can quickly
1256                          *   establish addressability).
1257                          */
1258                         regs->gpr[12] = start;
1259                         /* Make sure that's restored on entry to userspace. */
1260                         set_thread_flag(TIF_RESTOREALL);
1261                 } else {
1262                         unsigned long toc;
1263
1264                         /* start is a relocated pointer to the function
1265                          * descriptor for the elf _start routine.  The first
1266                          * entry in the function descriptor is the entry
1267                          * address of _start and the second entry is the TOC
1268                          * value we need to use.
1269                          */
1270                         __get_user(entry, (unsigned long __user *)start);
1271                         __get_user(toc, (unsigned long __user *)start+1);
1272
1273                         /* Check whether the e_entry function descriptor entries
1274                          * need to be relocated before we can use them.
1275                          */
1276                         if (load_addr != 0) {
1277                                 entry += load_addr;
1278                                 toc   += load_addr;
1279                         }
1280                         regs->gpr[2] = toc;
1281                 }
1282                 regs->nip = entry;
1283                 regs->msr = MSR_USER64;
1284         } else {
1285                 regs->nip = start;
1286                 regs->gpr[2] = 0;
1287                 regs->msr = MSR_USER32;
1288         }
1289 #endif
1290         discard_lazy_cpu_state();
1291 #ifdef CONFIG_VSX
1292         current->thread.used_vsr = 0;
1293 #endif
1294         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1295         current->thread.fp_save_area = NULL;
1296 #ifdef CONFIG_ALTIVEC
1297         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1298         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1299         current->thread.vr_save_area = NULL;
1300         current->thread.vrsave = 0;
1301         current->thread.used_vr = 0;
1302 #endif /* CONFIG_ALTIVEC */
1303 #ifdef CONFIG_SPE
1304         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1305         current->thread.acc = 0;
1306         current->thread.spefscr = 0;
1307         current->thread.used_spe = 0;
1308 #endif /* CONFIG_SPE */
1309 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1310         if (cpu_has_feature(CPU_FTR_TM))
1311                 regs->msr |= MSR_TM;
1312         current->thread.tm_tfhar = 0;
1313         current->thread.tm_texasr = 0;
1314         current->thread.tm_tfiar = 0;
1315 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1316 }
1317 EXPORT_SYMBOL(start_thread);
1318
1319 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1320                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1321
1322 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1323 {
1324         struct pt_regs *regs = tsk->thread.regs;
1325
1326         /* This is a bit hairy.  If we are an SPE enabled  processor
1327          * (have embedded fp) we store the IEEE exception enable flags in
1328          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1329          * mode (asyn, precise, disabled) for 'Classic' FP. */
1330         if (val & PR_FP_EXC_SW_ENABLE) {
1331 #ifdef CONFIG_SPE
1332                 if (cpu_has_feature(CPU_FTR_SPE)) {
1333                         /*
1334                          * When the sticky exception bits are set
1335                          * directly by userspace, it must call prctl
1336                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1337                          * in the existing prctl settings) or
1338                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1339                          * the bits being set).  <fenv.h> functions
1340                          * saving and restoring the whole
1341                          * floating-point environment need to do so
1342                          * anyway to restore the prctl settings from
1343                          * the saved environment.
1344                          */
1345                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1346                         tsk->thread.fpexc_mode = val &
1347                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1348                         return 0;
1349                 } else {
1350                         return -EINVAL;
1351                 }
1352 #else
1353                 return -EINVAL;
1354 #endif
1355         }
1356
1357         /* on a CONFIG_SPE this does not hurt us.  The bits that
1358          * __pack_fe01 use do not overlap with bits used for
1359          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1360          * on CONFIG_SPE implementations are reserved so writing to
1361          * them does not change anything */
1362         if (val > PR_FP_EXC_PRECISE)
1363                 return -EINVAL;
1364         tsk->thread.fpexc_mode = __pack_fe01(val);
1365         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1366                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1367                         | tsk->thread.fpexc_mode;
1368         return 0;
1369 }
1370
1371 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1372 {
1373         unsigned int val;
1374
1375         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1376 #ifdef CONFIG_SPE
1377                 if (cpu_has_feature(CPU_FTR_SPE)) {
1378                         /*
1379                          * When the sticky exception bits are set
1380                          * directly by userspace, it must call prctl
1381                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1382                          * in the existing prctl settings) or
1383                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1384                          * the bits being set).  <fenv.h> functions
1385                          * saving and restoring the whole
1386                          * floating-point environment need to do so
1387                          * anyway to restore the prctl settings from
1388                          * the saved environment.
1389                          */
1390                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1391                         val = tsk->thread.fpexc_mode;
1392                 } else
1393                         return -EINVAL;
1394 #else
1395                 return -EINVAL;
1396 #endif
1397         else
1398                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1399         return put_user(val, (unsigned int __user *) adr);
1400 }
1401
1402 int set_endian(struct task_struct *tsk, unsigned int val)
1403 {
1404         struct pt_regs *regs = tsk->thread.regs;
1405
1406         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1407             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1408                 return -EINVAL;
1409
1410         if (regs == NULL)
1411                 return -EINVAL;
1412
1413         if (val == PR_ENDIAN_BIG)
1414                 regs->msr &= ~MSR_LE;
1415         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1416                 regs->msr |= MSR_LE;
1417         else
1418                 return -EINVAL;
1419
1420         return 0;
1421 }
1422
1423 int get_endian(struct task_struct *tsk, unsigned long adr)
1424 {
1425         struct pt_regs *regs = tsk->thread.regs;
1426         unsigned int val;
1427
1428         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1429             !cpu_has_feature(CPU_FTR_REAL_LE))
1430                 return -EINVAL;
1431
1432         if (regs == NULL)
1433                 return -EINVAL;
1434
1435         if (regs->msr & MSR_LE) {
1436                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1437                         val = PR_ENDIAN_LITTLE;
1438                 else
1439                         val = PR_ENDIAN_PPC_LITTLE;
1440         } else
1441                 val = PR_ENDIAN_BIG;
1442
1443         return put_user(val, (unsigned int __user *)adr);
1444 }
1445
1446 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1447 {
1448         tsk->thread.align_ctl = val;
1449         return 0;
1450 }
1451
1452 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1453 {
1454         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1455 }
1456
1457 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1458                                   unsigned long nbytes)
1459 {
1460         unsigned long stack_page;
1461         unsigned long cpu = task_cpu(p);
1462
1463         /*
1464          * Avoid crashing if the stack has overflowed and corrupted
1465          * task_cpu(p), which is in the thread_info struct.
1466          */
1467         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1468                 stack_page = (unsigned long) hardirq_ctx[cpu];
1469                 if (sp >= stack_page + sizeof(struct thread_struct)
1470                     && sp <= stack_page + THREAD_SIZE - nbytes)
1471                         return 1;
1472
1473                 stack_page = (unsigned long) softirq_ctx[cpu];
1474                 if (sp >= stack_page + sizeof(struct thread_struct)
1475                     && sp <= stack_page + THREAD_SIZE - nbytes)
1476                         return 1;
1477         }
1478         return 0;
1479 }
1480
1481 int validate_sp(unsigned long sp, struct task_struct *p,
1482                        unsigned long nbytes)
1483 {
1484         unsigned long stack_page = (unsigned long)task_stack_page(p);
1485
1486         if (sp >= stack_page + sizeof(struct thread_struct)
1487             && sp <= stack_page + THREAD_SIZE - nbytes)
1488                 return 1;
1489
1490         return valid_irq_stack(sp, p, nbytes);
1491 }
1492
1493 EXPORT_SYMBOL(validate_sp);
1494
1495 unsigned long get_wchan(struct task_struct *p)
1496 {
1497         unsigned long ip, sp;
1498         int count = 0;
1499
1500         if (!p || p == current || p->state == TASK_RUNNING)
1501                 return 0;
1502
1503         sp = p->thread.ksp;
1504         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1505                 return 0;
1506
1507         do {
1508                 sp = *(unsigned long *)sp;
1509                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1510                         return 0;
1511                 if (count > 0) {
1512                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1513                         if (!in_sched_functions(ip))
1514                                 return ip;
1515                 }
1516         } while (count++ < 16);
1517         return 0;
1518 }
1519
1520 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1521
1522 void show_stack(struct task_struct *tsk, unsigned long *stack)
1523 {
1524         unsigned long sp, ip, lr, newsp;
1525         int count = 0;
1526         int firstframe = 1;
1527 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1528         int curr_frame = current->curr_ret_stack;
1529         extern void return_to_handler(void);
1530         unsigned long rth = (unsigned long)return_to_handler;
1531 #endif
1532
1533         sp = (unsigned long) stack;
1534         if (tsk == NULL)
1535                 tsk = current;
1536         if (sp == 0) {
1537                 if (tsk == current)
1538                         sp = current_stack_pointer();
1539                 else
1540                         sp = tsk->thread.ksp;
1541         }
1542
1543         lr = 0;
1544         printk("Call Trace:\n");
1545         do {
1546                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1547                         return;
1548
1549                 stack = (unsigned long *) sp;
1550                 newsp = stack[0];
1551                 ip = stack[STACK_FRAME_LR_SAVE];
1552                 if (!firstframe || ip != lr) {
1553                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1554 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1555                         if ((ip == rth) && curr_frame >= 0) {
1556                                 printk(" (%pS)",
1557                                        (void *)current->ret_stack[curr_frame].ret);
1558                                 curr_frame--;
1559                         }
1560 #endif
1561                         if (firstframe)
1562                                 printk(" (unreliable)");
1563                         printk("\n");
1564                 }
1565                 firstframe = 0;
1566
1567                 /*
1568                  * See if this is an exception frame.
1569                  * We look for the "regshere" marker in the current frame.
1570                  */
1571                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1572                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1573                         struct pt_regs *regs = (struct pt_regs *)
1574                                 (sp + STACK_FRAME_OVERHEAD);
1575                         lr = regs->link;
1576                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1577                                regs->trap, (void *)regs->nip, (void *)lr);
1578                         firstframe = 1;
1579                 }
1580
1581                 sp = newsp;
1582         } while (count++ < kstack_depth_to_print);
1583 }
1584
1585 #ifdef CONFIG_PPC64
1586 /* Called with hard IRQs off */
1587 void notrace __ppc64_runlatch_on(void)
1588 {
1589         struct thread_info *ti = current_thread_info();
1590         unsigned long ctrl;
1591
1592         ctrl = mfspr(SPRN_CTRLF);
1593         ctrl |= CTRL_RUNLATCH;
1594         mtspr(SPRN_CTRLT, ctrl);
1595
1596         ti->local_flags |= _TLF_RUNLATCH;
1597 }
1598
1599 /* Called with hard IRQs off */
1600 void notrace __ppc64_runlatch_off(void)
1601 {
1602         struct thread_info *ti = current_thread_info();
1603         unsigned long ctrl;
1604
1605         ti->local_flags &= ~_TLF_RUNLATCH;
1606
1607         ctrl = mfspr(SPRN_CTRLF);
1608         ctrl &= ~CTRL_RUNLATCH;
1609         mtspr(SPRN_CTRLT, ctrl);
1610 }
1611 #endif /* CONFIG_PPC64 */
1612
1613 unsigned long arch_align_stack(unsigned long sp)
1614 {
1615         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1616                 sp -= get_random_int() & ~PAGE_MASK;
1617         return sp & ~0xf;
1618 }
1619
1620 static inline unsigned long brk_rnd(void)
1621 {
1622         unsigned long rnd = 0;
1623
1624         /* 8MB for 32bit, 1GB for 64bit */
1625         if (is_32bit_task())
1626                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1627         else
1628                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1629
1630         return rnd << PAGE_SHIFT;
1631 }
1632
1633 unsigned long arch_randomize_brk(struct mm_struct *mm)
1634 {
1635         unsigned long base = mm->brk;
1636         unsigned long ret;
1637
1638 #ifdef CONFIG_PPC_STD_MMU_64
1639         /*
1640          * If we are using 1TB segments and we are allowed to randomise
1641          * the heap, we can put it above 1TB so it is backed by a 1TB
1642          * segment. Otherwise the heap will be in the bottom 1TB
1643          * which always uses 256MB segments and this may result in a
1644          * performance penalty.
1645          */
1646         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1647                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1648 #endif
1649
1650         ret = PAGE_ALIGN(base + brk_rnd());
1651
1652         if (ret < mm->brk)
1653                 return mm->brk;
1654
1655         return ret;
1656 }
1657