2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 #include <linux/init.h>
13 #include <asm/irq_cpu.h>
14 #include <asm/setup.h>
16 #include <asm/mips-boards/sead3int.h>
18 #define SEAD_CONFIG_GIC_PRESENT_SHF 1
19 #define SEAD_CONFIG_GIC_PRESENT_MSK (1 << SEAD_CONFIG_GIC_PRESENT_SHF)
20 #define SEAD_CONFIG_BASE 0x1b100110
21 #define SEAD_CONFIG_SIZE 4
23 static unsigned long sead3_config_reg;
26 * This table defines the setup for each external GIC interrupt. It is
27 * indexed by interrupt number.
29 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
30 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
31 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
32 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
33 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
34 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
35 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
36 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
37 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
38 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
39 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
40 { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
41 { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
42 { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
43 { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
44 { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
45 { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
46 { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
49 asmlinkage void plat_irq_dispatch(void)
51 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
54 irq = (fls(pending) - CAUSEB_IP - 1);
56 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
61 void __init arch_init_irq(void)
69 /* install generic handler */
70 for (i = 0; i < 8; i++)
71 set_vi_handler(i, plat_irq_dispatch);
75 sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE,
77 gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >>
78 SEAD_CONFIG_GIC_PRESENT_SHF;
79 pr_info("GIC: %spresent\n", (gic_present) ? "" : "not ");
81 (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off");
84 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
85 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
88 void __init gic_platform_init(int irqs, struct irq_chip *irq_controller)
93 * For non-EIC mode, we want to setup the GIC in pass-through
94 * mode, as if the GIC didn't exist. Do not map any interrupts
95 * for an external interrupt controller.
100 for (i = gic_irq_base; i < (gic_irq_base + irqs); i++)
101 irq_set_chip_and_handler(i, irq_controller, handle_percpu_irq);