2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
22 * The following macros are especially useful for __asm__
29 #define STR(x) __STR(x)
38 #define _ULCAST_ (unsigned long)
42 * Coprocessor 0 register names
46 #define CP0_ENTRYLO0 $2
47 #define CP0_ENTRYLO1 $3
49 #define CP0_CONTEXT $4
50 #define CP0_PAGEMASK $5
53 #define CP0_BADVADDR $8
55 #define CP0_ENTRYHI $10
56 #define CP0_COMPARE $11
57 #define CP0_STATUS $12
61 #define CP0_CONFIG $16
62 #define CP0_LLADDR $17
63 #define CP0_WATCHLO $18
64 #define CP0_WATCHHI $19
65 #define CP0_XCONTEXT $20
66 #define CP0_FRAMEMASK $21
67 #define CP0_DIAGNOSTIC $22
70 #define CP0_PERFORMANCE $25
72 #define CP0_CACHEERR $27
75 #define CP0_ERROREPC $30
76 #define CP0_DESAVE $31
79 * R4640/R4650 cp0 register names. These registers are listed
80 * here only for completeness; without MMU these CPUs are not useable
81 * by Linux. A future ELKS port might take make Linux run on them
89 #define CP0_IWATCH $18
90 #define CP0_DWATCH $19
93 * Coprocessor 0 Set 1 register names
95 #define CP0_S1_DERRADDR0 $26
96 #define CP0_S1_DERRADDR1 $27
97 #define CP0_S1_INTCONTROL $20
100 * Coprocessor 0 Set 2 register names
102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
105 * Coprocessor 0 Set 3 register names
107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
112 #define CP0_TX39_CACHE $7
115 * Coprocessor 1 (FPU) register names
117 #define CP1_REVISION $0
118 #define CP1_STATUS $31
121 * FPU Status Register Values
124 * Status Register Values
127 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
128 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
129 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
130 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
131 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
132 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
133 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
134 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
135 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
136 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
139 * Bits 18 - 20 of the FPU Status Register will be read as 0,
140 * and should be written as zero.
142 #define FPU_CSR_RSVD 0x001c0000
145 * X the exception cause indicator
146 * E the exception enable
147 * S the sticky/flag bit
149 #define FPU_CSR_ALL_X 0x0003f000
150 #define FPU_CSR_UNI_X 0x00020000
151 #define FPU_CSR_INV_X 0x00010000
152 #define FPU_CSR_DIV_X 0x00008000
153 #define FPU_CSR_OVF_X 0x00004000
154 #define FPU_CSR_UDF_X 0x00002000
155 #define FPU_CSR_INE_X 0x00001000
157 #define FPU_CSR_ALL_E 0x00000f80
158 #define FPU_CSR_INV_E 0x00000800
159 #define FPU_CSR_DIV_E 0x00000400
160 #define FPU_CSR_OVF_E 0x00000200
161 #define FPU_CSR_UDF_E 0x00000100
162 #define FPU_CSR_INE_E 0x00000080
164 #define FPU_CSR_ALL_S 0x0000007c
165 #define FPU_CSR_INV_S 0x00000040
166 #define FPU_CSR_DIV_S 0x00000020
167 #define FPU_CSR_OVF_S 0x00000010
168 #define FPU_CSR_UDF_S 0x00000008
169 #define FPU_CSR_INE_S 0x00000004
171 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
172 #define FPU_CSR_RM 0x00000003
173 #define FPU_CSR_RN 0x0 /* nearest */
174 #define FPU_CSR_RZ 0x1 /* towards zero */
175 #define FPU_CSR_RU 0x2 /* towards +Infinity */
176 #define FPU_CSR_RD 0x3 /* towards -Infinity */
180 * Values for PageMask register
182 #ifdef CONFIG_CPU_VR41XX
184 /* Why doesn't stupidity hurt ... */
186 #define PM_1K 0x00000000
187 #define PM_4K 0x00001800
188 #define PM_16K 0x00007800
189 #define PM_64K 0x0001f800
190 #define PM_256K 0x0007f800
194 #define PM_4K 0x00000000
195 #define PM_8K 0x00002000
196 #define PM_16K 0x00006000
197 #define PM_32K 0x0000e000
198 #define PM_64K 0x0001e000
199 #define PM_128K 0x0003e000
200 #define PM_256K 0x0007e000
201 #define PM_512K 0x000fe000
202 #define PM_1M 0x001fe000
203 #define PM_2M 0x003fe000
204 #define PM_4M 0x007fe000
205 #define PM_8M 0x00ffe000
206 #define PM_16M 0x01ffe000
207 #define PM_32M 0x03ffe000
208 #define PM_64M 0x07ffe000
209 #define PM_256M 0x1fffe000
210 #define PM_1G 0x7fffe000
215 * Default page size for a given kernel configuration
217 #ifdef CONFIG_PAGE_SIZE_4KB
218 #define PM_DEFAULT_MASK PM_4K
219 #elif defined(CONFIG_PAGE_SIZE_8KB)
220 #define PM_DEFAULT_MASK PM_8K
221 #elif defined(CONFIG_PAGE_SIZE_16KB)
222 #define PM_DEFAULT_MASK PM_16K
223 #elif defined(CONFIG_PAGE_SIZE_32KB)
224 #define PM_DEFAULT_MASK PM_32K
225 #elif defined(CONFIG_PAGE_SIZE_64KB)
226 #define PM_DEFAULT_MASK PM_64K
228 #error Bad page size configuration!
232 * Default huge tlb size for a given kernel configuration
234 #ifdef CONFIG_PAGE_SIZE_4KB
235 #define PM_HUGE_MASK PM_1M
236 #elif defined(CONFIG_PAGE_SIZE_8KB)
237 #define PM_HUGE_MASK PM_4M
238 #elif defined(CONFIG_PAGE_SIZE_16KB)
239 #define PM_HUGE_MASK PM_16M
240 #elif defined(CONFIG_PAGE_SIZE_32KB)
241 #define PM_HUGE_MASK PM_64M
242 #elif defined(CONFIG_PAGE_SIZE_64KB)
243 #define PM_HUGE_MASK PM_256M
244 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
245 #error Bad page size configuration for hugetlbfs!
249 * Values used for computation of new tlb entries
264 #define PG_RIE (_ULCAST_(1) << 31)
265 #define PG_XIE (_ULCAST_(1) << 30)
266 #define PG_ELPA (_ULCAST_(1) << 29)
267 #define PG_ESP (_ULCAST_(1) << 28)
270 * R4x00 interrupt enable / cause bits
272 #define IE_SW0 (_ULCAST_(1) << 8)
273 #define IE_SW1 (_ULCAST_(1) << 9)
274 #define IE_IRQ0 (_ULCAST_(1) << 10)
275 #define IE_IRQ1 (_ULCAST_(1) << 11)
276 #define IE_IRQ2 (_ULCAST_(1) << 12)
277 #define IE_IRQ3 (_ULCAST_(1) << 13)
278 #define IE_IRQ4 (_ULCAST_(1) << 14)
279 #define IE_IRQ5 (_ULCAST_(1) << 15)
282 * R4x00 interrupt cause bits
284 #define C_SW0 (_ULCAST_(1) << 8)
285 #define C_SW1 (_ULCAST_(1) << 9)
286 #define C_IRQ0 (_ULCAST_(1) << 10)
287 #define C_IRQ1 (_ULCAST_(1) << 11)
288 #define C_IRQ2 (_ULCAST_(1) << 12)
289 #define C_IRQ3 (_ULCAST_(1) << 13)
290 #define C_IRQ4 (_ULCAST_(1) << 14)
291 #define C_IRQ5 (_ULCAST_(1) << 15)
294 * Bitfields in the R4xx0 cp0 status register
296 #define ST0_IE 0x00000001
297 #define ST0_EXL 0x00000002
298 #define ST0_ERL 0x00000004
299 #define ST0_KSU 0x00000018
300 # define KSU_USER 0x00000010
301 # define KSU_SUPERVISOR 0x00000008
302 # define KSU_KERNEL 0x00000000
303 #define ST0_UX 0x00000020
304 #define ST0_SX 0x00000040
305 #define ST0_KX 0x00000080
306 #define ST0_DE 0x00010000
307 #define ST0_CE 0x00020000
310 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
311 * cacheops in userspace. This bit exists only on RM7000 and RM9000
314 #define ST0_CO 0x08000000
317 * Bitfields in the R[23]000 cp0 status register.
319 #define ST0_IEC 0x00000001
320 #define ST0_KUC 0x00000002
321 #define ST0_IEP 0x00000004
322 #define ST0_KUP 0x00000008
323 #define ST0_IEO 0x00000010
324 #define ST0_KUO 0x00000020
325 /* bits 6 & 7 are reserved on R[23]000 */
326 #define ST0_ISC 0x00010000
327 #define ST0_SWC 0x00020000
328 #define ST0_CM 0x00080000
331 * Bits specific to the R4640/R4650
333 #define ST0_UM (_ULCAST_(1) << 4)
334 #define ST0_IL (_ULCAST_(1) << 23)
335 #define ST0_DL (_ULCAST_(1) << 24)
338 * Enable the MIPS MDMX and DSP ASEs
340 #define ST0_MX 0x01000000
343 * Bitfields in the TX39 family CP0 Configuration Register 3
345 #define TX39_CONF_ICS_SHIFT 19
346 #define TX39_CONF_ICS_MASK 0x00380000
347 #define TX39_CONF_ICS_1KB 0x00000000
348 #define TX39_CONF_ICS_2KB 0x00080000
349 #define TX39_CONF_ICS_4KB 0x00100000
350 #define TX39_CONF_ICS_8KB 0x00180000
351 #define TX39_CONF_ICS_16KB 0x00200000
353 #define TX39_CONF_DCS_SHIFT 16
354 #define TX39_CONF_DCS_MASK 0x00070000
355 #define TX39_CONF_DCS_1KB 0x00000000
356 #define TX39_CONF_DCS_2KB 0x00010000
357 #define TX39_CONF_DCS_4KB 0x00020000
358 #define TX39_CONF_DCS_8KB 0x00030000
359 #define TX39_CONF_DCS_16KB 0x00040000
361 #define TX39_CONF_CWFON 0x00004000
362 #define TX39_CONF_WBON 0x00002000
363 #define TX39_CONF_RF_SHIFT 10
364 #define TX39_CONF_RF_MASK 0x00000c00
365 #define TX39_CONF_DOZE 0x00000200
366 #define TX39_CONF_HALT 0x00000100
367 #define TX39_CONF_LOCK 0x00000080
368 #define TX39_CONF_ICE 0x00000020
369 #define TX39_CONF_DCE 0x00000010
370 #define TX39_CONF_IRSIZE_SHIFT 2
371 #define TX39_CONF_IRSIZE_MASK 0x0000000c
372 #define TX39_CONF_DRSIZE_SHIFT 0
373 #define TX39_CONF_DRSIZE_MASK 0x00000003
376 * Status register bits available in all MIPS CPUs.
378 #define ST0_IM 0x0000ff00
379 #define STATUSB_IP0 8
380 #define STATUSF_IP0 (_ULCAST_(1) << 8)
381 #define STATUSB_IP1 9
382 #define STATUSF_IP1 (_ULCAST_(1) << 9)
383 #define STATUSB_IP2 10
384 #define STATUSF_IP2 (_ULCAST_(1) << 10)
385 #define STATUSB_IP3 11
386 #define STATUSF_IP3 (_ULCAST_(1) << 11)
387 #define STATUSB_IP4 12
388 #define STATUSF_IP4 (_ULCAST_(1) << 12)
389 #define STATUSB_IP5 13
390 #define STATUSF_IP5 (_ULCAST_(1) << 13)
391 #define STATUSB_IP6 14
392 #define STATUSF_IP6 (_ULCAST_(1) << 14)
393 #define STATUSB_IP7 15
394 #define STATUSF_IP7 (_ULCAST_(1) << 15)
395 #define STATUSB_IP8 0
396 #define STATUSF_IP8 (_ULCAST_(1) << 0)
397 #define STATUSB_IP9 1
398 #define STATUSF_IP9 (_ULCAST_(1) << 1)
399 #define STATUSB_IP10 2
400 #define STATUSF_IP10 (_ULCAST_(1) << 2)
401 #define STATUSB_IP11 3
402 #define STATUSF_IP11 (_ULCAST_(1) << 3)
403 #define STATUSB_IP12 4
404 #define STATUSF_IP12 (_ULCAST_(1) << 4)
405 #define STATUSB_IP13 5
406 #define STATUSF_IP13 (_ULCAST_(1) << 5)
407 #define STATUSB_IP14 6
408 #define STATUSF_IP14 (_ULCAST_(1) << 6)
409 #define STATUSB_IP15 7
410 #define STATUSF_IP15 (_ULCAST_(1) << 7)
411 #define ST0_CH 0x00040000
412 #define ST0_NMI 0x00080000
413 #define ST0_SR 0x00100000
414 #define ST0_TS 0x00200000
415 #define ST0_BEV 0x00400000
416 #define ST0_RE 0x02000000
417 #define ST0_FR 0x04000000
418 #define ST0_CU 0xf0000000
419 #define ST0_CU0 0x10000000
420 #define ST0_CU1 0x20000000
421 #define ST0_CU2 0x40000000
422 #define ST0_CU3 0x80000000
423 #define ST0_XX 0x80000000 /* MIPS IV naming */
426 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
428 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
430 #define INTCTLB_IPPCI 26
431 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
432 #define INTCTLB_IPTI 29
433 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
436 * Bitfields and bit numbers in the coprocessor 0 cause register.
438 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
440 #define CAUSEB_EXCCODE 2
441 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
443 #define CAUSEF_IP (_ULCAST_(255) << 8)
445 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
447 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
448 #define CAUSEB_IP2 10
449 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
450 #define CAUSEB_IP3 11
451 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
452 #define CAUSEB_IP4 12
453 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
454 #define CAUSEB_IP5 13
455 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
456 #define CAUSEB_IP6 14
457 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
458 #define CAUSEB_IP7 15
459 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
461 #define CAUSEF_IV (_ULCAST_(1) << 23)
462 #define CAUSEB_PCI 26
463 #define CAUSEF_PCI (_ULCAST_(1) << 26)
465 #define CAUSEF_CE (_ULCAST_(3) << 28)
467 #define CAUSEF_TI (_ULCAST_(1) << 30)
469 #define CAUSEF_BD (_ULCAST_(1) << 31)
472 * Bits in the coprocessor 0 config register.
475 #define CONF_CM_CACHABLE_NO_WA 0
476 #define CONF_CM_CACHABLE_WA 1
477 #define CONF_CM_UNCACHED 2
478 #define CONF_CM_CACHABLE_NONCOHERENT 3
479 #define CONF_CM_CACHABLE_CE 4
480 #define CONF_CM_CACHABLE_COW 5
481 #define CONF_CM_CACHABLE_CUW 6
482 #define CONF_CM_CACHABLE_ACCELERATED 7
483 #define CONF_CM_CMASK 7
484 #define CONF_BE (_ULCAST_(1) << 15)
486 /* Bits common to various processors. */
487 #define CONF_CU (_ULCAST_(1) << 3)
488 #define CONF_DB (_ULCAST_(1) << 4)
489 #define CONF_IB (_ULCAST_(1) << 5)
490 #define CONF_DC (_ULCAST_(7) << 6)
491 #define CONF_IC (_ULCAST_(7) << 9)
492 #define CONF_EB (_ULCAST_(1) << 13)
493 #define CONF_EM (_ULCAST_(1) << 14)
494 #define CONF_SM (_ULCAST_(1) << 16)
495 #define CONF_SC (_ULCAST_(1) << 17)
496 #define CONF_EW (_ULCAST_(3) << 18)
497 #define CONF_EP (_ULCAST_(15)<< 24)
498 #define CONF_EC (_ULCAST_(7) << 28)
499 #define CONF_CM (_ULCAST_(1) << 31)
501 /* Bits specific to the R4xx0. */
502 #define R4K_CONF_SW (_ULCAST_(1) << 20)
503 #define R4K_CONF_SS (_ULCAST_(1) << 21)
504 #define R4K_CONF_SB (_ULCAST_(3) << 22)
506 /* Bits specific to the R5000. */
507 #define R5K_CONF_SE (_ULCAST_(1) << 12)
508 #define R5K_CONF_SS (_ULCAST_(3) << 20)
510 /* Bits specific to the RM7000. */
511 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
512 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
513 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
514 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
515 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
516 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
518 /* Bits specific to the R10000. */
519 #define R10K_CONF_DN (_ULCAST_(3) << 3)
520 #define R10K_CONF_CT (_ULCAST_(1) << 5)
521 #define R10K_CONF_PE (_ULCAST_(1) << 6)
522 #define R10K_CONF_PM (_ULCAST_(3) << 7)
523 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
524 #define R10K_CONF_SB (_ULCAST_(1) << 13)
525 #define R10K_CONF_SK (_ULCAST_(1) << 14)
526 #define R10K_CONF_SS (_ULCAST_(7) << 16)
527 #define R10K_CONF_SC (_ULCAST_(7) << 19)
528 #define R10K_CONF_DC (_ULCAST_(7) << 26)
529 #define R10K_CONF_IC (_ULCAST_(7) << 29)
531 /* Bits specific to the VR41xx. */
532 #define VR41_CONF_CS (_ULCAST_(1) << 12)
533 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
534 #define VR41_CONF_BP (_ULCAST_(1) << 16)
535 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
536 #define VR41_CONF_AD (_ULCAST_(1) << 23)
538 /* Bits specific to the R30xx. */
539 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
540 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
541 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
542 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
543 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
544 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
545 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
546 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
547 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
549 /* Bits specific to the TX49. */
550 #define TX49_CONF_DC (_ULCAST_(1) << 16)
551 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
552 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
553 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
555 /* Bits specific to the MIPS32/64 PRA. */
556 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
557 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
558 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
559 #define MIPS_CONF_M (_ULCAST_(1) << 31)
562 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
564 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
565 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
566 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
567 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
568 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
569 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
570 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
571 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
572 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
573 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
574 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
575 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
576 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
577 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
579 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
580 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
581 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
582 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
583 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
584 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
585 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
586 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
588 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
589 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
590 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
591 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
592 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
593 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
594 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
595 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
596 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
597 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
598 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
599 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
600 #define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16)
601 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
603 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
604 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
605 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
607 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
609 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
611 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
615 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
617 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
618 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
619 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
620 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
621 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
622 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
623 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
628 * Macros for handling the ISA mode bit for microMIPS.
630 #define get_isa16_mode(x) ((x) & 0x1)
631 #define msk_isa16_mode(x) ((x) & ~0x1)
632 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
635 * microMIPS instructions can be 16-bit or 32-bit in length. This
636 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
638 static inline int mm_insn_16bit(u16 insn)
640 u16 opcode = (insn >> 10) & 0x7;
642 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
646 * Functions to access the R10000 performance counters. These are basically
647 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
648 * performance counter number encoded into bits 1 ... 5 of the instruction.
649 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
650 * disassembler these will look like an access to sel 0 or 1.
652 #define read_r10k_perf_cntr(counter) \
654 unsigned int __res; \
655 __asm__ __volatile__( \
663 #define write_r10k_perf_cntr(counter,val) \
665 __asm__ __volatile__( \
668 : "r" (val), "i" (counter)); \
671 #define read_r10k_perf_event(counter) \
673 unsigned int __res; \
674 __asm__ __volatile__( \
682 #define write_r10k_perf_cntl(counter,val) \
684 __asm__ __volatile__( \
687 : "r" (val), "i" (counter)); \
692 * Macros to access the system control coprocessor
695 #define __read_32bit_c0_register(source, sel) \
698 __asm__ __volatile__( \
699 "mfc0\t%0, " #source "\n\t" \
702 __asm__ __volatile__( \
704 "mfc0\t%0, " #source ", " #sel "\n\t" \
710 #define __read_64bit_c0_register(source, sel) \
711 ({ unsigned long long __res; \
712 if (sizeof(unsigned long) == 4) \
713 __res = __read_64bit_c0_split(source, sel); \
715 __asm__ __volatile__( \
717 "dmfc0\t%0, " #source "\n\t" \
721 __asm__ __volatile__( \
723 "dmfc0\t%0, " #source ", " #sel "\n\t" \
729 #define __write_32bit_c0_register(register, sel, value) \
732 __asm__ __volatile__( \
733 "mtc0\t%z0, " #register "\n\t" \
734 : : "Jr" ((unsigned int)(value))); \
736 __asm__ __volatile__( \
738 "mtc0\t%z0, " #register ", " #sel "\n\t" \
740 : : "Jr" ((unsigned int)(value))); \
743 #define __write_64bit_c0_register(register, sel, value) \
745 if (sizeof(unsigned long) == 4) \
746 __write_64bit_c0_split(register, sel, value); \
748 __asm__ __volatile__( \
750 "dmtc0\t%z0, " #register "\n\t" \
754 __asm__ __volatile__( \
756 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
761 #define __read_ulong_c0_register(reg, sel) \
762 ((sizeof(unsigned long) == 4) ? \
763 (unsigned long) __read_32bit_c0_register(reg, sel) : \
764 (unsigned long) __read_64bit_c0_register(reg, sel))
766 #define __write_ulong_c0_register(reg, sel, val) \
768 if (sizeof(unsigned long) == 4) \
769 __write_32bit_c0_register(reg, sel, val); \
771 __write_64bit_c0_register(reg, sel, val); \
775 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
777 #define __read_32bit_c0_ctrl_register(source) \
779 __asm__ __volatile__( \
780 "cfc0\t%0, " #source "\n\t" \
785 #define __write_32bit_c0_ctrl_register(register, value) \
787 __asm__ __volatile__( \
788 "ctc0\t%z0, " #register "\n\t" \
789 : : "Jr" ((unsigned int)(value))); \
793 * These versions are only needed for systems with more than 38 bits of
794 * physical address space running the 32-bit kernel. That's none atm :-)
796 #define __read_64bit_c0_split(source, sel) \
798 unsigned long long __val; \
799 unsigned long __flags; \
801 local_irq_save(__flags); \
803 __asm__ __volatile__( \
805 "dmfc0\t%M0, " #source "\n\t" \
806 "dsll\t%L0, %M0, 32\n\t" \
807 "dsra\t%M0, %M0, 32\n\t" \
808 "dsra\t%L0, %L0, 32\n\t" \
812 __asm__ __volatile__( \
814 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
815 "dsll\t%L0, %M0, 32\n\t" \
816 "dsra\t%M0, %M0, 32\n\t" \
817 "dsra\t%L0, %L0, 32\n\t" \
820 local_irq_restore(__flags); \
825 #define __write_64bit_c0_split(source, sel, val) \
827 unsigned long __flags; \
829 local_irq_save(__flags); \
831 __asm__ __volatile__( \
833 "dsll\t%L0, %L0, 32\n\t" \
834 "dsrl\t%L0, %L0, 32\n\t" \
835 "dsll\t%M0, %M0, 32\n\t" \
836 "or\t%L0, %L0, %M0\n\t" \
837 "dmtc0\t%L0, " #source "\n\t" \
841 __asm__ __volatile__( \
843 "dsll\t%L0, %L0, 32\n\t" \
844 "dsrl\t%L0, %L0, 32\n\t" \
845 "dsll\t%M0, %M0, 32\n\t" \
846 "or\t%L0, %L0, %M0\n\t" \
847 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
850 local_irq_restore(__flags); \
853 #define read_c0_index() __read_32bit_c0_register($0, 0)
854 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
856 #define read_c0_random() __read_32bit_c0_register($1, 0)
857 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
859 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
860 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
862 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
863 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
865 #define read_c0_conf() __read_32bit_c0_register($3, 0)
866 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
868 #define read_c0_context() __read_ulong_c0_register($4, 0)
869 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
871 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
872 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
874 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
875 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
877 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
878 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
880 #define read_c0_wired() __read_32bit_c0_register($6, 0)
881 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
883 #define read_c0_info() __read_32bit_c0_register($7, 0)
885 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
886 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
888 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
889 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
891 #define read_c0_count() __read_32bit_c0_register($9, 0)
892 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
894 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
895 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
897 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
898 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
900 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
901 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
903 #define read_c0_compare() __read_32bit_c0_register($11, 0)
904 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
906 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
907 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
909 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
910 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
912 #define read_c0_status() __read_32bit_c0_register($12, 0)
913 #ifdef CONFIG_MIPS_MT_SMTC
914 #define write_c0_status(val) \
916 __write_32bit_c0_register($12, 0, val); \
921 * Legacy non-SMTC code, which may be hazardous
922 * but which might not support EHB
924 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
925 #endif /* CONFIG_MIPS_MT_SMTC */
927 #define read_c0_cause() __read_32bit_c0_register($13, 0)
928 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
930 #define read_c0_epc() __read_ulong_c0_register($14, 0)
931 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
933 #define read_c0_prid() __read_32bit_c0_register($15, 0)
935 #define read_c0_config() __read_32bit_c0_register($16, 0)
936 #define read_c0_config1() __read_32bit_c0_register($16, 1)
937 #define read_c0_config2() __read_32bit_c0_register($16, 2)
938 #define read_c0_config3() __read_32bit_c0_register($16, 3)
939 #define read_c0_config4() __read_32bit_c0_register($16, 4)
940 #define read_c0_config5() __read_32bit_c0_register($16, 5)
941 #define read_c0_config6() __read_32bit_c0_register($16, 6)
942 #define read_c0_config7() __read_32bit_c0_register($16, 7)
943 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
944 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
945 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
946 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
947 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
948 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
949 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
950 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
953 * The WatchLo register. There may be up to 8 of them.
955 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
956 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
957 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
958 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
959 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
960 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
961 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
962 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
963 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
964 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
965 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
966 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
967 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
968 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
969 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
970 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
973 * The WatchHi register. There may be up to 8 of them.
975 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
976 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
977 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
978 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
979 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
980 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
981 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
982 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
984 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
985 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
986 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
987 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
988 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
989 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
990 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
991 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
993 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
994 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
996 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
997 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
999 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1000 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1002 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1003 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1005 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1006 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1008 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1009 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1011 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1012 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1014 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1015 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1017 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1018 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1020 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1021 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1023 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1024 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1027 * MIPS32 / MIPS64 performance counters
1029 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1030 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1031 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1032 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1033 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1034 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1035 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1036 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1037 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1038 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1039 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1040 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1041 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1042 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1043 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1044 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1045 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1046 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1047 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1048 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1049 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1050 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1051 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1052 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1054 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1055 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1057 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1058 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1060 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1062 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1063 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1065 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1066 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1068 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1069 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1071 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1072 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1074 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1075 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1077 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1078 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1080 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1081 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1084 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1085 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1087 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1088 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1090 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1091 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1093 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1094 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1096 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1097 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1100 /* Cavium OCTEON (cnMIPS) */
1101 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1102 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1104 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1105 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1107 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1108 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1110 * The cacheerr registers are not standardized. On OCTEON, they are
1113 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1114 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1116 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1117 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1120 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1121 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1123 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1124 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1126 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1127 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1130 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1131 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1133 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1134 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1136 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1137 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1139 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1140 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1142 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1143 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1146 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1147 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1149 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1150 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1152 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1153 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1155 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1156 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1158 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1159 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1161 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1162 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1165 * Macros to access the floating point coprocessor control registers
1167 #define read_32bit_cp1_register(source) \
1171 __asm__ __volatile__( \
1173 " .set reorder \n" \
1174 " # gas fails to assemble cfc1 for some archs, \n" \
1175 " # like Octeon. \n" \
1177 " cfc1 %0,"STR(source)" \n" \
1184 #define rddsp(mask) \
1186 unsigned int __dspctl; \
1188 __asm__ __volatile__( \
1191 " rddsp %0, %x1 \n" \
1198 #define wrdsp(val, mask) \
1200 __asm__ __volatile__( \
1203 " wrdsp %0, %x1 \n" \
1206 : "r" (val), "i" (mask)); \
1215 " mflo %0, $ac0 \n" \
1227 " mflo %0, $ac1 \n" \
1239 " mflo %0, $ac2 \n" \
1251 " mflo %0, $ac3 \n" \
1263 " mfhi %0, $ac0 \n" \
1275 " mfhi %0, $ac1 \n" \
1287 " mfhi %0, $ac2 \n" \
1299 " mfhi %0, $ac3 \n" \
1311 " mtlo %0, $ac0 \n" \
1322 " mtlo %0, $ac1 \n" \
1333 " mtlo %0, $ac2 \n" \
1344 " mtlo %0, $ac3 \n" \
1355 " mthi %0, $ac0 \n" \
1366 " mthi %0, $ac1 \n" \
1377 " mthi %0, $ac2 \n" \
1388 " mthi %0, $ac3 \n" \
1396 #ifdef CONFIG_CPU_MICROMIPS
1397 #define rddsp(mask) \
1399 unsigned int __res; \
1401 __asm__ __volatile__( \
1404 " # rddsp $1, %x1 \n" \
1405 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1406 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1414 #define wrdsp(val, mask) \
1416 __asm__ __volatile__( \
1420 " # wrdsp $1, %x1 \n" \
1421 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1422 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1425 : "r" (val), "i" (mask)); \
1428 #define _umips_dsp_mfxxx(ins) \
1430 unsigned long __treg; \
1432 __asm__ __volatile__( \
1435 " .hword 0x0001 \n" \
1444 #define _umips_dsp_mtxxx(val, ins) \
1446 __asm__ __volatile__( \
1450 " .hword 0x0001 \n" \
1454 : "r" (val), "i" (ins)); \
1457 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1458 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1460 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1461 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1463 #define mflo0() _umips_dsp_mflo(0)
1464 #define mflo1() _umips_dsp_mflo(1)
1465 #define mflo2() _umips_dsp_mflo(2)
1466 #define mflo3() _umips_dsp_mflo(3)
1468 #define mfhi0() _umips_dsp_mfhi(0)
1469 #define mfhi1() _umips_dsp_mfhi(1)
1470 #define mfhi2() _umips_dsp_mfhi(2)
1471 #define mfhi3() _umips_dsp_mfhi(3)
1473 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1474 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1475 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1476 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1478 #define mthi0(x) _umips_dsp_mthi(x, 0)
1479 #define mthi1(x) _umips_dsp_mthi(x, 1)
1480 #define mthi2(x) _umips_dsp_mthi(x, 2)
1481 #define mthi3(x) _umips_dsp_mthi(x, 3)
1483 #else /* !CONFIG_CPU_MICROMIPS */
1484 #define rddsp(mask) \
1486 unsigned int __res; \
1488 __asm__ __volatile__( \
1491 " # rddsp $1, %x1 \n" \
1492 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1500 #define wrdsp(val, mask) \
1502 __asm__ __volatile__( \
1506 " # wrdsp $1, %x1 \n" \
1507 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1510 : "r" (val), "i" (mask)); \
1513 #define _dsp_mfxxx(ins) \
1515 unsigned long __treg; \
1517 __asm__ __volatile__( \
1520 " .word (0x00000810 | %1) \n" \
1528 #define _dsp_mtxxx(val, ins) \
1530 __asm__ __volatile__( \
1534 " .word (0x00200011 | %1) \n" \
1537 : "r" (val), "i" (ins)); \
1540 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1541 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1543 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1544 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1546 #define mflo0() _dsp_mflo(0)
1547 #define mflo1() _dsp_mflo(1)
1548 #define mflo2() _dsp_mflo(2)
1549 #define mflo3() _dsp_mflo(3)
1551 #define mfhi0() _dsp_mfhi(0)
1552 #define mfhi1() _dsp_mfhi(1)
1553 #define mfhi2() _dsp_mfhi(2)
1554 #define mfhi3() _dsp_mfhi(3)
1556 #define mtlo0(x) _dsp_mtlo(x, 0)
1557 #define mtlo1(x) _dsp_mtlo(x, 1)
1558 #define mtlo2(x) _dsp_mtlo(x, 2)
1559 #define mtlo3(x) _dsp_mtlo(x, 3)
1561 #define mthi0(x) _dsp_mthi(x, 0)
1562 #define mthi1(x) _dsp_mthi(x, 1)
1563 #define mthi2(x) _dsp_mthi(x, 2)
1564 #define mthi3(x) _dsp_mthi(x, 3)
1566 #endif /* CONFIG_CPU_MICROMIPS */
1572 * It is responsibility of the caller to take care of any TLB hazards.
1574 static inline void tlb_probe(void)
1576 __asm__ __volatile__(
1577 ".set noreorder\n\t"
1582 static inline void tlb_read(void)
1584 #if MIPS34K_MISSED_ITLB_WAR
1587 __asm__ __volatile__(
1589 " .set noreorder \n"
1592 " .word 0x41610001 # dvpe $1 \n"
1598 instruction_hazard();
1601 __asm__ __volatile__(
1602 ".set noreorder\n\t"
1606 #if MIPS34K_MISSED_ITLB_WAR
1607 if ((res & _ULCAST_(1)))
1608 __asm__ __volatile__(
1610 " .set noreorder \n"
1613 " .word 0x41600021 # evpe \n"
1619 static inline void tlb_write_indexed(void)
1621 __asm__ __volatile__(
1622 ".set noreorder\n\t"
1627 static inline void tlb_write_random(void)
1629 __asm__ __volatile__(
1630 ".set noreorder\n\t"
1636 * Manipulate bits in a c0 register.
1638 #ifndef CONFIG_MIPS_MT_SMTC
1640 * SMTC Linux requires shutting-down microthread scheduling
1641 * during CP0 register read-modify-write sequences.
1643 #define __BUILD_SET_C0(name) \
1644 static inline unsigned int \
1645 set_c0_##name(unsigned int set) \
1647 unsigned int res, new; \
1649 res = read_c0_##name(); \
1651 write_c0_##name(new); \
1656 static inline unsigned int \
1657 clear_c0_##name(unsigned int clear) \
1659 unsigned int res, new; \
1661 res = read_c0_##name(); \
1662 new = res & ~clear; \
1663 write_c0_##name(new); \
1668 static inline unsigned int \
1669 change_c0_##name(unsigned int change, unsigned int val) \
1671 unsigned int res, new; \
1673 res = read_c0_##name(); \
1674 new = res & ~change; \
1675 new |= (val & change); \
1676 write_c0_##name(new); \
1681 #else /* SMTC versions that manage MT scheduling */
1683 #include <linux/irqflags.h>
1686 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1687 * header file recursion.
1689 static inline unsigned int __dmt(void)
1693 __asm__ __volatile__(
1697 " .word 0x41610BC1 # dmt $1 \n"
1703 instruction_hazard();
1708 #define __VPECONTROL_TE_SHIFT 15
1709 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
1711 #define __EMT_ENABLE __VPECONTROL_TE
1713 static inline void __emt(unsigned int previous)
1715 if ((previous & __EMT_ENABLE))
1716 __asm__ __volatile__(
1718 " .word 0x41600be1 # emt \n"
1723 static inline void __ehb(void)
1725 __asm__ __volatile__(
1727 " ehb \n" " .set mips0 \n");
1731 * Note that local_irq_save/restore affect TC-specific IXMT state,
1732 * not Status.IE as in non-SMTC kernel.
1735 #define __BUILD_SET_C0(name) \
1736 static inline unsigned int \
1737 set_c0_##name(unsigned int set) \
1742 unsigned long flags; \
1744 local_irq_save(flags); \
1746 res = read_c0_##name(); \
1748 write_c0_##name(new); \
1750 local_irq_restore(flags); \
1755 static inline unsigned int \
1756 clear_c0_##name(unsigned int clear) \
1761 unsigned long flags; \
1763 local_irq_save(flags); \
1765 res = read_c0_##name(); \
1766 new = res & ~clear; \
1767 write_c0_##name(new); \
1769 local_irq_restore(flags); \
1774 static inline unsigned int \
1775 change_c0_##name(unsigned int change, unsigned int newbits) \
1780 unsigned long flags; \
1782 local_irq_save(flags); \
1785 res = read_c0_##name(); \
1786 new = res & ~change; \
1787 new |= (newbits & change); \
1788 write_c0_##name(new); \
1790 local_irq_restore(flags); \
1796 __BUILD_SET_C0(status)
1797 __BUILD_SET_C0(cause)
1798 __BUILD_SET_C0(config)
1799 __BUILD_SET_C0(intcontrol)
1800 __BUILD_SET_C0(intctl)
1801 __BUILD_SET_C0(srsmap)
1802 __BUILD_SET_C0(brcm_config_0)
1803 __BUILD_SET_C0(brcm_bus_pll)
1804 __BUILD_SET_C0(brcm_reset)
1805 __BUILD_SET_C0(brcm_cmt_intr)
1806 __BUILD_SET_C0(brcm_cmt_ctrl)
1807 __BUILD_SET_C0(brcm_config)
1808 __BUILD_SET_C0(brcm_mode)
1810 #endif /* !__ASSEMBLY__ */
1812 #endif /* _ASM_MIPSREGS_H */