arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <436>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 261         };
 262
 263         pmu_a53 {
 264                 compatible = "arm,cortex-a53-pmu";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 266         };
 267
 268         pmu_a72 {
 269                 compatible = "arm,cortex-a72-pmu";
 270                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 271         };
 272
 273         xin24m: xin24m {
 274                 compatible = "fixed-clock";
 275                 #clock-cells = <0>;
 276                 clock-frequency = <24000000>;
 277                 clock-output-names = "xin24m";
 278         };
 279
 280         amba {
 281                 compatible = "arm,amba-bus";
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges;
 285
 286                 dmac_bus: dma-controller@ff6d0000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 289                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 290                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 291                         #dma-cells = <1>;
 292                         clocks = <&cru ACLK_DMAC0_PERILP>;
 293                         clock-names = "apb_pclk";
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_peri: dma-controller@ff6e0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 301                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC1_PERILP>;
 304                         clock-names = "apb_pclk";
 305                         peripherals-req-type-burst;
 306                 };
 307         };
 308
 309         gmac: eth@fe300000 {
 310                 compatible = "rockchip,rk3399-gmac";
 311                 reg = <0x0 0xfe300000 0x0 0x10000>;
 312                 rockchip,grf = <&grf>;
 313                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 interrupt-names = "macirq";
 315                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 316                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 317                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 318                          <&cru PCLK_GMAC>;
 319                 clock-names = "stmmaceth", "mac_clk_rx",
 320                               "mac_clk_tx", "clk_mac_ref",
 321                               "clk_mac_refout", "aclk_mac",
 322                               "pclk_mac";
 323                 resets = <&cru SRST_A_GMAC>;
 324                 reset-names = "stmmaceth";
 325                 status = "disabled";
 326         };
 327
 328         emmc_phy: phy {
 329                 compatible = "rockchip,rk3399-emmc-phy";
 330                 reg-offset = <0xf780>;
 331                 #phy-cells = <0>;
 332                 rockchip,grf = <&grf>;
 333                 ctrl-base = <0xfe330000>;
 334                 status = "disabled";
 335         };
 336
 337         sdio0: dwmmc@fe310000 {
 338                 compatible = "rockchip,rk3399-dw-mshc",
 339                              "rockchip,rk3288-dw-mshc";
 340                 reg = <0x0 0xfe310000 0x0 0x4000>;
 341                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clock-freq-min-max = <400000 150000000>;
 343                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 344                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 345                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 346                 fifo-depth = <0x100>;
 347                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 348                 status = "disabled";
 349         };
 350
 351         sdmmc: dwmmc@fe320000 {
 352                 compatible = "rockchip,rk3399-dw-mshc",
 353                              "rockchip,rk3288-dw-mshc";
 354                 reg = <0x0 0xfe320000 0x0 0x4000>;
 355                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 356                 clock-freq-min-max = <400000 150000000>;
 357                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 358                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 359                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 360                 fifo-depth = <0x100>;
 361                 power-domains = <&power RK3399_PD_SD>;
 362                 status = "disabled";
 363         };
 364
 365         sdhci: sdhci@fe330000 {
 366                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 367                 reg = <0x0 0xfe330000 0x0 0x10000>;
 368                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 369                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 370                 clock-names = "clk_xin", "clk_ahb";
 371                 assigned-clocks = <&cru SCLK_EMMC>;
 372                 assigned-clock-parents = <&cru PLL_CPLL>;
 373                 assigned-clock-rates = <200000000>;
 374                 phys = <&emmc_phy>;
 375                 phy-names = "phy_arasan";
 376                 power-domains = <&power RK3399_PD_EMMC>;
 377                 status = "disabled";
 378         };
 379
 380         usb_host0_ehci: usb@fe380000 {
 381                 compatible = "generic-ehci";
 382                 reg = <0x0 0xfe380000 0x0 0x20000>;
 383                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 384                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 385                          <&cru SCLK_USBPHY0_480M_SRC>;
 386                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 387                 phys = <&u2phy0_host>;
 388                 phy-names = "usb";
 389                 power-domains = <&power RK3399_PD_PERIHP>;
 390                 status = "disabled";
 391         };
 392
 393         usb_host0_ohci: usb@fe3a0000 {
 394                 compatible = "generic-ohci";
 395                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 396                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 397                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 398                          <&cru SCLK_USBPHY0_480M_SRC>;
 399                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 400                 phys = <&u2phy0_host>;
 401                 phy-names = "usb";
 402                 power-domains = <&power RK3399_PD_PERIHP>;
 403                 status = "disabled";
 404         };
 405
 406         usb_host1_ehci: usb@fe3c0000 {
 407                 compatible = "generic-ehci";
 408                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 409                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 410                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 411                          <&cru SCLK_USBPHY1_480M_SRC>;
 412                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 413                 phys = <&u2phy1_host>;
 414                 phy-names = "usb";
 415                 power-domains = <&power RK3399_PD_PERIHP>;
 416                 status = "disabled";
 417         };
 418
 419         usb_host1_ohci: usb@fe3e0000 {
 420                 compatible = "generic-ohci";
 421                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 422                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 423                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 424                          <&cru SCLK_USBPHY1_480M_SRC>;
 425                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 426                 phys = <&u2phy1_host>;
 427                 phy-names = "usb";
 428                 power-domains = <&power RK3399_PD_PERIHP>;
 429                 status = "disabled";
 430         };
 431
 432         usbdrd3_0: usb@fe800000 {
 433                 compatible = "rockchip,dwc3";
 434                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 435                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 436                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 437                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 438                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 439                               "aclk_usb3", "aclk_usb3_grf";
 440                 power-domains = <&power RK3399_PD_USB3>;
 441                 #address-cells = <2>;
 442                 #size-cells = <2>;
 443                 ranges;
 444                 status = "disabled";
 445                 usbdrd_dwc3_0: dwc3@fe800000 {
 446                         compatible = "snps,dwc3";
 447                         reg = <0x0 0xfe800000 0x0 0x100000>;
 448                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 449                         dr_mode = "otg";
 450                         phys = <&u2phy0_otg>;
 451                         phy-names = "usb2-phy";
 452                         snps,dis_enblslpm_quirk;
 453                         snps,phyif_utmi_16_bits;
 454                         snps,dis_u2_freeclk_exists_quirk;
 455                         snps,dis_del_phy_power_chg_quirk;
 456                         snps,xhci_slow_suspend_quirk;
 457                         status = "disabled";
 458                 };
 459         };
 460
 461         usbdrd3_1: usb@fe900000 {
 462                 compatible = "rockchip,dwc3";
 463                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 464                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 465                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 466                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 467                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 468                               "aclk_usb3", "aclk_usb3_grf";
 469                 power-domains = <&power RK3399_PD_USB3>;
 470                 #address-cells = <2>;
 471                 #size-cells = <2>;
 472                 ranges;
 473                 status = "disabled";
 474                 usbdrd_dwc3_1: dwc3@fe900000 {
 475                         compatible = "snps,dwc3";
 476                         reg = <0x0 0xfe900000 0x0 0x100000>;
 477                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 478                         dr_mode = "otg";
 479                         phys = <&u2phy1_otg>;
 480                         phy-names = "usb2-phy";
 481                         snps,dis_enblslpm_quirk;
 482                         snps,phyif_utmi_16_bits;
 483                         snps,dis_u2_freeclk_exists_quirk;
 484                         snps,dis_del_phy_power_chg_quirk;
 485                         snps,xhci_slow_suspend_quirk;
 486                         status = "disabled";
 487                 };
 488         };
 489
 490         gic: interrupt-controller@fee00000 {
 491                 compatible = "arm,gic-v3";
 492                 #interrupt-cells = <4>;
 493                 #address-cells = <2>;
 494                 #size-cells = <2>;
 495                 ranges;
 496                 interrupt-controller;
 497
 498                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 499                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 500                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 501                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 502                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 503                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 504                 its: interrupt-controller@fee20000 {
 505                         compatible = "arm,gic-v3-its";
 506                         msi-controller;
 507                         reg = <0x0 0xfee20000 0x0 0x20000>;
 508                 };
 509
 510                 ppi-partitions {
 511                         part0: interrupt-partition-0 {
 512                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 513                         };
 514
 515                         part1: interrupt-partition-1 {
 516                                 affinity = <&cpu_b0 &cpu_b1>;
 517                         };
 518                 };
 519         };
 520
 521         saradc: saradc@ff100000 {
 522                 compatible = "rockchip,rk3399-saradc";
 523                 reg = <0x0 0xff100000 0x0 0x100>;
 524                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 525                 #io-channel-cells = <1>;
 526                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 527                 clock-names = "saradc", "apb_pclk";
 528                 status = "disabled";
 529         };
 530
 531         i2c0: i2c@ff3c0000 {
 532                 compatible = "rockchip,rk3399-i2c";
 533                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 534                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 535                 clock-names = "i2c", "pclk";
 536                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c0_xfer>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 status = "disabled";
 542         };
 543
 544         i2c1: i2c@ff110000 {
 545                 compatible = "rockchip,rk3399-i2c";
 546                 reg = <0x0 0xff110000 0x0 0x1000>;
 547                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 548                 clock-names = "i2c", "pclk";
 549                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c1_xfer>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         i2c2: i2c@ff120000 {
 558                 compatible = "rockchip,rk3399-i2c";
 559                 reg = <0x0 0xff120000 0x0 0x1000>;
 560                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 561                 clock-names = "i2c", "pclk";
 562                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&i2c2_xfer>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         i2c3: i2c@ff130000 {
 571                 compatible = "rockchip,rk3399-i2c";
 572                 reg = <0x0 0xff130000 0x0 0x1000>;
 573                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 574                 clock-names = "i2c", "pclk";
 575                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c3_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         i2c5: i2c@ff140000 {
 584                 compatible = "rockchip,rk3399-i2c";
 585                 reg = <0x0 0xff140000 0x0 0x1000>;
 586                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 587                 clock-names = "i2c", "pclk";
 588                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 589                 pinctrl-names = "default";
 590                 pinctrl-0 = <&i2c5_xfer>;
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 status = "disabled";
 594         };
 595
 596         i2c6: i2c@ff150000 {
 597                 compatible = "rockchip,rk3399-i2c";
 598                 reg = <0x0 0xff150000 0x0 0x1000>;
 599                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 600                 clock-names = "i2c", "pclk";
 601                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&i2c6_xfer>;
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 status = "disabled";
 607         };
 608
 609         i2c7: i2c@ff160000 {
 610                 compatible = "rockchip,rk3399-i2c";
 611                 reg = <0x0 0xff160000 0x0 0x1000>;
 612                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 613                 clock-names = "i2c", "pclk";
 614                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&i2c7_xfer>;
 617                 #address-cells = <1>;
 618                 #size-cells = <0>;
 619                 status = "disabled";
 620         };
 621
 622         uart0: serial@ff180000 {
 623                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 624                 reg = <0x0 0xff180000 0x0 0x100>;
 625                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 626                 clock-names = "baudclk", "apb_pclk";
 627                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 628                 reg-shift = <2>;
 629                 reg-io-width = <4>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 632                 status = "disabled";
 633         };
 634
 635         uart1: serial@ff190000 {
 636                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 637                 reg = <0x0 0xff190000 0x0 0x100>;
 638                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 639                 clock-names = "baudclk", "apb_pclk";
 640                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 641                 reg-shift = <2>;
 642                 reg-io-width = <4>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&uart1_xfer>;
 645                 status = "disabled";
 646         };
 647
 648         uart2: serial@ff1a0000 {
 649                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 650                 reg = <0x0 0xff1a0000 0x0 0x100>;
 651                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 652                 clock-names = "baudclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 654                 reg-shift = <2>;
 655                 reg-io-width = <4>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&uart2c_xfer>;
 658                 status = "disabled";
 659         };
 660
 661         uart3: serial@ff1b0000 {
 662                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 663                 reg = <0x0 0xff1b0000 0x0 0x100>;
 664                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 665                 clock-names = "baudclk", "apb_pclk";
 666                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 667                 reg-shift = <2>;
 668                 reg-io-width = <4>;
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 671                 status = "disabled";
 672         };
 673
 674         spi0: spi@ff1c0000 {
 675                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 676                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 677                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 678                 clock-names = "spiclk", "apb_pclk";
 679                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 status = "disabled";
 685         };
 686
 687         spi1: spi@ff1d0000 {
 688                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 689                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 690                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 691                 clock-names = "spiclk", "apb_pclk";
 692                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 status = "disabled";
 698         };
 699
 700         spi2: spi@ff1e0000 {
 701                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 702                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 703                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 704                 clock-names = "spiclk", "apb_pclk";
 705                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710                 status = "disabled";
 711         };
 712
 713         spi4: spi@ff1f0000 {
 714                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 715                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 716                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 717                 clock-names = "spiclk", "apb_pclk";
 718                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 719                 pinctrl-names = "default";
 720                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 721                 #address-cells = <1>;
 722                 #size-cells = <0>;
 723                 status = "disabled";
 724         };
 725
 726         spi5: spi@ff200000 {
 727                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 728                 reg = <0x0 0xff200000 0x0 0x1000>;
 729                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 730                 clock-names = "spiclk", "apb_pclk";
 731                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 732                 pinctrl-names = "default";
 733                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 734                 #address-cells = <1>;
 735                 #size-cells = <0>;
 736                 status = "disabled";
 737         };
 738
 739         thermal-zones {
 740                 soc_thermal: soc-thermal {
 741                         polling-delay-passive = <20>; /* milliseconds */
 742                         polling-delay = <1000>; /* milliseconds */
 743                         sustainable-power = <1000>; /* milliwatts */
 744
 745                         thermal-sensors = <&tsadc 0>;
 746
 747                         trips {
 748                                 threshold: trip-point@0 {
 749                                         temperature = <70000>; /* millicelsius */
 750                                         hysteresis = <2000>; /* millicelsius */
 751                                         type = "passive";
 752                                 };
 753                                 target: trip-point@1 {
 754                                         temperature = <85000>; /* millicelsius */
 755                                         hysteresis = <2000>; /* millicelsius */
 756                                         type = "passive";
 757                                 };
 758                                 soc_crit: soc-crit {
 759                                         temperature = <95000>; /* millicelsius */
 760                                         hysteresis = <2000>; /* millicelsius */
 761                                         type = "critical";
 762                                 };
 763                         };
 764
 765                         cooling-maps {
 766                                 map0 {
 767                                         trip = <&target>;
 768                                         cooling-device =
 769                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 770                                         contribution = <4096>;
 771                                 };
 772                                 map1 {
 773                                         trip = <&target>;
 774                                         cooling-device =
 775                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 776                                         contribution = <1024>;
 777                                 };
 778                                 map2 {
 779                                         trip = <&target>;
 780                                         cooling-device =
 781                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 782                                         contribution = <4096>;
 783                                 };
 784                         };
 785                 };
 786
 787                 gpu_thermal: gpu-thermal {
 788                         polling-delay-passive = <100>; /* milliseconds */
 789                         polling-delay = <1000>; /* milliseconds */
 790
 791                         thermal-sensors = <&tsadc 1>;
 792                 };
 793         };
 794
 795         tsadc: tsadc@ff260000 {
 796                 compatible = "rockchip,rk3399-tsadc";
 797                 reg = <0x0 0xff260000 0x0 0x100>;
 798                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 799                 rockchip,grf = <&grf>;
 800                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 801                 clock-names = "tsadc", "apb_pclk";
 802                 assigned-clocks = <&cru SCLK_TSADC>;
 803                 assigned-clock-rates = <750000>;
 804                 resets = <&cru SRST_TSADC>;
 805                 reset-names = "tsadc-apb";
 806                 pinctrl-names = "init", "default", "sleep";
 807                 pinctrl-0 = <&otp_gpio>;
 808                 pinctrl-1 = <&otp_out>;
 809                 pinctrl-2 = <&otp_gpio>;
 810                 #thermal-sensor-cells = <1>;
 811                 rockchip,hw-tshut-temp = <95000>;
 812                 status = "disabled";
 813         };
 814
 815         qos_emmc: qos@ffa58000 {
 816                 compatible = "syscon";
 817                 reg = <0x0 0xffa58000 0x0 0x20>;
 818         };
 819
 820         qos_gmac: qos@ffa5c000 {
 821                 compatible = "syscon";
 822                 reg = <0x0 0xffa5c000 0x0 0x20>;
 823         };
 824
 825         qos_pcie: qos@ffa60080 {
 826                 compatible = "syscon";
 827                 reg = <0x0 0xffa60080 0x0 0x20>;
 828         };
 829
 830         qos_usb_host0: qos@ffa60100 {
 831                 compatible = "syscon";
 832                 reg = <0x0 0xffa60100 0x0 0x20>;
 833         };
 834
 835         qos_usb_host1: qos@ffa60180 {
 836                 compatible = "syscon";
 837                 reg = <0x0 0xffa60180 0x0 0x20>;
 838         };
 839
 840         qos_usb_otg0: qos@ffa70000 {
 841                 compatible = "syscon";
 842                 reg = <0x0 0xffa70000 0x0 0x20>;
 843         };
 844
 845         qos_usb_otg1: qos@ffa70080 {
 846                 compatible = "syscon";
 847                 reg = <0x0 0xffa70080 0x0 0x20>;
 848         };
 849
 850         qos_sd: qos@ffa74000 {
 851                 compatible = "syscon";
 852                 reg = <0x0 0xffa74000 0x0 0x20>;
 853         };
 854
 855         qos_sdioaudio: qos@ffa76000 {
 856                 compatible = "syscon";
 857                 reg = <0x0 0xffa76000 0x0 0x20>;
 858         };
 859
 860         qos_hdcp: qos@ffa90000 {
 861                 compatible = "syscon";
 862                 reg = <0x0 0xffa90000 0x0 0x20>;
 863         };
 864
 865         qos_iep: qos@ffa98000 {
 866                 compatible = "syscon";
 867                 reg = <0x0 0xffa98000 0x0 0x20>;
 868         };
 869
 870         qos_isp0_m0: qos@ffaa0000 {
 871                 compatible = "syscon";
 872                 reg = <0x0 0xffaa0000 0x0 0x20>;
 873         };
 874
 875         qos_isp0_m1: qos@ffaa0080 {
 876                 compatible = "syscon";
 877                 reg = <0x0 0xffaa0080 0x0 0x20>;
 878         };
 879
 880         qos_isp1_m0: qos@ffaa8000 {
 881                 compatible = "syscon";
 882                 reg = <0x0 0xffaa8000 0x0 0x20>;
 883         };
 884
 885         qos_isp1_m1: qos@ffaa8080 {
 886                 compatible = "syscon";
 887                 reg = <0x0 0xffaa8080 0x0 0x20>;
 888         };
 889
 890         qos_rga_r: qos@ffab0000 {
 891                 compatible = "syscon";
 892                 reg = <0x0 0xffab0000 0x0 0x20>;
 893         };
 894
 895         qos_rga_w: qos@ffab0080 {
 896                 compatible = "syscon";
 897                 reg = <0x0 0xffab0080 0x0 0x20>;
 898         };
 899
 900         qos_video_m0: qos@ffab8000 {
 901                 compatible = "syscon";
 902                 reg = <0x0 0xffab8000 0x0 0x20>;
 903         };
 904
 905         qos_video_m1_r: qos@ffac0000 {
 906                 compatible = "syscon";
 907                 reg = <0x0 0xffac0000 0x0 0x20>;
 908         };
 909
 910         qos_video_m1_w: qos@ffac0080 {
 911                 compatible = "syscon";
 912                 reg = <0x0 0xffac0080 0x0 0x20>;
 913         };
 914
 915         qos_vop_big_r: qos@ffac8000 {
 916                 compatible = "syscon";
 917                 reg = <0x0 0xffac8000 0x0 0x20>;
 918         };
 919
 920         qos_vop_big_w: qos@ffac8080 {
 921                 compatible = "syscon";
 922                 reg = <0x0 0xffac8080 0x0 0x20>;
 923         };
 924
 925         qos_vop_little: qos@ffad0000 {
 926                 compatible = "syscon";
 927                 reg = <0x0 0xffad0000 0x0 0x20>;
 928         };
 929
 930         qos_perihp: qos@ffad8080 {
 931                 compatible = "syscon";
 932                 reg = <0x0 0xffad8080 0x0 0x20>;
 933         };
 934
 935         qos_gpu: qos@ffae0000 {
 936                 compatible = "syscon";
 937                 reg = <0x0 0xffae0000 0x0 0x20>;
 938         };
 939
 940         pmu: power-management@ff310000 {
 941                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 942                 reg = <0x0 0xff310000 0x0 0x1000>;
 943
 944                 /*
 945                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 946                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 947                  * Some of the power domains are grouped together for every
 948                  * voltage domain.
 949                  * The detail contents as below.
 950                  */
 951                 power: power-controller {
 952                         compatible = "rockchip,rk3399-power-controller";
 953                         #power-domain-cells = <1>;
 954                         #address-cells = <1>;
 955                         #size-cells = <0>;
 956
 957                         /* These power domains are grouped by VD_CENTER */
 958                         pd_iep@RK3399_PD_IEP {
 959                                 reg = <RK3399_PD_IEP>;
 960                                 clocks = <&cru ACLK_IEP>,
 961                                          <&cru HCLK_IEP>;
 962                                 pm_qos = <&qos_iep>;
 963                         };
 964                         pd_rga@RK3399_PD_RGA {
 965                                 reg = <RK3399_PD_RGA>;
 966                                 clocks = <&cru ACLK_RGA>,
 967                                          <&cru HCLK_RGA>;
 968                                 pm_qos = <&qos_rga_r>,
 969                                          <&qos_rga_w>;
 970                         };
 971                         pd_vcodec@RK3399_PD_VCODEC {
 972                                 reg = <RK3399_PD_VCODEC>;
 973                                 clocks = <&cru ACLK_VCODEC>,
 974                                          <&cru HCLK_VCODEC>;
 975                                 pm_qos = <&qos_video_m0>;
 976                         };
 977                         pd_vdu@RK3399_PD_VDU {
 978                                 reg = <RK3399_PD_VDU>;
 979                                 clocks = <&cru ACLK_VDU>,
 980                                          <&cru HCLK_VDU>;
 981                                 pm_qos = <&qos_video_m1_r>,
 982                                          <&qos_video_m1_w>;
 983                         };
 984
 985                         /* These power domains are grouped by VD_GPU */
 986                         pd_gpu@RK3399_PD_GPU {
 987                                 reg = <RK3399_PD_GPU>;
 988                                 clocks = <&cru ACLK_GPU>;
 989                                 pm_qos = <&qos_gpu>;
 990                         };
 991
 992                         /* These power domains are grouped by VD_LOGIC */
 993                         pd_emmc@RK3399_PD_EMMC {
 994                                 reg = <RK3399_PD_EMMC>;
 995                                 clocks = <&cru ACLK_EMMC>;
 996                                 pm_qos = <&qos_emmc>;
 997                         };
 998                         pd_gmac@RK3399_PD_GMAC {
 999                                 reg = <RK3399_PD_GMAC>;
1000                                 clocks = <&cru ACLK_GMAC>;
1001                                 pm_qos = <&qos_gmac>;
1002                         };
1003                         pd_perihp@RK3399_PD_PERIHP {
1004                                 reg = <RK3399_PD_PERIHP>;
1005                                 clocks = <&cru ACLK_PERIHP>;
1006                                 pm_qos = <&qos_perihp>,
1007                                          <&qos_pcie>,
1008                                          <&qos_usb_host0>,
1009                                          <&qos_usb_host1>;
1010                         };
1011                         pd_sd@RK3399_PD_SD {
1012                                 reg = <RK3399_PD_SD>;
1013                                 clocks = <&cru HCLK_SDMMC>;
1014                                 pm_qos = <&qos_sd>;
1015                         };
1016                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1017                                 reg = <RK3399_PD_SDIOAUDIO>;
1018                                 clocks = <&cru HCLK_SDIO>;
1019                                 pm_qos = <&qos_sdioaudio>;
1020                         };
1021                         pd_usb3@RK3399_PD_USB3 {
1022                                 reg = <RK3399_PD_USB3>;
1023                                 clocks = <&cru ACLK_USB3>;
1024                                 pm_qos = <&qos_usb_otg0>,
1025                                          <&qos_usb_otg1>;
1026                         };
1027                         pd_vio@RK3399_PD_VIO {
1028                                 reg = <RK3399_PD_VIO>;
1029                                 #address-cells = <1>;
1030                                 #size-cells = <0>;
1031
1032                                 pd_hdcp@RK3399_PD_HDCP {
1033                                         reg = <RK3399_PD_HDCP>;
1034                                         clocks = <&cru ACLK_HDCP>,
1035                                                  <&cru HCLK_HDCP>,
1036                                                  <&cru PCLK_HDCP>;
1037                                         pm_qos = <&qos_hdcp>;
1038                                 };
1039                                 pd_isp0@RK3399_PD_ISP0 {
1040                                         reg = <RK3399_PD_ISP0>;
1041                                         clocks = <&cru ACLK_ISP0>,
1042                                                  <&cru HCLK_ISP0>;
1043                                         pm_qos = <&qos_isp0_m0>,
1044                                                  <&qos_isp0_m1>;
1045                                 };
1046                                 pd_isp1@RK3399_PD_ISP1 {
1047                                         reg = <RK3399_PD_ISP1>;
1048                                         clocks = <&cru ACLK_ISP1>,
1049                                                  <&cru HCLK_ISP1>;
1050                                         pm_qos = <&qos_isp1_m0>,
1051                                                  <&qos_isp1_m1>;
1052                                 };
1053                                 pd_vo@RK3399_PD_VO {
1054                                         reg = <RK3399_PD_VO>;
1055                                         #address-cells = <1>;
1056                                         #size-cells = <0>;
1057
1058                                         pd_vopb@RK3399_PD_VOPB {
1059                                                 reg = <RK3399_PD_VOPB>;
1060                                                 clocks = <&cru ACLK_VOP0>,
1061                                                          <&cru HCLK_VOP0>;
1062                                                 pm_qos = <&qos_vop_big_r>,
1063                                                          <&qos_vop_big_w>;
1064                                         };
1065                                         pd_vopl@RK3399_PD_VOPL {
1066                                                 reg = <RK3399_PD_VOPL>;
1067                                                 clocks = <&cru ACLK_VOP1>,
1068                                                          <&cru HCLK_VOP1>;
1069                                                 pm_qos = <&qos_vop_little>;
1070                                         };
1071                                 };
1072                         };
1073                 };
1074         };
1075
1076         pmugrf: syscon@ff320000 {
1077                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1078                 reg = <0x0 0xff320000 0x0 0x1000>;
1079
1080                 reboot-mode {
1081                         compatible = "syscon-reboot-mode";
1082                         offset = <0x300>;
1083                         mode-bootloader = <BOOT_LOADER>;
1084                         mode-charge = <BOOT_CHARGING>;
1085                         mode-fastboot = <BOOT_FASTBOOT>;
1086                         mode-loader = <BOOT_LOADER>;
1087                         mode-normal = <BOOT_NORMAL>;
1088                         mode-recovery = <BOOT_RECOVERY>;
1089                 };
1090         };
1091
1092         spi3: spi@ff350000 {
1093                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1094                 reg = <0x0 0xff350000 0x0 0x1000>;
1095                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1096                 clock-names = "spiclk", "apb_pclk";
1097                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1098                 pinctrl-names = "default";
1099                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1100                 #address-cells = <1>;
1101                 #size-cells = <0>;
1102                 status = "disabled";
1103         };
1104
1105         uart4: serial@ff370000 {
1106                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1107                 reg = <0x0 0xff370000 0x0 0x100>;
1108                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1109                 clock-names = "baudclk", "apb_pclk";
1110                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1111                 reg-shift = <2>;
1112                 reg-io-width = <4>;
1113                 pinctrl-names = "default";
1114                 pinctrl-0 = <&uart4_xfer>;
1115                 status = "disabled";
1116         };
1117
1118         i2c4: i2c@ff3d0000 {
1119                 compatible = "rockchip,rk3399-i2c";
1120                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1121                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1122                 clock-names = "i2c", "pclk";
1123                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1124                 pinctrl-names = "default";
1125                 pinctrl-0 = <&i2c4_xfer>;
1126                 #address-cells = <1>;
1127                 #size-cells = <0>;
1128                 status = "disabled";
1129         };
1130
1131         i2c8: i2c@ff3e0000 {
1132                 compatible = "rockchip,rk3399-i2c";
1133                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1134                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1135                 clock-names = "i2c", "pclk";
1136                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1137                 pinctrl-names = "default";
1138                 pinctrl-0 = <&i2c8_xfer>;
1139                 #address-cells = <1>;
1140                 #size-cells = <0>;
1141                 status = "disabled";
1142         };
1143
1144         pcie0: pcie@f8000000 {
1145                 compatible = "rockchip,rk3399-pcie";
1146                 #address-cells = <3>;
1147                 #size-cells = <2>;
1148                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1149                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1150                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1151                               "hclk_pcie", "clk_pciephy_ref";
1152                 bus-range = <0x0 0x1>;
1153                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1154                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1155                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1156                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1157                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1158                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1159                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1160                       < 0x0 0xfd000000 0x0 0x1000000 >;
1161                 reg-name = "axi-base", "apb-base";
1162                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1163                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1164                          <&cru SRST_PCIE_PIPE>;
1165                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1166                               "mgmt-sticky-rst", "pipe-rst";
1167                 rockchip,grf = <&grf>;
1168                 pcie-conf = <0xe220>;
1169                 pcie-status = <0xe2a4>;
1170                 pcie-laneoff = <0xe214>;
1171                 power-domains = <&power RK3399_PD_PERIHP>;
1172                 msi-parent = <&its>;
1173                 #interrupt-cells = <1>;
1174                 interrupt-map-mask = <0 0 0 7>;
1175                 interrupt-map = <0 0 0 1 &pcie0 1>,
1176                                 <0 0 0 2 &pcie0 2>,
1177                                 <0 0 0 3 &pcie0 3>,
1178                                 <0 0 0 4 &pcie0 4>;
1179                 status = "disabled";
1180                 pcie_intc: interrupt-controller {
1181                         interrupt-controller;
1182                         #address-cells = <0>;
1183                         #interrupt-cells = <1>;
1184                 };
1185         };
1186
1187         pwm0: pwm@ff420000 {
1188                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1189                 reg = <0x0 0xff420000 0x0 0x10>;
1190                 #pwm-cells = <3>;
1191                 pinctrl-names = "default";
1192                 pinctrl-0 = <&pwm0_pin>;
1193                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1194                 clock-names = "pwm";
1195                 status = "disabled";
1196         };
1197
1198         pwm1: pwm@ff420010 {
1199                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1200                 reg = <0x0 0xff420010 0x0 0x10>;
1201                 #pwm-cells = <3>;
1202                 pinctrl-names = "default";
1203                 pinctrl-0 = <&pwm1_pin>;
1204                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1205                 clock-names = "pwm";
1206                 status = "disabled";
1207         };
1208
1209         pwm2: pwm@ff420020 {
1210                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1211                 reg = <0x0 0xff420020 0x0 0x10>;
1212                 #pwm-cells = <3>;
1213                 pinctrl-names = "default";
1214                 pinctrl-0 = <&pwm2_pin>;
1215                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1216                 clock-names = "pwm";
1217                 status = "disabled";
1218         };
1219
1220         pwm3: pwm@ff420030 {
1221                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1222                 reg = <0x0 0xff420030 0x0 0x10>;
1223                 #pwm-cells = <3>;
1224                 pinctrl-names = "default";
1225                 pinctrl-0 = <&pwm3a_pin>;
1226                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1227                 clock-names = "pwm";
1228                 status = "disabled";
1229         };
1230
1231         rga: rga@ff680000 {
1232                 compatible = "rockchip,rk3399-rga";
1233                 reg = <0x0 0xff680000 0x0 0x10000>;
1234                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1235                 interrupt-names = "rga";
1236                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1237                 clock-names = "aclk", "hclk", "sclk";
1238                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1239                 reset-names = "core", "axi", "ahb";
1240                 power-domains = <&power RK3399_PD_RGA>;
1241                 status = "disabled";
1242         };
1243
1244         pmucru: pmu-clock-controller@ff750000 {
1245                 compatible = "rockchip,rk3399-pmucru";
1246                 reg = <0x0 0xff750000 0x0 0x1000>;
1247                 #clock-cells = <1>;
1248                 #reset-cells = <1>;
1249                 assigned-clocks = <&pmucru PLL_PPLL>;
1250                 assigned-clock-rates = <676000000>;
1251         };
1252
1253         cru: clock-controller@ff760000 {
1254                 compatible = "rockchip,rk3399-cru";
1255                 reg = <0x0 0xff760000 0x0 0x1000>;
1256                 #clock-cells = <1>;
1257                 #reset-cells = <1>;
1258                 assigned-clocks =
1259                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1260                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1261                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1262                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1263                         <&cru PLL_NPLL>,
1264                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1265                         <&cru PCLK_PERIHP>,
1266                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1267                         <&cru PCLK_PERILP0>,
1268                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1269                 assigned-clock-rates =
1270                          <400000000>,  <200000000>,
1271                          <400000000>,  <200000000>,
1272                          <816000000>, <816000000>,
1273                          <594000000>,  <800000000>,
1274                         <1000000000>,
1275                          <150000000>,   <75000000>,
1276                           <37500000>,
1277                          <100000000>,  <100000000>,
1278                           <50000000>,
1279                          <100000000>,   <50000000>;
1280         };
1281
1282         grf: syscon@ff770000 {
1283                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1284                 reg = <0x0 0xff770000 0x0 0x10000>;
1285                 #address-cells = <1>;
1286                 #size-cells = <1>;
1287
1288                 u2phy0: usb2-phy@e450 {
1289                         compatible = "rockchip,rk3399-usb2phy";
1290                         reg = <0xe450 0x10>;
1291                         clocks = <&cru SCLK_USB2PHY0_REF>;
1292                         clock-names = "phyclk";
1293                         #clock-cells = <0>;
1294                         clock-output-names = "clk_usbphy0_480m";
1295                         status = "disabled";
1296
1297                         u2phy0_otg: otg-port {
1298                                 #phy-cells = <0>;
1299                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1300                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1301                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1302                                 interrupt-names = "otg-bvalid", "otg-id",
1303                                                   "linestate";
1304                                 status = "disabled";
1305                         };
1306
1307                         u2phy0_host: host-port {
1308                                 #phy-cells = <0>;
1309                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1310                                 interrupt-names = "linestate";
1311                                 status = "disabled";
1312                         };
1313                 };
1314
1315                 u2phy1: usb2-phy@e460 {
1316                         compatible = "rockchip,rk3399-usb2phy";
1317                         reg = <0xe460 0x10>;
1318                         clocks = <&cru SCLK_USB2PHY1_REF>;
1319                         clock-names = "phyclk";
1320                         #clock-cells = <0>;
1321                         clock-output-names = "clk_usbphy1_480m";
1322                         status = "disabled";
1323
1324                         u2phy1_otg: otg-port {
1325                                 #phy-cells = <0>;
1326                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1327                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1328                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1329                                 interrupt-names = "otg-bvalid", "otg-id",
1330                                                   "linestate";
1331                                 status = "disabled";
1332                         };
1333
1334                         u2phy1_host: host-port {
1335                                 #phy-cells = <0>;
1336                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1337                                 interrupt-names = "linestate";
1338                                 status = "disabled";
1339                         };
1340                 };
1341         };
1342
1343         tcphy0: phy@ff7c0000 {
1344                 compatible = "rockchip,rk3399-typec-phy";
1345                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1346                 rockchip,grf = <&grf>;
1347                 #phy-cells = <0>;
1348                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1349                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1350                 clock-names = "tcpdcore", "tcpdphy-ref";
1351                 resets = <&cru SRST_UPHY0>,
1352                          <&cru SRST_UPHY0_PIPE_L00>,
1353                          <&cru SRST_P_UPHY0_TCPHY>;
1354                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1355                 rockchip,typec-conn-dir = <0xe580 0 16>;
1356                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1357                 rockchip,external-psm = <0xe588 14 30>;
1358                 rockchip,pipe-status = <0xe5c0 0 0>;
1359                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1360                 status = "disabled";
1361         };
1362
1363         tcphy1: phy@ff800000 {
1364                 compatible = "rockchip,rk3399-typec-phy";
1365                 reg = <0x0 0xff800000 0x0 0x40000>;
1366                 rockchip,grf = <&grf>;
1367                 #phy-cells = <0>;
1368                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1369                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1370                 clock-names = "tcpdcore", "tcpdphy-ref";
1371                 resets = <&cru SRST_UPHY1>,
1372                          <&cru SRST_UPHY1_PIPE_L00>,
1373                          <&cru SRST_P_UPHY1_TCPHY>;
1374                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1375                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1376                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1377                 rockchip,external-psm = <0xe594 14 30>;
1378                 rockchip,pipe-status = <0xe5c0 16 16>;
1379                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1380                 status = "disabled";
1381         };
1382
1383         watchdog@ff840000 {
1384                 compatible = "snps,dw-wdt";
1385                 reg = <0x0 0xff840000 0x0 0x100>;
1386                 clocks = <&cru PCLK_WDT>;
1387                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1388         };
1389
1390         rktimer: rktimer@ff850000 {
1391                 compatible = "rockchip,rk3399-timer";
1392                 reg = <0x0 0xff850000 0x0 0x1000>;
1393                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1394                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1395                 clock-names = "pclk", "timer";
1396         };
1397
1398         spdif: spdif@ff870000 {
1399                 compatible = "rockchip,rk3399-spdif";
1400                 reg = <0x0 0xff870000 0x0 0x1000>;
1401                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1402                 dmas = <&dmac_bus 7>;
1403                 dma-names = "tx";
1404                 clock-names = "mclk", "hclk";
1405                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1406                 pinctrl-names = "default";
1407                 pinctrl-0 = <&spdif_bus>;
1408                 status = "disabled";
1409         };
1410
1411         i2s0: i2s@ff880000 {
1412                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1413                 reg = <0x0 0xff880000 0x0 0x1000>;
1414                 rockchip,grf = <&grf>;
1415                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1416                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1417                 dma-names = "tx", "rx";
1418                 clock-names = "i2s_clk", "i2s_hclk";
1419                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1420                 pinctrl-names = "default";
1421                 pinctrl-0 = <&i2s0_8ch_bus>;
1422                 status = "disabled";
1423         };
1424
1425         i2s1: i2s@ff890000 {
1426                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1427                 reg = <0x0 0xff890000 0x0 0x1000>;
1428                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1429                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1430                 dma-names = "tx", "rx";
1431                 clock-names = "i2s_clk", "i2s_hclk";
1432                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1433                 pinctrl-names = "default";
1434                 pinctrl-0 = <&i2s1_2ch_bus>;
1435                 status = "disabled";
1436         };
1437
1438         i2s2: i2s@ff8a0000 {
1439                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1440                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1441                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1442                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1443                 dma-names = "tx", "rx";
1444                 clock-names = "i2s_clk", "i2s_hclk";
1445                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1446                 status = "disabled";
1447         };
1448
1449         gpu: gpu@ff9a0000 {
1450                 compatible = "arm,malit860",
1451                              "arm,malit86x",
1452                              "arm,malit8xx",
1453                              "arm,mali-midgard";
1454
1455                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1456
1457                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1458                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1459                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1460                 interrupt-names = "GPU", "JOB", "MMU";
1461
1462                 clocks = <&cru ACLK_GPU>;
1463                 clock-names = "clk_mali";
1464                 #cooling-cells = <2>; /* min followed by max */
1465                 operating-points-v2 = <&gpu_opp_table>;
1466                 power-domains = <&power RK3399_PD_GPU>;
1467                 power-off-delay-ms = <200>;
1468                 status = "disabled";
1469
1470                 gpu_power_model: power_model {
1471                         compatible = "arm,mali-simple-power-model";
1472                         voltage = <900>;
1473                         frequency = <500>;
1474                         static-power = <300>;
1475                         dynamic-power = <396>;
1476                         ts = <32000 4700 (-80) 2>;
1477                         thermal-zone = "gpu-thermal";
1478                 };
1479         };
1480
1481         gpu_opp_table: gpu_opp_table {
1482                 compatible = "operating-points-v2";
1483                 opp-shared;
1484
1485                 opp@200000000 {
1486                         opp-hz = /bits/ 64 <200000000>;
1487                         opp-microvolt = <900000>;
1488                 };
1489                 opp@300000000 {
1490                         opp-hz = /bits/ 64 <300000000>;
1491                         opp-microvolt = <900000>;
1492                 };
1493                 opp@400000000 {
1494                         opp-hz = /bits/ 64 <400000000>;
1495                         opp-microvolt = <900000>;
1496                 };
1497
1498         };
1499
1500         vopl: vop@ff8f0000 {
1501                 compatible = "rockchip,rk3399-vop-lit";
1502                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1503                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1504                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1505                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1506                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1507                 reset-names = "axi", "ahb", "dclk";
1508                 power-domains = <&power RK3399_PD_VOPL>;
1509                 iommus = <&vopl_mmu>;
1510                 status = "disabled";
1511
1512                 vopl_out: port {
1513                         #address-cells = <1>;
1514                         #size-cells = <0>;
1515
1516                         vopl_out_mipi: endpoint@0 {
1517                                 reg = <0>;
1518                                 remote-endpoint = <&mipi_in_vopl>;
1519                         };
1520
1521                         vopl_out_edp: endpoint@1 {
1522                                 reg = <1>;
1523                                 remote-endpoint = <&edp_in_vopl>;
1524                         };
1525
1526                         vopl_out_hdmi: endpoint@2 {
1527                                 reg = <2>;
1528                                 remote-endpoint = <&hdmi_in_vopl>;
1529                         };
1530                 };
1531         };
1532
1533         vopl_mmu: iommu@ff8f3f00 {
1534                 compatible = "rockchip,iommu";
1535                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1536                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1537                 interrupt-names = "vopl_mmu";
1538                 #iommu-cells = <0>;
1539                 status = "disabled";
1540         };
1541
1542         vopb: vop@ff900000 {
1543                 compatible = "rockchip,rk3399-vop-big";
1544                 reg = <0x0 0xff900000 0x0 0x3efc>;
1545                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1546                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1547                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1548                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1549                 reset-names = "axi", "ahb", "dclk";
1550                 power-domains = <&power RK3399_PD_VOPB>;
1551                 iommus = <&vopb_mmu>;
1552                 status = "disabled";
1553
1554                 vopb_out: port {
1555                         #address-cells = <1>;
1556                         #size-cells = <0>;
1557
1558                         vopb_out_edp: endpoint@0 {
1559                                 reg = <0>;
1560                                 remote-endpoint = <&edp_in_vopb>;
1561                         };
1562
1563                         vopb_out_mipi: endpoint@1 {
1564                                 reg = <1>;
1565                                 remote-endpoint = <&mipi_in_vopb>;
1566                         };
1567
1568                         vopb_out_hdmi: endpoint@2 {
1569                                 reg = <2>;
1570                                 remote-endpoint = <&hdmi_in_vopb>;
1571                         };
1572                 };
1573         };
1574
1575         vopb_mmu: iommu@ff903f00 {
1576                 compatible = "rockchip,iommu";
1577                 reg = <0x0 0xff903f00 0x0 0x100>;
1578                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1579                 interrupt-names = "vopb_mmu";
1580                 #iommu-cells = <0>;
1581                 status = "disabled";
1582         };
1583
1584         hdmi: hdmi@ff940000 {
1585                 compatible = "rockchip,rk3399-dw-hdmi";
1586                 reg = <0x0 0xff940000 0x0 0x20000>;
1587                 reg-io-width = <4>;
1588                 rockchip,grf = <&grf>;
1589                 power-domains = <&power RK3399_PD_HDCP>;
1590                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1591                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1592                 clock-names = "iahb", "isfr", "vpll", "grf";
1593                 status = "disabled";
1594
1595                 ports {
1596                         hdmi_in: port {
1597                                 #address-cells = <1>;
1598                                 #size-cells = <0>;
1599                                 hdmi_in_vopb: endpoint@0 {
1600                                         reg = <0>;
1601                                         remote-endpoint = <&vopb_out_hdmi>;
1602                                 };
1603                                 hdmi_in_vopl: endpoint@1 {
1604                                         reg = <1>;
1605                                         remote-endpoint = <&vopl_out_hdmi>;
1606                                 };
1607                         };
1608                 };
1609         };
1610
1611         mipi_dsi: mipi@ff960000 {
1612                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1613                 reg = <0x0 0xff960000 0x0 0x8000>;
1614                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1615                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1616                          <&cru SCLK_DPHY_TX0_CFG>;
1617                 clock-names = "ref", "pclk", "phy_cfg";
1618                 power-domains = <&power RK3399_PD_VIO>;
1619                 rockchip,grf = <&grf>;
1620                 #address-cells = <1>;
1621                 #size-cells = <0>;
1622                 status = "disabled";
1623
1624                 ports {
1625                         #address-cells = <1>;
1626                         #size-cells = <0>;
1627                         reg = <1>;
1628
1629                         mipi_in: port {
1630                                 #address-cells = <1>;
1631                                 #size-cells = <0>;
1632
1633                                 mipi_in_vopb: endpoint@0 {
1634                                         reg = <0>;
1635                                         remote-endpoint = <&vopb_out_mipi>;
1636                                 };
1637                                 mipi_in_vopl: endpoint@1 {
1638                                         reg = <1>;
1639                                         remote-endpoint = <&vopl_out_mipi>;
1640                                 };
1641                         };
1642                 };
1643         };
1644
1645         edp: edp@ff970000 {
1646                 compatible = "rockchip,rk3399-edp";
1647                 reg = <0x0 0xff970000 0x0 0x8000>;
1648                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1649                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1650                 clock-names = "dp", "pclk";
1651                 resets = <&cru SRST_P_EDP_CTRL>;
1652                 reset-names = "dp";
1653                 rockchip,grf = <&grf>;
1654                 status = "disabled";
1655                 pinctrl-names = "default";
1656                 pinctrl-0 = <&edp_hpd>;
1657
1658                 ports {
1659                         #address-cells = <1>;
1660                         #size-cells = <0>;
1661
1662                         edp_in: port@0 {
1663                                 reg = <0>;
1664                                 #address-cells = <1>;
1665                                 #size-cells = <0>;
1666
1667                                 edp_in_vopb: endpoint@0 {
1668                                         reg = <0>;
1669                                         remote-endpoint = <&vopb_out_edp>;
1670                                 };
1671
1672                                 edp_in_vopl: endpoint@1 {
1673                                         reg = <1>;
1674                                         remote-endpoint = <&vopl_out_edp>;
1675                                 };
1676                         };
1677                 };
1678         };
1679
1680         display_subsystem: display-subsystem {
1681                 compatible = "rockchip,display-subsystem";
1682                 ports = <&vopl_out>, <&vopb_out>;
1683                 status = "disabled";
1684         };
1685
1686         pinctrl: pinctrl {
1687                 compatible = "rockchip,rk3399-pinctrl";
1688                 rockchip,grf = <&grf>;
1689                 rockchip,pmu = <&pmugrf>;
1690                 #address-cells = <0x2>;
1691                 #size-cells = <0x2>;
1692                 ranges;
1693
1694                 gpio0: gpio0@ff720000 {
1695                         compatible = "rockchip,gpio-bank";
1696                         reg = <0x0 0xff720000 0x0 0x100>;
1697                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1698                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1699
1700                         gpio-controller;
1701                         #gpio-cells = <0x2>;
1702
1703                         interrupt-controller;
1704                         #interrupt-cells = <0x2>;
1705                 };
1706
1707                 gpio1: gpio1@ff730000 {
1708                         compatible = "rockchip,gpio-bank";
1709                         reg = <0x0 0xff730000 0x0 0x100>;
1710                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1711                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1712
1713                         gpio-controller;
1714                         #gpio-cells = <0x2>;
1715
1716                         interrupt-controller;
1717                         #interrupt-cells = <0x2>;
1718                 };
1719
1720                 gpio2: gpio2@ff780000 {
1721                         compatible = "rockchip,gpio-bank";
1722                         reg = <0x0 0xff780000 0x0 0x100>;
1723                         clocks = <&cru PCLK_GPIO2>;
1724                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1725
1726                         gpio-controller;
1727                         #gpio-cells = <0x2>;
1728
1729                         interrupt-controller;
1730                         #interrupt-cells = <0x2>;
1731                 };
1732
1733                 gpio3: gpio3@ff788000 {
1734                         compatible = "rockchip,gpio-bank";
1735                         reg = <0x0 0xff788000 0x0 0x100>;
1736                         clocks = <&cru PCLK_GPIO3>;
1737                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1738
1739                         gpio-controller;
1740                         #gpio-cells = <0x2>;
1741
1742                         interrupt-controller;
1743                         #interrupt-cells = <0x2>;
1744                 };
1745
1746                 gpio4: gpio4@ff790000 {
1747                         compatible = "rockchip,gpio-bank";
1748                         reg = <0x0 0xff790000 0x0 0x100>;
1749                         clocks = <&cru PCLK_GPIO4>;
1750                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1751
1752                         gpio-controller;
1753                         #gpio-cells = <0x2>;
1754
1755                         interrupt-controller;
1756                         #interrupt-cells = <0x2>;
1757                 };
1758
1759                 pcfg_pull_up: pcfg-pull-up {
1760                         bias-pull-up;
1761                 };
1762
1763                 pcfg_pull_down: pcfg-pull-down {
1764                         bias-pull-down;
1765                 };
1766
1767                 pcfg_pull_none: pcfg-pull-none {
1768                         bias-disable;
1769                 };
1770
1771                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1772                         bias-pull-up;
1773                         drive-strength = <20>;
1774                 };
1775
1776                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1777                         bias-disable;
1778                         drive-strength = <20>;
1779                 };
1780
1781                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1782                         bias-disable;
1783                         drive-strength = <18>;
1784                 };
1785
1786                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1787                         bias-disable;
1788                         drive-strength = <12>;
1789                 };
1790
1791                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1792                         bias-pull-up;
1793                         drive-strength = <8>;
1794                 };
1795
1796                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1797                         bias-pull-down;
1798                         drive-strength = <4>;
1799                 };
1800
1801                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1802                         bias-pull-up;
1803                         drive-strength = <2>;
1804                 };
1805
1806                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1807                         bias-pull-down;
1808                         drive-strength = <12>;
1809                 };
1810
1811                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1812                         bias-disable;
1813                         drive-strength = <13>;
1814                 };
1815
1816                 emmc {
1817                         emmc_pwr: emmc-pwr {
1818                                 rockchip,pins =
1819                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1820                         };
1821                 };
1822
1823                 gmac {
1824                         rgmii_pins: rgmii-pins {
1825                                 rockchip,pins =
1826                                         /* mac_txclk */
1827                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1828                                         /* mac_rxclk */
1829                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1830                                         /* mac_mdio */
1831                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1832                                         /* mac_txen */
1833                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1834                                         /* mac_clk */
1835                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1836                                         /* mac_rxdv */
1837                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1838                                         /* mac_mdc */
1839                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1840                                         /* mac_rxd1 */
1841                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1842                                         /* mac_rxd0 */
1843                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1844                                         /* mac_txd1 */
1845                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1846                                         /* mac_txd0 */
1847                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1848                                         /* mac_rxd3 */
1849                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1850                                         /* mac_rxd2 */
1851                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1852                                         /* mac_txd3 */
1853                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1854                                         /* mac_txd2 */
1855                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1856                         };
1857
1858                         rmii_pins: rmii-pins {
1859                                 rockchip,pins =
1860                                         /* mac_mdio */
1861                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1862                                         /* mac_txen */
1863                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1864                                         /* mac_clk */
1865                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1866                                         /* mac_rxer */
1867                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1868                                         /* mac_rxdv */
1869                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1870                                         /* mac_mdc */
1871                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1872                                         /* mac_rxd1 */
1873                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1874                                         /* mac_rxd0 */
1875                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1876                                         /* mac_txd1 */
1877                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1878                                         /* mac_txd0 */
1879                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1880                         };
1881                 };
1882
1883                 i2c0 {
1884                         i2c0_xfer: i2c0-xfer {
1885                                 rockchip,pins =
1886                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1887                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1888                         };
1889                 };
1890
1891                 i2c1 {
1892                         i2c1_xfer: i2c1-xfer {
1893                                 rockchip,pins =
1894                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1895                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1896                         };
1897                 };
1898
1899                 i2c2 {
1900                         i2c2_xfer: i2c2-xfer {
1901                                 rockchip,pins =
1902                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1903                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1904                         };
1905                 };
1906
1907                 i2c3 {
1908                         i2c3_xfer: i2c3-xfer {
1909                                 rockchip,pins =
1910                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1911                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1912                         };
1913
1914                         i2c3_gpio: i2c3_gpio {
1915                                 rockchip,pins =
1916                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1917                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1918                         };
1919
1920                 };
1921
1922                 i2c4 {
1923                         i2c4_xfer: i2c4-xfer {
1924                                 rockchip,pins =
1925                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1926                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1927                         };
1928                 };
1929
1930                 i2c5 {
1931                         i2c5_xfer: i2c5-xfer {
1932                                 rockchip,pins =
1933                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1934                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1935                         };
1936                 };
1937
1938                 i2c6 {
1939                         i2c6_xfer: i2c6-xfer {
1940                                 rockchip,pins =
1941                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1942                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1943                         };
1944                 };
1945
1946                 i2c7 {
1947                         i2c7_xfer: i2c7-xfer {
1948                                 rockchip,pins =
1949                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1950                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1951                         };
1952                 };
1953
1954                 i2c8 {
1955                         i2c8_xfer: i2c8-xfer {
1956                                 rockchip,pins =
1957                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1958                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1959                         };
1960                 };
1961
1962                 i2s0 {
1963                         i2s0_8ch_bus: i2s0-8ch-bus {
1964                                 rockchip,pins =
1965                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1966                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1967                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1968                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1969                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1970                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1971                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1972                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1973                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1974                         };
1975                 };
1976
1977                 i2s1 {
1978                         i2s1_2ch_bus: i2s1-2ch-bus {
1979                                 rockchip,pins =
1980                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1981                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1982                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1983                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1984                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1985                         };
1986                 };
1987
1988                 sdio0 {
1989                         sdio0_bus1: sdio0-bus1 {
1990                                 rockchip,pins =
1991                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1992                         };
1993
1994                         sdio0_bus4: sdio0-bus4 {
1995                                 rockchip,pins =
1996                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1997                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1998                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1999                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2000                         };
2001
2002                         sdio0_cmd: sdio0-cmd {
2003                                 rockchip,pins =
2004                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2005                         };
2006
2007                         sdio0_clk: sdio0-clk {
2008                                 rockchip,pins =
2009                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2010                         };
2011
2012                         sdio0_cd: sdio0-cd {
2013                                 rockchip,pins =
2014                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2015                         };
2016
2017                         sdio0_pwr: sdio0-pwr {
2018                                 rockchip,pins =
2019                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2020                         };
2021
2022                         sdio0_bkpwr: sdio0-bkpwr {
2023                                 rockchip,pins =
2024                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2025                         };
2026
2027                         sdio0_wp: sdio0-wp {
2028                                 rockchip,pins =
2029                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2030                         };
2031
2032                         sdio0_int: sdio0-int {
2033                                 rockchip,pins =
2034                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2035                         };
2036                 };
2037
2038                 sdmmc {
2039                         sdmmc_bus1: sdmmc-bus1 {
2040                                 rockchip,pins =
2041                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2042                         };
2043
2044                         sdmmc_bus4: sdmmc-bus4 {
2045                                 rockchip,pins =
2046                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2047                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2048                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2049                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2050                         };
2051
2052                         sdmmc_clk: sdmmc-clk {
2053                                 rockchip,pins =
2054                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2055                         };
2056
2057                         sdmmc_cmd: sdmmc-cmd {
2058                                 rockchip,pins =
2059                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2060                         };
2061
2062                         sdmmc_cd: sdmcc-cd {
2063                                 rockchip,pins =
2064                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2065                         };
2066
2067                         sdmmc_wp: sdmmc-wp {
2068                                 rockchip,pins =
2069                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2070                         };
2071                 };
2072
2073                 spdif {
2074                         spdif_bus: spdif-bus {
2075                                 rockchip,pins =
2076                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2077                         };
2078
2079                         spdif_bus_1: spdif-bus-1 {
2080                                 rockchip,pins =
2081                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2082                         };
2083                 };
2084
2085                 spi0 {
2086                         spi0_clk: spi0-clk {
2087                                 rockchip,pins =
2088                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2089                         };
2090                         spi0_cs0: spi0-cs0 {
2091                                 rockchip,pins =
2092                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2093                         };
2094                         spi0_cs1: spi0-cs1 {
2095                                 rockchip,pins =
2096                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2097                         };
2098                         spi0_tx: spi0-tx {
2099                                 rockchip,pins =
2100                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2101                         };
2102                         spi0_rx: spi0-rx {
2103                                 rockchip,pins =
2104                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2105                         };
2106                 };
2107
2108                 spi1 {
2109                         spi1_clk: spi1-clk {
2110                                 rockchip,pins =
2111                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2112                         };
2113                         spi1_cs0: spi1-cs0 {
2114                                 rockchip,pins =
2115                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2116                         };
2117                         spi1_rx: spi1-rx {
2118                                 rockchip,pins =
2119                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2120                         };
2121                         spi1_tx: spi1-tx {
2122                                 rockchip,pins =
2123                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2124                         };
2125                 };
2126
2127                 spi2 {
2128                         spi2_clk: spi2-clk {
2129                                 rockchip,pins =
2130                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2131                         };
2132                         spi2_cs0: spi2-cs0 {
2133                                 rockchip,pins =
2134                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2135                         };
2136                         spi2_rx: spi2-rx {
2137                                 rockchip,pins =
2138                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2139                         };
2140                         spi2_tx: spi2-tx {
2141                                 rockchip,pins =
2142                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2143                         };
2144                 };
2145
2146                 spi3 {
2147                         spi3_clk: spi3-clk {
2148                                 rockchip,pins =
2149                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2150                         };
2151                         spi3_cs0: spi3-cs0 {
2152                                 rockchip,pins =
2153                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2154                         };
2155                         spi3_rx: spi3-rx {
2156                                 rockchip,pins =
2157                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2158                         };
2159                         spi3_tx: spi3-tx {
2160                                 rockchip,pins =
2161                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2162                         };
2163                 };
2164
2165                 spi4 {
2166                         spi4_clk: spi4-clk {
2167                                 rockchip,pins =
2168                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2169                         };
2170                         spi4_cs0: spi4-cs0 {
2171                                 rockchip,pins =
2172                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2173                         };
2174                         spi4_rx: spi4-rx {
2175                                 rockchip,pins =
2176                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2177                         };
2178                         spi4_tx: spi4-tx {
2179                                 rockchip,pins =
2180                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2181                         };
2182                 };
2183
2184                 spi5 {
2185                         spi5_clk: spi5-clk {
2186                                 rockchip,pins =
2187                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2188                         };
2189                         spi5_cs0: spi5-cs0 {
2190                                 rockchip,pins =
2191                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2192                         };
2193                         spi5_rx: spi5-rx {
2194                                 rockchip,pins =
2195                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2196                         };
2197                         spi5_tx: spi5-tx {
2198                                 rockchip,pins =
2199                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2200                         };
2201                 };
2202
2203                 tsadc {
2204                         otp_gpio: otp-gpio {
2205                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2206                         };
2207
2208                         otp_out: otp-out {
2209                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2210                         };
2211                 };
2212
2213                 uart0 {
2214                         uart0_xfer: uart0-xfer {
2215                                 rockchip,pins =
2216                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2217                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2218                         };
2219
2220                         uart0_cts: uart0-cts {
2221                                 rockchip,pins =
2222                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2223                         };
2224
2225                         uart0_rts: uart0-rts {
2226                                 rockchip,pins =
2227                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2228                         };
2229                 };
2230
2231                 uart1 {
2232                         uart1_xfer: uart1-xfer {
2233                                 rockchip,pins =
2234                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2235                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2236                         };
2237                 };
2238
2239                 uart2a {
2240                         uart2a_xfer: uart2a-xfer {
2241                                 rockchip,pins =
2242                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2243                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2244                         };
2245                 };
2246
2247                 uart2b {
2248                         uart2b_xfer: uart2b-xfer {
2249                                 rockchip,pins =
2250                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2251                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2252                         };
2253                 };
2254
2255                 uart2c {
2256                         uart2c_xfer: uart2c-xfer {
2257                                 rockchip,pins =
2258                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2259                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2260                         };
2261                 };
2262
2263                 uart3 {
2264                         uart3_xfer: uart3-xfer {
2265                                 rockchip,pins =
2266                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2267                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2268                         };
2269
2270                         uart3_cts: uart3-cts {
2271                                 rockchip,pins =
2272                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2273                         };
2274
2275                         uart3_rts: uart3-rts {
2276                                 rockchip,pins =
2277                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2278                         };
2279                 };
2280
2281                 uart4 {
2282                         uart4_xfer: uart4-xfer {
2283                                 rockchip,pins =
2284                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2285                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2286                         };
2287                 };
2288
2289                 uarthdcp {
2290                         uarthdcp_xfer: uarthdcp-xfer {
2291                                 rockchip,pins =
2292                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2293                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2294                         };
2295                 };
2296
2297                 pwm0 {
2298                         pwm0_pin: pwm0-pin {
2299                                 rockchip,pins =
2300                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2301                         };
2302
2303                         vop0_pwm_pin: vop0-pwm-pin {
2304                                 rockchip,pins =
2305                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2306                         };
2307                 };
2308
2309                 pwm1 {
2310                         pwm1_pin: pwm1-pin {
2311                                 rockchip,pins =
2312                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2313                         };
2314
2315                         vop1_pwm_pin: vop1-pwm-pin {
2316                                 rockchip,pins =
2317                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2318                         };
2319                 };
2320
2321                 pwm2 {
2322                         pwm2_pin: pwm2-pin {
2323                                 rockchip,pins =
2324                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2325                         };
2326                 };
2327
2328                 pwm3a {
2329                         pwm3a_pin: pwm3a-pin {
2330                                 rockchip,pins =
2331                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2332                         };
2333                 };
2334
2335                 pwm3b {
2336                         pwm3b_pin: pwm3b-pin {
2337                                 rockchip,pins =
2338                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2339                         };
2340                 };
2341
2342                 edp {
2343                         edp_hpd: edp-hpd {
2344                                 rockchip,pins =
2345                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2346                         };
2347                 };
2348
2349                 hdmi {
2350                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2351                                 rockchip,pins =
2352                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2353                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2354                         };
2355
2356                         hdmi_cec: hdmi-cec {
2357                                 rockchip,pins =
2358                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2359                         };
2360                 };
2361
2362                 pcie {
2363                         pcie_clkreqn: pci-clkreqn {
2364                                 rockchip,pins =
2365                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2366                         };
2367
2368                         pcie_clkreqnb: pci-clkreqnb {
2369                                 rockchip,pins =
2370                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2371                         };
2372                 };
2373         };
2374 };