arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/clock/rk3399-cru.h>
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/pinctrl/rockchip.h>
  47 #include <dt-bindings/thermal/thermal.h>
  48
  49 / {
  50         compatible = "rockchip,rk3399";
  51         interrupt-parent = <&gic>;
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         aliases {
  56                 serial0 = &uart0;
  57                 serial1 = &uart1;
  58                 serial2 = &uart2;
  59                 serial3 = &uart3;
  60         };
  61
  62         cpus {
  63                 #address-cells = <2>;
  64                 #size-cells = <0>;
  65
  66                 cpu-map {
  67                         cluster0 {
  68                                 core0 {
  69                                         cpu = <&cpu_l0>;
  70                                 };
  71                                 core1 {
  72                                         cpu = <&cpu_l1>;
  73                                 };
  74                                 core2 {
  75                                         cpu = <&cpu_l2>;
  76                                 };
  77                                 core3 {
  78                                         cpu = <&cpu_l3>;
  79                                 };
  80                         };
  81
  82                         cluster1 {
  83                                 core0 {
  84                                         cpu = <&cpu_b0>;
  85                                 };
  86                                 core1 {
  87                                         cpu = <&cpu_b1>;
  88                                 };
  89                         };
  90                 };
  91
  92                 cpu_l0: cpu@0 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         reg = <0x0 0x0>;
  96
  97                         #cooling-cells = <2>; /* min followed by max */
  98                 };
  99
 100                 cpu_l1: cpu@1 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x1>;
 104                 };
 105
 106                 cpu_l2: cpu@2 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a53", "arm,armv8";
 109                         reg = <0x0 0x2>;
 110                 };
 111
 112                 cpu_l3: cpu@3 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a53", "arm,armv8";
 115                         reg = <0x0 0x3>;
 116                 };
 117
 118                 cpu_b0: cpu@100 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a72", "arm,armv8";
 121                         reg = <0x0 0x100>;
 122
 123                         #cooling-cells = <2>; /* min followed by max */
 124                 };
 125
 126                 cpu_b1: cpu@101 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a72", "arm,armv8";
 129                         reg = <0x0 0x101>;
 130                 };
 131         };
 132
 133         timer {
 134                 compatible = "arm,armv8-timer";
 135                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 136                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 137                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 138                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 139         };
 140
 141         xin24m: xin24m {
 142                 compatible = "fixed-clock";
 143                 #clock-cells = <0>;
 144                 clock-frequency = <24000000>;
 145                 clock-output-names = "xin24m";
 146         };
 147
 148         gic: interrupt-controller@fee00000 {
 149                 compatible = "arm,gic-v3";
 150                 #interrupt-cells = <3>;
 151                 #address-cells = <2>;
 152                 #size-cells = <2>;
 153                 ranges;
 154                 interrupt-controller;
 155
 156                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 157                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 158                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 159                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 160                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 161                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 162                 its: interrupt-controller@fee20000 {
 163                         compatible = "arm,gic-v3-its";
 164                         msi-controller;
 165                         reg = <0x0 0xfee20000 0x0 0x20000>;
 166                 };
 167         };
 168
 169         amba {
 170                 compatible = "arm,amba-bus";
 171                 #address-cells = <2>;
 172                 #size-cells = <2>;
 173                 ranges;
 174
 175                 dmac_bus: dma-controller@ff6d0000 {
 176                         compatible = "arm,pl330", "arm,primecell";
 177                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 178                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 180                         #dma-cells = <1>;
 181                         clocks = <&cru ACLK_DMAC0_PERILP>;
 182                         clock-names = "apb_pclk";
 183                 };
 184
 185                 dmac_peri: dma-controller@ff6e0000 {
 186                         compatible = "arm,pl330", "arm,primecell";
 187                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 188                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 189                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 190                         #dma-cells = <1>;
 191                         clocks = <&cru ACLK_DMAC1_PERILP>;
 192                         clock-names = "apb_pclk";
 193                 };
 194         };
 195
 196         uart0: serial@ff180000 {
 197                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 198                 reg = <0x0 0xff180000 0x0 0x100>;
 199                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 200                 clock-names = "baudclk", "apb_pclk";
 201                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 202                 reg-shift = <2>;
 203                 reg-io-width = <4>;
 204                 status = "disabled";
 205         };
 206
 207         uart1: serial@ff190000 {
 208                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 209                 reg = <0x0 0xff190000 0x0 0x100>;
 210                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 211                 clock-names = "baudclk", "apb_pclk";
 212                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 213                 reg-shift = <2>;
 214                 reg-io-width = <4>;
 215                 status = "disabled";
 216         };
 217
 218         uart2: serial@ff1a0000 {
 219                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 220                 reg = <0x0 0xff1a0000 0x0 0x100>;
 221                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 222                 clock-names = "baudclk", "apb_pclk";
 223                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 224                 reg-shift = <2>;
 225                 reg-io-width = <4>;
 226                 status = "disabled";
 227         };
 228
 229         uart3: serial@ff1b0000 {
 230                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 231                 reg = <0x0 0xff1b0000 0x0 0x100>;
 232                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 233                 clock-names = "baudclk", "apb_pclk";
 234                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 235                 reg-shift = <2>;
 236                 reg-io-width = <4>;
 237                 status = "disabled";
 238         };
 239
 240         spi0: spi@ff1c0000 {
 241                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 242                 reg = <0x0 0xff110000 0x0 0x1000>;
 243                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 244                 clock-names = "spiclk", "apb_pclk";
 245                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250                 status = "disabled";
 251         };
 252
 253         spi1: spi@ff1d0000 {
 254                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 255                 reg = <0x0 0xff120000 0x0 0x1000>;
 256                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 257                 clock-names = "spiclk", "apb_pclk";
 258                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 259                 pinctrl-names = "default";
 260                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 status = "disabled";
 264         };
 265
 266         spi2: spi@ff1e0000 {
 267                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 268                 reg = <0x0 0xff130000 0x0 0x1000>;
 269                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 270                 clock-names = "spiclk", "apb_pclk";
 271                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 status = "disabled";
 277         };
 278
 279         spi4: spi@ff1f0000 {
 280                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 281                 reg = <0x0 0xff120000 0x0 0x1000>;
 282                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 283                 clock-names = "spiclk", "apb_pclk";
 284                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 285                 pinctrl-names = "default";
 286                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 287                 #address-cells = <1>;
 288                 #size-cells = <0>;
 289                 status = "disabled";
 290         };
 291
 292         spi5: spi@ff200000 {
 293                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 294                 reg = <0x0 0xff130000 0x0 0x1000>;
 295                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 296                 clock-names = "spiclk", "apb_pclk";
 297                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 status = "disabled";
 303         };
 304
 305         thermal-zones {
 306                 #include "rk3368-thermal.dtsi"
 307         };
 308
 309         tsadc: tsadc@ff260000 {
 310                 compatible = "rockchip,rk3399-tsadc";
 311                 reg = <0x0 0xff260000 0x0 0x100>;
 312                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 314                 clock-names = "tsadc", "apb_pclk";
 315                 resets = <&cru SRST_TSADC>;
 316                 reset-names = "tsadc-apb";
 317                 pinctrl-names = "init", "default", "sleep";
 318                 pinctrl-0 = <&otp_gpio>;
 319                 pinctrl-1 = <&otp_out>;
 320                 pinctrl-2 = <&otp_gpio>;
 321                 #thermal-sensor-cells = <1>;
 322                 rockchip,hw-tshut-temp = <95000>;
 323                 status = "disabled";
 324         };
 325
 326         pmugrf: syscon@ff320000 {
 327                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 328                 reg = <0x0 0xff320000 0x0 0x1000>;
 329         };
 330
 331         spi3: spi@ff350000 {
 332                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 333                 reg = <0x0 0xff110000 0x0 0x1000>;
 334                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 335                 clock-names = "spiclk", "apb_pclk";
 336                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 status = "disabled";
 342         };
 343
 344         uart4: serial@ff370000 {
 345                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 346                 reg = <0x0 0xff370000 0x0 0x100>;
 347                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 348                 clock-names = "baudclk", "apb_pclk";
 349                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 350                 reg-shift = <2>;
 351                 reg-io-width = <4>;
 352                 status = "disabled";
 353         };
 354
 355         pmucru: pmu-clock-controller@ff750000 {
 356                 compatible = "rockchip,rk3399-pmucru";
 357                 reg = <0x0 0xff750000 0x0 0x1000>;
 358                 rockchip,grf = <&pmugrf>;
 359                 #clock-cells = <1>;
 360                 #reset-cells = <1>;
 361         };
 362
 363         cru: clock-controller@ff760000 {
 364                 compatible = "rockchip,rk3399-cru";
 365                 reg = <0x0 0xff760000 0x0 0x1000>;
 366                 rockchip,grf = <&grf>;
 367                 #clock-cells = <1>;
 368                 #reset-cells = <1>;
 369         };
 370
 371         grf: syscon@ff770000 {
 372                 compatible = "rockchip,rk3399-grf", "syscon";
 373                 reg = <0x0 0xff770000 0x0 0x10000>;
 374         };
 375
 376         spdif: spdif@ff870000 {
 377                 compatible = "rockchip,rk3399-spdif";
 378                 reg = <0x0 0xff870000 0x0 0x1000>;
 379                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 380                 dmas = <&dmac_bus 7>;
 381                 dma-names = "tx";
 382                 clock-names = "hclk", "mclk";
 383                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&spdif_bus>;
 386                 status = "disabled";
 387         };
 388
 389         i2s0: i2s@ff880000 {
 390                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 391                 reg = <0x0 0xff880000 0x0 0x1000>;
 392                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 396                 dma-names = "tx", "rx";
 397                 clock-names = "i2s_hclk", "i2s_clk";
 398                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&i2s0_8ch_bus>;
 401                 status = "disabled";
 402         };
 403
 404         i2s1: i2s@ff890000 {
 405                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 406                 reg = <0x0 0xff890000 0x0 0x1000>;
 407                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 411                 dma-names = "tx", "rx";
 412                 clock-names = "i2s_hclk", "i2s_clk";
 413                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&i2s1_2ch_bus>;
 416                 status = "disabled";
 417         };
 418
 419         i2s2: i2s@ff8a0000 {
 420                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 421                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 422                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 426                 dma-names = "tx", "rx";
 427                 clock-names = "i2s_hclk", "i2s_clk";
 428                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 429                 status = "disabled";
 430         };
 431
 432         pinctrl: pinctrl {
 433                 compatible = "rockchip,rk3399-pinctrl";
 434                 rockchip,grf = <&grf>;
 435                 rockchip,pmu = <&pmugrf>;
 436                 #address-cells = <0x2>;
 437                 #size-cells = <0x2>;
 438                 ranges;
 439
 440                 gpio0: gpio0@ff720000 {
 441                         compatible = "rockchip,gpio-bank";
 442                         reg = <0x0 0xff720000 0x0 0x100>;
 443                         clocks = <&xin24m>;
 444                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 445
 446                         gpio-controller;
 447                         #gpio-cells = <0x2>;
 448
 449                         interrupt-controller;
 450                         #interrupt-cells = <0x2>;
 451                 };
 452
 453                 gpio1: gpio1@ff730000 {
 454                         compatible = "rockchip,gpio-bank";
 455                         reg = <0x0 0xff730000 0x0 0x100>;
 456                         clocks = <&xin24m>;
 457                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 458
 459                         gpio-controller;
 460                         #gpio-cells = <0x2>;
 461
 462                         interrupt-controller;
 463                         #interrupt-cells = <0x2>;
 464                 };
 465
 466                 gpio2: gpio2@ff780000 {
 467                         compatible = "rockchip,gpio-bank";
 468                         reg = <0x0 0xff780000 0x0 0x100>;
 469                         clocks = <&xin24m>;
 470                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 471
 472                         gpio-controller;
 473                         #gpio-cells = <0x2>;
 474
 475                         interrupt-controller;
 476                         #interrupt-cells = <0x2>;
 477                 };
 478
 479                 gpio3: gpio3@ff788000 {
 480                         compatible = "rockchip,gpio-bank";
 481                         reg = <0x0 0xff788000 0x0 0x100>;
 482                         clocks = <&xin24m>;
 483                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 484
 485                         gpio-controller;
 486                         #gpio-cells = <0x2>;
 487
 488                         interrupt-controller;
 489                         #interrupt-cells = <0x2>;
 490                 };
 491
 492                 gpio4: gpio4@ff790000 {
 493                         compatible = "rockchip,gpio-bank";
 494                         reg = <0x0 0xff790000 0x0 0x100>;
 495                         clocks = <&xin24m>;
 496                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 497
 498                         gpio-controller;
 499                         #gpio-cells = <0x2>;
 500
 501                         interrupt-controller;
 502                         #interrupt-cells = <0x2>;
 503                 };
 504
 505                 pcfg_pull_up: pcfg-pull-up {
 506                         bias-pull-up;
 507                 };
 508
 509                 pcfg_pull_down: pcfg-pull-down {
 510                         bias-pull-down;
 511                 };
 512
 513                 pcfg_pull_none: pcfg-pull-none {
 514                         bias-disable;
 515                 };
 516
 517                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 518                         bias-disable;
 519                         drive-strength = <12>;
 520                 };
 521
 522                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 523                         bias-pull-up;
 524                         drive-strength = <8>;
 525                 };
 526
 527                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 528                         bias-pull-down;
 529                         drive-strength = <4>;
 530                 };
 531
 532                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 533                         bias-pull-up;
 534                         drive-strength = <2>;
 535                 };
 536
 537                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 538                         bias-pull-down;
 539                         drive-strength = <12>;
 540                 };
 541
 542                 emmc {
 543                         emmc_pwr: emmc-pwr {
 544                                 rockchip,pins =
 545                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 546                         };
 547                 };
 548
 549                 gmac {
 550                         rgmii_pins: rgmii-pins {
 551                                 rockchip,pins =
 552                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 553                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 554                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 555                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 556                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 557                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 558                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 559                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 560                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 561                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 562                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 563                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 564                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 565                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 566                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 567                         };
 568
 569                         rmii_pins: rmii-pins {
 570                                 rockchip,pins =
 571                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 572                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 573                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 574                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 575                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 576                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 577                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 578                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 579                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 580                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 581                         };
 582                 };
 583
 584                 i2c0 {
 585                         i2c0_xfer: i2c0-xfer {
 586                                 rockchip,pins =
 587                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 588                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 589                         };
 590                 };
 591
 592                 i2c1 {
 593                         i2c1_xfer: i2c1-xfer {
 594                                 rockchip,pins =
 595                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 596                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 597                         };
 598                 };
 599
 600                 i2c2 {
 601                         i2c2_xfer: i2c2-xfer {
 602                                 rockchip,pins =
 603                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 604                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 605                         };
 606                 };
 607
 608                 i2c3 {
 609                         i2c3_xfer: i2c3-xfer {
 610                                 rockchip,pins =
 611                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 612                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 613                         };
 614                 };
 615
 616                 i2c4 {
 617                         i2c4_xfer: i2c4-xfer {
 618                                 rockchip,pins =
 619                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 620                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 621                         };
 622                 };
 623
 624                 i2c5 {
 625                         i2c5_xfer: i2c5-xfer {
 626                                 rockchip,pins =
 627                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 628                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 629                         };
 630                 };
 631
 632                 i2c6 {
 633                         i2c6_xfer: i2c6-xfer {
 634                                 rockchip,pins =
 635                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 636                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 637                         };
 638                 };
 639
 640                 i2c7 {
 641                         i2c7_xfer: i2c7-xfer {
 642                                 rockchip,pins =
 643                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 644                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 645                         };
 646                 };
 647
 648                 i2c8 {
 649                         i2c8_xfer: i2c8-xfer {
 650                                 rockchip,pins =
 651                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 652                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 653                         };
 654                 };
 655
 656                 i2s0 {
 657                         i2s0_8ch_bus: i2s0-8ch-bus {
 658                                 rockchip,pins =
 659                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 660                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 661                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 662                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 663                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 664                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 665                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 666                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 667                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 668                         };
 669                 };
 670
 671                 i2s1 {
 672                         i2s1_2ch_bus: i2s1-2ch-bus {
 673                                 rockchip,pins =
 674                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 675                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 676                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 677                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 678                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 679                         };
 680                 };
 681
 682                 sdio0 {
 683                         sdio0_bus1: sdio0-bus1 {
 684                                 rockchip,pins =
 685                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
 686                         };
 687
 688                         sdio0_bus4: sdio0-bus4 {
 689                                 rockchip,pins =
 690                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
 691                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
 692                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
 693                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
 694                         };
 695
 696                         sdio0_cmd: sdio0-cmd {
 697                                 rockchip,pins =
 698                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
 699                         };
 700
 701                         sdio0_clk: sdio0-clk {
 702                                 rockchip,pins =
 703                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 704                         };
 705
 706                         sdio0_cd: sdio0-cd {
 707                                 rockchip,pins =
 708                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
 709                         };
 710
 711                         sdio0_pwr: sdio0-pwr {
 712                                 rockchip,pins =
 713                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
 714                         };
 715
 716                         sdio0_bkpwr: sdio0-bkpwr {
 717                                 rockchip,pins =
 718                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
 719                         };
 720
 721                         sdio0_wp: sdio0-wp {
 722                                 rockchip,pins =
 723                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
 724                         };
 725
 726                         sdio0_int: sdio0-int {
 727                                 rockchip,pins =
 728                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
 729                         };
 730                 };
 731
 732                 sdmmc {
 733                         sdmmc_bus1: sdmmc-bus1 {
 734                                 rockchip,pins =
 735                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 736                         };
 737
 738                         sdmmc_bus4: sdmmc-bus4 {
 739                                 rockchip,pins =
 740                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 741                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 742                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 743                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 744                         };
 745
 746                         sdmmc_clk: sdmmc-clk {
 747                                 rockchip,pins =
 748                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 749                         };
 750
 751                         sdmmc_cmd: sdmmc-cmd {
 752                                 rockchip,pins =
 753                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 754                         };
 755
 756                         sdmmc_cd: sdmcc-cd {
 757                                 rockchip,pins =
 758                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 759                         };
 760
 761                         sdmmc_wp: sdmmc-wp {
 762                                 rockchip,pins =
 763                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 764                         };
 765                 };
 766
 767                 spdif {
 768                         spdif_bus: spdif-bus {
 769                                 rockchip,pins =
 770                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
 771                         };
 772                 };
 773
 774                 spi0 {
 775                         spi0_clk: spi0-clk {
 776                                 rockchip,pins =
 777                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 778                         };
 779                         spi0_cs0: spi0-cs0 {
 780                                 rockchip,pins =
 781                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 782                         };
 783                         spi0_cs1: spi0-cs1 {
 784                                 rockchip,pins =
 785                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 786                         };
 787                         spi0_tx: spi0-tx {
 788                                 rockchip,pins =
 789                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 790                         };
 791                         spi0_rx: spi0-rx {
 792                                 rockchip,pins =
 793                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 794                         };
 795                 };
 796
 797                 spi1 {
 798                         spi1_clk: spi1-clk {
 799                                 rockchip,pins =
 800                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
 801                         };
 802                         spi1_cs0: spi1-cs0 {
 803                                 rockchip,pins =
 804                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
 805                         };
 806                         spi1_rx: spi1-rx {
 807                                 rockchip,pins =
 808                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
 809                         };
 810                         spi1_tx: spi1-tx {
 811                                 rockchip,pins =
 812                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
 813                         };
 814                 };
 815
 816                 spi2 {
 817                         spi2_clk: spi2-clk {
 818                                 rockchip,pins =
 819                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 820                         };
 821                         spi2_cs0: spi2-cs0 {
 822                                 rockchip,pins =
 823                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 824                         };
 825                         spi2_rx: spi2-rx {
 826                                 rockchip,pins =
 827                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 828                         };
 829                         spi2_tx: spi2-tx {
 830                                 rockchip,pins =
 831                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 832                         };
 833                 };
 834
 835                 spi3 {
 836                         spi3_clk: spi3-clk {
 837                                 rockchip,pins =
 838                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
 839                         };
 840                         spi3_cs0: spi3-cs0 {
 841                                 rockchip,pins =
 842                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
 843                         };
 844                         spi3_rx: spi3-rx {
 845                                 rockchip,pins =
 846                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
 847                         };
 848                         spi3_tx: spi3-tx {
 849                                 rockchip,pins =
 850                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
 851                         };
 852                 };
 853
 854                 spi4 {
 855                         spi4_clk: spi4-clk {
 856                                 rockchip,pins =
 857                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
 858                         };
 859                         spi4_cs0: spi4-cs0 {
 860                                 rockchip,pins =
 861                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
 862                         };
 863                         spi4_rx: spi4-rx {
 864                                 rockchip,pins =
 865                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
 866                         };
 867                         spi4_tx: spi4-tx {
 868                                 rockchip,pins =
 869                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
 870                         };
 871                 };
 872
 873                 spi5 {
 874                         spi5_clk: spi5-clk {
 875                                 rockchip,pins =
 876                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
 877                         };
 878                         spi5_cs0: spi5-cs0 {
 879                                 rockchip,pins =
 880                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
 881                         };
 882                         spi5_rx: spi5-rx {
 883                                 rockchip,pins =
 884                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
 885                         };
 886                         spi5_tx: spi5-tx {
 887                                 rockchip,pins =
 888                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 889                         };
 890                 };
 891
 892                 tsadc {
 893                         otp_gpio: otp-gpio {
 894                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
 895                         };
 896
 897                         otp_out: otp-out {
 898                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
 899                         };
 900                 };
 901
 902                 uart0 {
 903                         uart0_xfer: uart0-xfer {
 904                                 rockchip,pins =
 905                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
 906                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 907                         };
 908
 909                         uart0_cts: uart0-cts {
 910                                 rockchip,pins =
 911                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 912                         };
 913
 914                         uart0_rts: uart0-rts {
 915                                 rockchip,pins =
 916                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 917                         };
 918                 };
 919
 920                 uart1 {
 921                         uart1_xfer: uart1-xfer {
 922                                 rockchip,pins =
 923                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
 924                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
 925                         };
 926                 };
 927
 928                 uart2a {
 929                         uart2a_xfer: uart2a-xfer {
 930                                 rockchip,pins =
 931                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
 932                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
 933                         };
 934                 };
 935
 936                 uart2b {
 937                         uart2b_xfer: uart2b-xfer {
 938                                 rockchip,pins =
 939                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
 940                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
 941                         };
 942                 };
 943
 944                 uart2c {
 945                         uart2c_xfer: uart2c-xfer {
 946                                 rockchip,pins =
 947                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
 948                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
 949                         };
 950                 };
 951
 952                 uart3 {
 953                         uart3_xfer: uart3-xfer {
 954                                 rockchip,pins =
 955                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
 956                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
 957                         };
 958
 959                         uart3_cts: uart3-cts {
 960                                 rockchip,pins =
 961                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
 962                         };
 963
 964                         uart3_rts: uart3-rts {
 965                                 rockchip,pins =
 966                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
 967                         };
 968                 };
 969
 970                 uart4 {
 971                         uart4_xfer: uart4-xfer {
 972                                 rockchip,pins =
 973                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
 974                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 975                         };
 976                 };
 977
 978                 uarthdcp {
 979                         uarthdcp_xfer: uarthdcp-xfer {
 980                                 rockchip,pins =
 981                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
 982                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
 983                         };
 984                 };
 985
 986                 pwm0 {
 987                         pwm0_pin: pwm0-pin {
 988                                 rockchip,pins =
 989                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
 990                         };
 991
 992                         vop0_pwm_pin: vop0-pwm-pin {
 993                                 rockchip,pins =
 994                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
 995                         };
 996                 };
 997
 998                 pwm1 {
 999                         pwm1_pin: pwm1-pin {
1000                                 rockchip,pins =
1001                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1002                         };
1003
1004                         vop1_pwm_pin: vop1-pwm-pin {
1005                                 rockchip,pins =
1006                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1007                         };
1008                 };
1009         };
1010 };