arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 131                 };
 132
 133                 cpu_l2: cpu@2 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x0 0x2>;
 137                         enable-method = "psci";
 138                         clocks = <&cru ARMCLKL>;
 139                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 140                 };
 141
 142                 cpu_l3: cpu@3 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a53", "arm,armv8";
 145                         reg = <0x0 0x3>;
 146                         enable-method = "psci";
 147                         clocks = <&cru ARMCLKL>;
 148                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 149                 };
 150
 151                 cpu_b0: cpu@100 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a72", "arm,armv8";
 154                         reg = <0x0 0x100>;
 155                         enable-method = "psci";
 156                         #cooling-cells = <2>; /* min followed by max */
 157                         dynamic-power-coefficient = <436>;
 158                         clocks = <&cru ARMCLKB>;
 159                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 160                 };
 161
 162                 cpu_b1: cpu@101 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a72", "arm,armv8";
 165                         reg = <0x0 0x101>;
 166                         enable-method = "psci";
 167                         clocks = <&cru ARMCLKB>;
 168                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 169                 };
 170
 171                 idle-states {
 172                         entry-method = "psci";
 173
 174                         CPU_SLEEP: cpu-sleep {
 175                                 compatible = "arm,idle-state";
 176                                 local-timer-stop;
 177                                 arm,psci-suspend-param = <0x0010000>;
 178                                 entry-latency-us = <120>;
 179                                 exit-latency-us = <250>;
 180                                 min-residency-us = <900>;
 181                         };
 182
 183                         CLUSTER_SLEEP: cluster-sleep {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x1010000>;
 187                                 entry-latency-us = <400>;
 188                                 exit-latency-us = <500>;
 189                                 min-residency-us = <2000>;
 190                         };
 191                 };
 192         };
 193
 194         cpu_avs: cpu-avs {
 195                 cluster0-avs {
 196                         cluster-id = <0>;
 197                         min-volt = <800000>; /* uV */
 198                         min-freq = <408000>; /* KHz */
 199                         leakage-adjust-volt = <
 200                         /*  mA        mA         uV */
 201                             0         254        0
 202                         >;
 203                         nvmem-cells = <&cpul_leakage>;
 204                         nvmem-cell-names = "cpu_leakage";
 205                 };
 206                 cluster1-avs {
 207                         cluster-id = <1>;
 208                         min-volt = <800000>; /* uV */
 209                         min-freq = <408000>; /* KHz */
 210                         leakage-adjust-volt = <
 211                         /*  mA        mA         uV */
 212                             0         254        0
 213                         >;
 214                         nvmem-cells = <&cpub_leakage>;
 215                         nvmem-cell-names = "cpu_leakage";
 216                 };
 217         };
 218
 219         timer {
 220                 compatible = "arm,armv8-timer";
 221                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 222                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 223                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 224                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 225         };
 226
 227         pmu_a53 {
 228                 compatible = "arm,cortex-a53-pmu";
 229                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 230         };
 231
 232         pmu_a72 {
 233                 compatible = "arm,cortex-a72-pmu";
 234                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 235         };
 236
 237         xin24m: xin24m {
 238                 compatible = "fixed-clock";
 239                 #clock-cells = <0>;
 240                 clock-frequency = <24000000>;
 241                 clock-output-names = "xin24m";
 242         };
 243
 244         amba {
 245                 compatible = "arm,amba-bus";
 246                 #address-cells = <2>;
 247                 #size-cells = <2>;
 248                 ranges;
 249
 250                 dmac_bus: dma-controller@ff6d0000 {
 251                         compatible = "arm,pl330", "arm,primecell";
 252                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 253                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 254                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 255                         #dma-cells = <1>;
 256                         clocks = <&cru ACLK_DMAC0_PERILP>;
 257                         clock-names = "apb_pclk";
 258                         peripherals-req-type-burst;
 259                 };
 260
 261                 dmac_peri: dma-controller@ff6e0000 {
 262                         compatible = "arm,pl330", "arm,primecell";
 263                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 264                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 265                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 266                         #dma-cells = <1>;
 267                         clocks = <&cru ACLK_DMAC1_PERILP>;
 268                         clock-names = "apb_pclk";
 269                         peripherals-req-type-burst;
 270                 };
 271         };
 272
 273         gmac: eth@fe300000 {
 274                 compatible = "rockchip,rk3399-gmac";
 275                 reg = <0x0 0xfe300000 0x0 0x10000>;
 276                 rockchip,grf = <&grf>;
 277                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 278                 interrupt-names = "macirq";
 279                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 280                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 281                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 282                          <&cru PCLK_GMAC>;
 283                 clock-names = "stmmaceth", "mac_clk_rx",
 284                               "mac_clk_tx", "clk_mac_ref",
 285                               "clk_mac_refout", "aclk_mac",
 286                               "pclk_mac";
 287                 resets = <&cru SRST_A_GMAC>;
 288                 reset-names = "stmmaceth";
 289                 power-domains = <&power RK3399_PD_GMAC>;
 290                 status = "disabled";
 291         };
 292
 293         sdio0: dwmmc@fe310000 {
 294                 compatible = "rockchip,rk3399-dw-mshc",
 295                              "rockchip,rk3288-dw-mshc";
 296                 reg = <0x0 0xfe310000 0x0 0x4000>;
 297                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 298                 clock-freq-min-max = <400000 150000000>;
 299                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 300                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 301                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 302                 fifo-depth = <0x100>;
 303                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 304                 status = "disabled";
 305         };
 306
 307         sdmmc: dwmmc@fe320000 {
 308                 compatible = "rockchip,rk3399-dw-mshc",
 309                              "rockchip,rk3288-dw-mshc";
 310                 reg = <0x0 0xfe320000 0x0 0x4000>;
 311                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 312                 clock-freq-min-max = <400000 150000000>;
 313                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 314                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 315                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 316                 fifo-depth = <0x100>;
 317                 power-domains = <&power RK3399_PD_SD>;
 318                 status = "disabled";
 319         };
 320
 321         sdhci: sdhci@fe330000 {
 322                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 323                 reg = <0x0 0xfe330000 0x0 0x10000>;
 324                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 325                 arasan,soc-ctl-syscon = <&grf>;
 326                 assigned-clocks = <&cru SCLK_EMMC>;
 327                 assigned-clock-rates = <200000000>;
 328                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 329                 clock-names = "clk_xin", "clk_ahb";
 330                 clock-output-names = "emmc_cardclock";
 331                 #clock-cells = <0>;
 332                 phys = <&emmc_phy>;
 333                 phy-names = "phy_arasan";
 334                 power-domains = <&power RK3399_PD_EMMC>;
 335                 status = "disabled";
 336         };
 337
 338         usb_host0_ehci: usb@fe380000 {
 339                 compatible = "generic-ehci";
 340                 reg = <0x0 0xfe380000 0x0 0x20000>;
 341                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 343                          <&cru SCLK_USBPHY0_480M_SRC>;
 344                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 345                 phys = <&u2phy0_host>;
 346                 phy-names = "usb";
 347                 power-domains = <&power RK3399_PD_PERIHP>;
 348                 status = "disabled";
 349         };
 350
 351         usb_host0_ohci: usb@fe3a0000 {
 352                 compatible = "generic-ohci";
 353                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 354                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 355                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 356                          <&cru SCLK_USBPHY0_480M_SRC>;
 357                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 358                 phys = <&u2phy0_host>;
 359                 phy-names = "usb";
 360                 power-domains = <&power RK3399_PD_PERIHP>;
 361                 status = "disabled";
 362         };
 363
 364         usb_host1_ehci: usb@fe3c0000 {
 365                 compatible = "generic-ehci";
 366                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 367                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 368                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 369                          <&cru SCLK_USBPHY1_480M_SRC>;
 370                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 371                 phys = <&u2phy1_host>;
 372                 phy-names = "usb";
 373                 power-domains = <&power RK3399_PD_PERIHP>;
 374                 status = "disabled";
 375         };
 376
 377         usb_host1_ohci: usb@fe3e0000 {
 378                 compatible = "generic-ohci";
 379                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 380                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 381                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 382                          <&cru SCLK_USBPHY1_480M_SRC>;
 383                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 384                 phys = <&u2phy1_host>;
 385                 phy-names = "usb";
 386                 power-domains = <&power RK3399_PD_PERIHP>;
 387                 status = "disabled";
 388         };
 389
 390         usbdrd3_0: usb@fe800000 {
 391                 compatible = "rockchip,rk3399-dwc3";
 392                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 393                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 394                 clock-names = "ref_clk", "suspend_clk",
 395                               "bus_clk", "grf_clk";
 396                 power-domains = <&power RK3399_PD_USB3>;
 397                 resets = <&cru SRST_A_USB3_OTG0>;
 398                 reset-names = "usb3-otg";
 399                 #address-cells = <2>;
 400                 #size-cells = <2>;
 401                 ranges;
 402                 status = "disabled";
 403                 usbdrd_dwc3_0: dwc3@fe800000 {
 404                         compatible = "snps,dwc3";
 405                         reg = <0x0 0xfe800000 0x0 0x100000>;
 406                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 407                         dr_mode = "otg";
 408                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 409                         phy-names = "usb2-phy", "usb3-phy";
 410                         phy_type = "utmi_wide";
 411                         snps,dis_enblslpm_quirk;
 412                         snps,dis-u2-freeclk-exists-quirk;
 413                         snps,dis_u2_susphy_quirk;
 414                         snps,dis-del-phy-power-chg-quirk;
 415                         snps,xhci-slow-suspend-quirk;
 416                         status = "disabled";
 417                 };
 418         };
 419
 420         usbdrd3_1: usb@fe900000 {
 421                 compatible = "rockchip,rk3399-dwc3";
 422                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 423                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 424                 clock-names = "ref_clk", "suspend_clk",
 425                               "bus_clk", "grf_clk";
 426                 power-domains = <&power RK3399_PD_USB3>;
 427                 resets = <&cru SRST_A_USB3_OTG1>;
 428                 reset-names = "usb3-otg";
 429                 #address-cells = <2>;
 430                 #size-cells = <2>;
 431                 ranges;
 432                 status = "disabled";
 433                 usbdrd_dwc3_1: dwc3@fe900000 {
 434                         compatible = "snps,dwc3";
 435                         reg = <0x0 0xfe900000 0x0 0x100000>;
 436                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 437                         dr_mode = "host";
 438                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 439                         phy-names = "usb2-phy", "usb3-phy";
 440                         phy_type = "utmi_wide";
 441                         snps,dis_enblslpm_quirk;
 442                         snps,dis-u2-freeclk-exists-quirk;
 443                         snps,dis_u2_susphy_quirk;
 444                         snps,dis-del-phy-power-chg-quirk;
 445                         snps,xhci-slow-suspend-quirk;
 446                         status = "disabled";
 447                 };
 448         };
 449
 450         cdn_dp: dp@fec00000 {
 451                 compatible = "rockchip,rk3399-cdn-dp";
 452                 reg = <0x0 0xfec00000 0x0 0x100000>;
 453                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 455                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 456                 clock-names = "core-clk", "pclk", "spdif", "grf";
 457                 assigned-clocks = <&cru SCLK_DP_CORE>;
 458                 assigned-clock-rates = <100000000>;
 459                 power-domains = <&power RK3399_PD_HDCP>;
 460                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 461                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 462                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 463                 reset-names = "spdif", "dptx", "apb", "core";
 464                 rockchip,grf = <&grf>;
 465                 #address-cells = <1>;
 466                 #size-cells = <0>;
 467                 #sound-dai-cells = <1>;
 468                 status = "disabled";
 469
 470                 ports {
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473
 474                         dp_in: port {
 475                                 #address-cells = <1>;
 476                                 #size-cells = <0>;
 477                                 dp_in_vopb: endpoint@0 {
 478                                         reg = <0>;
 479                                         remote-endpoint = <&vopb_out_dp>;
 480                                 };
 481
 482                                 dp_in_vopl: endpoint@1 {
 483                                         reg = <1>;
 484                                         remote-endpoint = <&vopl_out_dp>;
 485                                 };
 486                         };
 487                 };
 488         };
 489
 490         gic: interrupt-controller@fee00000 {
 491                 compatible = "arm,gic-v3";
 492                 #interrupt-cells = <4>;
 493                 #address-cells = <2>;
 494                 #size-cells = <2>;
 495                 ranges;
 496                 interrupt-controller;
 497
 498                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 499                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 500                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 501                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 502                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 503                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 504                 its: interrupt-controller@fee20000 {
 505                         compatible = "arm,gic-v3-its";
 506                         msi-controller;
 507                         reg = <0x0 0xfee20000 0x0 0x20000>;
 508                 };
 509
 510                 ppi-partitions {
 511                         part0: interrupt-partition-0 {
 512                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 513                         };
 514
 515                         part1: interrupt-partition-1 {
 516                                 affinity = <&cpu_b0 &cpu_b1>;
 517                         };
 518                 };
 519         };
 520
 521         saradc: saradc@ff100000 {
 522                 compatible = "rockchip,rk3399-saradc";
 523                 reg = <0x0 0xff100000 0x0 0x100>;
 524                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 525                 #io-channel-cells = <1>;
 526                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 527                 clock-names = "saradc", "apb_pclk";
 528                 resets = <&cru SRST_P_SARADC>;
 529                 reset-names = "saradc-apb";
 530                 status = "disabled";
 531         };
 532
 533         i2c0: i2c@ff3c0000 {
 534                 compatible = "rockchip,rk3399-i2c";
 535                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 536                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 537                 clock-names = "i2c", "pclk";
 538                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 539                 pinctrl-names = "default";
 540                 pinctrl-0 = <&i2c0_xfer>;
 541                 #address-cells = <1>;
 542                 #size-cells = <0>;
 543                 status = "disabled";
 544         };
 545
 546         i2c1: i2c@ff110000 {
 547                 compatible = "rockchip,rk3399-i2c";
 548                 reg = <0x0 0xff110000 0x0 0x1000>;
 549                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 550                 clock-names = "i2c", "pclk";
 551                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&i2c1_xfer>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 status = "disabled";
 557         };
 558
 559         i2c2: i2c@ff120000 {
 560                 compatible = "rockchip,rk3399-i2c";
 561                 reg = <0x0 0xff120000 0x0 0x1000>;
 562                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 563                 clock-names = "i2c", "pclk";
 564                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&i2c2_xfer>;
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 status = "disabled";
 570         };
 571
 572         i2c3: i2c@ff130000 {
 573                 compatible = "rockchip,rk3399-i2c";
 574                 reg = <0x0 0xff130000 0x0 0x1000>;
 575                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 576                 clock-names = "i2c", "pclk";
 577                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 578                 pinctrl-names = "default";
 579                 pinctrl-0 = <&i2c3_xfer>;
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582                 status = "disabled";
 583         };
 584
 585         i2c5: i2c@ff140000 {
 586                 compatible = "rockchip,rk3399-i2c";
 587                 reg = <0x0 0xff140000 0x0 0x1000>;
 588                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 589                 clock-names = "i2c", "pclk";
 590                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&i2c5_xfer>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 status = "disabled";
 596         };
 597
 598         i2c6: i2c@ff150000 {
 599                 compatible = "rockchip,rk3399-i2c";
 600                 reg = <0x0 0xff150000 0x0 0x1000>;
 601                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 602                 clock-names = "i2c", "pclk";
 603                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&i2c6_xfer>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 status = "disabled";
 609         };
 610
 611         i2c7: i2c@ff160000 {
 612                 compatible = "rockchip,rk3399-i2c";
 613                 reg = <0x0 0xff160000 0x0 0x1000>;
 614                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 615                 clock-names = "i2c", "pclk";
 616                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&i2c7_xfer>;
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621                 status = "disabled";
 622         };
 623
 624         uart0: serial@ff180000 {
 625                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 626                 reg = <0x0 0xff180000 0x0 0x100>;
 627                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 628                 clock-names = "baudclk", "apb_pclk";
 629                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 630                 reg-shift = <2>;
 631                 reg-io-width = <4>;
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 634                 status = "disabled";
 635         };
 636
 637         uart1: serial@ff190000 {
 638                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 639                 reg = <0x0 0xff190000 0x0 0x100>;
 640                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 641                 clock-names = "baudclk", "apb_pclk";
 642                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 643                 reg-shift = <2>;
 644                 reg-io-width = <4>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&uart1_xfer>;
 647                 status = "disabled";
 648         };
 649
 650         uart2: serial@ff1a0000 {
 651                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 652                 reg = <0x0 0xff1a0000 0x0 0x100>;
 653                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 654                 clock-names = "baudclk", "apb_pclk";
 655                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 656                 reg-shift = <2>;
 657                 reg-io-width = <4>;
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&uart2c_xfer>;
 660                 status = "disabled";
 661         };
 662
 663         uart3: serial@ff1b0000 {
 664                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 665                 reg = <0x0 0xff1b0000 0x0 0x100>;
 666                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 667                 clock-names = "baudclk", "apb_pclk";
 668                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 669                 reg-shift = <2>;
 670                 reg-io-width = <4>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 673                 status = "disabled";
 674         };
 675
 676         spi0: spi@ff1c0000 {
 677                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 678                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 679                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 680                 clock-names = "spiclk", "apb_pclk";
 681                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 682                 pinctrl-names = "default";
 683                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 684                 #address-cells = <1>;
 685                 #size-cells = <0>;
 686                 status = "disabled";
 687         };
 688
 689         spi1: spi@ff1d0000 {
 690                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 691                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 692                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 693                 clock-names = "spiclk", "apb_pclk";
 694                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 695                 pinctrl-names = "default";
 696                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 697                 #address-cells = <1>;
 698                 #size-cells = <0>;
 699                 status = "disabled";
 700         };
 701
 702         spi2: spi@ff1e0000 {
 703                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 704                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 705                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 706                 clock-names = "spiclk", "apb_pclk";
 707                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 708                 pinctrl-names = "default";
 709                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 710                 #address-cells = <1>;
 711                 #size-cells = <0>;
 712                 status = "disabled";
 713         };
 714
 715         spi4: spi@ff1f0000 {
 716                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 717                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 718                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 719                 clock-names = "spiclk", "apb_pclk";
 720                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 721                 pinctrl-names = "default";
 722                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 723                 #address-cells = <1>;
 724                 #size-cells = <0>;
 725                 status = "disabled";
 726         };
 727
 728         spi5: spi@ff200000 {
 729                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 730                 reg = <0x0 0xff200000 0x0 0x1000>;
 731                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 732                 clock-names = "spiclk", "apb_pclk";
 733                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 734                 pinctrl-names = "default";
 735                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 736                 #address-cells = <1>;
 737                 #size-cells = <0>;
 738                 status = "disabled";
 739         };
 740
 741         thermal-zones {
 742                 soc_thermal: soc-thermal {
 743                         polling-delay-passive = <20>; /* milliseconds */
 744                         polling-delay = <1000>; /* milliseconds */
 745                         sustainable-power = <1000>; /* milliwatts */
 746
 747                         thermal-sensors = <&tsadc 0>;
 748
 749                         trips {
 750                                 threshold: trip-point@0 {
 751                                         temperature = <70000>; /* millicelsius */
 752                                         hysteresis = <2000>; /* millicelsius */
 753                                         type = "passive";
 754                                 };
 755                                 target: trip-point@1 {
 756                                         temperature = <85000>; /* millicelsius */
 757                                         hysteresis = <2000>; /* millicelsius */
 758                                         type = "passive";
 759                                 };
 760                                 soc_crit: soc-crit {
 761                                         temperature = <95000>; /* millicelsius */
 762                                         hysteresis = <2000>; /* millicelsius */
 763                                         type = "critical";
 764                                 };
 765                         };
 766
 767                         cooling-maps {
 768                                 map0 {
 769                                         trip = <&target>;
 770                                         cooling-device =
 771                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 772                                         contribution = <4096>;
 773                                 };
 774                                 map1 {
 775                                         trip = <&target>;
 776                                         cooling-device =
 777                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 778                                         contribution = <1024>;
 779                                 };
 780                                 map2 {
 781                                         trip = <&target>;
 782                                         cooling-device =
 783                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 784                                         contribution = <4096>;
 785                                 };
 786                         };
 787                 };
 788
 789                 gpu_thermal: gpu-thermal {
 790                         polling-delay-passive = <100>; /* milliseconds */
 791                         polling-delay = <1000>; /* milliseconds */
 792
 793                         thermal-sensors = <&tsadc 1>;
 794                 };
 795         };
 796
 797         tsadc: tsadc@ff260000 {
 798                 compatible = "rockchip,rk3399-tsadc";
 799                 reg = <0x0 0xff260000 0x0 0x100>;
 800                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 801                 rockchip,grf = <&grf>;
 802                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 803                 clock-names = "tsadc", "apb_pclk";
 804                 assigned-clocks = <&cru SCLK_TSADC>;
 805                 assigned-clock-rates = <750000>;
 806                 resets = <&cru SRST_TSADC>;
 807                 reset-names = "tsadc-apb";
 808                 pinctrl-names = "init", "default", "sleep";
 809                 pinctrl-0 = <&otp_gpio>;
 810                 pinctrl-1 = <&otp_out>;
 811                 pinctrl-2 = <&otp_gpio>;
 812                 #thermal-sensor-cells = <1>;
 813                 rockchip,hw-tshut-temp = <95000>;
 814                 status = "disabled";
 815         };
 816
 817         qos_emmc: qos@ffa58000 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffa58000 0x0 0x20>;
 820         };
 821
 822         qos_gmac: qos@ffa5c000 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffa5c000 0x0 0x20>;
 825         };
 826
 827         qos_pcie: qos@ffa60080 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffa60080 0x0 0x20>;
 830         };
 831
 832         qos_usb_host0: qos@ffa60100 {
 833                 compatible = "syscon";
 834                 reg = <0x0 0xffa60100 0x0 0x20>;
 835         };
 836
 837         qos_usb_host1: qos@ffa60180 {
 838                 compatible = "syscon";
 839                 reg = <0x0 0xffa60180 0x0 0x20>;
 840         };
 841
 842         qos_usb_otg0: qos@ffa70000 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffa70000 0x0 0x20>;
 845         };
 846
 847         qos_usb_otg1: qos@ffa70080 {
 848                 compatible = "syscon";
 849                 reg = <0x0 0xffa70080 0x0 0x20>;
 850         };
 851
 852         qos_sd: qos@ffa74000 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffa74000 0x0 0x20>;
 855         };
 856
 857         qos_sdioaudio: qos@ffa76000 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffa76000 0x0 0x20>;
 860         };
 861
 862         qos_hdcp: qos@ffa90000 {
 863                 compatible = "syscon";
 864                 reg = <0x0 0xffa90000 0x0 0x20>;
 865         };
 866
 867         qos_iep: qos@ffa98000 {
 868                 compatible = "syscon";
 869                 reg = <0x0 0xffa98000 0x0 0x20>;
 870         };
 871
 872         qos_isp0_m0: qos@ffaa0000 {
 873                 compatible = "syscon";
 874                 reg = <0x0 0xffaa0000 0x0 0x20>;
 875         };
 876
 877         qos_isp0_m1: qos@ffaa0080 {
 878                 compatible = "syscon";
 879                 reg = <0x0 0xffaa0080 0x0 0x20>;
 880         };
 881
 882         qos_isp1_m0: qos@ffaa8000 {
 883                 compatible = "syscon";
 884                 reg = <0x0 0xffaa8000 0x0 0x20>;
 885         };
 886
 887         qos_isp1_m1: qos@ffaa8080 {
 888                 compatible = "syscon";
 889                 reg = <0x0 0xffaa8080 0x0 0x20>;
 890         };
 891
 892         qos_rga_r: qos@ffab0000 {
 893                 compatible = "syscon";
 894                 reg = <0x0 0xffab0000 0x0 0x20>;
 895         };
 896
 897         qos_rga_w: qos@ffab0080 {
 898                 compatible = "syscon";
 899                 reg = <0x0 0xffab0080 0x0 0x20>;
 900         };
 901
 902         qos_video_m0: qos@ffab8000 {
 903                 compatible = "syscon";
 904                 reg = <0x0 0xffab8000 0x0 0x20>;
 905         };
 906
 907         qos_video_m1_r: qos@ffac0000 {
 908                 compatible = "syscon";
 909                 reg = <0x0 0xffac0000 0x0 0x20>;
 910         };
 911
 912         qos_video_m1_w: qos@ffac0080 {
 913                 compatible = "syscon";
 914                 reg = <0x0 0xffac0080 0x0 0x20>;
 915         };
 916
 917         qos_vop_big_r: qos@ffac8000 {
 918                 compatible = "syscon";
 919                 reg = <0x0 0xffac8000 0x0 0x20>;
 920         };
 921
 922         qos_vop_big_w: qos@ffac8080 {
 923                 compatible = "syscon";
 924                 reg = <0x0 0xffac8080 0x0 0x20>;
 925         };
 926
 927         qos_vop_little: qos@ffad0000 {
 928                 compatible = "syscon";
 929                 reg = <0x0 0xffad0000 0x0 0x20>;
 930         };
 931
 932         qos_perihp: qos@ffad8080 {
 933                 compatible = "syscon";
 934                 reg = <0x0 0xffad8080 0x0 0x20>;
 935         };
 936
 937         qos_gpu: qos@ffae0000 {
 938                 compatible = "syscon";
 939                 reg = <0x0 0xffae0000 0x0 0x20>;
 940         };
 941
 942         pmu: power-management@ff310000 {
 943                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 944                 reg = <0x0 0xff310000 0x0 0x1000>;
 945
 946                 /*
 947                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 948                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 949                  * Some of the power domains are grouped together for every
 950                  * voltage domain.
 951                  * The detail contents as below.
 952                  */
 953                 power: power-controller {
 954                         compatible = "rockchip,rk3399-power-controller";
 955                         #power-domain-cells = <1>;
 956                         #address-cells = <1>;
 957                         #size-cells = <0>;
 958
 959                         /* These power domains are grouped by VD_CENTER */
 960                         pd_iep@RK3399_PD_IEP {
 961                                 reg = <RK3399_PD_IEP>;
 962                                 clocks = <&cru ACLK_IEP>,
 963                                          <&cru HCLK_IEP>;
 964                                 pm_qos = <&qos_iep>;
 965                         };
 966                         pd_rga@RK3399_PD_RGA {
 967                                 reg = <RK3399_PD_RGA>;
 968                                 clocks = <&cru ACLK_RGA>,
 969                                          <&cru HCLK_RGA>;
 970                                 pm_qos = <&qos_rga_r>,
 971                                          <&qos_rga_w>;
 972                         };
 973                         pd_vcodec@RK3399_PD_VCODEC {
 974                                 reg = <RK3399_PD_VCODEC>;
 975                                 clocks = <&cru ACLK_VCODEC>,
 976                                          <&cru HCLK_VCODEC>;
 977                                 pm_qos = <&qos_video_m0>;
 978                         };
 979                         pd_vdu@RK3399_PD_VDU {
 980                                 reg = <RK3399_PD_VDU>;
 981                                 clocks = <&cru ACLK_VDU>,
 982                                          <&cru HCLK_VDU>;
 983                                 pm_qos = <&qos_video_m1_r>,
 984                                          <&qos_video_m1_w>;
 985                         };
 986
 987                         /* These power domains are grouped by VD_GPU */
 988                         pd_gpu@RK3399_PD_GPU {
 989                                 reg = <RK3399_PD_GPU>;
 990                                 clocks = <&cru ACLK_GPU>;
 991                                 pm_qos = <&qos_gpu>;
 992                         };
 993
 994                         /* These power domains are grouped by VD_LOGIC */
 995                         pd_edp@RK3399_PD_EDP {
 996                                 reg = <RK3399_PD_EDP>;
 997                                 clocks = <&cru PCLK_EDP_CTRL>;
 998                         };
 999                         pd_emmc@RK3399_PD_EMMC {
1000                                 reg = <RK3399_PD_EMMC>;
1001                                 clocks = <&cru ACLK_EMMC>;
1002                                 pm_qos = <&qos_emmc>;
1003                         };
1004                         pd_gmac@RK3399_PD_GMAC {
1005                                 reg = <RK3399_PD_GMAC>;
1006                                 clocks = <&cru ACLK_GMAC>,
1007                                          <&cru PCLK_GMAC>;
1008                                 pm_qos = <&qos_gmac>;
1009                         };
1010                         pd_perihp@RK3399_PD_PERIHP {
1011                                 reg = <RK3399_PD_PERIHP>;
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 clocks = <&cru ACLK_PERIHP>;
1015                                 pm_qos = <&qos_perihp>,
1016                                          <&qos_pcie>,
1017                                          <&qos_usb_host0>,
1018                                          <&qos_usb_host1>;
1019
1020                                 pd_sd@RK3399_PD_SD {
1021                                         reg = <RK3399_PD_SD>;
1022                                         clocks = <&cru HCLK_SDMMC>,
1023                                                  <&cru SCLK_SDMMC>;
1024                                         pm_qos = <&qos_sd>;
1025                                 };
1026                         };
1027                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1028                                 reg = <RK3399_PD_SDIOAUDIO>;
1029                                 clocks = <&cru HCLK_SDIO>;
1030                                 pm_qos = <&qos_sdioaudio>;
1031                         };
1032                         pd_usb3@RK3399_PD_USB3 {
1033                                 reg = <RK3399_PD_USB3>;
1034                                 clocks = <&cru ACLK_USB3>;
1035                                 pm_qos = <&qos_usb_otg0>,
1036                                          <&qos_usb_otg1>;
1037                         };
1038                         pd_vio@RK3399_PD_VIO {
1039                                 reg = <RK3399_PD_VIO>;
1040                                 #address-cells = <1>;
1041                                 #size-cells = <0>;
1042
1043                                 pd_hdcp@RK3399_PD_HDCP {
1044                                         reg = <RK3399_PD_HDCP>;
1045                                         clocks = <&cru ACLK_HDCP>,
1046                                                  <&cru HCLK_HDCP>,
1047                                                  <&cru PCLK_HDCP>;
1048                                         pm_qos = <&qos_hdcp>;
1049                                 };
1050                                 pd_isp0@RK3399_PD_ISP0 {
1051                                         reg = <RK3399_PD_ISP0>;
1052                                         clocks = <&cru ACLK_ISP0>,
1053                                                  <&cru HCLK_ISP0>;
1054                                         pm_qos = <&qos_isp0_m0>,
1055                                                  <&qos_isp0_m1>;
1056                                 };
1057                                 pd_isp1@RK3399_PD_ISP1 {
1058                                         reg = <RK3399_PD_ISP1>;
1059                                         clocks = <&cru ACLK_ISP1>,
1060                                                  <&cru HCLK_ISP1>;
1061                                         pm_qos = <&qos_isp1_m0>,
1062                                                  <&qos_isp1_m1>;
1063                                 };
1064                                 pd_tcpc0@RK3399_PD_TCPC0 {
1065                                         reg = <RK3399_PD_TCPD0>;
1066                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1067                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1068                                 };
1069                                 pd_tcpc1@RK3399_PD_TCPC1 {
1070                                         reg = <RK3399_PD_TCPD1>;
1071                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1072                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1073                                 };
1074                                 pd_vo@RK3399_PD_VO {
1075                                         reg = <RK3399_PD_VO>;
1076                                         #address-cells = <1>;
1077                                         #size-cells = <0>;
1078
1079                                         pd_vopb@RK3399_PD_VOPB {
1080                                                 reg = <RK3399_PD_VOPB>;
1081                                                 clocks = <&cru ACLK_VOP0>,
1082                                                          <&cru HCLK_VOP0>;
1083                                                 pm_qos = <&qos_vop_big_r>,
1084                                                          <&qos_vop_big_w>;
1085                                         };
1086                                         pd_vopl@RK3399_PD_VOPL {
1087                                                 reg = <RK3399_PD_VOPL>;
1088                                                 clocks = <&cru ACLK_VOP1>,
1089                                                          <&cru HCLK_VOP1>;
1090                                                 pm_qos = <&qos_vop_little>;
1091                                         };
1092                                 };
1093                         };
1094                 };
1095         };
1096
1097         pmugrf: syscon@ff320000 {
1098                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1099                 reg = <0x0 0xff320000 0x0 0x1000>;
1100
1101                 pmu_io_domains: pmu-io-domains {
1102                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1103                         status = "disabled";
1104                 };
1105
1106                 reboot-mode {
1107                         compatible = "syscon-reboot-mode";
1108                         offset = <0x300>;
1109                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
1110                         mode-charge = <BOOT_CHARGING>;
1111                         mode-fastboot = <BOOT_FASTBOOT>;
1112                         mode-loader = <BOOT_BL_DOWNLOAD>;
1113                         mode-normal = <BOOT_NORMAL>;
1114                         mode-recovery = <BOOT_RECOVERY>;
1115                         mode-ums = <BOOT_UMS>;
1116                 };
1117
1118                 pmu_pvtm: pmu-pvtm {
1119                         compatible = "rockchip,rk3399-pmu-pvtm";
1120                         clocks = <&pmucru SCLK_PVTM_PMU>;
1121                         clock-names = "pmu";
1122                         status = "disabled";
1123                 };
1124         };
1125
1126         spi3: spi@ff350000 {
1127                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1128                 reg = <0x0 0xff350000 0x0 0x1000>;
1129                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1130                 clock-names = "spiclk", "apb_pclk";
1131                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1132                 pinctrl-names = "default";
1133                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1134                 #address-cells = <1>;
1135                 #size-cells = <0>;
1136                 status = "disabled";
1137         };
1138
1139         uart4: serial@ff370000 {
1140                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1141                 reg = <0x0 0xff370000 0x0 0x100>;
1142                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1143                 clock-names = "baudclk", "apb_pclk";
1144                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1145                 reg-shift = <2>;
1146                 reg-io-width = <4>;
1147                 pinctrl-names = "default";
1148                 pinctrl-0 = <&uart4_xfer>;
1149                 status = "disabled";
1150         };
1151
1152         i2c4: i2c@ff3d0000 {
1153                 compatible = "rockchip,rk3399-i2c";
1154                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1155                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1156                 clock-names = "i2c", "pclk";
1157                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1158                 pinctrl-names = "default";
1159                 pinctrl-0 = <&i2c4_xfer>;
1160                 #address-cells = <1>;
1161                 #size-cells = <0>;
1162                 status = "disabled";
1163         };
1164
1165         i2c8: i2c@ff3e0000 {
1166                 compatible = "rockchip,rk3399-i2c";
1167                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1168                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1169                 clock-names = "i2c", "pclk";
1170                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1171                 pinctrl-names = "default";
1172                 pinctrl-0 = <&i2c8_xfer>;
1173                 #address-cells = <1>;
1174                 #size-cells = <0>;
1175                 status = "disabled";
1176         };
1177
1178         pcie_phy: phy@e220 {
1179                 compatible = "rockchip,rk3399-pcie-phy";
1180                 #phy-cells = <0>;
1181                 rockchip,grf = <&grf>;
1182                 clocks = <&cru SCLK_PCIEPHY_REF>;
1183                 clock-names = "refclk";
1184                 resets = <&cru SRST_PCIEPHY>;
1185                 reset-names = "phy";
1186                 status = "disabled";
1187         };
1188
1189         pcie0: pcie@f8000000 {
1190                 compatible = "rockchip,rk3399-pcie";
1191                 #address-cells = <3>;
1192                 #size-cells = <2>;
1193                 aspm-no-l0s;
1194                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1195                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1196                 clock-names = "aclk", "aclk-perf",
1197                               "hclk", "pm";
1198                 bus-range = <0x0 0x1>;
1199                 max-link-speed = <1>;
1200                 msi-map = <0x0 &its 0x0 0x1000>;
1201                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1202                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1203                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1204                 interrupt-names = "sys", "legacy", "client";
1205                 #interrupt-cells = <1>;
1206                 interrupt-map-mask = <0 0 0 7>;
1207                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1208                                 <0 0 0 2 &pcie0_intc 1>,
1209                                 <0 0 0 3 &pcie0_intc 2>,
1210                                 <0 0 0 4 &pcie0_intc 3>;
1211                 phys = <&pcie_phy>;
1212                 phy-names = "pcie-phy";
1213                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1214                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1215                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1216                       <0x0 0xfd000000 0x0 0x1000000>;
1217                 reg-names = "axi-base", "apb-base";
1218                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1219                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1220                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1221                          <&cru SRST_A_PCIE>;
1222                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1223                               "pm", "pclk", "aclk";
1224                 status = "disabled";
1225                 pcie0_intc: interrupt-controller {
1226                         interrupt-controller;
1227                         #address-cells = <0>;
1228                         #interrupt-cells = <1>;
1229                 };
1230         };
1231
1232         pwm0: pwm@ff420000 {
1233                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1234                 reg = <0x0 0xff420000 0x0 0x10>;
1235                 #pwm-cells = <3>;
1236                 pinctrl-names = "default";
1237                 pinctrl-0 = <&pwm0_pin>;
1238                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1239                 clock-names = "pwm";
1240                 status = "disabled";
1241         };
1242
1243         pwm1: pwm@ff420010 {
1244                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1245                 reg = <0x0 0xff420010 0x0 0x10>;
1246                 #pwm-cells = <3>;
1247                 pinctrl-names = "default";
1248                 pinctrl-0 = <&pwm1_pin>;
1249                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1250                 clock-names = "pwm";
1251                 status = "disabled";
1252         };
1253
1254         pwm2: pwm@ff420020 {
1255                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1256                 reg = <0x0 0xff420020 0x0 0x10>;
1257                 #pwm-cells = <3>;
1258                 pinctrl-names = "default";
1259                 pinctrl-0 = <&pwm2_pin>;
1260                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1261                 clock-names = "pwm";
1262                 status = "disabled";
1263         };
1264
1265         pwm3: pwm@ff420030 {
1266                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1267                 reg = <0x0 0xff420030 0x0 0x10>;
1268                 #pwm-cells = <3>;
1269                 pinctrl-names = "default";
1270                 pinctrl-0 = <&pwm3a_pin>;
1271                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1272                 clock-names = "pwm";
1273                 status = "disabled";
1274         };
1275
1276         dfi: dfi@ff630000 {
1277                 reg = <0x00 0xff630000 0x00 0x4000>;
1278                 compatible = "rockchip,rk3399-dfi";
1279                 rockchip,pmu = <&pmugrf>;
1280                 clocks = <&cru PCLK_DDR_MON>;
1281                 clock-names = "pclk_ddr_mon";
1282                 status = "disabled";
1283         };
1284
1285         dmc: dmc {
1286                 compatible = "rockchip,rk3399-dmc";
1287                 devfreq-events = <&dfi>;
1288                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1289                 clocks = <&cru SCLK_DDRCLK>;
1290                 clock-names = "dmc_clk";
1291                 ddr_timing = <&ddr_timing>;
1292                 status = "disabled";
1293         };
1294
1295         vpu: vpu_service@ff650000 {
1296                 compatible = "rockchip,vpu_service";
1297                 rockchip,grf = <&grf>;
1298                 iommus = <&vpu_mmu>;
1299                 iommu_enabled = <1>;
1300                 reg = <0x0 0xff650000 0x0 0x800>;
1301                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1302                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1303                 interrupt-names = "irq_dec", "irq_enc";
1304                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1305                 clock-names = "aclk_vcodec", "hclk_vcodec";
1306                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1307                 reset-names = "video_h", "video_a";
1308                 power-domains = <&power RK3399_PD_VCODEC>;
1309                 name = "vpu_service";
1310                 dev_mode = <0>;
1311                 /* 0 means ion, 1 means drm */
1312                 allocator = <1>;
1313                 status = "disabled";
1314         };
1315
1316         vpu_mmu: iommu@ff650800 {
1317                 compatible = "rockchip,iommu";
1318                 reg = <0x0 0xff650800 0x0 0x40>;
1319                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1320                 interrupt-names = "vpu_mmu";
1321                 #iommu-cells = <0>;
1322         };
1323
1324         rkvdec: rkvdec@ff660000 {
1325                 compatible = "rockchip,rkvdec";
1326                 rockchip,grf = <&grf>;
1327                 iommus = <&vdec_mmu>;
1328                 iommu_enabled = <1>;
1329                 reg = <0x0 0xff660000 0x0 0x400>;
1330                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1331                 interrupt-names = "irq_dec";
1332                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1333                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1334                 clock-names = "aclk_vcodec", "hclk_vcodec",
1335                               "clk_cabac", "clk_core";
1336                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1337                 reset-names = "video_h", "video_a";
1338                 power-domains = <&power RK3399_PD_VDU>;
1339                 dev_mode = <2>;
1340                 name = "rkvdec";
1341                 /* 0 means ion, 1 means drm */
1342                 allocator = <1>;
1343                 status = "disabled";
1344         };
1345
1346         vdec_mmu: iommu@ff660480 {
1347                 compatible = "rockchip,iommu";
1348                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1349                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1350                 interrupt-names = "vdec_mmu";
1351                 #iommu-cells = <0>;
1352         };
1353
1354         rga: rga@ff680000 {
1355                 compatible = "rockchip,rk3399-rga";
1356                 reg = <0x0 0xff680000 0x0 0x10000>;
1357                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1358                 interrupt-names = "rga";
1359                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1360                 clock-names = "aclk", "hclk", "sclk";
1361                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1362                 reset-names = "core", "axi", "ahb";
1363                 power-domains = <&power RK3399_PD_RGA>;
1364                 status = "disabled";
1365         };
1366
1367         efuse0: efuse@ff690000 {
1368                 compatible = "rockchip,rk3399-efuse";
1369                 reg = <0x0 0xff690000 0x0 0x80>;
1370                 #address-cells = <1>;
1371                 #size-cells = <1>;
1372                 clocks = <&cru PCLK_EFUSE1024NS>;
1373                 clock-names = "pclk_efuse";
1374
1375                 /* Data cells */
1376                 cpul_leakage: cpul-leakage {
1377                         reg = <0x1a 0x1>;
1378                 };
1379                 cpub_leakage: cpub-leakage {
1380                         reg = <0x17 0x1>;
1381                 };
1382                 gpu_leakage: gpu-leakage {
1383                         reg = <0x18 0x1>;
1384                 };
1385                 center_leakage: center-leakage {
1386                         reg = <0x19 0x1>;
1387                 };
1388                 logic_leakage: logic-leakage {
1389                         reg = <0x1b 0x1>;
1390                 };
1391                 wafer_info: wafer-info {
1392                         reg = <0x1c 0x1>;
1393                 };
1394         };
1395
1396         pmucru: pmu-clock-controller@ff750000 {
1397                 compatible = "rockchip,rk3399-pmucru";
1398                 reg = <0x0 0xff750000 0x0 0x1000>;
1399                 #clock-cells = <1>;
1400                 #reset-cells = <1>;
1401                 assigned-clocks = <&pmucru PLL_PPLL>;
1402                 assigned-clock-rates = <676000000>;
1403         };
1404
1405         cru: clock-controller@ff760000 {
1406                 compatible = "rockchip,rk3399-cru";
1407                 reg = <0x0 0xff760000 0x0 0x1000>;
1408                 #clock-cells = <1>;
1409                 #reset-cells = <1>;
1410                 assigned-clocks =
1411                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1412                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1413                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1414                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1415                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1416                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1417                         <&cru PCLK_PERIHP>,
1418                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1419                         <&cru PCLK_PERILP0>,
1420                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1421                 assigned-clock-rates =
1422                          <400000000>,  <200000000>,
1423                          <400000000>,  <200000000>,
1424                          <816000000>, <816000000>,
1425                          <594000000>,  <800000000>,
1426                          <200000000>, <1000000000>,
1427                          <150000000>,   <75000000>,
1428                           <37500000>,
1429                          <100000000>,  <100000000>,
1430                           <50000000>,
1431                          <100000000>,   <50000000>;
1432         };
1433
1434         grf: syscon@ff770000 {
1435                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1436                 reg = <0x0 0xff770000 0x0 0x10000>;
1437                 #address-cells = <1>;
1438                 #size-cells = <1>;
1439
1440                 io_domains: io-domains {
1441                         compatible = "rockchip,rk3399-io-voltage-domain";
1442                         status = "disabled";
1443                 };
1444
1445                 emmc_phy: phy@f780 {
1446                         compatible = "rockchip,rk3399-emmc-phy";
1447                         reg = <0xf780 0x24>;
1448                         clocks = <&sdhci>;
1449                         clock-names = "emmcclk";
1450                         #phy-cells = <0>;
1451                         status = "disabled";
1452                 };
1453
1454                 u2phy0: usb2-phy@e450 {
1455                         compatible = "rockchip,rk3399-usb2phy";
1456                         reg = <0xe450 0x10>;
1457                         clocks = <&cru SCLK_USB2PHY0_REF>;
1458                         clock-names = "phyclk";
1459                         #clock-cells = <0>;
1460                         clock-output-names = "clk_usbphy0_480m";
1461                         status = "disabled";
1462
1463                         u2phy0_otg: otg-port {
1464                                 #phy-cells = <0>;
1465                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1466                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1467                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1468                                 interrupt-names = "otg-bvalid", "otg-id",
1469                                                   "linestate";
1470                                 status = "disabled";
1471                         };
1472
1473                         u2phy0_host: host-port {
1474                                 #phy-cells = <0>;
1475                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1476                                 interrupt-names = "linestate";
1477                                 status = "disabled";
1478                         };
1479                 };
1480
1481                 u2phy1: usb2-phy@e460 {
1482                         compatible = "rockchip,rk3399-usb2phy";
1483                         reg = <0xe460 0x10>;
1484                         clocks = <&cru SCLK_USB2PHY1_REF>;
1485                         clock-names = "phyclk";
1486                         #clock-cells = <0>;
1487                         clock-output-names = "clk_usbphy1_480m";
1488                         status = "disabled";
1489
1490                         u2phy1_otg: otg-port {
1491                                 #phy-cells = <0>;
1492                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1493                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1494                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1495                                 interrupt-names = "otg-bvalid", "otg-id",
1496                                                   "linestate";
1497                                 status = "disabled";
1498                         };
1499
1500                         u2phy1_host: host-port {
1501                                 #phy-cells = <0>;
1502                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1503                                 interrupt-names = "linestate";
1504                                 status = "disabled";
1505                         };
1506                 };
1507
1508                 pvtm: pvtm {
1509                         compatible = "rockchip,rk3399-pvtm";
1510                         clocks = <&cru SCLK_PVTM_CORE_L>,
1511                                  <&cru SCLK_PVTM_CORE_B>,
1512                                  <&cru SCLK_PVTM_GPU>,
1513                                  <&cru SCLK_PVTM_DDR>;
1514                         clock-names = "core_l", "core_b", "gpu", "ddr";
1515                         status = "disabled";
1516                 };
1517         };
1518
1519         tcphy0: phy@ff7c0000 {
1520                 compatible = "rockchip,rk3399-typec-phy";
1521                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1522                 rockchip,grf = <&grf>;
1523                 #phy-cells = <1>;
1524                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1525                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1526                 clock-names = "tcpdcore", "tcpdphy-ref";
1527                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1528                 assigned-clock-rates = <50000000>;
1529                 power-domains = <&power RK3399_PD_TCPD0>;
1530                 resets = <&cru SRST_UPHY0>,
1531                          <&cru SRST_UPHY0_PIPE_L00>,
1532                          <&cru SRST_P_UPHY0_TCPHY>;
1533                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1534                 rockchip,typec-conn-dir = <0xe580 0 16>;
1535                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1536                 rockchip,usb3-host-disable = <0x2434 0 16>;
1537                 rockchip,usb3-host-port = <0x2434 12 28>;
1538                 rockchip,external-psm = <0xe588 14 30>;
1539                 rockchip,pipe-status = <0xe5c0 0 0>;
1540                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1541                 status = "disabled";
1542
1543                 tcphy0_dp: dp-port {
1544                         #phy-cells = <0>;
1545                 };
1546
1547                 tcphy0_usb3: usb3-port {
1548                         #phy-cells = <0>;
1549                 };
1550         };
1551
1552         tcphy1: phy@ff800000 {
1553                 compatible = "rockchip,rk3399-typec-phy";
1554                 reg = <0x0 0xff800000 0x0 0x40000>;
1555                 rockchip,grf = <&grf>;
1556                 #phy-cells = <1>;
1557                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1558                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1559                 clock-names = "tcpdcore", "tcpdphy-ref";
1560                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1561                 assigned-clock-rates = <50000000>;
1562                 power-domains = <&power RK3399_PD_TCPD1>;
1563                 resets = <&cru SRST_UPHY1>,
1564                          <&cru SRST_UPHY1_PIPE_L00>,
1565                          <&cru SRST_P_UPHY1_TCPHY>;
1566                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1567                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1568                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1569                 rockchip,usb3-host-disable = <0x2444 0 16>;
1570                 rockchip,usb3-host-port = <0x2444 12 28>;
1571                 rockchip,external-psm = <0xe594 14 30>;
1572                 rockchip,pipe-status = <0xe5c0 16 16>;
1573                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1574                 status = "disabled";
1575
1576                 tcphy1_dp: dp-port {
1577                         #phy-cells = <0>;
1578                 };
1579
1580                 tcphy1_usb3: usb3-port {
1581                         #phy-cells = <0>;
1582                 };
1583         };
1584
1585         watchdog@ff848000 {
1586                 compatible = "snps,dw-wdt";
1587                 reg = <0x0 0xff848000 0x0 0x100>;
1588                 clocks = <&cru PCLK_WDT>;
1589                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1590         };
1591
1592         rktimer: rktimer@ff850000 {
1593                 compatible = "rockchip,rk3399-timer";
1594                 reg = <0x0 0xff850000 0x0 0x1000>;
1595                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1596                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1597                 clock-names = "pclk", "timer";
1598         };
1599
1600         spdif: spdif@ff870000 {
1601                 compatible = "rockchip,rk3399-spdif";
1602                 reg = <0x0 0xff870000 0x0 0x1000>;
1603                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1604                 dmas = <&dmac_bus 7>;
1605                 dma-names = "tx";
1606                 clock-names = "mclk", "hclk";
1607                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1608                 pinctrl-names = "default";
1609                 pinctrl-0 = <&spdif_bus>;
1610                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1611                 status = "disabled";
1612         };
1613
1614         i2s0: i2s@ff880000 {
1615                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1616                 reg = <0x0 0xff880000 0x0 0x1000>;
1617                 rockchip,grf = <&grf>;
1618                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1619                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1620                 dma-names = "tx", "rx";
1621                 clock-names = "i2s_clk", "i2s_hclk";
1622                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1623                 pinctrl-names = "default";
1624                 pinctrl-0 = <&i2s0_8ch_bus>;
1625                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1626                 status = "disabled";
1627         };
1628
1629         i2s1: i2s@ff890000 {
1630                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1631                 reg = <0x0 0xff890000 0x0 0x1000>;
1632                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1633                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1634                 dma-names = "tx", "rx";
1635                 clock-names = "i2s_clk", "i2s_hclk";
1636                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1637                 pinctrl-names = "default";
1638                 pinctrl-0 = <&i2s1_2ch_bus>;
1639                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1640                 status = "disabled";
1641         };
1642
1643         i2s2: i2s@ff8a0000 {
1644                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1645                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1646                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1647                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1648                 dma-names = "tx", "rx";
1649                 clock-names = "i2s_clk", "i2s_hclk";
1650                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1651                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1652                 status = "disabled";
1653         };
1654
1655         gpu: gpu@ff9a0000 {
1656                 compatible = "arm,malit860",
1657                              "arm,malit86x",
1658                              "arm,malit8xx",
1659                              "arm,mali-midgard";
1660
1661                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1662
1663                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1664                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1665                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1666                 interrupt-names = "GPU", "JOB", "MMU";
1667
1668                 clocks = <&cru ACLK_GPU>;
1669                 clock-names = "clk_mali";
1670                 #cooling-cells = <2>; /* min followed by max */
1671                 power-domains = <&power RK3399_PD_GPU>;
1672                 power-off-delay-ms = <200>;
1673                 status = "disabled";
1674
1675                 gpu_power_model: power_model {
1676                         compatible = "arm,mali-simple-power-model";
1677                         voltage = <900>;
1678                         frequency = <500>;
1679                         static-power = <300>;
1680                         dynamic-power = <396>;
1681                         ts = <32000 4700 (-80) 2>;
1682                         thermal-zone = "gpu-thermal";
1683                 };
1684         };
1685
1686         vopl: vop@ff8f0000 {
1687                 compatible = "rockchip,rk3399-vop-lit";
1688                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1689                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1690                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1691                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1692                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1693                 reset-names = "axi", "ahb", "dclk";
1694                 power-domains = <&power RK3399_PD_VOPL>;
1695                 iommus = <&vopl_mmu>;
1696                 status = "disabled";
1697
1698                 vopl_out: port {
1699                         #address-cells = <1>;
1700                         #size-cells = <0>;
1701
1702                         vopl_out_mipi: endpoint@0 {
1703                                 reg = <0>;
1704                                 remote-endpoint = <&mipi_in_vopl>;
1705                         };
1706
1707                         vopl_out_edp: endpoint@1 {
1708                                 reg = <1>;
1709                                 remote-endpoint = <&edp_in_vopl>;
1710                         };
1711
1712                         vopl_out_hdmi: endpoint@2 {
1713                                 reg = <2>;
1714                                 remote-endpoint = <&hdmi_in_vopl>;
1715                         };
1716
1717                         vopl_out_dp: endpoint@3 {
1718                                 reg = <3>;
1719                                 remote-endpoint = <&dp_in_vopl>;
1720                         };
1721                 };
1722         };
1723
1724         vop1_pwm: voppwm@ff8f01a0 {
1725                 compatible = "rockchip,vop-pwm";
1726                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1727                 #pwm-cells = <3>;
1728                 pinctrl-names = "default";
1729                 pinctrl-0 = <&vop1_pwm_pin>;
1730                 clocks = <&cru SCLK_VOP1_PWM>;
1731                 clock-names = "pwm";
1732                 status = "disabled";
1733         };
1734
1735         vopl_mmu: iommu@ff8f3f00 {
1736                 compatible = "rockchip,iommu";
1737                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1738                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1739                 interrupt-names = "vopl_mmu";
1740                 #iommu-cells = <0>;
1741                 status = "disabled";
1742         };
1743
1744         vopb: vop@ff900000 {
1745                 compatible = "rockchip,rk3399-vop-big";
1746                 reg = <0x0 0xff900000 0x0 0x3efc>;
1747                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1748                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1749                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1750                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1751                 reset-names = "axi", "ahb", "dclk";
1752                 power-domains = <&power RK3399_PD_VOPB>;
1753                 iommus = <&vopb_mmu>;
1754                 status = "disabled";
1755
1756                 vopb_out: port {
1757                         #address-cells = <1>;
1758                         #size-cells = <0>;
1759
1760                         vopb_out_edp: endpoint@0 {
1761                                 reg = <0>;
1762                                 remote-endpoint = <&edp_in_vopb>;
1763                         };
1764
1765                         vopb_out_mipi: endpoint@1 {
1766                                 reg = <1>;
1767                                 remote-endpoint = <&mipi_in_vopb>;
1768                         };
1769
1770                         vopb_out_hdmi: endpoint@2 {
1771                                 reg = <2>;
1772                                 remote-endpoint = <&hdmi_in_vopb>;
1773                         };
1774
1775                         vopb_out_dp: endpoint@3 {
1776                                 reg = <3>;
1777                                 remote-endpoint = <&dp_in_vopb>;
1778                         };
1779                 };
1780         };
1781
1782         vop0_pwm: voppwm@ff9001a0 {
1783                 compatible = "rockchip,vop-pwm";
1784                 reg = <0x0 0xff9001a0 0x0 0x10>;
1785                 #pwm-cells = <3>;
1786                 pinctrl-names = "default";
1787                 pinctrl-0 = <&vop0_pwm_pin>;
1788                 clocks = <&cru SCLK_VOP0_PWM>;
1789                 clock-names = "pwm";
1790                 status = "disabled";
1791         };
1792
1793         vopb_mmu: iommu@ff903f00 {
1794                 compatible = "rockchip,iommu";
1795                 reg = <0x0 0xff903f00 0x0 0x100>;
1796                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1797                 interrupt-names = "vopb_mmu";
1798                 #iommu-cells = <0>;
1799                 status = "disabled";
1800         };
1801
1802         isp0_mmu: iommu@ff914000 {
1803                 compatible = "rockchip,iommu";
1804                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1805                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1806                 interrupt-names = "isp0_mmu";
1807                 #iommu-cells = <0>;
1808                 rk_iommu,disable_reset_quirk;
1809                 status = "disabled";
1810         };
1811
1812         isp1_mmu: iommu@ff924000 {
1813                 compatible = "rockchip,iommu";
1814                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1815                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1816                 interrupt-names = "isp1_mmu";
1817                 #iommu-cells = <0>;
1818                 rk_iommu,disable_reset_quirk;
1819                 status = "disabled";
1820         };
1821
1822         hdmi: hdmi@ff940000 {
1823                 compatible = "rockchip,rk3399-dw-hdmi";
1824                 reg = <0x0 0xff940000 0x0 0x20000>;
1825                 reg-io-width = <4>;
1826                 rockchip,grf = <&grf>;
1827                 power-domains = <&power RK3399_PD_HDCP>;
1828                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1829                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1830                 clock-names = "iahb", "isfr", "vpll", "grf";
1831                 status = "disabled";
1832
1833                 ports {
1834                         hdmi_in: port {
1835                                 #address-cells = <1>;
1836                                 #size-cells = <0>;
1837                                 hdmi_in_vopb: endpoint@0 {
1838                                         reg = <0>;
1839                                         remote-endpoint = <&vopb_out_hdmi>;
1840                                 };
1841                                 hdmi_in_vopl: endpoint@1 {
1842                                         reg = <1>;
1843                                         remote-endpoint = <&vopl_out_hdmi>;
1844                                 };
1845                         };
1846                 };
1847         };
1848
1849         mipi_dsi: mipi@ff960000 {
1850                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1851                 reg = <0x0 0xff960000 0x0 0x8000>;
1852                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1853                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1854                          <&cru SCLK_DPHY_TX0_CFG>;
1855                 clock-names = "ref", "pclk", "phy_cfg";
1856                 power-domains = <&power RK3399_PD_VIO>;
1857                 rockchip,grf = <&grf>;
1858                 #address-cells = <1>;
1859                 #size-cells = <0>;
1860                 status = "disabled";
1861
1862                 ports {
1863                         #address-cells = <1>;
1864                         #size-cells = <0>;
1865                         reg = <1>;
1866
1867                         mipi_in: port {
1868                                 #address-cells = <1>;
1869                                 #size-cells = <0>;
1870
1871                                 mipi_in_vopb: endpoint@0 {
1872                                         reg = <0>;
1873                                         remote-endpoint = <&vopb_out_mipi>;
1874                                 };
1875                                 mipi_in_vopl: endpoint@1 {
1876                                         reg = <1>;
1877                                         remote-endpoint = <&vopl_out_mipi>;
1878                                 };
1879                         };
1880                 };
1881         };
1882
1883         edp: edp@ff970000 {
1884                 compatible = "rockchip,rk3399-edp";
1885                 reg = <0x0 0xff970000 0x0 0x8000>;
1886                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1887                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1888                 clock-names = "dp", "pclk";
1889                 power-domains = <&power RK3399_PD_EDP>;
1890                 resets = <&cru SRST_P_EDP_CTRL>;
1891                 reset-names = "dp";
1892                 rockchip,grf = <&grf>;
1893                 status = "disabled";
1894                 pinctrl-names = "default";
1895                 pinctrl-0 = <&edp_hpd>;
1896
1897                 ports {
1898                         #address-cells = <1>;
1899                         #size-cells = <0>;
1900
1901                         edp_in: port@0 {
1902                                 reg = <0>;
1903                                 #address-cells = <1>;
1904                                 #size-cells = <0>;
1905
1906                                 edp_in_vopb: endpoint@0 {
1907                                         reg = <0>;
1908                                         remote-endpoint = <&vopb_out_edp>;
1909                                 };
1910
1911                                 edp_in_vopl: endpoint@1 {
1912                                         reg = <1>;
1913                                         remote-endpoint = <&vopl_out_edp>;
1914                                 };
1915                         };
1916                 };
1917         };
1918
1919         display_subsystem: display-subsystem {
1920                 compatible = "rockchip,display-subsystem";
1921                 ports = <&vopl_out>, <&vopb_out>;
1922                 status = "disabled";
1923         };
1924
1925         pinctrl: pinctrl {
1926                 compatible = "rockchip,rk3399-pinctrl";
1927                 rockchip,grf = <&grf>;
1928                 rockchip,pmu = <&pmugrf>;
1929                 #address-cells = <0x2>;
1930                 #size-cells = <0x2>;
1931                 ranges;
1932
1933                 gpio0: gpio0@ff720000 {
1934                         compatible = "rockchip,gpio-bank";
1935                         reg = <0x0 0xff720000 0x0 0x100>;
1936                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1937                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1938
1939                         gpio-controller;
1940                         #gpio-cells = <0x2>;
1941
1942                         interrupt-controller;
1943                         #interrupt-cells = <0x2>;
1944                 };
1945
1946                 gpio1: gpio1@ff730000 {
1947                         compatible = "rockchip,gpio-bank";
1948                         reg = <0x0 0xff730000 0x0 0x100>;
1949                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1950                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1951
1952                         gpio-controller;
1953                         #gpio-cells = <0x2>;
1954
1955                         interrupt-controller;
1956                         #interrupt-cells = <0x2>;
1957                 };
1958
1959                 gpio2: gpio2@ff780000 {
1960                         compatible = "rockchip,gpio-bank";
1961                         reg = <0x0 0xff780000 0x0 0x100>;
1962                         clocks = <&cru PCLK_GPIO2>;
1963                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1964
1965                         gpio-controller;
1966                         #gpio-cells = <0x2>;
1967
1968                         interrupt-controller;
1969                         #interrupt-cells = <0x2>;
1970                 };
1971
1972                 gpio3: gpio3@ff788000 {
1973                         compatible = "rockchip,gpio-bank";
1974                         reg = <0x0 0xff788000 0x0 0x100>;
1975                         clocks = <&cru PCLK_GPIO3>;
1976                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1977
1978                         gpio-controller;
1979                         #gpio-cells = <0x2>;
1980
1981                         interrupt-controller;
1982                         #interrupt-cells = <0x2>;
1983                 };
1984
1985                 gpio4: gpio4@ff790000 {
1986                         compatible = "rockchip,gpio-bank";
1987                         reg = <0x0 0xff790000 0x0 0x100>;
1988                         clocks = <&cru PCLK_GPIO4>;
1989                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1990
1991                         gpio-controller;
1992                         #gpio-cells = <0x2>;
1993
1994                         interrupt-controller;
1995                         #interrupt-cells = <0x2>;
1996                 };
1997
1998                 pcfg_pull_up: pcfg-pull-up {
1999                         bias-pull-up;
2000                 };
2001
2002                 pcfg_pull_down: pcfg-pull-down {
2003                         bias-pull-down;
2004                 };
2005
2006                 pcfg_pull_none: pcfg-pull-none {
2007                         bias-disable;
2008                 };
2009
2010                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2011                         bias-pull-up;
2012                         drive-strength = <20>;
2013                 };
2014
2015                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2016                         bias-disable;
2017                         drive-strength = <20>;
2018                 };
2019
2020                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2021                         bias-disable;
2022                         drive-strength = <18>;
2023                 };
2024
2025                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2026                         bias-disable;
2027                         drive-strength = <12>;
2028                 };
2029
2030                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2031                         bias-pull-up;
2032                         drive-strength = <8>;
2033                 };
2034
2035                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2036                         bias-pull-down;
2037                         drive-strength = <4>;
2038                 };
2039
2040                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2041                         bias-pull-up;
2042                         drive-strength = <2>;
2043                 };
2044
2045                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2046                         bias-pull-down;
2047                         drive-strength = <12>;
2048                 };
2049
2050                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2051                         bias-disable;
2052                         drive-strength = <13>;
2053                 };
2054
2055                 pcfg_output_high: pcfg-output-high {
2056                         output-high;
2057                 };
2058
2059                 pcfg_output_low: pcfg-output-low {
2060                         output-low;
2061                 };
2062
2063                 pcfg_input: pcfg-input {
2064                         input-enable;
2065                 };
2066
2067                 emmc {
2068                         emmc_pwr: emmc-pwr {
2069                                 rockchip,pins =
2070                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2071                         };
2072                 };
2073
2074                 gmac {
2075                         rgmii_pins: rgmii-pins {
2076                                 rockchip,pins =
2077                                         /* mac_txclk */
2078                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2079                                         /* mac_rxclk */
2080                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2081                                         /* mac_mdio */
2082                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2083                                         /* mac_txen */
2084                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2085                                         /* mac_clk */
2086                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2087                                         /* mac_rxdv */
2088                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2089                                         /* mac_mdc */
2090                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2091                                         /* mac_rxd1 */
2092                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2093                                         /* mac_rxd0 */
2094                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2095                                         /* mac_txd1 */
2096                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2097                                         /* mac_txd0 */
2098                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2099                                         /* mac_rxd3 */
2100                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2101                                         /* mac_rxd2 */
2102                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2103                                         /* mac_txd3 */
2104                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2105                                         /* mac_txd2 */
2106                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2107                         };
2108
2109                         rmii_pins: rmii-pins {
2110                                 rockchip,pins =
2111                                         /* mac_mdio */
2112                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2113                                         /* mac_txen */
2114                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2115                                         /* mac_clk */
2116                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2117                                         /* mac_rxer */
2118                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2119                                         /* mac_rxdv */
2120                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2121                                         /* mac_mdc */
2122                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2123                                         /* mac_rxd1 */
2124                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2125                                         /* mac_rxd0 */
2126                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2127                                         /* mac_txd1 */
2128                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2129                                         /* mac_txd0 */
2130                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2131                         };
2132                 };
2133
2134                 i2c0 {
2135                         i2c0_xfer: i2c0-xfer {
2136                                 rockchip,pins =
2137                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2138                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2139                         };
2140                 };
2141
2142                 i2c1 {
2143                         i2c1_xfer: i2c1-xfer {
2144                                 rockchip,pins =
2145                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2146                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2147                         };
2148                 };
2149
2150                 i2c2 {
2151                         i2c2_xfer: i2c2-xfer {
2152                                 rockchip,pins =
2153                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2154                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2155                         };
2156                 };
2157
2158                 i2c3 {
2159                         i2c3_xfer: i2c3-xfer {
2160                                 rockchip,pins =
2161                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2162                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2163                         };
2164
2165                         i2c3_gpio: i2c3_gpio {
2166                                 rockchip,pins =
2167                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2168                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2169                         };
2170
2171                 };
2172
2173                 i2c4 {
2174                         i2c4_xfer: i2c4-xfer {
2175                                 rockchip,pins =
2176                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2177                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2178                         };
2179                 };
2180
2181                 i2c5 {
2182                         i2c5_xfer: i2c5-xfer {
2183                                 rockchip,pins =
2184                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2185                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2186                         };
2187                 };
2188
2189                 i2c6 {
2190                         i2c6_xfer: i2c6-xfer {
2191                                 rockchip,pins =
2192                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2193                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2194                         };
2195                 };
2196
2197                 i2c7 {
2198                         i2c7_xfer: i2c7-xfer {
2199                                 rockchip,pins =
2200                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2201                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2202                         };
2203                 };
2204
2205                 i2c8 {
2206                         i2c8_xfer: i2c8-xfer {
2207                                 rockchip,pins =
2208                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2209                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2210                         };
2211                 };
2212
2213                 i2s0 {
2214                         i2s0_8ch_bus: i2s0-8ch-bus {
2215                                 rockchip,pins =
2216                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2217                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2218                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2219                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2220                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2221                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2222                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2223                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2224                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2225                         };
2226                 };
2227
2228                 i2s1 {
2229                         i2s1_2ch_bus: i2s1-2ch-bus {
2230                                 rockchip,pins =
2231                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2232                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2233                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2234                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2235                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2236                         };
2237                 };
2238
2239                 sdio0 {
2240                         sdio0_bus1: sdio0-bus1 {
2241                                 rockchip,pins =
2242                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2243                         };
2244
2245                         sdio0_bus4: sdio0-bus4 {
2246                                 rockchip,pins =
2247                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2248                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2249                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2250                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2251                         };
2252
2253                         sdio0_cmd: sdio0-cmd {
2254                                 rockchip,pins =
2255                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2256                         };
2257
2258                         sdio0_clk: sdio0-clk {
2259                                 rockchip,pins =
2260                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2261                         };
2262
2263                         sdio0_cd: sdio0-cd {
2264                                 rockchip,pins =
2265                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2266                         };
2267
2268                         sdio0_pwr: sdio0-pwr {
2269                                 rockchip,pins =
2270                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2271                         };
2272
2273                         sdio0_bkpwr: sdio0-bkpwr {
2274                                 rockchip,pins =
2275                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2276                         };
2277
2278                         sdio0_wp: sdio0-wp {
2279                                 rockchip,pins =
2280                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2281                         };
2282
2283                         sdio0_int: sdio0-int {
2284                                 rockchip,pins =
2285                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2286                         };
2287                 };
2288
2289                 sdmmc {
2290                         sdmmc_bus1: sdmmc-bus1 {
2291                                 rockchip,pins =
2292                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2293                         };
2294
2295                         sdmmc_bus4: sdmmc-bus4 {
2296                                 rockchip,pins =
2297                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2298                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2299                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2300                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2301                         };
2302
2303                         sdmmc_clk: sdmmc-clk {
2304                                 rockchip,pins =
2305                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2306                         };
2307
2308                         sdmmc_cmd: sdmmc-cmd {
2309                                 rockchip,pins =
2310                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2311                         };
2312
2313                         sdmmc_cd: sdmcc-cd {
2314                                 rockchip,pins =
2315                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2316                         };
2317
2318                         sdmmc_wp: sdmmc-wp {
2319                                 rockchip,pins =
2320                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2321                         };
2322                 };
2323
2324                 spdif {
2325                         spdif_bus: spdif-bus {
2326                                 rockchip,pins =
2327                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2328                         };
2329
2330                         spdif_bus_1: spdif-bus-1 {
2331                                 rockchip,pins =
2332                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2333                         };
2334                 };
2335
2336                 spi0 {
2337                         spi0_clk: spi0-clk {
2338                                 rockchip,pins =
2339                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2340                         };
2341                         spi0_cs0: spi0-cs0 {
2342                                 rockchip,pins =
2343                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2344                         };
2345                         spi0_cs1: spi0-cs1 {
2346                                 rockchip,pins =
2347                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2348                         };
2349                         spi0_tx: spi0-tx {
2350                                 rockchip,pins =
2351                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2352                         };
2353                         spi0_rx: spi0-rx {
2354                                 rockchip,pins =
2355                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2356                         };
2357                 };
2358
2359                 spi1 {
2360                         spi1_clk: spi1-clk {
2361                                 rockchip,pins =
2362                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2363                         };
2364                         spi1_cs0: spi1-cs0 {
2365                                 rockchip,pins =
2366                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2367                         };
2368                         spi1_rx: spi1-rx {
2369                                 rockchip,pins =
2370                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2371                         };
2372                         spi1_tx: spi1-tx {
2373                                 rockchip,pins =
2374                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2375                         };
2376                 };
2377
2378                 spi2 {
2379                         spi2_clk: spi2-clk {
2380                                 rockchip,pins =
2381                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2382                         };
2383                         spi2_cs0: spi2-cs0 {
2384                                 rockchip,pins =
2385                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2386                         };
2387                         spi2_rx: spi2-rx {
2388                                 rockchip,pins =
2389                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2390                         };
2391                         spi2_tx: spi2-tx {
2392                                 rockchip,pins =
2393                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2394                         };
2395                 };
2396
2397                 spi3 {
2398                         spi3_clk: spi3-clk {
2399                                 rockchip,pins =
2400                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2401                         };
2402                         spi3_cs0: spi3-cs0 {
2403                                 rockchip,pins =
2404                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2405                         };
2406                         spi3_rx: spi3-rx {
2407                                 rockchip,pins =
2408                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2409                         };
2410                         spi3_tx: spi3-tx {
2411                                 rockchip,pins =
2412                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2413                         };
2414                 };
2415
2416                 spi4 {
2417                         spi4_clk: spi4-clk {
2418                                 rockchip,pins =
2419                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2420                         };
2421                         spi4_cs0: spi4-cs0 {
2422                                 rockchip,pins =
2423                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2424                         };
2425                         spi4_rx: spi4-rx {
2426                                 rockchip,pins =
2427                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2428                         };
2429                         spi4_tx: spi4-tx {
2430                                 rockchip,pins =
2431                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2432                         };
2433                 };
2434
2435                 spi5 {
2436                         spi5_clk: spi5-clk {
2437                                 rockchip,pins =
2438                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2439                         };
2440                         spi5_cs0: spi5-cs0 {
2441                                 rockchip,pins =
2442                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2443                         };
2444                         spi5_rx: spi5-rx {
2445                                 rockchip,pins =
2446                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2447                         };
2448                         spi5_tx: spi5-tx {
2449                                 rockchip,pins =
2450                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2451                         };
2452                 };
2453
2454                 tsadc {
2455                         otp_gpio: otp-gpio {
2456                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2457                         };
2458
2459                         otp_out: otp-out {
2460                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2461                         };
2462                 };
2463
2464                 uart0 {
2465                         uart0_xfer: uart0-xfer {
2466                                 rockchip,pins =
2467                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2468                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2469                         };
2470
2471                         uart0_cts: uart0-cts {
2472                                 rockchip,pins =
2473                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2474                         };
2475
2476                         uart0_rts: uart0-rts {
2477                                 rockchip,pins =
2478                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2479                         };
2480                 };
2481
2482                 uart1 {
2483                         uart1_xfer: uart1-xfer {
2484                                 rockchip,pins =
2485                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2486                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2487                         };
2488                 };
2489
2490                 uart2a {
2491                         uart2a_xfer: uart2a-xfer {
2492                                 rockchip,pins =
2493                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2494                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2495                         };
2496                 };
2497
2498                 uart2b {
2499                         uart2b_xfer: uart2b-xfer {
2500                                 rockchip,pins =
2501                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2502                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2503                         };
2504                 };
2505
2506                 uart2c {
2507                         uart2c_xfer: uart2c-xfer {
2508                                 rockchip,pins =
2509                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2510                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2511                         };
2512                 };
2513
2514                 uart3 {
2515                         uart3_xfer: uart3-xfer {
2516                                 rockchip,pins =
2517                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2518                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2519                         };
2520
2521                         uart3_cts: uart3-cts {
2522                                 rockchip,pins =
2523                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2524                         };
2525
2526                         uart3_rts: uart3-rts {
2527                                 rockchip,pins =
2528                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2529                         };
2530                 };
2531
2532                 uart4 {
2533                         uart4_xfer: uart4-xfer {
2534                                 rockchip,pins =
2535                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2536                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2537                         };
2538                 };
2539
2540                 uarthdcp {
2541                         uarthdcp_xfer: uarthdcp-xfer {
2542                                 rockchip,pins =
2543                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2544                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2545                         };
2546                 };
2547
2548                 pwm0 {
2549                         pwm0_pin: pwm0-pin {
2550                                 rockchip,pins =
2551                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2552                         };
2553
2554                         vop0_pwm_pin: vop0-pwm-pin {
2555                                 rockchip,pins =
2556                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2557                         };
2558                 };
2559
2560                 pwm1 {
2561                         pwm1_pin: pwm1-pin {
2562                                 rockchip,pins =
2563                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2564                         };
2565
2566                         vop1_pwm_pin: vop1-pwm-pin {
2567                                 rockchip,pins =
2568                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2569                         };
2570                 };
2571
2572                 pwm2 {
2573                         pwm2_pin: pwm2-pin {
2574                                 rockchip,pins =
2575                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2576                         };
2577                 };
2578
2579                 pwm3a {
2580                         pwm3a_pin: pwm3a-pin {
2581                                 rockchip,pins =
2582                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2583                         };
2584                 };
2585
2586                 pwm3b {
2587                         pwm3b_pin: pwm3b-pin {
2588                                 rockchip,pins =
2589                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2590                         };
2591                 };
2592
2593                 edp {
2594                         edp_hpd: edp-hpd {
2595                                 rockchip,pins =
2596                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2597                         };
2598                 };
2599
2600                 hdmi {
2601                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2602                                 rockchip,pins =
2603                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2604                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2605                         };
2606
2607                         hdmi_cec: hdmi-cec {
2608                                 rockchip,pins =
2609                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2610                         };
2611                 };
2612
2613                 pcie {
2614                         pcie_clkreqn: pci-clkreqn {
2615                                 rockchip,pins =
2616                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2617                         };
2618
2619                         pcie_clkreqnb: pci-clkreqnb {
2620                                 rockchip,pins =
2621                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2622                         };
2623
2624                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2625                                 /*
2626                                  * Since our pcie doesn't support
2627                                  * ClockPM(CPM), we want to hack this as
2628                                  * gpio, so the EP could be able to
2629                                  * de-assert it along and make ClockPM(CPM)
2630                                  * work.
2631                                  */
2632                                 rockchip,pins =
2633                                         <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2634                         };
2635
2636                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2637                                 rockchip,pins =
2638                                         <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2639                         };
2640                 };
2641         };
2642 };