arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <900000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <900000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <900000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <900000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <900000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <900000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <900000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <900000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         arm-pmu {
 225                 compatible = "arm,armv8-pmuv3";
 226                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 227         };
 228
 229         xin24m: xin24m {
 230                 compatible = "fixed-clock";
 231                 #clock-cells = <0>;
 232                 clock-frequency = <24000000>;
 233                 clock-output-names = "xin24m";
 234         };
 235
 236         amba {
 237                 compatible = "arm,amba-bus";
 238                 #address-cells = <2>;
 239                 #size-cells = <2>;
 240                 ranges;
 241
 242                 dmac_bus: dma-controller@ff6d0000 {
 243                         compatible = "arm,pl330", "arm,primecell";
 244                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 245                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 247                         #dma-cells = <1>;
 248                         clocks = <&cru ACLK_DMAC0_PERILP>;
 249                         clock-names = "apb_pclk";
 250                 };
 251
 252                 dmac_peri: dma-controller@ff6e0000 {
 253                         compatible = "arm,pl330", "arm,primecell";
 254                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 255                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 257                         #dma-cells = <1>;
 258                         clocks = <&cru ACLK_DMAC1_PERILP>;
 259                         clock-names = "apb_pclk";
 260                 };
 261         };
 262
 263         gmac: eth@fe300000 {
 264                 compatible = "rockchip,rk3399-gmac";
 265                 reg = <0x0 0xfe300000 0x0 0x10000>;
 266                 rockchip,grf = <&grf>;
 267                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 268                 interrupt-names = "macirq";
 269                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 270                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 271                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 272                          <&cru PCLK_GMAC>;
 273                 clock-names = "stmmaceth", "mac_clk_rx",
 274                               "mac_clk_tx", "clk_mac_ref",
 275                               "clk_mac_refout", "aclk_mac",
 276                               "pclk_mac";
 277                 resets = <&cru SRST_A_GMAC>;
 278                 reset-names = "stmmaceth";
 279                 status = "disabled";
 280         };
 281
 282         emmc_phy: phy {
 283                 compatible = "rockchip,rk3399-emmc-phy";
 284                 reg-offset = <0xf780>;
 285                 #phy-cells = <0>;
 286                 rockchip,grf = <&grf>;
 287                 status = "disabled";
 288         };
 289
 290         sdio0: dwmmc@fe310000 {
 291                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 292                 reg = <0x0 0xfe310000 0x0 0x4000>;
 293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 294                 clock-freq-min-max = <400000 150000000>;
 295                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 296                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 status = "disabled";
 300         };
 301
 302         sdmmc: dwmmc@fe320000 {
 303                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 304                 reg = <0x0 0xfe320000 0x0 0x4000>;
 305                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 306                 clock-freq-min-max = <400000 150000000>;
 307                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 308                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 309                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 310                 fifo-depth = <0x100>;
 311                 status = "disabled";
 312         };
 313
 314         sdhci: sdhci@fe330000 {
 315                 compatible = "arasan,sdhci-5.1";
 316                 reg = <0x0 0xfe330000 0x0 0x10000>;
 317                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 319                 clock-names = "clk_xin", "clk_ahb";
 320                 phys = <&emmc_phy>;
 321                 phy-names = "phy_arasan";
 322                 status = "disabled";
 323         };
 324
 325         usb2phy: usb2phy {
 326                 compatible = "rockchip,rk3399-usb-phy";
 327                 rockchip,grf = <&grf>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330
 331                 usb2phy0: usb2-phy0 {
 332                         #phy-cells = <0>;
 333                         #clock-cells = <0>;
 334                         reg = <0xe458>;
 335                 };
 336
 337                 usb2phy1: usb2-phy1 {
 338                         #phy-cells = <0>;
 339                         #clock-cells = <0>;
 340                         reg = <0xe468>;
 341                 };
 342         };
 343
 344         usb_host0_echi: usb@fe380000 {
 345                 compatible = "generic-ehci";
 346                 reg = <0x0 0xfe380000 0x0 0x20000>;
 347                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 349                 clock-names = "hclk_host0", "hclk_host0_arb";
 350                 phys = <&usb2phy0>;
 351                 phy-names = "usb2_phy0";
 352                 status = "disabled";
 353         };
 354
 355         usb_host0_ohci: usb@fe3a0000 {
 356                 compatible = "generic-ohci";
 357                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 358                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 360                 clock-names = "hclk_host0", "hclk_host0_arb";
 361                 status = "disabled";
 362         };
 363
 364         usb_host1_echi: usb@fe3c0000 {
 365                 compatible = "generic-ehci";
 366                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 367                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 369                 clock-names = "hclk_host1", "hclk_host1_arb";
 370                 phys = <&usb2phy1>;
 371                 phy-names = "usb2_phy1";
 372                 status = "disabled";
 373         };
 374
 375         usb_host1_ohci: usb@fe3e0000 {
 376                 compatible = "generic-ohci";
 377                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 378                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 380                 clock-names = "hclk_host1", "hclk_host1_arb";
 381                 status = "disabled";
 382         };
 383
 384         usbdrd3_0: usb@fe800000 {
 385                 compatible = "rockchip,dwc3";
 386                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 387                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 388                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 389                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 390                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 391                               "aclk_usb3", "aclk_usb3_grf";
 392                 #address-cells = <2>;
 393                 #size-cells = <2>;
 394                 ranges;
 395                 status = "disabled";
 396                 usbdrd_dwc3_0: dwc3 {
 397                         compatible = "snps,dwc3";
 398                         reg = <0x0 0xfe800000 0x0 0x100000>;
 399                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 400                         dr_mode = "otg";
 401                         tx-fifo-resize;
 402                         snps,dis_enblslpm_quirk;
 403                         snps,phyif_utmi_16_bits;
 404                         snps,dis_u2_freeclk_exists_quirk;
 405                         snps,dis_del_phy_power_chg_quirk;
 406                         status = "disabled";
 407                 };
 408         };
 409
 410         usbdrd3_1: usb@fe900000 {
 411                 compatible = "rockchip,dwc3";
 412                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 413                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 414                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 415                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 416                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 417                               "aclk_usb3", "aclk_usb3_grf";
 418                 #address-cells = <2>;
 419                 #size-cells = <2>;
 420                 ranges;
 421                 status = "disabled";
 422                 usbdrd_dwc3_1: dwc3 {
 423                         compatible = "snps,dwc3";
 424                         reg = <0x0 0xfe900000 0x0 0x100000>;
 425                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 426                         dr_mode = "otg";
 427                         tx-fifo-resize;
 428                         snps,dis_enblslpm_quirk;
 429                         snps,phyif_utmi_16_bits;
 430                         snps,dis_u2_freeclk_exists_quirk;
 431                         snps,dis_del_phy_power_chg_quirk;
 432                         status = "disabled";
 433                 };
 434         };
 435
 436         gic: interrupt-controller@fee00000 {
 437                 compatible = "arm,gic-v3";
 438                 #interrupt-cells = <3>;
 439                 #address-cells = <2>;
 440                 #size-cells = <2>;
 441                 ranges;
 442                 interrupt-controller;
 443
 444                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 445                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 446                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 447                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 448                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 449                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 450                 its: interrupt-controller@fee20000 {
 451                         compatible = "arm,gic-v3-its";
 452                         msi-controller;
 453                         reg = <0x0 0xfee20000 0x0 0x20000>;
 454                 };
 455         };
 456
 457         saradc: saradc@ff100000 {
 458                 compatible = "rockchip,rk3399-saradc";
 459                 reg = <0x0 0xff100000 0x0 0x100>;
 460                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 461                 #io-channel-cells = <1>;
 462                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 463                 clock-names = "saradc", "apb_pclk";
 464                 status = "disabled";
 465         };
 466
 467         i2c0: i2c@ff3c0000 {
 468                 compatible = "rockchip,rk3399-i2c";
 469                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 470                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 471                 clock-names = "i2c", "pclk";
 472                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&i2c0_xfer>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 status = "disabled";
 478         };
 479
 480         i2c1: i2c@ff110000 {
 481                 compatible = "rockchip,rk3399-i2c";
 482                 reg = <0x0 0xff110000 0x0 0x1000>;
 483                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 484                 clock-names = "i2c", "pclk";
 485                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&i2c1_xfer>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 status = "disabled";
 491         };
 492
 493         i2c2: i2c@ff120000 {
 494                 compatible = "rockchip,rk3399-i2c";
 495                 reg = <0x0 0xff120000 0x0 0x1000>;
 496                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 497                 clock-names = "i2c", "pclk";
 498                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c2_xfer>;
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 status = "disabled";
 504         };
 505
 506         i2c3: i2c@ff130000 {
 507                 compatible = "rockchip,rk3399-i2c";
 508                 reg = <0x0 0xff130000 0x0 0x1000>;
 509                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 510                 clock-names = "i2c", "pclk";
 511                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c3_xfer>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 status = "disabled";
 517         };
 518
 519         i2c5: i2c@ff140000 {
 520                 compatible = "rockchip,rk3399-i2c";
 521                 reg = <0x0 0xff140000 0x0 0x1000>;
 522                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 523                 clock-names = "i2c", "pclk";
 524                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&i2c5_xfer>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 status = "disabled";
 530         };
 531
 532         i2c6: i2c@ff150000 {
 533                 compatible = "rockchip,rk3399-i2c";
 534                 reg = <0x0 0xff150000 0x0 0x1000>;
 535                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 536                 clock-names = "i2c", "pclk";
 537                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2c6_xfer>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         i2c7: i2c@ff160000 {
 546                 compatible = "rockchip,rk3399-i2c";
 547                 reg = <0x0 0xff160000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 549                 clock-names = "i2c", "pclk";
 550                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c7_xfer>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         uart0: serial@ff180000 {
 559                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 560                 reg = <0x0 0xff180000 0x0 0x100>;
 561                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 562                 clock-names = "baudclk", "apb_pclk";
 563                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 564                 reg-shift = <2>;
 565                 reg-io-width = <4>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 568                 status = "disabled";
 569         };
 570
 571         uart1: serial@ff190000 {
 572                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 573                 reg = <0x0 0xff190000 0x0 0x100>;
 574                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 575                 clock-names = "baudclk", "apb_pclk";
 576                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 577                 reg-shift = <2>;
 578                 reg-io-width = <4>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&uart1_xfer>;
 581                 status = "disabled";
 582         };
 583
 584         uart2: serial@ff1a0000 {
 585                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 586                 reg = <0x0 0xff1a0000 0x0 0x100>;
 587                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 588                 clock-names = "baudclk", "apb_pclk";
 589                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 590                 reg-shift = <2>;
 591                 reg-io-width = <4>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&uart2c_xfer>;
 594                 status = "disabled";
 595         };
 596
 597         uart3: serial@ff1b0000 {
 598                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 599                 reg = <0x0 0xff1b0000 0x0 0x100>;
 600                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 601                 clock-names = "baudclk", "apb_pclk";
 602                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 603                 reg-shift = <2>;
 604                 reg-io-width = <4>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 607                 status = "disabled";
 608         };
 609
 610         spi0: spi@ff1c0000 {
 611                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 612                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 613                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 614                 clock-names = "spiclk", "apb_pclk";
 615                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 status = "disabled";
 621         };
 622
 623         spi1: spi@ff1d0000 {
 624                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 625                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 626                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 627                 clock-names = "spiclk", "apb_pclk";
 628                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 629                 pinctrl-names = "default";
 630                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 status = "disabled";
 634         };
 635
 636         spi2: spi@ff1e0000 {
 637                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 638                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 639                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 640                 clock-names = "spiclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         spi4: spi@ff1f0000 {
 650                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 651                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 652                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 653                 clock-names = "spiclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 status = "disabled";
 660         };
 661
 662         spi5: spi@ff200000 {
 663                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 664                 reg = <0x0 0xff200000 0x0 0x1000>;
 665                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 666                 clock-names = "spiclk", "apb_pclk";
 667                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 status = "disabled";
 673         };
 674
 675         thermal-zones {
 676                 #include "rk3368-thermal.dtsi"
 677         };
 678
 679         tsadc: tsadc@ff260000 {
 680                 compatible = "rockchip,rk3399-tsadc";
 681                 reg = <0x0 0xff260000 0x0 0x100>;
 682                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 683                 rockchip,grf = <&grf>;
 684                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 685                 clock-names = "tsadc", "apb_pclk";
 686                 assigned-clocks = <&cru SCLK_TSADC>;
 687                 assigned-clock-rates = <750000>;
 688                 resets = <&cru SRST_TSADC>;
 689                 reset-names = "tsadc-apb";
 690                 pinctrl-names = "init", "default", "sleep";
 691                 pinctrl-0 = <&otp_gpio>;
 692                 pinctrl-1 = <&otp_out>;
 693                 pinctrl-2 = <&otp_gpio>;
 694                 #thermal-sensor-cells = <1>;
 695                 rockchip,hw-tshut-temp = <95000>;
 696                 status = "disabled";
 697         };
 698
 699         pmu: power-management@ff31000 {
 700                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 701                 reg = <0x0 0xff310000 0x0 0x1000>;
 702
 703                 power: power-controller {
 704                         status = "disabled";
 705                         compatible = "rockchip,rk3399-power-controller";
 706                         #power-domain-cells = <1>;
 707                         #address-cells = <1>;
 708                         #size-cells = <0>;
 709
 710                         pd_center {
 711                                 reg = <RK3399_PD_CENTER>;
 712                                 #address-cells = <1>;
 713                                 #size-cells = <0>;
 714
 715                                 pd_vdu {
 716                                         reg = <RK3399_PD_VDU>;
 717                                 };
 718                                 pd_vcodec {
 719                                         reg = <RK3399_PD_VCODEC>;
 720                                 };
 721                                 pd_iep {
 722                                         reg = <RK3399_PD_IEP>;
 723                                 };
 724                                 pd_rga {
 725                                         reg = <RK3399_PD_RGA>;
 726                                 };
 727                         };
 728                         pd_vio {
 729                                 reg = <RK3399_PD_VIO>;
 730                                 #address-cells = <1>;
 731                                 #size-cells = <0>;
 732
 733                                 pd_isp0 {
 734                                         reg = <RK3399_PD_ISP0>;
 735                                 };
 736                                 pd_isp1 {
 737                                         reg = <RK3399_PD_ISP1>;
 738                                 };
 739                                 pd_hdcp {
 740                                         reg = <RK3399_PD_HDCP>;
 741                                 };
 742                                 pd_vo {
 743                                         reg = <RK3399_PD_VO>;
 744                                         #address-cells = <1>;
 745                                         #size-cells = <0>;
 746
 747                                         pd_vopb {
 748                                                 reg = <RK3399_PD_VOPB>;
 749                                         };
 750                                         pd_vopl {
 751                                                 reg = <RK3399_PD_VOPL>;
 752                                         };
 753                                 };
 754                         };
 755                         pd_gpu {
 756                                 reg = <RK3399_PD_GPU>;
 757                         };
 758                 };
 759         };
 760
 761         pmugrf: syscon@ff320000 {
 762                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 763                 reg = <0x0 0xff320000 0x0 0x1000>;
 764         };
 765
 766         spi3: spi@ff350000 {
 767                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 768                 reg = <0x0 0xff350000 0x0 0x1000>;
 769                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 770                 clock-names = "spiclk", "apb_pclk";
 771                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 772                 pinctrl-names = "default";
 773                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 774                 #address-cells = <1>;
 775                 #size-cells = <0>;
 776                 status = "disabled";
 777         };
 778
 779         uart4: serial@ff370000 {
 780                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 781                 reg = <0x0 0xff370000 0x0 0x100>;
 782                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 783                 clock-names = "baudclk", "apb_pclk";
 784                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 785                 reg-shift = <2>;
 786                 reg-io-width = <4>;
 787                 pinctrl-names = "default";
 788                 pinctrl-0 = <&uart4_xfer>;
 789                 status = "disabled";
 790         };
 791
 792         i2c4: i2c@ff3d0000 {
 793                 compatible = "rockchip,rk3399-i2c";
 794                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 795                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 796                 clock-names = "i2c", "pclk";
 797                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 798                 pinctrl-names = "default";
 799                 pinctrl-0 = <&i2c4_xfer>;
 800                 #address-cells = <1>;
 801                 #size-cells = <0>;
 802                 status = "disabled";
 803         };
 804
 805         i2c8: i2c@ff3e0000 {
 806                 compatible = "rockchip,rk3399-i2c";
 807                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 808                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 809                 clock-names = "i2c", "pclk";
 810                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 811                 pinctrl-names = "default";
 812                 pinctrl-0 = <&i2c8_xfer>;
 813                 #address-cells = <1>;
 814                 #size-cells = <0>;
 815                 status = "disabled";
 816         };
 817
 818         pwm0: pwm@ff420000 {
 819                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 820                 reg = <0x0 0xff420000 0x0 0x10>;
 821                 #pwm-cells = <3>;
 822                 pinctrl-names = "default";
 823                 pinctrl-0 = <&pwm0_pin>;
 824                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 825                 clock-names = "pwm";
 826                 status = "disabled";
 827         };
 828
 829         pwm1: pwm@ff420010 {
 830                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 831                 reg = <0x0 0xff420010 0x0 0x10>;
 832                 #pwm-cells = <3>;
 833                 pinctrl-names = "default";
 834                 pinctrl-0 = <&pwm1_pin>;
 835                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 836                 clock-names = "pwm";
 837                 status = "disabled";
 838         };
 839
 840         pwm2: pwm@ff420020 {
 841                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 842                 reg = <0x0 0xff420020 0x0 0x10>;
 843                 #pwm-cells = <3>;
 844                 pinctrl-names = "default";
 845                 pinctrl-0 = <&pwm2_pin>;
 846                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 847                 clock-names = "pwm";
 848                 status = "disabled";
 849         };
 850
 851         pwm3: pwm@ff420030 {
 852                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 853                 reg = <0x0 0xff420030 0x0 0x10>;
 854                 #pwm-cells = <3>;
 855                 pinctrl-names = "default";
 856                 pinctrl-0 = <&pwm3a_pin>;
 857                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 858                 clock-names = "pwm";
 859                 status = "disabled";
 860         };
 861
 862         pmucru: pmu-clock-controller@ff750000 {
 863                 compatible = "rockchip,rk3399-pmucru";
 864                 reg = <0x0 0xff750000 0x0 0x1000>;
 865                 #clock-cells = <1>;
 866                 #reset-cells = <1>;
 867                 assigned-clocks = <&pmucru PLL_PPLL>;
 868                 assigned-clock-rates = <676000000>;
 869         };
 870
 871         cru: clock-controller@ff760000 {
 872                 compatible = "rockchip,rk3399-cru";
 873                 reg = <0x0 0xff760000 0x0 0x1000>;
 874                 #clock-cells = <1>;
 875                 #reset-cells = <1>;
 876                 assigned-clocks =
 877                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
 878                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
 879                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 880                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 881                         <&cru PLL_NPLL>,
 882                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 883                         <&cru PCLK_PERIHP>,
 884                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 885                         <&cru PCLK_PERILP0>,
 886                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 887                 assigned-clock-rates =
 888                          <400000000>,  <200000000>,
 889                          <400000000>,  <200000000>,
 890                          <816000000>, <1008000000>,
 891                          <594000000>,  <800000000>,
 892                         <1000000000>,
 893                          <150000000>,   <75000000>,
 894                           <37500000>,
 895                          <100000000>,  <100000000>,
 896                           <50000000>,
 897                          <100000000>,   <50000000>;
 898         };
 899
 900         grf: syscon@ff770000 {
 901                 compatible = "rockchip,rk3399-grf", "syscon";
 902                 reg = <0x0 0xff770000 0x0 0x10000>;
 903         };
 904
 905         wdt0: watchdog@ff840000 {
 906                 compatible = "snps,dw-wdt";
 907                 reg = <0x0 0xff840000 0x0 0x100>;
 908                 clocks = <&cru PCLK_WDT>;
 909                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 910                 status = "disabled";
 911         };
 912
 913         spdif: spdif@ff870000 {
 914                 compatible = "rockchip,rk3399-spdif";
 915                 reg = <0x0 0xff870000 0x0 0x1000>;
 916                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 917                 dmas = <&dmac_bus 7>;
 918                 dma-names = "tx";
 919                 clock-names = "mclk", "hclk";
 920                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 921                 pinctrl-names = "default";
 922                 pinctrl-0 = <&spdif_bus>;
 923                 status = "disabled";
 924         };
 925
 926         i2s0: i2s@ff880000 {
 927                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 928                 reg = <0x0 0xff880000 0x0 0x1000>;
 929                 rockchip,grf = <&grf>;
 930                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 931                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 932                 dma-names = "tx", "rx";
 933                 clock-names = "i2s_clk", "i2s_hclk";
 934                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 935                 pinctrl-names = "default";
 936                 pinctrl-0 = <&i2s0_8ch_bus>;
 937                 status = "disabled";
 938         };
 939
 940         i2s1: i2s@ff890000 {
 941                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 942                 reg = <0x0 0xff890000 0x0 0x1000>;
 943                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 944                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 945                 dma-names = "tx", "rx";
 946                 clock-names = "i2s_clk", "i2s_hclk";
 947                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
 948                 pinctrl-names = "default";
 949                 pinctrl-0 = <&i2s1_2ch_bus>;
 950                 status = "disabled";
 951         };
 952
 953         i2s2: i2s@ff8a0000 {
 954                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 955                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 956                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 957                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 958                 dma-names = "tx", "rx";
 959                 clock-names = "i2s_clk", "i2s_hclk";
 960                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
 961                 status = "disabled";
 962         };
 963
 964         gpu: gpu@ff9a0000 {
 965                 compatible = "arm,malit860",
 966                              "arm,malit86x",
 967                              "arm,malit8xx",
 968                              "arm,mali-midgard";
 969
 970                 reg = <0x0 0xff9a0000 0x0 0x10000>;
 971
 972                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 973                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 974                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 975                 interrupt-names = "GPU", "JOB", "MMU";
 976
 977                 clocks = <&cru ACLK_GPU>;
 978                 clock-names = "clk_mali";
 979                 operating-points-v2 = <&gpu_opp_table>;
 980                 status = "disabled";
 981         };
 982
 983         gpu_opp_table: gpu_opp_table {
 984                 compatible = "operating-points-v2";
 985                 opp-shared;
 986
 987                 opp00 {
 988                         opp-hz = /bits/ 64 <200000000>;
 989                         opp-microvolt = <900000>;
 990                 };
 991                 opp01 {
 992                         opp-hz = /bits/ 64 <300000000>;
 993                         opp-microvolt = <900000>;
 994                 };
 995                 opp02 {
 996                         opp-hz = /bits/ 64 <400000000>;
 997                         opp-microvolt = <900000>;
 998                 };
 999                 opp03 {
1000                         opp-hz = /bits/ 64 <500000000>;
1001                         opp-microvolt = <900000>;
1002                 };
1003         };
1004
1005         vopl: vop@ff8f0000 {
1006                 compatible = "rockchip,rk3399-vop-lit";
1007                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1008                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1009                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1010                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1011                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1012                 reset-names = "axi", "ahb", "dclk";
1013                 iommus = <&vopl_mmu>;
1014                 status = "disabled";
1015
1016                 vopl_out: port {
1017                         #address-cells = <1>;
1018                         #size-cells = <0>;
1019
1020                         vopl_out_edp: endpoint@0 {
1021                                 reg = <0>;
1022                                 remote-endpoint = <&edp_in_vopl>;
1023                         };
1024
1025                         vopl_out_mipi: endpoint@1 {
1026                                 reg = <1>;
1027                                 remote-endpoint = <&mipi_in_vopl>;
1028                         };
1029                 };
1030         };
1031
1032         vopl_mmu: iommu@ff8f3f00 {
1033                 compatible = "rockchip,iommu";
1034                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1035                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1036                 interrupt-names = "vopl_mmu";
1037                 #iommu-cells = <0>;
1038                 status = "disabled";
1039         };
1040
1041         vopb: vop@ff900000 {
1042                 compatible = "rockchip,rk3399-vop-big";
1043                 reg = <0x0 0xff900000 0x0 0x3efc>;
1044                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1045                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1046                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1047                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1048                 reset-names = "axi", "ahb", "dclk";
1049                 iommus = <&vopb_mmu>;
1050                 status = "disabled";
1051
1052                 vopb_out: port {
1053                         #address-cells = <1>;
1054                         #size-cells = <0>;
1055
1056                         vopb_out_edp: endpoint@0 {
1057                                 reg = <0>;
1058                                 remote-endpoint = <&edp_in_vopb>;
1059                         };
1060
1061                         vopb_out_mipi: endpoint@1 {
1062                                 reg = <1>;
1063                                 remote-endpoint = <&mipi_in_vopb>;
1064                         };
1065                 };
1066         };
1067
1068         vopb_mmu: iommu@ff903f00 {
1069                 compatible = "rockchip,iommu";
1070                 reg = <0x0 0xff903f00 0x0 0x100>;
1071                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1072                 interrupt-names = "vopb_mmu";
1073                 #iommu-cells = <0>;
1074                 status = "disabled";
1075         };
1076
1077         mipi_dsi: mipi@ff960000 {
1078                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1079                 reg = <0x0 0xff960000 0x0 0x8000>;
1080                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1081                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1082                          <&cru SCLK_DPHY_TX0_CFG>;
1083                 clock-names = "ref", "pclk", "phy_cfg";
1084                 rockchip,grf = <&grf>;
1085                 #address-cells = <1>;
1086                 #size-cells = <0>;
1087                 status = "disabled";
1088
1089                 ports {
1090                         #address-cells = <1>;
1091                         #size-cells = <0>;
1092                         reg = <1>;
1093
1094                         mipi_in: port {
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097
1098                                 mipi_in_vopb: endpoint@0 {
1099                                         reg = <0>;
1100                                         remote-endpoint = <&vopb_out_mipi>;
1101                                 };
1102                                 mipi_in_vopl: endpoint@1 {
1103                                         reg = <1>;
1104                                         remote-endpoint = <&vopl_out_mipi>;
1105                                 };
1106                         };
1107                 };
1108         };
1109
1110         edp: edp@ff970000 {
1111                 compatible = "rockchip,rk3399-edp";
1112                 reg = <0x0 0xff970000 0x0 0x8000>;
1113                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1114                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1115                 clock-names = "dp", "pclk";
1116                 resets = <&cru SRST_P_EDP_CTRL>;
1117                 reset-names = "dp";
1118                 rockchip,grf = <&grf>;
1119                 status = "disabled";
1120                 pinctrl-names = "default";
1121                 pinctrl-0 = <&edp_hpd>;
1122
1123                 ports {
1124                         #address-cells = <1>;
1125                         #size-cells = <0>;
1126
1127                         edp_in: port@0 {
1128                                 reg = <0>;
1129                                 #address-cells = <1>;
1130                                 #size-cells = <0>;
1131
1132                                 edp_in_vopb: endpoint@0 {
1133                                         reg = <0>;
1134                                         remote-endpoint = <&vopb_out_edp>;
1135                                 };
1136
1137                                 edp_in_vopl: endpoint@1 {
1138                                         reg = <1>;
1139                                         remote-endpoint = <&vopl_out_edp>;
1140                                 };
1141                         };
1142                 };
1143         };
1144
1145         display_subsystem: display-subsystem {
1146                 compatible = "rockchip,display-subsystem";
1147                 ports = <&vopl_out>, <&vopb_out>;
1148                 status = "disabled";
1149         };
1150
1151         pinctrl: pinctrl {
1152                 compatible = "rockchip,rk3399-pinctrl";
1153                 rockchip,grf = <&grf>;
1154                 rockchip,pmu = <&pmugrf>;
1155                 #address-cells = <0x2>;
1156                 #size-cells = <0x2>;
1157                 ranges;
1158
1159                 gpio0: gpio0@ff720000 {
1160                         compatible = "rockchip,gpio-bank";
1161                         reg = <0x0 0xff720000 0x0 0x100>;
1162                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1163                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1164
1165                         gpio-controller;
1166                         #gpio-cells = <0x2>;
1167
1168                         interrupt-controller;
1169                         #interrupt-cells = <0x2>;
1170                 };
1171
1172                 gpio1: gpio1@ff730000 {
1173                         compatible = "rockchip,gpio-bank";
1174                         reg = <0x0 0xff730000 0x0 0x100>;
1175                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1176                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1177
1178                         gpio-controller;
1179                         #gpio-cells = <0x2>;
1180
1181                         interrupt-controller;
1182                         #interrupt-cells = <0x2>;
1183                 };
1184
1185                 gpio2: gpio2@ff780000 {
1186                         compatible = "rockchip,gpio-bank";
1187                         reg = <0x0 0xff780000 0x0 0x100>;
1188                         clocks = <&cru PCLK_GPIO2>;
1189                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1190
1191                         gpio-controller;
1192                         #gpio-cells = <0x2>;
1193
1194                         interrupt-controller;
1195                         #interrupt-cells = <0x2>;
1196                 };
1197
1198                 gpio3: gpio3@ff788000 {
1199                         compatible = "rockchip,gpio-bank";
1200                         reg = <0x0 0xff788000 0x0 0x100>;
1201                         clocks = <&cru PCLK_GPIO3>;
1202                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1203
1204                         gpio-controller;
1205                         #gpio-cells = <0x2>;
1206
1207                         interrupt-controller;
1208                         #interrupt-cells = <0x2>;
1209                 };
1210
1211                 gpio4: gpio4@ff790000 {
1212                         compatible = "rockchip,gpio-bank";
1213                         reg = <0x0 0xff790000 0x0 0x100>;
1214                         clocks = <&cru PCLK_GPIO4>;
1215                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1216
1217                         gpio-controller;
1218                         #gpio-cells = <0x2>;
1219
1220                         interrupt-controller;
1221                         #interrupt-cells = <0x2>;
1222                 };
1223
1224                 pcfg_pull_up: pcfg-pull-up {
1225                         bias-pull-up;
1226                 };
1227
1228                 pcfg_pull_down: pcfg-pull-down {
1229                         bias-pull-down;
1230                 };
1231
1232                 pcfg_pull_none: pcfg-pull-none {
1233                         bias-disable;
1234                 };
1235
1236                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1237                         bias-disable;
1238                         drive-strength = <12>;
1239                 };
1240
1241                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1242                         bias-pull-up;
1243                         drive-strength = <8>;
1244                 };
1245
1246                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1247                         bias-pull-down;
1248                         drive-strength = <4>;
1249                 };
1250
1251                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1252                         bias-pull-up;
1253                         drive-strength = <2>;
1254                 };
1255
1256                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1257                         bias-pull-down;
1258                         drive-strength = <12>;
1259                 };
1260
1261                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1262                         bias-disable;
1263                         drive-strength = <13>;
1264                 };
1265
1266                 emmc {
1267                         emmc_pwr: emmc-pwr {
1268                                 rockchip,pins =
1269                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1270                         };
1271                 };
1272
1273                 gmac {
1274                         rgmii_pins: rgmii-pins {
1275                                 rockchip,pins =
1276                                         /* mac_txclk */
1277                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1278                                         /* mac_rxclk */
1279                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1280                                         /* mac_mdio */
1281                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1282                                         /* mac_txen */
1283                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1284                                         /* mac_clk */
1285                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1286                                         /* mac_rxdv */
1287                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1288                                         /* mac_mdc */
1289                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1290                                         /* mac_rxd1 */
1291                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1292                                         /* mac_rxd0 */
1293                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1294                                         /* mac_txd1 */
1295                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1296                                         /* mac_txd0 */
1297                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1298                                         /* mac_rxd3 */
1299                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1300                                         /* mac_rxd2 */
1301                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1302                                         /* mac_txd3 */
1303                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1304                                         /* mac_txd2 */
1305                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1306                         };
1307
1308                         rmii_pins: rmii-pins {
1309                                 rockchip,pins =
1310                                         /* mac_mdio */
1311                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1312                                         /* mac_txen */
1313                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1314                                         /* mac_clk */
1315                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1316                                         /* mac_rxer */
1317                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1318                                         /* mac_rxdv */
1319                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1320                                         /* mac_mdc */
1321                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1322                                         /* mac_rxd1 */
1323                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1324                                         /* mac_rxd0 */
1325                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1326                                         /* mac_txd1 */
1327                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1328                                         /* mac_txd0 */
1329                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1330                         };
1331                 };
1332
1333                 i2c0 {
1334                         i2c0_xfer: i2c0-xfer {
1335                                 rockchip,pins =
1336                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1337                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1338                         };
1339                 };
1340
1341                 i2c1 {
1342                         i2c1_xfer: i2c1-xfer {
1343                                 rockchip,pins =
1344                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1345                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1346                         };
1347                 };
1348
1349                 i2c2 {
1350                         i2c2_xfer: i2c2-xfer {
1351                                 rockchip,pins =
1352                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1353                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1354                         };
1355                 };
1356
1357                 i2c3 {
1358                         i2c3_xfer: i2c3-xfer {
1359                                 rockchip,pins =
1360                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1361                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1362                         };
1363                 };
1364
1365                 i2c4 {
1366                         i2c4_xfer: i2c4-xfer {
1367                                 rockchip,pins =
1368                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1369                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1370                         };
1371                 };
1372
1373                 i2c5 {
1374                         i2c5_xfer: i2c5-xfer {
1375                                 rockchip,pins =
1376                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1377                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1378                         };
1379                 };
1380
1381                 i2c6 {
1382                         i2c6_xfer: i2c6-xfer {
1383                                 rockchip,pins =
1384                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1385                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1386                         };
1387                 };
1388
1389                 i2c7 {
1390                         i2c7_xfer: i2c7-xfer {
1391                                 rockchip,pins =
1392                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1393                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1394                         };
1395                 };
1396
1397                 i2c8 {
1398                         i2c8_xfer: i2c8-xfer {
1399                                 rockchip,pins =
1400                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1401                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1402                         };
1403                 };
1404
1405                 i2s0 {
1406                         i2s0_8ch_bus: i2s0-8ch-bus {
1407                                 rockchip,pins =
1408                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1409                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1410                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1411                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1412                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1413                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1414                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1415                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1416                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1417                         };
1418                 };
1419
1420                 i2s1 {
1421                         i2s1_2ch_bus: i2s1-2ch-bus {
1422                                 rockchip,pins =
1423                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1424                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1425                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1426                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1427                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1428                         };
1429                 };
1430
1431                 sdio0 {
1432                         sdio0_bus1: sdio0-bus1 {
1433                                 rockchip,pins =
1434                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1435                         };
1436
1437                         sdio0_bus4: sdio0-bus4 {
1438                                 rockchip,pins =
1439                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1440                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1441                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1442                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1443                         };
1444
1445                         sdio0_cmd: sdio0-cmd {
1446                                 rockchip,pins =
1447                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1448                         };
1449
1450                         sdio0_clk: sdio0-clk {
1451                                 rockchip,pins =
1452                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1453                         };
1454
1455                         sdio0_cd: sdio0-cd {
1456                                 rockchip,pins =
1457                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1458                         };
1459
1460                         sdio0_pwr: sdio0-pwr {
1461                                 rockchip,pins =
1462                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1463                         };
1464
1465                         sdio0_bkpwr: sdio0-bkpwr {
1466                                 rockchip,pins =
1467                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1468                         };
1469
1470                         sdio0_wp: sdio0-wp {
1471                                 rockchip,pins =
1472                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1473                         };
1474
1475                         sdio0_int: sdio0-int {
1476                                 rockchip,pins =
1477                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1478                         };
1479                 };
1480
1481                 sdmmc {
1482                         sdmmc_bus1: sdmmc-bus1 {
1483                                 rockchip,pins =
1484                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1485                         };
1486
1487                         sdmmc_bus4: sdmmc-bus4 {
1488                                 rockchip,pins =
1489                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1490                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1491                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1492                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1493                         };
1494
1495                         sdmmc_clk: sdmmc-clk {
1496                                 rockchip,pins =
1497                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1498                         };
1499
1500                         sdmmc_cmd: sdmmc-cmd {
1501                                 rockchip,pins =
1502                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1503                         };
1504
1505                         sdmmc_cd: sdmcc-cd {
1506                                 rockchip,pins =
1507                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1508                         };
1509
1510                         sdmmc_wp: sdmmc-wp {
1511                                 rockchip,pins =
1512                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1513                         };
1514                 };
1515
1516                 spdif {
1517                         spdif_bus: spdif-bus {
1518                                 rockchip,pins =
1519                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1520                         };
1521                 };
1522
1523                 spi0 {
1524                         spi0_clk: spi0-clk {
1525                                 rockchip,pins =
1526                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1527                         };
1528                         spi0_cs0: spi0-cs0 {
1529                                 rockchip,pins =
1530                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1531                         };
1532                         spi0_cs1: spi0-cs1 {
1533                                 rockchip,pins =
1534                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1535                         };
1536                         spi0_tx: spi0-tx {
1537                                 rockchip,pins =
1538                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1539                         };
1540                         spi0_rx: spi0-rx {
1541                                 rockchip,pins =
1542                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1543                         };
1544                 };
1545
1546                 spi1 {
1547                         spi1_clk: spi1-clk {
1548                                 rockchip,pins =
1549                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1550                         };
1551                         spi1_cs0: spi1-cs0 {
1552                                 rockchip,pins =
1553                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1554                         };
1555                         spi1_rx: spi1-rx {
1556                                 rockchip,pins =
1557                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1558                         };
1559                         spi1_tx: spi1-tx {
1560                                 rockchip,pins =
1561                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1562                         };
1563                 };
1564
1565                 spi2 {
1566                         spi2_clk: spi2-clk {
1567                                 rockchip,pins =
1568                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1569                         };
1570                         spi2_cs0: spi2-cs0 {
1571                                 rockchip,pins =
1572                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574                         spi2_rx: spi2-rx {
1575                                 rockchip,pins =
1576                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1577                         };
1578                         spi2_tx: spi2-tx {
1579                                 rockchip,pins =
1580                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1581                         };
1582                 };
1583
1584                 spi3 {
1585                         spi3_clk: spi3-clk {
1586                                 rockchip,pins =
1587                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1588                         };
1589                         spi3_cs0: spi3-cs0 {
1590                                 rockchip,pins =
1591                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1592                         };
1593                         spi3_rx: spi3-rx {
1594                                 rockchip,pins =
1595                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1596                         };
1597                         spi3_tx: spi3-tx {
1598                                 rockchip,pins =
1599                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1600                         };
1601                 };
1602
1603                 spi4 {
1604                         spi4_clk: spi4-clk {
1605                                 rockchip,pins =
1606                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1607                         };
1608                         spi4_cs0: spi4-cs0 {
1609                                 rockchip,pins =
1610                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1611                         };
1612                         spi4_rx: spi4-rx {
1613                                 rockchip,pins =
1614                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1615                         };
1616                         spi4_tx: spi4-tx {
1617                                 rockchip,pins =
1618                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1619                         };
1620                 };
1621
1622                 spi5 {
1623                         spi5_clk: spi5-clk {
1624                                 rockchip,pins =
1625                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1626                         };
1627                         spi5_cs0: spi5-cs0 {
1628                                 rockchip,pins =
1629                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1630                         };
1631                         spi5_rx: spi5-rx {
1632                                 rockchip,pins =
1633                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1634                         };
1635                         spi5_tx: spi5-tx {
1636                                 rockchip,pins =
1637                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1638                         };
1639                 };
1640
1641                 tsadc {
1642                         otp_gpio: otp-gpio {
1643                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1644                         };
1645
1646                         otp_out: otp-out {
1647                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1648                         };
1649                 };
1650
1651                 uart0 {
1652                         uart0_xfer: uart0-xfer {
1653                                 rockchip,pins =
1654                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1655                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1656                         };
1657
1658                         uart0_cts: uart0-cts {
1659                                 rockchip,pins =
1660                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1661                         };
1662
1663                         uart0_rts: uart0-rts {
1664                                 rockchip,pins =
1665                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1666                         };
1667                 };
1668
1669                 uart1 {
1670                         uart1_xfer: uart1-xfer {
1671                                 rockchip,pins =
1672                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1673                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1674                         };
1675                 };
1676
1677                 uart2a {
1678                         uart2a_xfer: uart2a-xfer {
1679                                 rockchip,pins =
1680                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1681                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1682                         };
1683                 };
1684
1685                 uart2b {
1686                         uart2b_xfer: uart2b-xfer {
1687                                 rockchip,pins =
1688                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1689                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1690                         };
1691                 };
1692
1693                 uart2c {
1694                         uart2c_xfer: uart2c-xfer {
1695                                 rockchip,pins =
1696                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1697                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1698                         };
1699                 };
1700
1701                 uart3 {
1702                         uart3_xfer: uart3-xfer {
1703                                 rockchip,pins =
1704                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1705                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1706                         };
1707
1708                         uart3_cts: uart3-cts {
1709                                 rockchip,pins =
1710                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1711                         };
1712
1713                         uart3_rts: uart3-rts {
1714                                 rockchip,pins =
1715                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1716                         };
1717                 };
1718
1719                 uart4 {
1720                         uart4_xfer: uart4-xfer {
1721                                 rockchip,pins =
1722                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1723                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1724                         };
1725                 };
1726
1727                 uarthdcp {
1728                         uarthdcp_xfer: uarthdcp-xfer {
1729                                 rockchip,pins =
1730                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1731                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1732                         };
1733                 };
1734
1735                 pwm0 {
1736                         pwm0_pin: pwm0-pin {
1737                                 rockchip,pins =
1738                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1739                         };
1740
1741                         vop0_pwm_pin: vop0-pwm-pin {
1742                                 rockchip,pins =
1743                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1744                         };
1745                 };
1746
1747                 pwm1 {
1748                         pwm1_pin: pwm1-pin {
1749                                 rockchip,pins =
1750                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1751                         };
1752
1753                         vop1_pwm_pin: vop1-pwm-pin {
1754                                 rockchip,pins =
1755                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1756                         };
1757                 };
1758
1759                 pwm2 {
1760                         pwm2_pin: pwm2-pin {
1761                                 rockchip,pins =
1762                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1763                         };
1764                 };
1765
1766                 pwm3a {
1767                         pwm3a_pin: pwm3a-pin {
1768                                 rockchip,pins =
1769                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1770                         };
1771                 };
1772
1773                 pwm3b {
1774                         pwm3b_pin: pwm3b-pin {
1775                                 rockchip,pins =
1776                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 edp {
1781                         edp_hpd: edp-hpd {
1782                                 rockchip,pins =
1783                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1784                         };
1785                 };
1786         };
1787 };