arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/clock/rk3399-cru.h>
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/pinctrl/rockchip.h>
  47
  48 / {
  49         compatible = "rockchip,rk3399";
  50         interrupt-parent = <&gic>;
  51         #address-cells = <2>;
  52         #size-cells = <2>;
  53
  54         aliases {
  55                 serial0 = &uart0;
  56                 serial1 = &uart1;
  57                 serial2 = &uart2;
  58                 serial3 = &uart3;
  59         };
  60
  61         cpus {
  62                 #address-cells = <2>;
  63                 #size-cells = <0>;
  64
  65                 cpu-map {
  66                         cluster0 {
  67                                 core0 {
  68                                         cpu = <&cpu_l0>;
  69                                 };
  70                                 core1 {
  71                                         cpu = <&cpu_l1>;
  72                                 };
  73                                 core2 {
  74                                         cpu = <&cpu_l2>;
  75                                 };
  76                                 core3 {
  77                                         cpu = <&cpu_l3>;
  78                                 };
  79                         };
  80
  81                         cluster1 {
  82                                 core0 {
  83                                         cpu = <&cpu_b0>;
  84                                 };
  85                                 core1 {
  86                                         cpu = <&cpu_b1>;
  87                                 };
  88                         };
  89                 };
  90
  91                 cpu_l0: cpu@0 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53", "arm,armv8";
  94                         reg = <0x0 0x0>;
  95                 };
  96
  97                 cpu_l1: cpu@1 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53", "arm,armv8";
 100                         reg = <0x0 0x1>;
 101                 };
 102
 103                 cpu_l2: cpu@2 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a53", "arm,armv8";
 106                         reg = <0x0 0x2>;
 107                 };
 108
 109                 cpu_l3: cpu@3 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x3>;
 113                 };
 114
 115                 cpu_b0: cpu@100 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a72", "arm,armv8";
 118                         reg = <0x0 0x100>;
 119                 };
 120
 121                 cpu_b1: cpu@101 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a72", "arm,armv8";
 124                         reg = <0x0 0x101>;
 125                 };
 126         };
 127
 128         timer {
 129                 compatible = "arm,armv8-timer";
 130                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 131                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 132                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 134         };
 135
 136         xin24m: xin24m {
 137                 compatible = "fixed-clock";
 138                 #clock-cells = <0>;
 139                 clock-frequency = <24000000>;
 140                 clock-output-names = "xin24m";
 141         };
 142
 143         gic: interrupt-controller@fee00000 {
 144                 compatible = "arm,gic-v3";
 145                 #interrupt-cells = <3>;
 146                 #address-cells = <2>;
 147                 #size-cells = <2>;
 148                 ranges;
 149                 interrupt-controller;
 150
 151                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 152                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 153                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 154                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 155                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 156                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 157                 its: interrupt-controller@fee20000 {
 158                         compatible = "arm,gic-v3-its";
 159                         msi-controller;
 160                         reg = <0x0 0xfee20000 0x0 0x20000>;
 161                 };
 162         };
 163
 164         amba {
 165                 compatible = "arm,amba-bus";
 166                 #address-cells = <2>;
 167                 #size-cells = <2>;
 168                 ranges;
 169
 170                 dmac_bus: dma-controller@ff6d0000 {
 171                         compatible = "arm,pl330", "arm,primecell";
 172                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 173                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 174                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 175                         #dma-cells = <1>;
 176                         clocks = <&cru ACLK_DMAC0_PERILP>;
 177                         clock-names = "apb_pclk";
 178                 };
 179
 180                 dmac_peri: dma-controller@ff6e0000 {
 181                         compatible = "arm,pl330", "arm,primecell";
 182                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 183                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 185                         #dma-cells = <1>;
 186                         clocks = <&cru ACLK_DMAC1_PERILP>;
 187                         clock-names = "apb_pclk";
 188                 };
 189         };
 190
 191         uart0: serial@ff180000 {
 192                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 193                 reg = <0x0 0xff180000 0x0 0x100>;
 194                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 195                 clock-names = "baudclk", "apb_pclk";
 196                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 197                 reg-shift = <2>;
 198                 reg-io-width = <4>;
 199                 status = "disabled";
 200         };
 201
 202         uart1: serial@ff190000 {
 203                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 204                 reg = <0x0 0xff190000 0x0 0x100>;
 205                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 206                 clock-names = "baudclk", "apb_pclk";
 207                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 208                 reg-shift = <2>;
 209                 reg-io-width = <4>;
 210                 status = "disabled";
 211         };
 212
 213         uart2: serial@ff1a0000 {
 214                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 215                 reg = <0x0 0xff1a0000 0x0 0x100>;
 216                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 217                 clock-names = "baudclk", "apb_pclk";
 218                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 219                 reg-shift = <2>;
 220                 reg-io-width = <4>;
 221                 status = "disabled";
 222         };
 223
 224         uart3: serial@ff1b0000 {
 225                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 226                 reg = <0x0 0xff1b0000 0x0 0x100>;
 227                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 228                 clock-names = "baudclk", "apb_pclk";
 229                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 230                 reg-shift = <2>;
 231                 reg-io-width = <4>;
 232                 status = "disabled";
 233         };
 234
 235         spi0: spi@ff1c0000 {
 236                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 237                 reg = <0x0 0xff110000 0x0 0x1000>;
 238                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 239                 clock-names = "spiclk", "apb_pclk";
 240                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 241                 pinctrl-names = "default";
 242                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 status = "disabled";
 246         };
 247
 248         spi1: spi@ff1d0000 {
 249                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 250                 reg = <0x0 0xff120000 0x0 0x1000>;
 251                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 252                 clock-names = "spiclk", "apb_pclk";
 253                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 254                 pinctrl-names = "default";
 255                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258                 status = "disabled";
 259         };
 260
 261         spi2: spi@ff1e0000 {
 262                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 263                 reg = <0x0 0xff130000 0x0 0x1000>;
 264                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 265                 clock-names = "spiclk", "apb_pclk";
 266                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 267                 pinctrl-names = "default";
 268                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 status = "disabled";
 272         };
 273
 274         spi4: spi@ff1f0000 {
 275                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 276                 reg = <0x0 0xff120000 0x0 0x1000>;
 277                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 278                 clock-names = "spiclk", "apb_pclk";
 279                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 280                 pinctrl-names = "default";
 281                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 status = "disabled";
 285         };
 286
 287         spi5: spi@ff200000 {
 288                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 289                 reg = <0x0 0xff130000 0x0 0x1000>;
 290                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 291                 clock-names = "spiclk", "apb_pclk";
 292                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 293                 pinctrl-names = "default";
 294                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 status = "disabled";
 298         };
 299
 300         pmugrf: syscon@ff320000 {
 301                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 302                 reg = <0x0 0xff320000 0x0 0x1000>;
 303         };
 304
 305         spi3: spi@ff350000 {
 306                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 307                 reg = <0x0 0xff110000 0x0 0x1000>;
 308                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 309                 clock-names = "spiclk", "apb_pclk";
 310                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 status = "disabled";
 316         };
 317
 318         uart4: serial@ff370000 {
 319                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 320                 reg = <0x0 0xff370000 0x0 0x100>;
 321                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 322                 clock-names = "baudclk", "apb_pclk";
 323                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 324                 reg-shift = <2>;
 325                 reg-io-width = <4>;
 326                 status = "disabled";
 327         };
 328
 329         pmucru: pmu-clock-controller@ff750000 {
 330                 compatible = "rockchip,rk3399-pmucru";
 331                 reg = <0x0 0xff750000 0x0 0x1000>;
 332                 rockchip,grf = <&pmugrf>;
 333                 #clock-cells = <1>;
 334                 #reset-cells = <1>;
 335         };
 336
 337         cru: clock-controller@ff760000 {
 338                 compatible = "rockchip,rk3399-cru";
 339                 reg = <0x0 0xff760000 0x0 0x1000>;
 340                 rockchip,grf = <&grf>;
 341                 #clock-cells = <1>;
 342                 #reset-cells = <1>;
 343         };
 344
 345         grf: syscon@ff770000 {
 346                 compatible = "rockchip,rk3399-grf", "syscon";
 347                 reg = <0x0 0xff770000 0x0 0x10000>;
 348         };
 349
 350         i2s0: i2s@ff880000 {
 351                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 352                 reg = <0x0 0xff880000 0x0 0x1000>;
 353                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 357                 dma-names = "tx", "rx";
 358                 clock-names = "i2s_hclk", "i2s_clk";
 359                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 360                 status = "disabled";
 361         };
 362
 363         i2s1: i2s@ff890000 {
 364                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 365                 reg = <0x0 0xff890000 0x0 0x1000>;
 366                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 370                 dma-names = "tx", "rx";
 371                 clock-names = "i2s_hclk", "i2s_clk";
 372                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 373                 status = "disabled";
 374         };
 375
 376         i2s2: i2s@ff8a0000 {
 377                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 378                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 379                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 383                 dma-names = "tx", "rx";
 384                 clock-names = "i2s_hclk", "i2s_clk";
 385                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 386                 status = "disabled";
 387         };
 388
 389         pinctrl: pinctrl {
 390                 compatible = "rockchip,rk3399-pinctrl";
 391                 rockchip,grf = <&grf>;
 392                 rockchip,pmu = <&pmugrf>;
 393                 #address-cells = <0x2>;
 394                 #size-cells = <0x2>;
 395                 ranges;
 396
 397                 gpio0: gpio0@ff720000 {
 398                         compatible = "rockchip,gpio-bank";
 399                         reg = <0x0 0xff720000 0x0 0x100>;
 400                         clocks = <&xin24m>;
 401                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 402
 403                         gpio-controller;
 404                         #gpio-cells = <0x2>;
 405
 406                         interrupt-controller;
 407                         #interrupt-cells = <0x2>;
 408                 };
 409
 410                 gpio1: gpio1@ff730000 {
 411                         compatible = "rockchip,gpio-bank";
 412                         reg = <0x0 0xff730000 0x0 0x100>;
 413                         clocks = <&xin24m>;
 414                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 415
 416                         gpio-controller;
 417                         #gpio-cells = <0x2>;
 418
 419                         interrupt-controller;
 420                         #interrupt-cells = <0x2>;
 421                 };
 422
 423                 gpio2: gpio2@ff780000 {
 424                         compatible = "rockchip,gpio-bank";
 425                         reg = <0x0 0xff780000 0x0 0x100>;
 426                         clocks = <&xin24m>;
 427                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 428
 429                         gpio-controller;
 430                         #gpio-cells = <0x2>;
 431
 432                         interrupt-controller;
 433                         #interrupt-cells = <0x2>;
 434                 };
 435
 436                 gpio3: gpio3@ff788000 {
 437                         compatible = "rockchip,gpio-bank";
 438                         reg = <0x0 0xff788000 0x0 0x100>;
 439                         clocks = <&xin24m>;
 440                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 441
 442                         gpio-controller;
 443                         #gpio-cells = <0x2>;
 444
 445                         interrupt-controller;
 446                         #interrupt-cells = <0x2>;
 447                 };
 448
 449                 gpio4: gpio4@ff790000 {
 450                         compatible = "rockchip,gpio-bank";
 451                         reg = <0x0 0xff790000 0x0 0x100>;
 452                         clocks = <&xin24m>;
 453                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 454
 455                         gpio-controller;
 456                         #gpio-cells = <0x2>;
 457
 458                         interrupt-controller;
 459                         #interrupt-cells = <0x2>;
 460                 };
 461
 462                 pcfg_pull_up: pcfg-pull-up {
 463                         bias-pull-up;
 464                 };
 465
 466                 pcfg_pull_down: pcfg-pull-down {
 467                         bias-pull-down;
 468                 };
 469
 470                 pcfg_pull_none: pcfg-pull-none {
 471                         bias-disable;
 472                 };
 473
 474                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 475                         bias-disable;
 476                         drive-strength = <12>;
 477                 };
 478
 479                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 480                         bias-pull-up;
 481                         drive-strength = <8>;
 482                 };
 483
 484                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 485                         bias-pull-down;
 486                         drive-strength = <4>;
 487                 };
 488
 489                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 490                         bias-pull-up;
 491                         drive-strength = <2>;
 492                 };
 493
 494                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 495                         bias-pull-down;
 496                         drive-strength = <12>;
 497                 };
 498
 499                 emmc {
 500                         emmc_pwr: emmc-pwr {
 501                                 rockchip,pins =
 502                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 503                         };
 504                 };
 505
 506                 gmac {
 507                         rgmii_pins: rgmii-pins {
 508                                 rockchip,pins =
 509                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 510                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 511                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 512                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 513                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 514                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 515                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 516                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 517                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 518                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 519                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 520                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 521                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 522                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 523                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 524                         };
 525
 526                         rmii_pins: rmii-pins {
 527                                 rockchip,pins =
 528                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 529                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 530                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 531                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 532                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 533                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 534                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 535                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 536                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 537                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 538                         };
 539                 };
 540
 541                 i2c0 {
 542                         i2c0_xfer: i2c0-xfer {
 543                                 rockchip,pins =
 544                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 545                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 546                         };
 547                 };
 548
 549                 i2c1 {
 550                         i2c1_xfer: i2c1-xfer {
 551                                 rockchip,pins =
 552                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 553                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 554                         };
 555                 };
 556
 557                 i2c2 {
 558                         i2c2_xfer: i2c2-xfer {
 559                                 rockchip,pins =
 560                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 561                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 562                         };
 563                 };
 564
 565                 i2c3 {
 566                         i2c3_xfer: i2c3-xfer {
 567                                 rockchip,pins =
 568                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 569                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 570                         };
 571                 };
 572
 573                 i2c4 {
 574                         i2c4_xfer: i2c4-xfer {
 575                                 rockchip,pins =
 576                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 577                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 578                         };
 579                 };
 580
 581                 i2c5 {
 582                         i2c5_xfer: i2c5-xfer {
 583                                 rockchip,pins =
 584                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 585                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 586                         };
 587                 };
 588
 589                 i2c6 {
 590                         i2c6_xfer: i2c6-xfer {
 591                                 rockchip,pins =
 592                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 593                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 594                         };
 595                 };
 596
 597                 i2c7 {
 598                         i2c7_xfer: i2c7-xfer {
 599                                 rockchip,pins =
 600                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 601                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 602                         };
 603                 };
 604
 605                 i2c8 {
 606                         i2c8_xfer: i2c8-xfer {
 607                                 rockchip,pins =
 608                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 609                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 610                         };
 611                 };
 612
 613                 i2s0 {
 614                         i2s0_8ch_bus: i2s0-8ch-bus {
 615                                 rockchip,pins =
 616                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 617                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 618                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 619                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 620                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 621                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 622                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 623                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 624                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 625                         };
 626                 };
 627
 628                 i2s1 {
 629                         i2s1_2ch_bus: i2s1-2ch-bus {
 630                                 rockchip,pins =
 631                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 632                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 633                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 634                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 635                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 636                         };
 637                 };
 638
 639                 sdio0 {
 640                         sdio0_bus1: sdio0-bus1 {
 641                                 rockchip,pins =
 642                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
 643                         };
 644
 645                         sdio0_bus4: sdio0-bus4 {
 646                                 rockchip,pins =
 647                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
 648                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
 649                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
 650                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
 651                         };
 652
 653                         sdio0_cmd: sdio0-cmd {
 654                                 rockchip,pins =
 655                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
 656                         };
 657
 658                         sdio0_clk: sdio0-clk {
 659                                 rockchip,pins =
 660                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 661                         };
 662
 663                         sdio0_cd: sdio0-cd {
 664                                 rockchip,pins =
 665                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
 666                         };
 667
 668                         sdio0_pwr: sdio0-pwr {
 669                                 rockchip,pins =
 670                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
 671                         };
 672
 673                         sdio0_bkpwr: sdio0-bkpwr {
 674                                 rockchip,pins =
 675                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
 676                         };
 677
 678                         sdio0_wp: sdio0-wp {
 679                                 rockchip,pins =
 680                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
 681                         };
 682
 683                         sdio0_int: sdio0-int {
 684                                 rockchip,pins =
 685                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
 686                         };
 687                 };
 688
 689                 sdmmc {
 690                         sdmmc_bus1: sdmmc-bus1 {
 691                                 rockchip,pins =
 692                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 693                         };
 694
 695                         sdmmc_bus4: sdmmc-bus4 {
 696                                 rockchip,pins =
 697                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 698                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 699                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 700                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 701                         };
 702
 703                         sdmmc_clk: sdmmc-clk {
 704                                 rockchip,pins =
 705                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 706                         };
 707
 708                         sdmmc_cmd: sdmmc-cmd {
 709                                 rockchip,pins =
 710                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 711                         };
 712
 713                         sdmmc_cd: sdmcc-cd {
 714                                 rockchip,pins =
 715                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 716                         };
 717
 718                         sdmmc_wp: sdmmc-wp {
 719                                 rockchip,pins =
 720                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 721                         };
 722                 };
 723
 724                 spi0 {
 725                         spi0_clk: spi0-clk {
 726                                 rockchip,pins =
 727                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 728                         };
 729                         spi0_cs0: spi0-cs0 {
 730                                 rockchip,pins =
 731                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 732                         };
 733                         spi0_cs1: spi0-cs1 {
 734                                 rockchip,pins =
 735                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 736                         };
 737                         spi0_tx: spi0-tx {
 738                                 rockchip,pins =
 739                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 740                         };
 741                         spi0_rx: spi0-rx {
 742                                 rockchip,pins =
 743                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 744                         };
 745                 };
 746
 747                 spi1 {
 748                         spi1_clk: spi1-clk {
 749                                 rockchip,pins =
 750                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
 751                         };
 752                         spi1_cs0: spi1-cs0 {
 753                                 rockchip,pins =
 754                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
 755                         };
 756                         spi1_rx: spi1-rx {
 757                                 rockchip,pins =
 758                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
 759                         };
 760                         spi1_tx: spi1-tx {
 761                                 rockchip,pins =
 762                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
 763                         };
 764                 };
 765
 766                 spi2 {
 767                         spi2_clk: spi2-clk {
 768                                 rockchip,pins =
 769                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 770                         };
 771                         spi2_cs0: spi2-cs0 {
 772                                 rockchip,pins =
 773                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 774                         };
 775                         spi2_rx: spi2-rx {
 776                                 rockchip,pins =
 777                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 778                         };
 779                         spi2_tx: spi2-tx {
 780                                 rockchip,pins =
 781                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 782                         };
 783                 };
 784
 785                 spi3 {
 786                         spi3_clk: spi3-clk {
 787                                 rockchip,pins =
 788                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
 789                         };
 790                         spi3_cs0: spi3-cs0 {
 791                                 rockchip,pins =
 792                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
 793                         };
 794                         spi3_rx: spi3-rx {
 795                                 rockchip,pins =
 796                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
 797                         };
 798                         spi3_tx: spi3-tx {
 799                                 rockchip,pins =
 800                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
 801                         };
 802                 };
 803
 804                 spi4 {
 805                         spi4_clk: spi4-clk {
 806                                 rockchip,pins =
 807                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
 808                         };
 809                         spi4_cs0: spi4-cs0 {
 810                                 rockchip,pins =
 811                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
 812                         };
 813                         spi4_rx: spi4-rx {
 814                                 rockchip,pins =
 815                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
 816                         };
 817                         spi4_tx: spi4-tx {
 818                                 rockchip,pins =
 819                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
 820                         };
 821                 };
 822
 823                 spi5 {
 824                         spi5_clk: spi5-clk {
 825                                 rockchip,pins =
 826                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
 827                         };
 828                         spi5_cs0: spi5-cs0 {
 829                                 rockchip,pins =
 830                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
 831                         };
 832                         spi5_rx: spi5-rx {
 833                                 rockchip,pins =
 834                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
 835                         };
 836                         spi5_tx: spi5-tx {
 837                                 rockchip,pins =
 838                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 839                         };
 840                 };
 841
 842                 uart0 {
 843                         uart0_xfer: uart0-xfer {
 844                                 rockchip,pins =
 845                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
 846                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 847                         };
 848
 849                         uart0_cts: uart0-cts {
 850                                 rockchip,pins =
 851                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 852                         };
 853
 854                         uart0_rts: uart0-rts {
 855                                 rockchip,pins =
 856                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 857                         };
 858                 };
 859
 860                 uart1 {
 861                         uart1_xfer: uart1-xfer {
 862                                 rockchip,pins =
 863                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
 864                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
 865                         };
 866                 };
 867
 868                 uart2a {
 869                         uart2a_xfer: uart2a-xfer {
 870                                 rockchip,pins =
 871                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
 872                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
 873                         };
 874                 };
 875
 876                 uart2b {
 877                         uart2b_xfer: uart2b-xfer {
 878                                 rockchip,pins =
 879                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
 880                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
 881                         };
 882                 };
 883
 884                 uart2c {
 885                         uart2c_xfer: uart2c-xfer {
 886                                 rockchip,pins =
 887                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
 888                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
 889                         };
 890                 };
 891
 892                 uart3 {
 893                         uart3_xfer: uart3-xfer {
 894                                 rockchip,pins =
 895                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
 896                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
 897                         };
 898
 899                         uart3_cts: uart3-cts {
 900                                 rockchip,pins =
 901                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
 902                         };
 903
 904                         uart3_rts: uart3-rts {
 905                                 rockchip,pins =
 906                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
 907                         };
 908                 };
 909
 910                 uart4 {
 911                         uart4_xfer: uart4-xfer {
 912                                 rockchip,pins =
 913                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
 914                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 915                         };
 916                 };
 917
 918                 uarthdcp {
 919                         uarthdcp_xfer: uarthdcp-xfer {
 920                                 rockchip,pins =
 921                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
 922                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
 923                         };
 924                 };
 925
 926                 pwm0 {
 927                         pwm0_pin: pwm0-pin {
 928                                 rockchip,pins =
 929                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
 930                         };
 931
 932                         vop0_pwm_pin: vop0-pwm-pin {
 933                                 rockchip,pins =
 934                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
 935                         };
 936                 };
 937
 938                 pwm1 {
 939                         pwm1_pin: pwm1-pin {
 940                                 rockchip,pins =
 941                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
 942                         };
 943
 944                         vop1_pwm_pin: vop1-pwm-pin {
 945                                 rockchip,pins =
 946                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
 947                         };
 948                 };
 949         };
 950 };