arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <436>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 261         };
 262
 263         pmu_a53 {
 264                 compatible = "arm,cortex-a53-pmu";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 266         };
 267
 268         pmu_a72 {
 269                 compatible = "arm,cortex-a72-pmu";
 270                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 271         };
 272
 273         xin24m: xin24m {
 274                 compatible = "fixed-clock";
 275                 #clock-cells = <0>;
 276                 clock-frequency = <24000000>;
 277                 clock-output-names = "xin24m";
 278         };
 279
 280         amba {
 281                 compatible = "arm,amba-bus";
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges;
 285
 286                 dmac_bus: dma-controller@ff6d0000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 289                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 290                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 291                         #dma-cells = <1>;
 292                         clocks = <&cru ACLK_DMAC0_PERILP>;
 293                         clock-names = "apb_pclk";
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_peri: dma-controller@ff6e0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 301                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC1_PERILP>;
 304                         clock-names = "apb_pclk";
 305                         peripherals-req-type-burst;
 306                 };
 307         };
 308
 309         gmac: eth@fe300000 {
 310                 compatible = "rockchip,rk3399-gmac";
 311                 reg = <0x0 0xfe300000 0x0 0x10000>;
 312                 rockchip,grf = <&grf>;
 313                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 interrupt-names = "macirq";
 315                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 316                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 317                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 318                          <&cru PCLK_GMAC>;
 319                 clock-names = "stmmaceth", "mac_clk_rx",
 320                               "mac_clk_tx", "clk_mac_ref",
 321                               "clk_mac_refout", "aclk_mac",
 322                               "pclk_mac";
 323                 resets = <&cru SRST_A_GMAC>;
 324                 reset-names = "stmmaceth";
 325                 status = "disabled";
 326         };
 327
 328         emmc_phy: phy {
 329                 compatible = "rockchip,rk3399-emmc-phy";
 330                 reg-offset = <0xf780>;
 331                 #phy-cells = <0>;
 332                 rockchip,grf = <&grf>;
 333                 ctrl-base = <0xfe330000>;
 334                 status = "disabled";
 335         };
 336
 337         sdio0: dwmmc@fe310000 {
 338                 compatible = "rockchip,rk3399-dw-mshc",
 339                              "rockchip,rk3288-dw-mshc";
 340                 reg = <0x0 0xfe310000 0x0 0x4000>;
 341                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clock-freq-min-max = <400000 150000000>;
 343                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 344                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 345                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 346                 fifo-depth = <0x100>;
 347                 status = "disabled";
 348         };
 349
 350         sdmmc: dwmmc@fe320000 {
 351                 compatible = "rockchip,rk3399-dw-mshc",
 352                              "rockchip,rk3288-dw-mshc";
 353                 reg = <0x0 0xfe320000 0x0 0x4000>;
 354                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 355                 clock-freq-min-max = <400000 150000000>;
 356                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 357                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 358                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 359                 fifo-depth = <0x100>;
 360                 status = "disabled";
 361         };
 362
 363         sdhci: sdhci@fe330000 {
 364                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 365                 reg = <0x0 0xfe330000 0x0 0x10000>;
 366                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 367                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 368                 clock-names = "clk_xin", "clk_ahb";
 369                 assigned-clocks = <&cru SCLK_EMMC>;
 370                 assigned-clock-parents = <&cru PLL_CPLL>;
 371                 assigned-clock-rates = <200000000>;
 372                 phys = <&emmc_phy>;
 373                 phy-names = "phy_arasan";
 374                 status = "disabled";
 375         };
 376
 377         usb_host0_ehci: usb@fe380000 {
 378                 compatible = "generic-ehci";
 379                 reg = <0x0 0xfe380000 0x0 0x20000>;
 380                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 381                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 382                          <&cru SCLK_USBPHY0_480M_SRC>;
 383                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 384                 phys = <&u2phy0_host>;
 385                 phy-names = "usb";
 386                 status = "disabled";
 387         };
 388
 389         usb_host0_ohci: usb@fe3a0000 {
 390                 compatible = "generic-ohci";
 391                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 392                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 393                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 394                          <&cru SCLK_USBPHY0_480M_SRC>;
 395                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 396                 phys = <&u2phy0_host>;
 397                 phy-names = "usb";
 398                 status = "disabled";
 399         };
 400
 401         usb_host1_ehci: usb@fe3c0000 {
 402                 compatible = "generic-ehci";
 403                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 404                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 405                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 406                          <&cru SCLK_USBPHY1_480M_SRC>;
 407                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 408                 phys = <&u2phy1_host>;
 409                 phy-names = "usb";
 410                 status = "disabled";
 411         };
 412
 413         usb_host1_ohci: usb@fe3e0000 {
 414                 compatible = "generic-ohci";
 415                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 416                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 417                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 418                          <&cru SCLK_USBPHY1_480M_SRC>;
 419                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 420                 phys = <&u2phy1_host>;
 421                 phy-names = "usb";
 422                 status = "disabled";
 423         };
 424
 425         usbdrd3_0: usb@fe800000 {
 426                 compatible = "rockchip,dwc3";
 427                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 428                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 429                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 430                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 431                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 432                               "aclk_usb3", "aclk_usb3_grf";
 433                 #address-cells = <2>;
 434                 #size-cells = <2>;
 435                 ranges;
 436                 status = "disabled";
 437                 usbdrd_dwc3_0: dwc3@fe800000 {
 438                         compatible = "snps,dwc3";
 439                         reg = <0x0 0xfe800000 0x0 0x100000>;
 440                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 441                         dr_mode = "otg";
 442                         phys = <&u2phy0_otg>;
 443                         phy-names = "usb2-phy";
 444                         snps,dis_enblslpm_quirk;
 445                         snps,phyif_utmi_16_bits;
 446                         snps,dis_u2_freeclk_exists_quirk;
 447                         snps,dis_del_phy_power_chg_quirk;
 448                         snps,xhci_slow_suspend_quirk;
 449                         status = "disabled";
 450                 };
 451         };
 452
 453         usbdrd3_1: usb@fe900000 {
 454                 compatible = "rockchip,dwc3";
 455                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 456                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 457                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 458                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 459                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 460                               "aclk_usb3", "aclk_usb3_grf";
 461                 #address-cells = <2>;
 462                 #size-cells = <2>;
 463                 ranges;
 464                 status = "disabled";
 465                 usbdrd_dwc3_1: dwc3@fe900000 {
 466                         compatible = "snps,dwc3";
 467                         reg = <0x0 0xfe900000 0x0 0x100000>;
 468                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 469                         dr_mode = "otg";
 470                         phys = <&u2phy1_otg>;
 471                         phy-names = "usb2-phy";
 472                         snps,dis_enblslpm_quirk;
 473                         snps,phyif_utmi_16_bits;
 474                         snps,dis_u2_freeclk_exists_quirk;
 475                         snps,dis_del_phy_power_chg_quirk;
 476                         snps,xhci_slow_suspend_quirk;
 477                         status = "disabled";
 478                 };
 479         };
 480
 481         gic: interrupt-controller@fee00000 {
 482                 compatible = "arm,gic-v3";
 483                 #interrupt-cells = <4>;
 484                 #address-cells = <2>;
 485                 #size-cells = <2>;
 486                 ranges;
 487                 interrupt-controller;
 488
 489                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 490                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 491                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 492                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 493                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 494                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 495                 its: interrupt-controller@fee20000 {
 496                         compatible = "arm,gic-v3-its";
 497                         msi-controller;
 498                         reg = <0x0 0xfee20000 0x0 0x20000>;
 499                 };
 500
 501                 ppi-partitions {
 502                         part0: interrupt-partition-0 {
 503                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 504                         };
 505
 506                         part1: interrupt-partition-1 {
 507                                 affinity = <&cpu_b0 &cpu_b1>;
 508                         };
 509                 };
 510         };
 511
 512         saradc: saradc@ff100000 {
 513                 compatible = "rockchip,rk3399-saradc";
 514                 reg = <0x0 0xff100000 0x0 0x100>;
 515                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 516                 #io-channel-cells = <1>;
 517                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 518                 clock-names = "saradc", "apb_pclk";
 519                 status = "disabled";
 520         };
 521
 522         i2c0: i2c@ff3c0000 {
 523                 compatible = "rockchip,rk3399-i2c";
 524                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 525                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 526                 clock-names = "i2c", "pclk";
 527                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&i2c0_xfer>;
 530                 #address-cells = <1>;
 531                 #size-cells = <0>;
 532                 status = "disabled";
 533         };
 534
 535         i2c1: i2c@ff110000 {
 536                 compatible = "rockchip,rk3399-i2c";
 537                 reg = <0x0 0xff110000 0x0 0x1000>;
 538                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 539                 clock-names = "i2c", "pclk";
 540                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 541                 pinctrl-names = "default";
 542                 pinctrl-0 = <&i2c1_xfer>;
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 status = "disabled";
 546         };
 547
 548         i2c2: i2c@ff120000 {
 549                 compatible = "rockchip,rk3399-i2c";
 550                 reg = <0x0 0xff120000 0x0 0x1000>;
 551                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 552                 clock-names = "i2c", "pclk";
 553                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&i2c2_xfer>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 status = "disabled";
 559         };
 560
 561         i2c3: i2c@ff130000 {
 562                 compatible = "rockchip,rk3399-i2c";
 563                 reg = <0x0 0xff130000 0x0 0x1000>;
 564                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 565                 clock-names = "i2c", "pclk";
 566                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&i2c3_xfer>;
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 status = "disabled";
 572         };
 573
 574         i2c5: i2c@ff140000 {
 575                 compatible = "rockchip,rk3399-i2c";
 576                 reg = <0x0 0xff140000 0x0 0x1000>;
 577                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 578                 clock-names = "i2c", "pclk";
 579                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&i2c5_xfer>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 status = "disabled";
 585         };
 586
 587         i2c6: i2c@ff150000 {
 588                 compatible = "rockchip,rk3399-i2c";
 589                 reg = <0x0 0xff150000 0x0 0x1000>;
 590                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 591                 clock-names = "i2c", "pclk";
 592                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&i2c6_xfer>;
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         i2c7: i2c@ff160000 {
 601                 compatible = "rockchip,rk3399-i2c";
 602                 reg = <0x0 0xff160000 0x0 0x1000>;
 603                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 604                 clock-names = "i2c", "pclk";
 605                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&i2c7_xfer>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 status = "disabled";
 611         };
 612
 613         uart0: serial@ff180000 {
 614                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 615                 reg = <0x0 0xff180000 0x0 0x100>;
 616                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 617                 clock-names = "baudclk", "apb_pclk";
 618                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 619                 reg-shift = <2>;
 620                 reg-io-width = <4>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 623                 status = "disabled";
 624         };
 625
 626         uart1: serial@ff190000 {
 627                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 628                 reg = <0x0 0xff190000 0x0 0x100>;
 629                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 630                 clock-names = "baudclk", "apb_pclk";
 631                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 632                 reg-shift = <2>;
 633                 reg-io-width = <4>;
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&uart1_xfer>;
 636                 status = "disabled";
 637         };
 638
 639         uart2: serial@ff1a0000 {
 640                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 641                 reg = <0x0 0xff1a0000 0x0 0x100>;
 642                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 643                 clock-names = "baudclk", "apb_pclk";
 644                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 645                 reg-shift = <2>;
 646                 reg-io-width = <4>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&uart2c_xfer>;
 649                 status = "disabled";
 650         };
 651
 652         uart3: serial@ff1b0000 {
 653                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 654                 reg = <0x0 0xff1b0000 0x0 0x100>;
 655                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 656                 clock-names = "baudclk", "apb_pclk";
 657                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 658                 reg-shift = <2>;
 659                 reg-io-width = <4>;
 660                 pinctrl-names = "default";
 661                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 662                 status = "disabled";
 663         };
 664
 665         spi0: spi@ff1c0000 {
 666                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 667                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 668                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 669                 clock-names = "spiclk", "apb_pclk";
 670                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 status = "disabled";
 676         };
 677
 678         spi1: spi@ff1d0000 {
 679                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 680                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 681                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 682                 clock-names = "spiclk", "apb_pclk";
 683                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 status = "disabled";
 689         };
 690
 691         spi2: spi@ff1e0000 {
 692                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 693                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 694                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 695                 clock-names = "spiclk", "apb_pclk";
 696                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 697                 pinctrl-names = "default";
 698                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701                 status = "disabled";
 702         };
 703
 704         spi4: spi@ff1f0000 {
 705                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 706                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 707                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 708                 clock-names = "spiclk", "apb_pclk";
 709                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 710                 pinctrl-names = "default";
 711                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 712                 #address-cells = <1>;
 713                 #size-cells = <0>;
 714                 status = "disabled";
 715         };
 716
 717         spi5: spi@ff200000 {
 718                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 719                 reg = <0x0 0xff200000 0x0 0x1000>;
 720                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 721                 clock-names = "spiclk", "apb_pclk";
 722                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 723                 pinctrl-names = "default";
 724                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 725                 #address-cells = <1>;
 726                 #size-cells = <0>;
 727                 status = "disabled";
 728         };
 729
 730         thermal-zones {
 731                 soc_thermal: soc-thermal {
 732                         polling-delay-passive = <20>; /* milliseconds */
 733                         polling-delay = <1000>; /* milliseconds */
 734                         sustainable-power = <1000>; /* milliwatts */
 735
 736                         thermal-sensors = <&tsadc 0>;
 737
 738                         trips {
 739                                 threshold: trip-point@0 {
 740                                         temperature = <70000>; /* millicelsius */
 741                                         hysteresis = <2000>; /* millicelsius */
 742                                         type = "passive";
 743                                 };
 744                                 target: trip-point@1 {
 745                                         temperature = <85000>; /* millicelsius */
 746                                         hysteresis = <2000>; /* millicelsius */
 747                                         type = "passive";
 748                                 };
 749                                 soc_crit: soc-crit {
 750                                         temperature = <95000>; /* millicelsius */
 751                                         hysteresis = <2000>; /* millicelsius */
 752                                         type = "critical";
 753                                 };
 754                         };
 755
 756                         cooling-maps {
 757                                 map0 {
 758                                         trip = <&target>;
 759                                         cooling-device =
 760                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 761                                         contribution = <4096>;
 762                                 };
 763                                 map1 {
 764                                         trip = <&target>;
 765                                         cooling-device =
 766                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 767                                         contribution = <1024>;
 768                                 };
 769                                 map2 {
 770                                         trip = <&target>;
 771                                         cooling-device =
 772                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 773                                         contribution = <4096>;
 774                                 };
 775                         };
 776                 };
 777
 778                 gpu_thermal: gpu-thermal {
 779                         polling-delay-passive = <100>; /* milliseconds */
 780                         polling-delay = <1000>; /* milliseconds */
 781
 782                         thermal-sensors = <&tsadc 1>;
 783                 };
 784         };
 785
 786         tsadc: tsadc@ff260000 {
 787                 compatible = "rockchip,rk3399-tsadc";
 788                 reg = <0x0 0xff260000 0x0 0x100>;
 789                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 790                 rockchip,grf = <&grf>;
 791                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 792                 clock-names = "tsadc", "apb_pclk";
 793                 assigned-clocks = <&cru SCLK_TSADC>;
 794                 assigned-clock-rates = <750000>;
 795                 resets = <&cru SRST_TSADC>;
 796                 reset-names = "tsadc-apb";
 797                 pinctrl-names = "init", "default", "sleep";
 798                 pinctrl-0 = <&otp_gpio>;
 799                 pinctrl-1 = <&otp_out>;
 800                 pinctrl-2 = <&otp_gpio>;
 801                 #thermal-sensor-cells = <1>;
 802                 rockchip,hw-tshut-temp = <95000>;
 803                 status = "disabled";
 804         };
 805
 806         qos_hdcp: qos@ffa90000 {
 807                 compatible = "syscon";
 808                 reg = <0x0 0xffa90000 0x0 0x20>;
 809         };
 810
 811         qos_iep: qos@ffa98000 {
 812                 compatible = "syscon";
 813                 reg = <0x0 0xffa98000 0x0 0x20>;
 814         };
 815
 816         qos_isp0_m0: qos@ffaa0000 {
 817                 compatible = "syscon";
 818                 reg = <0x0 0xffaa0000 0x0 0x20>;
 819         };
 820
 821         qos_isp0_m1: qos@ffaa0080 {
 822                 compatible = "syscon";
 823                 reg = <0x0 0xffaa0080 0x0 0x20>;
 824         };
 825
 826         qos_isp1_m0: qos@ffaa8000 {
 827                 compatible = "syscon";
 828                 reg = <0x0 0xffaa8000 0x0 0x20>;
 829         };
 830
 831         qos_isp1_m1: qos@ffaa8080 {
 832                 compatible = "syscon";
 833                 reg = <0x0 0xffaa8080 0x0 0x20>;
 834         };
 835
 836         qos_rga_r: qos@ffab0000 {
 837                 compatible = "syscon";
 838                 reg = <0x0 0xffab0000 0x0 0x20>;
 839         };
 840
 841         qos_rga_w: qos@ffab0080 {
 842                 compatible = "syscon";
 843                 reg = <0x0 0xffab0080 0x0 0x20>;
 844         };
 845
 846         qos_video_m0: qos@ffab8000 {
 847                 compatible = "syscon";
 848                 reg = <0x0 0xffab8000 0x0 0x20>;
 849         };
 850
 851         qos_video_m1_r: qos@ffac0000 {
 852                 compatible = "syscon";
 853                 reg = <0x0 0xffac0000 0x0 0x20>;
 854         };
 855
 856         qos_video_m1_w: qos@ffac0080 {
 857                 compatible = "syscon";
 858                 reg = <0x0 0xffac0080 0x0 0x20>;
 859         };
 860
 861         qos_vop_big_r: qos@ffac8000 {
 862                 compatible = "syscon";
 863                 reg = <0x0 0xffac8000 0x0 0x20>;
 864         };
 865
 866         qos_vop_big_w: qos@ffac8080 {
 867                 compatible = "syscon";
 868                 reg = <0x0 0xffac8080 0x0 0x20>;
 869         };
 870
 871         qos_vop_little: qos@ffad0000 {
 872                 compatible = "syscon";
 873                 reg = <0x0 0xffad0000 0x0 0x20>;
 874         };
 875
 876         qos_gpu: qos@ffae0000 {
 877                 compatible = "syscon";
 878                 reg = <0x0 0xffae0000 0x0 0x20>;
 879         };
 880
 881         pmu: power-management@ff310000 {
 882                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 883                 reg = <0x0 0xff310000 0x0 0x1000>;
 884
 885                 /*
 886                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 887                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 888                  * Some of the power domains are grouped together for every
 889                  * voltage domain.
 890                  * The detail contents as below.
 891                  */
 892                 power: power-controller {
 893                         compatible = "rockchip,rk3399-power-controller";
 894                         #power-domain-cells = <1>;
 895                         #address-cells = <1>;
 896                         #size-cells = <0>;
 897
 898                         /* These power domains are grouped by VD_CENTER */
 899                         pd_iep@RK3399_PD_IEP {
 900                                 reg = <RK3399_PD_IEP>;
 901                                 clocks = <&cru ACLK_IEP>,
 902                                          <&cru HCLK_IEP>;
 903                                 pm_qos = <&qos_iep>;
 904                         };
 905                         pd_rga@RK3399_PD_RGA {
 906                                 reg = <RK3399_PD_RGA>;
 907                                 clocks = <&cru ACLK_RGA>,
 908                                          <&cru HCLK_RGA>;
 909                                 pm_qos = <&qos_rga_r>,
 910                                          <&qos_rga_w>;
 911                         };
 912                         pd_vcodec@RK3399_PD_VCODEC {
 913                                 reg = <RK3399_PD_VCODEC>;
 914                                 clocks = <&cru ACLK_VCODEC>,
 915                                          <&cru HCLK_VCODEC>;
 916                                 pm_qos = <&qos_video_m0>;
 917                         };
 918                         pd_vdu@RK3399_PD_VDU {
 919                                 reg = <RK3399_PD_VDU>;
 920                                 clocks = <&cru ACLK_VDU>,
 921                                          <&cru HCLK_VDU>;
 922                                 pm_qos = <&qos_video_m1_r>,
 923                                          <&qos_video_m1_w>;
 924                         };
 925
 926                         /* These power domains are grouped by VD_GPU */
 927                         pd_gpu@RK3399_PD_GPU {
 928                                 reg = <RK3399_PD_GPU>;
 929                                 clocks = <&cru ACLK_GPU>;
 930                                 pm_qos = <&qos_gpu>;
 931                         };
 932
 933                         /* These power domains are grouped by VD_LOGIC */
 934                         pd_vio@RK3399_PD_VIO {
 935                                 reg = <RK3399_PD_VIO>;
 936                                 #address-cells = <1>;
 937                                 #size-cells = <0>;
 938
 939                                 pd_hdcp@RK3399_PD_HDCP {
 940                                         reg = <RK3399_PD_HDCP>;
 941                                         clocks = <&cru ACLK_HDCP>,
 942                                                  <&cru HCLK_HDCP>,
 943                                                  <&cru PCLK_HDCP>;
 944                                         pm_qos = <&qos_hdcp>;
 945                                 };
 946                                 pd_isp0@RK3399_PD_ISP0 {
 947                                         reg = <RK3399_PD_ISP0>;
 948                                         clocks = <&cru ACLK_ISP0>,
 949                                                  <&cru HCLK_ISP0>;
 950                                         pm_qos = <&qos_isp0_m0>,
 951                                                  <&qos_isp0_m1>;
 952                                 };
 953                                 pd_isp1@RK3399_PD_ISP1 {
 954                                         reg = <RK3399_PD_ISP1>;
 955                                         clocks = <&cru ACLK_ISP1>,
 956                                                  <&cru HCLK_ISP1>;
 957                                         pm_qos = <&qos_isp1_m0>,
 958                                                  <&qos_isp1_m1>;
 959                                 };
 960                                 pd_vo@RK3399_PD_VO {
 961                                         reg = <RK3399_PD_VO>;
 962                                         #address-cells = <1>;
 963                                         #size-cells = <0>;
 964
 965                                         pd_vopb@RK3399_PD_VOPB {
 966                                                 reg = <RK3399_PD_VOPB>;
 967                                                 clocks = <&cru ACLK_VOP0>,
 968                                                          <&cru HCLK_VOP0>;
 969                                                 pm_qos = <&qos_vop_big_r>,
 970                                                          <&qos_vop_big_w>;
 971                                         };
 972                                         pd_vopl@RK3399_PD_VOPL {
 973                                                 reg = <RK3399_PD_VOPL>;
 974                                                 clocks = <&cru ACLK_VOP1>,
 975                                                          <&cru HCLK_VOP1>;
 976                                                 pm_qos = <&qos_vop_little>;
 977                                         };
 978                                 };
 979                         };
 980                 };
 981         };
 982
 983         pmugrf: syscon@ff320000 {
 984                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 985                 reg = <0x0 0xff320000 0x0 0x1000>;
 986
 987                 reboot-mode {
 988                         compatible = "syscon-reboot-mode";
 989                         offset = <0x300>;
 990                         mode-bootloader = <BOOT_LOADER>;
 991                         mode-charge = <BOOT_CHARGING>;
 992                         mode-fastboot = <BOOT_FASTBOOT>;
 993                         mode-loader = <BOOT_LOADER>;
 994                         mode-normal = <BOOT_NORMAL>;
 995                         mode-recovery = <BOOT_RECOVERY>;
 996                 };
 997         };
 998
 999         spi3: spi@ff350000 {
1000                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1001                 reg = <0x0 0xff350000 0x0 0x1000>;
1002                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1003                 clock-names = "spiclk", "apb_pclk";
1004                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1005                 pinctrl-names = "default";
1006                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1007                 #address-cells = <1>;
1008                 #size-cells = <0>;
1009                 status = "disabled";
1010         };
1011
1012         uart4: serial@ff370000 {
1013                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1014                 reg = <0x0 0xff370000 0x0 0x100>;
1015                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1016                 clock-names = "baudclk", "apb_pclk";
1017                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1018                 reg-shift = <2>;
1019                 reg-io-width = <4>;
1020                 pinctrl-names = "default";
1021                 pinctrl-0 = <&uart4_xfer>;
1022                 status = "disabled";
1023         };
1024
1025         i2c4: i2c@ff3d0000 {
1026                 compatible = "rockchip,rk3399-i2c";
1027                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1028                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1029                 clock-names = "i2c", "pclk";
1030                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1031                 pinctrl-names = "default";
1032                 pinctrl-0 = <&i2c4_xfer>;
1033                 #address-cells = <1>;
1034                 #size-cells = <0>;
1035                 status = "disabled";
1036         };
1037
1038         i2c8: i2c@ff3e0000 {
1039                 compatible = "rockchip,rk3399-i2c";
1040                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1041                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1042                 clock-names = "i2c", "pclk";
1043                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1044                 pinctrl-names = "default";
1045                 pinctrl-0 = <&i2c8_xfer>;
1046                 #address-cells = <1>;
1047                 #size-cells = <0>;
1048                 status = "disabled";
1049         };
1050
1051         pcie0: pcie@f8000000 {
1052                 compatible = "rockchip,rk3399-pcie";
1053                 #address-cells = <3>;
1054                 #size-cells = <2>;
1055                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1056                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1057                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1058                               "hclk_pcie", "clk_pciephy_ref";
1059                 bus-range = <0x0 0x1>;
1060                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1061                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1062                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1063                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1064                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1065                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1066                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1067                       < 0x0 0xfd000000 0x0 0x1000000 >;
1068                 reg-name = "axi-base", "apb-base";
1069                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1070                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1071                          <&cru SRST_PCIE_PIPE>;
1072                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1073                               "mgmt-sticky-rst", "pipe-rst";
1074                 rockchip,grf = <&grf>;
1075                 pcie-conf = <0xe220>;
1076                 pcie-status = <0xe2a4>;
1077                 pcie-laneoff = <0xe214>;
1078                 msi-parent = <&its>;
1079                 #interrupt-cells = <1>;
1080                 interrupt-map-mask = <0 0 0 7>;
1081                 interrupt-map = <0 0 0 1 &pcie0 1>,
1082                                 <0 0 0 2 &pcie0 2>,
1083                                 <0 0 0 3 &pcie0 3>,
1084                                 <0 0 0 4 &pcie0 4>;
1085                 status = "disabled";
1086                 pcie_intc: interrupt-controller {
1087                         interrupt-controller;
1088                         #address-cells = <0>;
1089                         #interrupt-cells = <1>;
1090                 };
1091         };
1092
1093         pwm0: pwm@ff420000 {
1094                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1095                 reg = <0x0 0xff420000 0x0 0x10>;
1096                 #pwm-cells = <3>;
1097                 pinctrl-names = "default";
1098                 pinctrl-0 = <&pwm0_pin>;
1099                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1100                 clock-names = "pwm";
1101                 status = "disabled";
1102         };
1103
1104         pwm1: pwm@ff420010 {
1105                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1106                 reg = <0x0 0xff420010 0x0 0x10>;
1107                 #pwm-cells = <3>;
1108                 pinctrl-names = "default";
1109                 pinctrl-0 = <&pwm1_pin>;
1110                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1111                 clock-names = "pwm";
1112                 status = "disabled";
1113         };
1114
1115         pwm2: pwm@ff420020 {
1116                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1117                 reg = <0x0 0xff420020 0x0 0x10>;
1118                 #pwm-cells = <3>;
1119                 pinctrl-names = "default";
1120                 pinctrl-0 = <&pwm2_pin>;
1121                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1122                 clock-names = "pwm";
1123                 status = "disabled";
1124         };
1125
1126         pwm3: pwm@ff420030 {
1127                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1128                 reg = <0x0 0xff420030 0x0 0x10>;
1129                 #pwm-cells = <3>;
1130                 pinctrl-names = "default";
1131                 pinctrl-0 = <&pwm3a_pin>;
1132                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1133                 clock-names = "pwm";
1134                 status = "disabled";
1135         };
1136
1137         rga: rga@ff680000 {
1138                 compatible = "rockchip,rk3399-rga";
1139                 reg = <0x0 0xff680000 0x0 0x10000>;
1140                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1141                 interrupt-names = "rga";
1142                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1143                 clock-names = "aclk", "hclk", "sclk";
1144                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1145                 reset-names = "core", "axi", "ahb";
1146                 power-domains = <&power RK3399_PD_RGA>;
1147                 status = "disabled";
1148         };
1149
1150         pmucru: pmu-clock-controller@ff750000 {
1151                 compatible = "rockchip,rk3399-pmucru";
1152                 reg = <0x0 0xff750000 0x0 0x1000>;
1153                 #clock-cells = <1>;
1154                 #reset-cells = <1>;
1155                 assigned-clocks = <&pmucru PLL_PPLL>;
1156                 assigned-clock-rates = <676000000>;
1157         };
1158
1159         cru: clock-controller@ff760000 {
1160                 compatible = "rockchip,rk3399-cru";
1161                 reg = <0x0 0xff760000 0x0 0x1000>;
1162                 #clock-cells = <1>;
1163                 #reset-cells = <1>;
1164                 assigned-clocks =
1165                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1166                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1167                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1168                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1169                         <&cru PLL_NPLL>,
1170                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1171                         <&cru PCLK_PERIHP>,
1172                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1173                         <&cru PCLK_PERILP0>,
1174                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1175                 assigned-clock-rates =
1176                          <400000000>,  <200000000>,
1177                          <400000000>,  <200000000>,
1178                          <816000000>, <816000000>,
1179                          <594000000>,  <800000000>,
1180                         <1000000000>,
1181                          <150000000>,   <75000000>,
1182                           <37500000>,
1183                          <100000000>,  <100000000>,
1184                           <50000000>,
1185                          <100000000>,   <50000000>;
1186         };
1187
1188         grf: syscon@ff770000 {
1189                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1190                 reg = <0x0 0xff770000 0x0 0x10000>;
1191                 #address-cells = <1>;
1192                 #size-cells = <1>;
1193
1194                 u2phy0: usb2-phy@e450 {
1195                         compatible = "rockchip,rk3399-usb2phy";
1196                         reg = <0xe450 0x10>;
1197                         clocks = <&cru SCLK_USB2PHY0_REF>;
1198                         clock-names = "phyclk";
1199                         #clock-cells = <0>;
1200                         clock-output-names = "clk_usbphy0_480m";
1201                         status = "disabled";
1202
1203                         u2phy0_otg: otg-port {
1204                                 #phy-cells = <0>;
1205                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1206                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1207                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1208                                 interrupt-names = "otg-bvalid", "otg-id",
1209                                                   "linestate";
1210                                 status = "disabled";
1211                         };
1212
1213                         u2phy0_host: host-port {
1214                                 #phy-cells = <0>;
1215                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1216                                 interrupt-names = "linestate";
1217                                 status = "disabled";
1218                         };
1219                 };
1220
1221                 u2phy1: usb2-phy@e460 {
1222                         compatible = "rockchip,rk3399-usb2phy";
1223                         reg = <0xe460 0x10>;
1224                         clocks = <&cru SCLK_USB2PHY1_REF>;
1225                         clock-names = "phyclk";
1226                         #clock-cells = <0>;
1227                         clock-output-names = "clk_usbphy1_480m";
1228                         status = "disabled";
1229
1230                         u2phy1_otg: otg-port {
1231                                 #phy-cells = <0>;
1232                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1233                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1234                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1235                                 interrupt-names = "otg-bvalid", "otg-id",
1236                                                   "linestate";
1237                                 status = "disabled";
1238                         };
1239
1240                         u2phy1_host: host-port {
1241                                 #phy-cells = <0>;
1242                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1243                                 interrupt-names = "linestate";
1244                                 status = "disabled";
1245                         };
1246                 };
1247         };
1248
1249         tcphy0: phy@ff7c0000 {
1250                 compatible = "rockchip,rk3399-typec-phy";
1251                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1252                 rockchip,grf = <&grf>;
1253                 #phy-cells = <0>;
1254                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1255                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1256                 clock-names = "tcpdcore", "tcpdphy-ref";
1257                 resets = <&cru SRST_UPHY0>,
1258                          <&cru SRST_UPHY0_PIPE_L00>,
1259                          <&cru SRST_P_UPHY0_TCPHY>;
1260                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1261                 rockchip,typec-conn-dir = <0xe580 0 16>;
1262                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1263                 rockchip,external-psm = <0xe588 14 30>;
1264                 rockchip,pipe-status = <0xe5c0 0 0>;
1265                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1266                 status = "disabled";
1267         };
1268
1269         tcphy1: phy@ff800000 {
1270                 compatible = "rockchip,rk3399-typec-phy";
1271                 reg = <0x0 0xff800000 0x0 0x40000>;
1272                 rockchip,grf = <&grf>;
1273                 #phy-cells = <0>;
1274                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1275                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1276                 clock-names = "tcpdcore", "tcpdphy-ref";
1277                 resets = <&cru SRST_UPHY1>,
1278                          <&cru SRST_UPHY1_PIPE_L00>,
1279                          <&cru SRST_P_UPHY1_TCPHY>;
1280                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1281                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1282                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1283                 rockchip,external-psm = <0xe594 14 30>;
1284                 rockchip,pipe-status = <0xe5c0 16 16>;
1285                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1286                 status = "disabled";
1287         };
1288
1289         watchdog@ff840000 {
1290                 compatible = "snps,dw-wdt";
1291                 reg = <0x0 0xff840000 0x0 0x100>;
1292                 clocks = <&cru PCLK_WDT>;
1293                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1294         };
1295
1296         rktimer: rktimer@ff850000 {
1297                 compatible = "rockchip,rk3399-timer";
1298                 reg = <0x0 0xff850000 0x0 0x1000>;
1299                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1300                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1301                 clock-names = "pclk", "timer";
1302         };
1303
1304         spdif: spdif@ff870000 {
1305                 compatible = "rockchip,rk3399-spdif";
1306                 reg = <0x0 0xff870000 0x0 0x1000>;
1307                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1308                 dmas = <&dmac_bus 7>;
1309                 dma-names = "tx";
1310                 clock-names = "mclk", "hclk";
1311                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1312                 pinctrl-names = "default";
1313                 pinctrl-0 = <&spdif_bus>;
1314                 status = "disabled";
1315         };
1316
1317         i2s0: i2s@ff880000 {
1318                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1319                 reg = <0x0 0xff880000 0x0 0x1000>;
1320                 rockchip,grf = <&grf>;
1321                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1322                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1323                 dma-names = "tx", "rx";
1324                 clock-names = "i2s_clk", "i2s_hclk";
1325                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1326                 pinctrl-names = "default";
1327                 pinctrl-0 = <&i2s0_8ch_bus>;
1328                 status = "disabled";
1329         };
1330
1331         i2s1: i2s@ff890000 {
1332                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1333                 reg = <0x0 0xff890000 0x0 0x1000>;
1334                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1335                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1336                 dma-names = "tx", "rx";
1337                 clock-names = "i2s_clk", "i2s_hclk";
1338                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1339                 pinctrl-names = "default";
1340                 pinctrl-0 = <&i2s1_2ch_bus>;
1341                 status = "disabled";
1342         };
1343
1344         i2s2: i2s@ff8a0000 {
1345                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1346                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1347                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1348                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1349                 dma-names = "tx", "rx";
1350                 clock-names = "i2s_clk", "i2s_hclk";
1351                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1352                 status = "disabled";
1353         };
1354
1355         gpu: gpu@ff9a0000 {
1356                 compatible = "arm,malit860",
1357                              "arm,malit86x",
1358                              "arm,malit8xx",
1359                              "arm,mali-midgard";
1360
1361                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1362
1363                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1364                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1365                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1366                 interrupt-names = "GPU", "JOB", "MMU";
1367
1368                 clocks = <&cru ACLK_GPU>;
1369                 clock-names = "clk_mali";
1370                 #cooling-cells = <2>; /* min followed by max */
1371                 operating-points-v2 = <&gpu_opp_table>;
1372                 power-domains = <&power RK3399_PD_GPU>;
1373                 power-off-delay-ms = <200>;
1374                 status = "disabled";
1375
1376                 gpu_power_model: power_model {
1377                         compatible = "arm,mali-simple-power-model";
1378                         voltage = <900>;
1379                         frequency = <500>;
1380                         static-power = <300>;
1381                         dynamic-power = <396>;
1382                         ts = <32000 4700 (-80) 2>;
1383                         thermal-zone = "gpu-thermal";
1384                 };
1385         };
1386
1387         gpu_opp_table: gpu_opp_table {
1388                 compatible = "operating-points-v2";
1389                 opp-shared;
1390
1391                 opp@200000000 {
1392                         opp-hz = /bits/ 64 <200000000>;
1393                         opp-microvolt = <900000>;
1394                 };
1395                 opp@300000000 {
1396                         opp-hz = /bits/ 64 <300000000>;
1397                         opp-microvolt = <900000>;
1398                 };
1399                 opp@400000000 {
1400                         opp-hz = /bits/ 64 <400000000>;
1401                         opp-microvolt = <900000>;
1402                 };
1403
1404         };
1405
1406         vopl: vop@ff8f0000 {
1407                 compatible = "rockchip,rk3399-vop-lit";
1408                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1409                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1410                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1411                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1412                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1413                 reset-names = "axi", "ahb", "dclk";
1414                 power-domains = <&power RK3399_PD_VOPL>;
1415                 iommus = <&vopl_mmu>;
1416                 status = "disabled";
1417
1418                 vopl_out: port {
1419                         #address-cells = <1>;
1420                         #size-cells = <0>;
1421
1422                         vopl_out_mipi: endpoint@0 {
1423                                 reg = <0>;
1424                                 remote-endpoint = <&mipi_in_vopl>;
1425                         };
1426
1427                         vopl_out_edp: endpoint@1 {
1428                                 reg = <1>;
1429                                 remote-endpoint = <&edp_in_vopl>;
1430                         };
1431
1432                         vopl_out_hdmi: endpoint@2 {
1433                                 reg = <2>;
1434                                 remote-endpoint = <&hdmi_in_vopl>;
1435                         };
1436                 };
1437         };
1438
1439         vopl_mmu: iommu@ff8f3f00 {
1440                 compatible = "rockchip,iommu";
1441                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1442                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1443                 interrupt-names = "vopl_mmu";
1444                 #iommu-cells = <0>;
1445                 status = "disabled";
1446         };
1447
1448         vopb: vop@ff900000 {
1449                 compatible = "rockchip,rk3399-vop-big";
1450                 reg = <0x0 0xff900000 0x0 0x3efc>;
1451                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1452                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1453                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1454                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1455                 reset-names = "axi", "ahb", "dclk";
1456                 power-domains = <&power RK3399_PD_VOPB>;
1457                 iommus = <&vopb_mmu>;
1458                 status = "disabled";
1459
1460                 vopb_out: port {
1461                         #address-cells = <1>;
1462                         #size-cells = <0>;
1463
1464                         vopb_out_edp: endpoint@0 {
1465                                 reg = <0>;
1466                                 remote-endpoint = <&edp_in_vopb>;
1467                         };
1468
1469                         vopb_out_mipi: endpoint@1 {
1470                                 reg = <1>;
1471                                 remote-endpoint = <&mipi_in_vopb>;
1472                         };
1473
1474                         vopb_out_hdmi: endpoint@2 {
1475                                 reg = <2>;
1476                                 remote-endpoint = <&hdmi_in_vopb>;
1477                         };
1478                 };
1479         };
1480
1481         vopb_mmu: iommu@ff903f00 {
1482                 compatible = "rockchip,iommu";
1483                 reg = <0x0 0xff903f00 0x0 0x100>;
1484                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1485                 interrupt-names = "vopb_mmu";
1486                 #iommu-cells = <0>;
1487                 status = "disabled";
1488         };
1489
1490         hdmi: hdmi@ff940000 {
1491                 compatible = "rockchip,rk3399-dw-hdmi";
1492                 reg = <0x0 0xff940000 0x0 0x20000>;
1493                 reg-io-width = <4>;
1494                 rockchip,grf = <&grf>;
1495                 power-domains = <&power RK3399_PD_HDCP>;
1496                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1497                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1498                 clock-names = "iahb", "isfr", "vpll", "grf";
1499                 status = "disabled";
1500
1501                 ports {
1502                         hdmi_in: port {
1503                                 #address-cells = <1>;
1504                                 #size-cells = <0>;
1505                                 hdmi_in_vopb: endpoint@0 {
1506                                         reg = <0>;
1507                                         remote-endpoint = <&vopb_out_hdmi>;
1508                                 };
1509                                 hdmi_in_vopl: endpoint@1 {
1510                                         reg = <1>;
1511                                         remote-endpoint = <&vopl_out_hdmi>;
1512                                 };
1513                         };
1514                 };
1515         };
1516
1517         mipi_dsi: mipi@ff960000 {
1518                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1519                 reg = <0x0 0xff960000 0x0 0x8000>;
1520                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1521                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1522                          <&cru SCLK_DPHY_TX0_CFG>;
1523                 clock-names = "ref", "pclk", "phy_cfg";
1524                 power-domains = <&power RK3399_PD_VIO>;
1525                 rockchip,grf = <&grf>;
1526                 #address-cells = <1>;
1527                 #size-cells = <0>;
1528                 status = "disabled";
1529
1530                 ports {
1531                         #address-cells = <1>;
1532                         #size-cells = <0>;
1533                         reg = <1>;
1534
1535                         mipi_in: port {
1536                                 #address-cells = <1>;
1537                                 #size-cells = <0>;
1538
1539                                 mipi_in_vopb: endpoint@0 {
1540                                         reg = <0>;
1541                                         remote-endpoint = <&vopb_out_mipi>;
1542                                 };
1543                                 mipi_in_vopl: endpoint@1 {
1544                                         reg = <1>;
1545                                         remote-endpoint = <&vopl_out_mipi>;
1546                                 };
1547                         };
1548                 };
1549         };
1550
1551         edp: edp@ff970000 {
1552                 compatible = "rockchip,rk3399-edp";
1553                 reg = <0x0 0xff970000 0x0 0x8000>;
1554                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1555                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1556                 clock-names = "dp", "pclk";
1557                 resets = <&cru SRST_P_EDP_CTRL>;
1558                 reset-names = "dp";
1559                 rockchip,grf = <&grf>;
1560                 status = "disabled";
1561                 pinctrl-names = "default";
1562                 pinctrl-0 = <&edp_hpd>;
1563
1564                 ports {
1565                         #address-cells = <1>;
1566                         #size-cells = <0>;
1567
1568                         edp_in: port@0 {
1569                                 reg = <0>;
1570                                 #address-cells = <1>;
1571                                 #size-cells = <0>;
1572
1573                                 edp_in_vopb: endpoint@0 {
1574                                         reg = <0>;
1575                                         remote-endpoint = <&vopb_out_edp>;
1576                                 };
1577
1578                                 edp_in_vopl: endpoint@1 {
1579                                         reg = <1>;
1580                                         remote-endpoint = <&vopl_out_edp>;
1581                                 };
1582                         };
1583                 };
1584         };
1585
1586         display_subsystem: display-subsystem {
1587                 compatible = "rockchip,display-subsystem";
1588                 ports = <&vopl_out>, <&vopb_out>;
1589                 status = "disabled";
1590         };
1591
1592         pinctrl: pinctrl {
1593                 compatible = "rockchip,rk3399-pinctrl";
1594                 rockchip,grf = <&grf>;
1595                 rockchip,pmu = <&pmugrf>;
1596                 #address-cells = <0x2>;
1597                 #size-cells = <0x2>;
1598                 ranges;
1599
1600                 gpio0: gpio0@ff720000 {
1601                         compatible = "rockchip,gpio-bank";
1602                         reg = <0x0 0xff720000 0x0 0x100>;
1603                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1604                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1605
1606                         gpio-controller;
1607                         #gpio-cells = <0x2>;
1608
1609                         interrupt-controller;
1610                         #interrupt-cells = <0x2>;
1611                 };
1612
1613                 gpio1: gpio1@ff730000 {
1614                         compatible = "rockchip,gpio-bank";
1615                         reg = <0x0 0xff730000 0x0 0x100>;
1616                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1617                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1618
1619                         gpio-controller;
1620                         #gpio-cells = <0x2>;
1621
1622                         interrupt-controller;
1623                         #interrupt-cells = <0x2>;
1624                 };
1625
1626                 gpio2: gpio2@ff780000 {
1627                         compatible = "rockchip,gpio-bank";
1628                         reg = <0x0 0xff780000 0x0 0x100>;
1629                         clocks = <&cru PCLK_GPIO2>;
1630                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1631
1632                         gpio-controller;
1633                         #gpio-cells = <0x2>;
1634
1635                         interrupt-controller;
1636                         #interrupt-cells = <0x2>;
1637                 };
1638
1639                 gpio3: gpio3@ff788000 {
1640                         compatible = "rockchip,gpio-bank";
1641                         reg = <0x0 0xff788000 0x0 0x100>;
1642                         clocks = <&cru PCLK_GPIO3>;
1643                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1644
1645                         gpio-controller;
1646                         #gpio-cells = <0x2>;
1647
1648                         interrupt-controller;
1649                         #interrupt-cells = <0x2>;
1650                 };
1651
1652                 gpio4: gpio4@ff790000 {
1653                         compatible = "rockchip,gpio-bank";
1654                         reg = <0x0 0xff790000 0x0 0x100>;
1655                         clocks = <&cru PCLK_GPIO4>;
1656                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1657
1658                         gpio-controller;
1659                         #gpio-cells = <0x2>;
1660
1661                         interrupt-controller;
1662                         #interrupt-cells = <0x2>;
1663                 };
1664
1665                 pcfg_pull_up: pcfg-pull-up {
1666                         bias-pull-up;
1667                 };
1668
1669                 pcfg_pull_down: pcfg-pull-down {
1670                         bias-pull-down;
1671                 };
1672
1673                 pcfg_pull_none: pcfg-pull-none {
1674                         bias-disable;
1675                 };
1676
1677                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1678                         bias-pull-up;
1679                         drive-strength = <20>;
1680                 };
1681
1682                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1683                         bias-disable;
1684                         drive-strength = <20>;
1685                 };
1686
1687                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1688                         bias-disable;
1689                         drive-strength = <18>;
1690                 };
1691
1692                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1693                         bias-disable;
1694                         drive-strength = <12>;
1695                 };
1696
1697                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1698                         bias-pull-up;
1699                         drive-strength = <8>;
1700                 };
1701
1702                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1703                         bias-pull-down;
1704                         drive-strength = <4>;
1705                 };
1706
1707                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1708                         bias-pull-up;
1709                         drive-strength = <2>;
1710                 };
1711
1712                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1713                         bias-pull-down;
1714                         drive-strength = <12>;
1715                 };
1716
1717                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1718                         bias-disable;
1719                         drive-strength = <13>;
1720                 };
1721
1722                 emmc {
1723                         emmc_pwr: emmc-pwr {
1724                                 rockchip,pins =
1725                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1726                         };
1727                 };
1728
1729                 gmac {
1730                         rgmii_pins: rgmii-pins {
1731                                 rockchip,pins =
1732                                         /* mac_txclk */
1733                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1734                                         /* mac_rxclk */
1735                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1736                                         /* mac_mdio */
1737                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1738                                         /* mac_txen */
1739                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1740                                         /* mac_clk */
1741                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1742                                         /* mac_rxdv */
1743                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1744                                         /* mac_mdc */
1745                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1746                                         /* mac_rxd1 */
1747                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1748                                         /* mac_rxd0 */
1749                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1750                                         /* mac_txd1 */
1751                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1752                                         /* mac_txd0 */
1753                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1754                                         /* mac_rxd3 */
1755                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1756                                         /* mac_rxd2 */
1757                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1758                                         /* mac_txd3 */
1759                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1760                                         /* mac_txd2 */
1761                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1762                         };
1763
1764                         rmii_pins: rmii-pins {
1765                                 rockchip,pins =
1766                                         /* mac_mdio */
1767                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1768                                         /* mac_txen */
1769                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1770                                         /* mac_clk */
1771                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1772                                         /* mac_rxer */
1773                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1774                                         /* mac_rxdv */
1775                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1776                                         /* mac_mdc */
1777                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1778                                         /* mac_rxd1 */
1779                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1780                                         /* mac_rxd0 */
1781                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1782                                         /* mac_txd1 */
1783                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1784                                         /* mac_txd0 */
1785                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1786                         };
1787                 };
1788
1789                 i2c0 {
1790                         i2c0_xfer: i2c0-xfer {
1791                                 rockchip,pins =
1792                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1793                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1794                         };
1795                 };
1796
1797                 i2c1 {
1798                         i2c1_xfer: i2c1-xfer {
1799                                 rockchip,pins =
1800                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1801                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1802                         };
1803                 };
1804
1805                 i2c2 {
1806                         i2c2_xfer: i2c2-xfer {
1807                                 rockchip,pins =
1808                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1809                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1810                         };
1811                 };
1812
1813                 i2c3 {
1814                         i2c3_xfer: i2c3-xfer {
1815                                 rockchip,pins =
1816                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1817                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1818                         };
1819
1820                         i2c3_gpio: i2c3_gpio {
1821                                 rockchip,pins =
1822                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1823                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1824                         };
1825
1826                 };
1827
1828                 i2c4 {
1829                         i2c4_xfer: i2c4-xfer {
1830                                 rockchip,pins =
1831                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1832                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1833                         };
1834                 };
1835
1836                 i2c5 {
1837                         i2c5_xfer: i2c5-xfer {
1838                                 rockchip,pins =
1839                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1840                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1841                         };
1842                 };
1843
1844                 i2c6 {
1845                         i2c6_xfer: i2c6-xfer {
1846                                 rockchip,pins =
1847                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1848                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1849                         };
1850                 };
1851
1852                 i2c7 {
1853                         i2c7_xfer: i2c7-xfer {
1854                                 rockchip,pins =
1855                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1856                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1857                         };
1858                 };
1859
1860                 i2c8 {
1861                         i2c8_xfer: i2c8-xfer {
1862                                 rockchip,pins =
1863                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1864                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1865                         };
1866                 };
1867
1868                 i2s0 {
1869                         i2s0_8ch_bus: i2s0-8ch-bus {
1870                                 rockchip,pins =
1871                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1872                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1873                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1874                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1875                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1876                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1877                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1878                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1879                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1880                         };
1881                 };
1882
1883                 i2s1 {
1884                         i2s1_2ch_bus: i2s1-2ch-bus {
1885                                 rockchip,pins =
1886                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1887                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1888                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1889                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1890                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1891                         };
1892                 };
1893
1894                 sdio0 {
1895                         sdio0_bus1: sdio0-bus1 {
1896                                 rockchip,pins =
1897                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1898                         };
1899
1900                         sdio0_bus4: sdio0-bus4 {
1901                                 rockchip,pins =
1902                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1903                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1904                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1905                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1906                         };
1907
1908                         sdio0_cmd: sdio0-cmd {
1909                                 rockchip,pins =
1910                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1911                         };
1912
1913                         sdio0_clk: sdio0-clk {
1914                                 rockchip,pins =
1915                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1916                         };
1917
1918                         sdio0_cd: sdio0-cd {
1919                                 rockchip,pins =
1920                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1921                         };
1922
1923                         sdio0_pwr: sdio0-pwr {
1924                                 rockchip,pins =
1925                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1926                         };
1927
1928                         sdio0_bkpwr: sdio0-bkpwr {
1929                                 rockchip,pins =
1930                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1931                         };
1932
1933                         sdio0_wp: sdio0-wp {
1934                                 rockchip,pins =
1935                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1936                         };
1937
1938                         sdio0_int: sdio0-int {
1939                                 rockchip,pins =
1940                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1941                         };
1942                 };
1943
1944                 sdmmc {
1945                         sdmmc_bus1: sdmmc-bus1 {
1946                                 rockchip,pins =
1947                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1948                         };
1949
1950                         sdmmc_bus4: sdmmc-bus4 {
1951                                 rockchip,pins =
1952                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1953                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1954                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1955                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1956                         };
1957
1958                         sdmmc_clk: sdmmc-clk {
1959                                 rockchip,pins =
1960                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1961                         };
1962
1963                         sdmmc_cmd: sdmmc-cmd {
1964                                 rockchip,pins =
1965                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1966                         };
1967
1968                         sdmmc_cd: sdmcc-cd {
1969                                 rockchip,pins =
1970                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1971                         };
1972
1973                         sdmmc_wp: sdmmc-wp {
1974                                 rockchip,pins =
1975                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1976                         };
1977                 };
1978
1979                 spdif {
1980                         spdif_bus: spdif-bus {
1981                                 rockchip,pins =
1982                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1983                         };
1984
1985                         spdif_bus_1: spdif-bus-1 {
1986                                 rockchip,pins =
1987                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
1988                         };
1989                 };
1990
1991                 spi0 {
1992                         spi0_clk: spi0-clk {
1993                                 rockchip,pins =
1994                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1995                         };
1996                         spi0_cs0: spi0-cs0 {
1997                                 rockchip,pins =
1998                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1999                         };
2000                         spi0_cs1: spi0-cs1 {
2001                                 rockchip,pins =
2002                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2003                         };
2004                         spi0_tx: spi0-tx {
2005                                 rockchip,pins =
2006                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2007                         };
2008                         spi0_rx: spi0-rx {
2009                                 rockchip,pins =
2010                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2011                         };
2012                 };
2013
2014                 spi1 {
2015                         spi1_clk: spi1-clk {
2016                                 rockchip,pins =
2017                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2018                         };
2019                         spi1_cs0: spi1-cs0 {
2020                                 rockchip,pins =
2021                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2022                         };
2023                         spi1_rx: spi1-rx {
2024                                 rockchip,pins =
2025                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2026                         };
2027                         spi1_tx: spi1-tx {
2028                                 rockchip,pins =
2029                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2030                         };
2031                 };
2032
2033                 spi2 {
2034                         spi2_clk: spi2-clk {
2035                                 rockchip,pins =
2036                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2037                         };
2038                         spi2_cs0: spi2-cs0 {
2039                                 rockchip,pins =
2040                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2041                         };
2042                         spi2_rx: spi2-rx {
2043                                 rockchip,pins =
2044                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2045                         };
2046                         spi2_tx: spi2-tx {
2047                                 rockchip,pins =
2048                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2049                         };
2050                 };
2051
2052                 spi3 {
2053                         spi3_clk: spi3-clk {
2054                                 rockchip,pins =
2055                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2056                         };
2057                         spi3_cs0: spi3-cs0 {
2058                                 rockchip,pins =
2059                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2060                         };
2061                         spi3_rx: spi3-rx {
2062                                 rockchip,pins =
2063                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2064                         };
2065                         spi3_tx: spi3-tx {
2066                                 rockchip,pins =
2067                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2068                         };
2069                 };
2070
2071                 spi4 {
2072                         spi4_clk: spi4-clk {
2073                                 rockchip,pins =
2074                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2075                         };
2076                         spi4_cs0: spi4-cs0 {
2077                                 rockchip,pins =
2078                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2079                         };
2080                         spi4_rx: spi4-rx {
2081                                 rockchip,pins =
2082                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2083                         };
2084                         spi4_tx: spi4-tx {
2085                                 rockchip,pins =
2086                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2087                         };
2088                 };
2089
2090                 spi5 {
2091                         spi5_clk: spi5-clk {
2092                                 rockchip,pins =
2093                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2094                         };
2095                         spi5_cs0: spi5-cs0 {
2096                                 rockchip,pins =
2097                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2098                         };
2099                         spi5_rx: spi5-rx {
2100                                 rockchip,pins =
2101                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2102                         };
2103                         spi5_tx: spi5-tx {
2104                                 rockchip,pins =
2105                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2106                         };
2107                 };
2108
2109                 tsadc {
2110                         otp_gpio: otp-gpio {
2111                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2112                         };
2113
2114                         otp_out: otp-out {
2115                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2116                         };
2117                 };
2118
2119                 uart0 {
2120                         uart0_xfer: uart0-xfer {
2121                                 rockchip,pins =
2122                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2123                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2124                         };
2125
2126                         uart0_cts: uart0-cts {
2127                                 rockchip,pins =
2128                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2129                         };
2130
2131                         uart0_rts: uart0-rts {
2132                                 rockchip,pins =
2133                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2134                         };
2135                 };
2136
2137                 uart1 {
2138                         uart1_xfer: uart1-xfer {
2139                                 rockchip,pins =
2140                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2141                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2142                         };
2143                 };
2144
2145                 uart2a {
2146                         uart2a_xfer: uart2a-xfer {
2147                                 rockchip,pins =
2148                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2149                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2150                         };
2151                 };
2152
2153                 uart2b {
2154                         uart2b_xfer: uart2b-xfer {
2155                                 rockchip,pins =
2156                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2157                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2158                         };
2159                 };
2160
2161                 uart2c {
2162                         uart2c_xfer: uart2c-xfer {
2163                                 rockchip,pins =
2164                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2165                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2166                         };
2167                 };
2168
2169                 uart3 {
2170                         uart3_xfer: uart3-xfer {
2171                                 rockchip,pins =
2172                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2173                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2174                         };
2175
2176                         uart3_cts: uart3-cts {
2177                                 rockchip,pins =
2178                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2179                         };
2180
2181                         uart3_rts: uart3-rts {
2182                                 rockchip,pins =
2183                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2184                         };
2185                 };
2186
2187                 uart4 {
2188                         uart4_xfer: uart4-xfer {
2189                                 rockchip,pins =
2190                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2191                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2192                         };
2193                 };
2194
2195                 uarthdcp {
2196                         uarthdcp_xfer: uarthdcp-xfer {
2197                                 rockchip,pins =
2198                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2199                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2200                         };
2201                 };
2202
2203                 pwm0 {
2204                         pwm0_pin: pwm0-pin {
2205                                 rockchip,pins =
2206                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2207                         };
2208
2209                         vop0_pwm_pin: vop0-pwm-pin {
2210                                 rockchip,pins =
2211                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2212                         };
2213                 };
2214
2215                 pwm1 {
2216                         pwm1_pin: pwm1-pin {
2217                                 rockchip,pins =
2218                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2219                         };
2220
2221                         vop1_pwm_pin: vop1-pwm-pin {
2222                                 rockchip,pins =
2223                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2224                         };
2225                 };
2226
2227                 pwm2 {
2228                         pwm2_pin: pwm2-pin {
2229                                 rockchip,pins =
2230                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2231                         };
2232                 };
2233
2234                 pwm3a {
2235                         pwm3a_pin: pwm3a-pin {
2236                                 rockchip,pins =
2237                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2238                         };
2239                 };
2240
2241                 pwm3b {
2242                         pwm3b_pin: pwm3b-pin {
2243                                 rockchip,pins =
2244                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2245                         };
2246                 };
2247
2248                 edp {
2249                         edp_hpd: edp-hpd {
2250                                 rockchip,pins =
2251                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2252                         };
2253                 };
2254
2255                 hdmi {
2256                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2257                                 rockchip,pins =
2258                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2259                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2260                         };
2261
2262                         hdmi_cec: hdmi-cec {
2263                                 rockchip,pins =
2264                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2265                         };
2266                 };
2267
2268                 pcie {
2269                         pcie_clkreqn: pci-clkreqn {
2270                                 rockchip,pins =
2271                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2272                         };
2273
2274                         pcie_clkreqnb: pci-clkreqnb {
2275                                 rockchip,pins =
2276                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2277                         };
2278                 };
2279         };
2280 };