arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <900000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <900000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <900000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <900000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <900000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <900000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <900000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <900000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         pmu_a53 {
 225                 compatible = "arm,cortex-a53-pmu";
 226                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 227                 interrupt-affinity = <&cpu_l0>,
 228                                      <&cpu_l1>,
 229                                      <&cpu_l2>,
 230                                      <&cpu_l3>;
 231         };
 232
 233         pmu_a72 {
 234                 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
 235                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 236                 interrupt-affinity = <&cpu_b0>,
 237                                      <&cpu_b1>;
 238         };
 239
 240         xin24m: xin24m {
 241                 compatible = "fixed-clock";
 242                 #clock-cells = <0>;
 243                 clock-frequency = <24000000>;
 244                 clock-output-names = "xin24m";
 245         };
 246
 247         amba {
 248                 compatible = "arm,amba-bus";
 249                 #address-cells = <2>;
 250                 #size-cells = <2>;
 251                 ranges;
 252
 253                 dmac_bus: dma-controller@ff6d0000 {
 254                         compatible = "arm,pl330", "arm,primecell";
 255                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 256                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 258                         #dma-cells = <1>;
 259                         clocks = <&cru ACLK_DMAC0_PERILP>;
 260                         clock-names = "apb_pclk";
 261                 };
 262
 263                 dmac_peri: dma-controller@ff6e0000 {
 264                         compatible = "arm,pl330", "arm,primecell";
 265                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 266                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 268                         #dma-cells = <1>;
 269                         clocks = <&cru ACLK_DMAC1_PERILP>;
 270                         clock-names = "apb_pclk";
 271                 };
 272         };
 273
 274         gmac: eth@fe300000 {
 275                 compatible = "rockchip,rk3399-gmac";
 276                 reg = <0x0 0xfe300000 0x0 0x10000>;
 277                 rockchip,grf = <&grf>;
 278                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 279                 interrupt-names = "macirq";
 280                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 281                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 282                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 283                          <&cru PCLK_GMAC>;
 284                 clock-names = "stmmaceth", "mac_clk_rx",
 285                               "mac_clk_tx", "clk_mac_ref",
 286                               "clk_mac_refout", "aclk_mac",
 287                               "pclk_mac";
 288                 resets = <&cru SRST_A_GMAC>;
 289                 reset-names = "stmmaceth";
 290                 status = "disabled";
 291         };
 292
 293         emmc_phy: phy {
 294                 compatible = "rockchip,rk3399-emmc-phy";
 295                 reg-offset = <0xf780>;
 296                 #phy-cells = <0>;
 297                 rockchip,grf = <&grf>;
 298                 status = "disabled";
 299         };
 300
 301         sdio0: dwmmc@fe310000 {
 302                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 303                 reg = <0x0 0xfe310000 0x0 0x4000>;
 304                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 305                 clock-freq-min-max = <400000 150000000>;
 306                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 307                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 308                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 309                 fifo-depth = <0x100>;
 310                 status = "disabled";
 311         };
 312
 313         sdmmc: dwmmc@fe320000 {
 314                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 315                 reg = <0x0 0xfe320000 0x0 0x4000>;
 316                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 317                 clock-freq-min-max = <400000 150000000>;
 318                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 319                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 320                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 321                 fifo-depth = <0x100>;
 322                 status = "disabled";
 323         };
 324
 325         sdhci: sdhci@fe330000 {
 326                 compatible = "arasan,sdhci-5.1";
 327                 reg = <0x0 0xfe330000 0x0 0x10000>;
 328                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 330                 clock-names = "clk_xin", "clk_ahb";
 331                 phys = <&emmc_phy>;
 332                 phy-names = "phy_arasan";
 333                 status = "disabled";
 334         };
 335
 336         usb_host0_echi: usb@fe380000 {
 337                 compatible = "generic-ehci";
 338                 reg = <0x0 0xfe380000 0x0 0x20000>;
 339                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&cru HCLK_HOST0>;
 341                 clock-names = "hclk_host0";
 342                 status = "disabled";
 343         };
 344
 345         usb_host0_ohci: usb@fe3a0000 {
 346                 compatible = "generic-ohci";
 347                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 348                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&cru HCLK_HOST0>;
 350                 clock-names = "hclk_host0";
 351                 status = "disabled";
 352         };
 353
 354         usb_host1_echi: usb@fe3c0000 {
 355                 compatible = "generic-ehci";
 356                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 357                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&cru HCLK_HOST1>;
 359                 clock-names = "hclk_host1";
 360                 status = "disabled";
 361         };
 362
 363         usb_host1_ohci: usb@fe3e0000 {
 364                 compatible = "generic-ohci";
 365                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 366                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&cru HCLK_HOST1>;
 368                 clock-names = "hclk_host1";
 369                 status = "disabled";
 370         };
 371
 372         usbdrd3_0: usb@fe800000 {
 373                 compatible = "rockchip,dwc3";
 374                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 375                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 376                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 377                          <&cru ACLK_USB3_GRF>;
 378                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 379                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 380                               "aclk_usb3", "aclk_usb3_noc",
 381                               "aclk_usb3_grf";
 382                 #address-cells = <2>;
 383                 #size-cells = <2>;
 384                 ranges;
 385                 status = "disabled";
 386                 usbdrd_dwc3_0: dwc3 {
 387                         compatible = "snps,dwc3";
 388                         reg = <0x0 0xfe800000 0x0 0x100000>;
 389                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 390                         dr_mode = "otg";
 391                         tx-fifo-resize;
 392                         snps,dis_enblslpm_quirk;
 393                         snps,phyif_utmi_16_bits;
 394                         snps,dis_u2_freeclk_exists_quirk;
 395                         snps,dis_del_phy_power_chg_quirk;
 396                         status = "disabled";
 397                 };
 398         };
 399
 400         usbdrd3_1: usb@fe900000 {
 401                 compatible = "rockchip,dwc3";
 402                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 403                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 404                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 405                          <&cru ACLK_USB3_GRF>;
 406                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 407                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 408                               "aclk_usb3", "aclk_usb3_noc",
 409                               "aclk_usb3_grf";
 410                 #address-cells = <2>;
 411                 #size-cells = <2>;
 412                 ranges;
 413                 status = "disabled";
 414                 usbdrd_dwc3_1: dwc3 {
 415                         compatible = "snps,dwc3";
 416                         reg = <0x0 0xfe900000 0x0 0x100000>;
 417                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 418                         dr_mode = "otg";
 419                         tx-fifo-resize;
 420                         snps,dis_enblslpm_quirk;
 421                         snps,phyif_utmi_16_bits;
 422                         snps,dis_u2_freeclk_exists_quirk;
 423                         snps,dis_del_phy_power_chg_quirk;
 424                         status = "disabled";
 425                 };
 426         };
 427
 428         gic: interrupt-controller@fee00000 {
 429                 compatible = "arm,gic-v3";
 430                 #interrupt-cells = <3>;
 431                 #address-cells = <2>;
 432                 #size-cells = <2>;
 433                 ranges;
 434                 interrupt-controller;
 435
 436                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 437                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 438                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 439                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 440                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 441                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 442                 its: interrupt-controller@fee20000 {
 443                         compatible = "arm,gic-v3-its";
 444                         msi-controller;
 445                         reg = <0x0 0xfee20000 0x0 0x20000>;
 446                 };
 447         };
 448
 449         saradc: saradc@ff100000 {
 450                 compatible = "rockchip,rk3399-saradc";
 451                 reg = <0x0 0xff100000 0x0 0x100>;
 452                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 453                 #io-channel-cells = <1>;
 454                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 455                 clock-names = "saradc", "apb_pclk";
 456                 status = "disabled";
 457         };
 458
 459         i2c0: i2c@ff3c0000 {
 460                 compatible = "rockchip,rk3399-i2c";
 461                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 462                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 463                 clock-names = "i2c", "pclk";
 464                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 465                 pinctrl-names = "default";
 466                 pinctrl-0 = <&i2c0_xfer>;
 467                 #address-cells = <1>;
 468                 #size-cells = <0>;
 469                 status = "disabled";
 470         };
 471
 472         i2c1: i2c@ff110000 {
 473                 compatible = "rockchip,rk3399-i2c";
 474                 reg = <0x0 0xff110000 0x0 0x1000>;
 475                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 476                 clock-names = "i2c", "pclk";
 477                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&i2c1_xfer>;
 480                 #address-cells = <1>;
 481                 #size-cells = <0>;
 482                 status = "disabled";
 483         };
 484
 485         i2c2: i2c@ff120000 {
 486                 compatible = "rockchip,rk3399-i2c";
 487                 reg = <0x0 0xff120000 0x0 0x1000>;
 488                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 489                 clock-names = "i2c", "pclk";
 490                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&i2c2_xfer>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 status = "disabled";
 496         };
 497
 498         i2c3: i2c@ff130000 {
 499                 compatible = "rockchip,rk3399-i2c";
 500                 reg = <0x0 0xff130000 0x0 0x1000>;
 501                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 502                 clock-names = "i2c", "pclk";
 503                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&i2c3_xfer>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 status = "disabled";
 509         };
 510
 511         i2c5: i2c@ff140000 {
 512                 compatible = "rockchip,rk3399-i2c";
 513                 reg = <0x0 0xff140000 0x0 0x1000>;
 514                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 515                 clock-names = "i2c", "pclk";
 516                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&i2c5_xfer>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 status = "disabled";
 522         };
 523
 524         i2c6: i2c@ff150000 {
 525                 compatible = "rockchip,rk3399-i2c";
 526                 reg = <0x0 0xff150000 0x0 0x1000>;
 527                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 528                 clock-names = "i2c", "pclk";
 529                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&i2c6_xfer>;
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 status = "disabled";
 535         };
 536
 537         i2c7: i2c@ff160000 {
 538                 compatible = "rockchip,rk3399-i2c";
 539                 reg = <0x0 0xff160000 0x0 0x1000>;
 540                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 541                 clock-names = "i2c", "pclk";
 542                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&i2c7_xfer>;
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 status = "disabled";
 548         };
 549
 550         uart0: serial@ff180000 {
 551                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 552                 reg = <0x0 0xff180000 0x0 0x100>;
 553                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 554                 clock-names = "baudclk", "apb_pclk";
 555                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 556                 reg-shift = <2>;
 557                 reg-io-width = <4>;
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 560                 status = "disabled";
 561         };
 562
 563         uart1: serial@ff190000 {
 564                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 565                 reg = <0x0 0xff190000 0x0 0x100>;
 566                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 567                 clock-names = "baudclk", "apb_pclk";
 568                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 569                 reg-shift = <2>;
 570                 reg-io-width = <4>;
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&uart1_xfer>;
 573                 status = "disabled";
 574         };
 575
 576         uart2: serial@ff1a0000 {
 577                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 578                 reg = <0x0 0xff1a0000 0x0 0x100>;
 579                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 580                 clock-names = "baudclk", "apb_pclk";
 581                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 582                 reg-shift = <2>;
 583                 reg-io-width = <4>;
 584                 pinctrl-names = "default";
 585                 pinctrl-0 = <&uart2c_xfer>;
 586                 status = "disabled";
 587         };
 588
 589         uart3: serial@ff1b0000 {
 590                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 591                 reg = <0x0 0xff1b0000 0x0 0x100>;
 592                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 593                 clock-names = "baudclk", "apb_pclk";
 594                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 595                 reg-shift = <2>;
 596                 reg-io-width = <4>;
 597                 pinctrl-names = "default";
 598                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 599                 status = "disabled";
 600         };
 601
 602         spi0: spi@ff1c0000 {
 603                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 604                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 605                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 606                 clock-names = "spiclk", "apb_pclk";
 607                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 608                 pinctrl-names = "default";
 609                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 status = "disabled";
 613         };
 614
 615         spi1: spi@ff1d0000 {
 616                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 617                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 618                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 619                 clock-names = "spiclk", "apb_pclk";
 620                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 status = "disabled";
 626         };
 627
 628         spi2: spi@ff1e0000 {
 629                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 630                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 631                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 632                 clock-names = "spiclk", "apb_pclk";
 633                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 status = "disabled";
 639         };
 640
 641         spi4: spi@ff1f0000 {
 642                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 643                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 644                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 645                 clock-names = "spiclk", "apb_pclk";
 646                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 649                 #address-cells = <1>;
 650                 #size-cells = <0>;
 651                 status = "disabled";
 652         };
 653
 654         spi5: spi@ff200000 {
 655                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 656                 reg = <0x0 0xff200000 0x0 0x1000>;
 657                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 658                 clock-names = "spiclk", "apb_pclk";
 659                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 660                 pinctrl-names = "default";
 661                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 status = "disabled";
 665         };
 666
 667         thermal-zones {
 668                 #include "rk3368-thermal.dtsi"
 669         };
 670
 671         tsadc: tsadc@ff260000 {
 672                 compatible = "rockchip,rk3399-tsadc";
 673                 reg = <0x0 0xff260000 0x0 0x100>;
 674                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 675                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 676                 clock-names = "tsadc", "apb_pclk";
 677                 resets = <&cru SRST_TSADC>;
 678                 reset-names = "tsadc-apb";
 679                 pinctrl-names = "init", "default", "sleep";
 680                 pinctrl-0 = <&otp_gpio>;
 681                 pinctrl-1 = <&otp_out>;
 682                 pinctrl-2 = <&otp_gpio>;
 683                 #thermal-sensor-cells = <1>;
 684                 rockchip,hw-tshut-temp = <95000>;
 685                 status = "disabled";
 686         };
 687
 688         pmu: power-management@ff31000 {
 689                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 690                 reg = <0x0 0xff310000 0x0 0x1000>;
 691
 692                 power: power-controller {
 693                         status = "disabled";
 694                         compatible = "rockchip,rk3399-power-controller";
 695                         #power-domain-cells = <1>;
 696                         #address-cells = <1>;
 697                         #size-cells = <0>;
 698
 699                         pd_center {
 700                                 reg = <RK3399_PD_CENTER>;
 701                                 #address-cells = <1>;
 702                                 #size-cells = <0>;
 703
 704                                 pd_vdu {
 705                                         reg = <RK3399_PD_VDU>;
 706                                 };
 707                                 pd_vcodec {
 708                                         reg = <RK3399_PD_VCODEC>;
 709                                 };
 710                                 pd_iep {
 711                                         reg = <RK3399_PD_IEP>;
 712                                 };
 713                                 pd_rga {
 714                                         reg = <RK3399_PD_RGA>;
 715                                 };
 716                         };
 717                         pd_vio {
 718                                 reg = <RK3399_PD_VIO>;
 719                                 #address-cells = <1>;
 720                                 #size-cells = <0>;
 721
 722                                 pd_isp0 {
 723                                         reg = <RK3399_PD_ISP0>;
 724                                 };
 725                                 pd_isp1 {
 726                                         reg = <RK3399_PD_ISP1>;
 727                                 };
 728                                 pd_hdcp {
 729                                         reg = <RK3399_PD_HDCP>;
 730                                 };
 731                                 pd_vo {
 732                                         reg = <RK3399_PD_VO>;
 733                                         #address-cells = <1>;
 734                                         #size-cells = <0>;
 735
 736                                         pd_vopb {
 737                                                 reg = <RK3399_PD_VOPB>;
 738                                         };
 739                                         pd_vopl {
 740                                                 reg = <RK3399_PD_VOPL>;
 741                                         };
 742                                 };
 743                         };
 744                         pd_gpu {
 745                                 reg = <RK3399_PD_GPU>;
 746                         };
 747                 };
 748         };
 749
 750         pmugrf: syscon@ff320000 {
 751                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 752                 reg = <0x0 0xff320000 0x0 0x1000>;
 753         };
 754
 755         spi3: spi@ff350000 {
 756                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 757                 reg = <0x0 0xff350000 0x0 0x1000>;
 758                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 759                 clock-names = "spiclk", "apb_pclk";
 760                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 761                 pinctrl-names = "default";
 762                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 763                 #address-cells = <1>;
 764                 #size-cells = <0>;
 765                 status = "disabled";
 766         };
 767
 768         uart4: serial@ff370000 {
 769                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 770                 reg = <0x0 0xff370000 0x0 0x100>;
 771                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 772                 clock-names = "baudclk", "apb_pclk";
 773                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 774                 reg-shift = <2>;
 775                 reg-io-width = <4>;
 776                 pinctrl-names = "default";
 777                 pinctrl-0 = <&uart4_xfer>;
 778                 status = "disabled";
 779         };
 780
 781         i2c4: i2c@ff3d0000 {
 782                 compatible = "rockchip,rk3399-i2c";
 783                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 784                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 785                 clock-names = "i2c", "pclk";
 786                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 787                 pinctrl-names = "default";
 788                 pinctrl-0 = <&i2c4_xfer>;
 789                 #address-cells = <1>;
 790                 #size-cells = <0>;
 791                 status = "disabled";
 792         };
 793
 794         i2c8: i2c@ff3e0000 {
 795                 compatible = "rockchip,rk3399-i2c";
 796                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 797                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 798                 clock-names = "i2c", "pclk";
 799                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 800                 pinctrl-names = "default";
 801                 pinctrl-0 = <&i2c8_xfer>;
 802                 #address-cells = <1>;
 803                 #size-cells = <0>;
 804                 status = "disabled";
 805         };
 806
 807         pwm0: pwm@ff420000 {
 808                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 809                 reg = <0x0 0xff420000 0x0 0x10>;
 810                 #pwm-cells = <3>;
 811                 pinctrl-names = "default";
 812                 pinctrl-0 = <&pwm0_pin>;
 813                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 814                 clock-names = "pwm";
 815                 status = "disabled";
 816         };
 817
 818         pwm1: pwm@ff420010 {
 819                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 820                 reg = <0x0 0xff420010 0x0 0x10>;
 821                 #pwm-cells = <3>;
 822                 pinctrl-names = "default";
 823                 pinctrl-0 = <&pwm1_pin>;
 824                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 825                 clock-names = "pwm";
 826                 status = "disabled";
 827         };
 828
 829         pwm2: pwm@ff420020 {
 830                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 831                 reg = <0x0 0xff420020 0x0 0x10>;
 832                 #pwm-cells = <3>;
 833                 pinctrl-names = "default";
 834                 pinctrl-0 = <&pwm2_pin>;
 835                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 836                 clock-names = "pwm";
 837                 status = "disabled";
 838         };
 839
 840         pwm3: pwm@ff420030 {
 841                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 842                 reg = <0x0 0xff420030 0x0 0x10>;
 843                 #pwm-cells = <3>;
 844                 pinctrl-names = "default";
 845                 pinctrl-0 = <&pwm3a_pin>;
 846                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 847                 clock-names = "pwm";
 848                 status = "disabled";
 849         };
 850
 851         pmucru: pmu-clock-controller@ff750000 {
 852                 compatible = "rockchip,rk3399-pmucru";
 853                 reg = <0x0 0xff750000 0x0 0x1000>;
 854                 rockchip,grf = <&pmugrf>;
 855                 #clock-cells = <1>;
 856                 #reset-cells = <1>;
 857                 assigned-clocks = <&pmucru PLL_PPLL>;
 858                 assigned-clock-rates = <676000000>;
 859         };
 860
 861         cru: clock-controller@ff760000 {
 862                 compatible = "rockchip,rk3399-cru";
 863                 reg = <0x0 0xff760000 0x0 0x1000>;
 864                 rockchip,grf = <&grf>;
 865                 #clock-cells = <1>;
 866                 #reset-cells = <1>;
 867                 assigned-clocks =
 868                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 869                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 870                         <&cru PLL_NPLL>,
 871                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 872                         <&cru PCLK_PERIHP>,
 873                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 874                         <&cru PCLK_PERILP0>,
 875                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 876                 assigned-clock-rates =
 877                          <816000000>, <1008000000>,
 878                          <594000000>,  <800000000>,
 879                         <1000000000>,
 880                          <150000000>,   <75000000>,
 881                           <37500000>,
 882                          <100000000>,  <100000000>,
 883                           <50000000>,
 884                          <100000000>,   <50000000>;
 885         };
 886
 887         grf: syscon@ff770000 {
 888                 compatible = "rockchip,rk3399-grf", "syscon";
 889                 reg = <0x0 0xff770000 0x0 0x10000>;
 890         };
 891
 892         wdt0: watchdog@ff840000 {
 893                 compatible = "snps,dw-wdt";
 894                 reg = <0x0 0xff840000 0x0 0x100>;
 895                 clocks = <&cru PCLK_WDT>;
 896                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 897                 status = "disabled";
 898         };
 899
 900         spdif: spdif@ff870000 {
 901                 compatible = "rockchip,rk3399-spdif";
 902                 reg = <0x0 0xff870000 0x0 0x1000>;
 903                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 904                 dmas = <&dmac_bus 7>;
 905                 dma-names = "tx";
 906                 clock-names = "hclk", "mclk";
 907                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 908                 pinctrl-names = "default";
 909                 pinctrl-0 = <&spdif_bus>;
 910                 status = "disabled";
 911         };
 912
 913         i2s0: i2s@ff880000 {
 914                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 915                 reg = <0x0 0xff880000 0x0 0x1000>;
 916                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 917                 #address-cells = <1>;
 918                 #size-cells = <0>;
 919                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 920                 dma-names = "tx", "rx";
 921                 clock-names = "i2s_hclk", "i2s_clk";
 922                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 923                 pinctrl-names = "default";
 924                 pinctrl-0 = <&i2s0_8ch_bus>;
 925                 status = "disabled";
 926         };
 927
 928         i2s1: i2s@ff890000 {
 929                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 930                 reg = <0x0 0xff890000 0x0 0x1000>;
 931                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 932                 #address-cells = <1>;
 933                 #size-cells = <0>;
 934                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 935                 dma-names = "tx", "rx";
 936                 clock-names = "i2s_hclk", "i2s_clk";
 937                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 938                 pinctrl-names = "default";
 939                 pinctrl-0 = <&i2s1_2ch_bus>;
 940                 status = "disabled";
 941         };
 942
 943         i2s2: i2s@ff8a0000 {
 944                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 945                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 946                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 947                 #address-cells = <1>;
 948                 #size-cells = <0>;
 949                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 950                 dma-names = "tx", "rx";
 951                 clock-names = "i2s_hclk", "i2s_clk";
 952                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 953                 status = "disabled";
 954         };
 955
 956         pinctrl: pinctrl {
 957                 compatible = "rockchip,rk3399-pinctrl";
 958                 rockchip,grf = <&grf>;
 959                 rockchip,pmu = <&pmugrf>;
 960                 #address-cells = <0x2>;
 961                 #size-cells = <0x2>;
 962                 ranges;
 963
 964                 gpio0: gpio0@ff720000 {
 965                         compatible = "rockchip,gpio-bank";
 966                         reg = <0x0 0xff720000 0x0 0x100>;
 967                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 968                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 969
 970                         gpio-controller;
 971                         #gpio-cells = <0x2>;
 972
 973                         interrupt-controller;
 974                         #interrupt-cells = <0x2>;
 975                 };
 976
 977                 gpio1: gpio1@ff730000 {
 978                         compatible = "rockchip,gpio-bank";
 979                         reg = <0x0 0xff730000 0x0 0x100>;
 980                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 981                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 982
 983                         gpio-controller;
 984                         #gpio-cells = <0x2>;
 985
 986                         interrupt-controller;
 987                         #interrupt-cells = <0x2>;
 988                 };
 989
 990                 gpio2: gpio2@ff780000 {
 991                         compatible = "rockchip,gpio-bank";
 992                         reg = <0x0 0xff780000 0x0 0x100>;
 993                         clocks = <&cru PCLK_GPIO2>;
 994                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 995
 996                         gpio-controller;
 997                         #gpio-cells = <0x2>;
 998
 999                         interrupt-controller;
1000                         #interrupt-cells = <0x2>;
1001                 };
1002
1003                 gpio3: gpio3@ff788000 {
1004                         compatible = "rockchip,gpio-bank";
1005                         reg = <0x0 0xff788000 0x0 0x100>;
1006                         clocks = <&cru PCLK_GPIO3>;
1007                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1008
1009                         gpio-controller;
1010                         #gpio-cells = <0x2>;
1011
1012                         interrupt-controller;
1013                         #interrupt-cells = <0x2>;
1014                 };
1015
1016                 gpio4: gpio4@ff790000 {
1017                         compatible = "rockchip,gpio-bank";
1018                         reg = <0x0 0xff790000 0x0 0x100>;
1019                         clocks = <&cru PCLK_GPIO4>;
1020                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1021
1022                         gpio-controller;
1023                         #gpio-cells = <0x2>;
1024
1025                         interrupt-controller;
1026                         #interrupt-cells = <0x2>;
1027                 };
1028
1029                 pcfg_pull_up: pcfg-pull-up {
1030                         bias-pull-up;
1031                 };
1032
1033                 pcfg_pull_down: pcfg-pull-down {
1034                         bias-pull-down;
1035                 };
1036
1037                 pcfg_pull_none: pcfg-pull-none {
1038                         bias-disable;
1039                 };
1040
1041                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1042                         bias-disable;
1043                         drive-strength = <12>;
1044                 };
1045
1046                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1047                         bias-pull-up;
1048                         drive-strength = <8>;
1049                 };
1050
1051                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1052                         bias-pull-down;
1053                         drive-strength = <4>;
1054                 };
1055
1056                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1057                         bias-pull-up;
1058                         drive-strength = <2>;
1059                 };
1060
1061                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1062                         bias-pull-down;
1063                         drive-strength = <12>;
1064                 };
1065
1066                 emmc {
1067                         emmc_pwr: emmc-pwr {
1068                                 rockchip,pins =
1069                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1070                         };
1071                 };
1072
1073                 gmac {
1074                         rgmii_pins: rgmii-pins {
1075                                 rockchip,pins =
1076                                         /* mac_txclk */
1077                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1078                                         /* mac_rxclk */
1079                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1080                                         /* mac_mdio */
1081                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1082                                         /* mac_txen */
1083                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1084                                         /* mac_clk */
1085                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1086                                         /* mac_rxdv */
1087                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1088                                         /* mac_mdc */
1089                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1090                                         /* mac_rxd1 */
1091                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1092                                         /* mac_rxd0 */
1093                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1094                                         /* mac_txd1 */
1095                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1096                                         /* mac_txd0 */
1097                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1098                                         /* mac_rxd3 */
1099                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1100                                         /* mac_rxd2 */
1101                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1102                                         /* mac_txd3 */
1103                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1104                                         /* mac_txd2 */
1105                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1106                         };
1107
1108                         rmii_pins: rmii-pins {
1109                                 rockchip,pins =
1110                                         /* mac_mdio */
1111                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1112                                         /* mac_txen */
1113                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1114                                         /* mac_clk */
1115                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1116                                         /* mac_rxer */
1117                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1118                                         /* mac_rxdv */
1119                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1120                                         /* mac_mdc */
1121                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1122                                         /* mac_rxd1 */
1123                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1124                                         /* mac_rxd0 */
1125                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1126                                         /* mac_txd1 */
1127                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1128                                         /* mac_txd0 */
1129                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1130                         };
1131                 };
1132
1133                 i2c0 {
1134                         i2c0_xfer: i2c0-xfer {
1135                                 rockchip,pins =
1136                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1137                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1138                         };
1139                 };
1140
1141                 i2c1 {
1142                         i2c1_xfer: i2c1-xfer {
1143                                 rockchip,pins =
1144                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1145                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1146                         };
1147                 };
1148
1149                 i2c2 {
1150                         i2c2_xfer: i2c2-xfer {
1151                                 rockchip,pins =
1152                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1153                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1154                         };
1155                 };
1156
1157                 i2c3 {
1158                         i2c3_xfer: i2c3-xfer {
1159                                 rockchip,pins =
1160                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1161                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1162                         };
1163                 };
1164
1165                 i2c4 {
1166                         i2c4_xfer: i2c4-xfer {
1167                                 rockchip,pins =
1168                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1169                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 i2c5 {
1174                         i2c5_xfer: i2c5-xfer {
1175                                 rockchip,pins =
1176                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1177                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1178                         };
1179                 };
1180
1181                 i2c6 {
1182                         i2c6_xfer: i2c6-xfer {
1183                                 rockchip,pins =
1184                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1185                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1186                         };
1187                 };
1188
1189                 i2c7 {
1190                         i2c7_xfer: i2c7-xfer {
1191                                 rockchip,pins =
1192                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1193                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1194                         };
1195                 };
1196
1197                 i2c8 {
1198                         i2c8_xfer: i2c8-xfer {
1199                                 rockchip,pins =
1200                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1201                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1202                         };
1203                 };
1204
1205                 i2s0 {
1206                         i2s0_8ch_bus: i2s0-8ch-bus {
1207                                 rockchip,pins =
1208                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1209                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1210                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1211                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1212                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1213                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1214                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1215                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1216                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1217                         };
1218                 };
1219
1220                 i2s1 {
1221                         i2s1_2ch_bus: i2s1-2ch-bus {
1222                                 rockchip,pins =
1223                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1224                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1225                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1226                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1227                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1228                         };
1229                 };
1230
1231                 sdio0 {
1232                         sdio0_bus1: sdio0-bus1 {
1233                                 rockchip,pins =
1234                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1235                         };
1236
1237                         sdio0_bus4: sdio0-bus4 {
1238                                 rockchip,pins =
1239                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1240                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1241                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1242                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1243                         };
1244
1245                         sdio0_cmd: sdio0-cmd {
1246                                 rockchip,pins =
1247                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1248                         };
1249
1250                         sdio0_clk: sdio0-clk {
1251                                 rockchip,pins =
1252                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1253                         };
1254
1255                         sdio0_cd: sdio0-cd {
1256                                 rockchip,pins =
1257                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1258                         };
1259
1260                         sdio0_pwr: sdio0-pwr {
1261                                 rockchip,pins =
1262                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1263                         };
1264
1265                         sdio0_bkpwr: sdio0-bkpwr {
1266                                 rockchip,pins =
1267                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1268                         };
1269
1270                         sdio0_wp: sdio0-wp {
1271                                 rockchip,pins =
1272                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1273                         };
1274
1275                         sdio0_int: sdio0-int {
1276                                 rockchip,pins =
1277                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1278                         };
1279                 };
1280
1281                 sdmmc {
1282                         sdmmc_bus1: sdmmc-bus1 {
1283                                 rockchip,pins =
1284                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1285                         };
1286
1287                         sdmmc_bus4: sdmmc-bus4 {
1288                                 rockchip,pins =
1289                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1290                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1291                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1292                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1293                         };
1294
1295                         sdmmc_clk: sdmmc-clk {
1296                                 rockchip,pins =
1297                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1298                         };
1299
1300                         sdmmc_cmd: sdmmc-cmd {
1301                                 rockchip,pins =
1302                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1303                         };
1304
1305                         sdmmc_cd: sdmcc-cd {
1306                                 rockchip,pins =
1307                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1308                         };
1309
1310                         sdmmc_wp: sdmmc-wp {
1311                                 rockchip,pins =
1312                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1313                         };
1314                 };
1315
1316                 spdif {
1317                         spdif_bus: spdif-bus {
1318                                 rockchip,pins =
1319                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1320                         };
1321                 };
1322
1323                 spi0 {
1324                         spi0_clk: spi0-clk {
1325                                 rockchip,pins =
1326                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1327                         };
1328                         spi0_cs0: spi0-cs0 {
1329                                 rockchip,pins =
1330                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1331                         };
1332                         spi0_cs1: spi0-cs1 {
1333                                 rockchip,pins =
1334                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1335                         };
1336                         spi0_tx: spi0-tx {
1337                                 rockchip,pins =
1338                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1339                         };
1340                         spi0_rx: spi0-rx {
1341                                 rockchip,pins =
1342                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1343                         };
1344                 };
1345
1346                 spi1 {
1347                         spi1_clk: spi1-clk {
1348                                 rockchip,pins =
1349                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1350                         };
1351                         spi1_cs0: spi1-cs0 {
1352                                 rockchip,pins =
1353                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1354                         };
1355                         spi1_rx: spi1-rx {
1356                                 rockchip,pins =
1357                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1358                         };
1359                         spi1_tx: spi1-tx {
1360                                 rockchip,pins =
1361                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1362                         };
1363                 };
1364
1365                 spi2 {
1366                         spi2_clk: spi2-clk {
1367                                 rockchip,pins =
1368                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1369                         };
1370                         spi2_cs0: spi2-cs0 {
1371                                 rockchip,pins =
1372                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1373                         };
1374                         spi2_rx: spi2-rx {
1375                                 rockchip,pins =
1376                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1377                         };
1378                         spi2_tx: spi2-tx {
1379                                 rockchip,pins =
1380                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1381                         };
1382                 };
1383
1384                 spi3 {
1385                         spi3_clk: spi3-clk {
1386                                 rockchip,pins =
1387                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1388                         };
1389                         spi3_cs0: spi3-cs0 {
1390                                 rockchip,pins =
1391                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1392                         };
1393                         spi3_rx: spi3-rx {
1394                                 rockchip,pins =
1395                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1396                         };
1397                         spi3_tx: spi3-tx {
1398                                 rockchip,pins =
1399                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1400                         };
1401                 };
1402
1403                 spi4 {
1404                         spi4_clk: spi4-clk {
1405                                 rockchip,pins =
1406                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1407                         };
1408                         spi4_cs0: spi4-cs0 {
1409                                 rockchip,pins =
1410                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1411                         };
1412                         spi4_rx: spi4-rx {
1413                                 rockchip,pins =
1414                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1415                         };
1416                         spi4_tx: spi4-tx {
1417                                 rockchip,pins =
1418                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1419                         };
1420                 };
1421
1422                 spi5 {
1423                         spi5_clk: spi5-clk {
1424                                 rockchip,pins =
1425                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1426                         };
1427                         spi5_cs0: spi5-cs0 {
1428                                 rockchip,pins =
1429                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1430                         };
1431                         spi5_rx: spi5-rx {
1432                                 rockchip,pins =
1433                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1434                         };
1435                         spi5_tx: spi5-tx {
1436                                 rockchip,pins =
1437                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1438                         };
1439                 };
1440
1441                 tsadc {
1442                         otp_gpio: otp-gpio {
1443                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1444                         };
1445
1446                         otp_out: otp-out {
1447                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1448                         };
1449                 };
1450
1451                 uart0 {
1452                         uart0_xfer: uart0-xfer {
1453                                 rockchip,pins =
1454                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1455                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1456                         };
1457
1458                         uart0_cts: uart0-cts {
1459                                 rockchip,pins =
1460                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1461                         };
1462
1463                         uart0_rts: uart0-rts {
1464                                 rockchip,pins =
1465                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 uart1 {
1470                         uart1_xfer: uart1-xfer {
1471                                 rockchip,pins =
1472                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1473                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1474                         };
1475                 };
1476
1477                 uart2a {
1478                         uart2a_xfer: uart2a-xfer {
1479                                 rockchip,pins =
1480                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1481                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1482                         };
1483                 };
1484
1485                 uart2b {
1486                         uart2b_xfer: uart2b-xfer {
1487                                 rockchip,pins =
1488                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1489                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1490                         };
1491                 };
1492
1493                 uart2c {
1494                         uart2c_xfer: uart2c-xfer {
1495                                 rockchip,pins =
1496                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1497                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1498                         };
1499                 };
1500
1501                 uart3 {
1502                         uart3_xfer: uart3-xfer {
1503                                 rockchip,pins =
1504                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1505                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1506                         };
1507
1508                         uart3_cts: uart3-cts {
1509                                 rockchip,pins =
1510                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1511                         };
1512
1513                         uart3_rts: uart3-rts {
1514                                 rockchip,pins =
1515                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1516                         };
1517                 };
1518
1519                 uart4 {
1520                         uart4_xfer: uart4-xfer {
1521                                 rockchip,pins =
1522                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1523                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1524                         };
1525                 };
1526
1527                 uarthdcp {
1528                         uarthdcp_xfer: uarthdcp-xfer {
1529                                 rockchip,pins =
1530                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1531                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1532                         };
1533                 };
1534
1535                 pwm0 {
1536                         pwm0_pin: pwm0-pin {
1537                                 rockchip,pins =
1538                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1539                         };
1540
1541                         vop0_pwm_pin: vop0-pwm-pin {
1542                                 rockchip,pins =
1543                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1544                         };
1545                 };
1546
1547                 pwm1 {
1548                         pwm1_pin: pwm1-pin {
1549                                 rockchip,pins =
1550                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1551                         };
1552
1553                         vop1_pwm_pin: vop1-pwm-pin {
1554                                 rockchip,pins =
1555                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1556                         };
1557                 };
1558
1559                 pwm2 {
1560                         pwm2_pin: pwm2-pin {
1561                                 rockchip,pins =
1562                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1563                         };
1564                 };
1565
1566                 pwm3a {
1567                         pwm3a_pin: pwm3a-pin {
1568                                 rockchip,pins =
1569                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1570                         };
1571                 };
1572
1573                 pwm3b {
1574                         pwm3b_pin: pwm3b-pin {
1575                                 rockchip,pins =
1576                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1577                         };
1578                 };
1579
1580                 pmic {
1581                         pmic_int_l: pmic-int-l {
1582                                 rockchip,pins =
1583                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1584                         };
1585                 };
1586         };
1587 };