arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <1068>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 261         };
 262
 263         arm-pmu {
 264                 compatible = "arm,armv8-pmuv3";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 266         };
 267
 268         xin24m: xin24m {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <24000000>;
 272                 clock-output-names = "xin24m";
 273         };
 274
 275         amba {
 276                 compatible = "arm,amba-bus";
 277                 #address-cells = <2>;
 278                 #size-cells = <2>;
 279                 ranges;
 280
 281                 dmac_bus: dma-controller@ff6d0000 {
 282                         compatible = "arm,pl330", "arm,primecell";
 283                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 284                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 286                         #dma-cells = <1>;
 287                         clocks = <&cru ACLK_DMAC0_PERILP>;
 288                         clock-names = "apb_pclk";
 289                         peripherals-req-type-burst;
 290                 };
 291
 292                 dmac_peri: dma-controller@ff6e0000 {
 293                         compatible = "arm,pl330", "arm,primecell";
 294                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 295                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 297                         #dma-cells = <1>;
 298                         clocks = <&cru ACLK_DMAC1_PERILP>;
 299                         clock-names = "apb_pclk";
 300                         peripherals-req-type-burst;
 301                 };
 302         };
 303
 304         gmac: eth@fe300000 {
 305                 compatible = "rockchip,rk3399-gmac";
 306                 reg = <0x0 0xfe300000 0x0 0x10000>;
 307                 rockchip,grf = <&grf>;
 308                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 309                 interrupt-names = "macirq";
 310                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 311                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 312                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 313                          <&cru PCLK_GMAC>;
 314                 clock-names = "stmmaceth", "mac_clk_rx",
 315                               "mac_clk_tx", "clk_mac_ref",
 316                               "clk_mac_refout", "aclk_mac",
 317                               "pclk_mac";
 318                 resets = <&cru SRST_A_GMAC>;
 319                 reset-names = "stmmaceth";
 320                 status = "disabled";
 321         };
 322
 323         emmc_phy: phy {
 324                 compatible = "rockchip,rk3399-emmc-phy";
 325                 reg-offset = <0xf780>;
 326                 #phy-cells = <0>;
 327                 rockchip,grf = <&grf>;
 328                 ctrl-base = <0xfe330000>;
 329                 status = "disabled";
 330         };
 331
 332         sdio0: dwmmc@fe310000 {
 333                 compatible = "rockchip,rk3399-dw-mshc",
 334                              "rockchip,rk3288-dw-mshc";
 335                 reg = <0x0 0xfe310000 0x0 0x4000>;
 336                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 339                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 status = "disabled";
 343         };
 344
 345         sdmmc: dwmmc@fe320000 {
 346                 compatible = "rockchip,rk3399-dw-mshc",
 347                              "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xfe320000 0x0 0x4000>;
 349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 350                 clock-freq-min-max = <400000 150000000>;
 351                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 352                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 354                 fifo-depth = <0x100>;
 355                 status = "disabled";
 356         };
 357
 358         sdhci: sdhci@fe330000 {
 359                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 360                 reg = <0x0 0xfe330000 0x0 0x10000>;
 361                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 363                 clock-names = "clk_xin", "clk_ahb";
 364                 assigned-clocks = <&cru SCLK_EMMC>;
 365                 assigned-clock-parents = <&cru PLL_CPLL>;
 366                 assigned-clock-rates = <200000000>;
 367                 phys = <&emmc_phy>;
 368                 phy-names = "phy_arasan";
 369                 status = "disabled";
 370         };
 371
 372         usb2phy: usb2phy {
 373                 compatible = "rockchip,rk3399-usb-phy";
 374                 rockchip,grf = <&grf>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377
 378                 usb2phy0: usb2-phy0 {
 379                         #phy-cells = <0>;
 380                         #clock-cells = <0>;
 381                         reg = <0xe458>;
 382                 };
 383
 384                 usb2phy1: usb2-phy1 {
 385                         #phy-cells = <0>;
 386                         #clock-cells = <0>;
 387                         reg = <0xe468>;
 388                 };
 389         };
 390
 391         usb_host0_ehci: usb@fe380000 {
 392                 compatible = "generic-ehci";
 393                 reg = <0x0 0xfe380000 0x0 0x20000>;
 394                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 396                 clock-names = "hclk_host0", "hclk_host0_arb";
 397                 phys = <&usb2phy0>;
 398                 phy-names = "usb2_phy0";
 399                 status = "disabled";
 400         };
 401
 402         usb_host0_ohci: usb@fe3a0000 {
 403                 compatible = "generic-ohci";
 404                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 405                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 407                 clock-names = "hclk_host0", "hclk_host0_arb";
 408                 status = "disabled";
 409         };
 410
 411         usb_host1_ehci: usb@fe3c0000 {
 412                 compatible = "generic-ehci";
 413                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 416                 clock-names = "hclk_host1", "hclk_host1_arb";
 417                 phys = <&usb2phy1>;
 418                 phy-names = "usb2_phy1";
 419                 status = "disabled";
 420         };
 421
 422         usb_host1_ohci: usb@fe3e0000 {
 423                 compatible = "generic-ohci";
 424                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 425                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 427                 clock-names = "hclk_host1", "hclk_host1_arb";
 428                 status = "disabled";
 429         };
 430
 431         usbdrd3_0: usb@fe800000 {
 432                 compatible = "rockchip,dwc3";
 433                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 434                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 435                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 436                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 437                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 438                               "aclk_usb3", "aclk_usb3_grf";
 439                 #address-cells = <2>;
 440                 #size-cells = <2>;
 441                 ranges;
 442                 status = "disabled";
 443                 usbdrd_dwc3_0: dwc3@fe800000 {
 444                         compatible = "snps,dwc3";
 445                         reg = <0x0 0xfe800000 0x0 0x100000>;
 446                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 447                         dr_mode = "otg";
 448                         snps,dis_enblslpm_quirk;
 449                         snps,phyif_utmi_16_bits;
 450                         snps,dis_u2_freeclk_exists_quirk;
 451                         snps,dis_del_phy_power_chg_quirk;
 452                         snps,xhci_slow_suspend_quirk;
 453                         status = "disabled";
 454                 };
 455         };
 456
 457         usbdrd3_1: usb@fe900000 {
 458                 compatible = "rockchip,dwc3";
 459                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 460                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 461                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 462                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 463                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 464                               "aclk_usb3", "aclk_usb3_grf";
 465                 #address-cells = <2>;
 466                 #size-cells = <2>;
 467                 ranges;
 468                 status = "disabled";
 469                 usbdrd_dwc3_1: dwc3@fe900000 {
 470                         compatible = "snps,dwc3";
 471                         reg = <0x0 0xfe900000 0x0 0x100000>;
 472                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 473                         dr_mode = "otg";
 474                         snps,dis_enblslpm_quirk;
 475                         snps,phyif_utmi_16_bits;
 476                         snps,dis_u2_freeclk_exists_quirk;
 477                         snps,dis_del_phy_power_chg_quirk;
 478                         snps,xhci_slow_suspend_quirk;
 479                         status = "disabled";
 480                 };
 481         };
 482
 483         gic: interrupt-controller@fee00000 {
 484                 compatible = "arm,gic-v3";
 485                 #interrupt-cells = <3>;
 486                 #address-cells = <2>;
 487                 #size-cells = <2>;
 488                 ranges;
 489                 interrupt-controller;
 490
 491                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 492                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 493                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 494                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 495                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 496                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 497                 its: interrupt-controller@fee20000 {
 498                         compatible = "arm,gic-v3-its";
 499                         msi-controller;
 500                         reg = <0x0 0xfee20000 0x0 0x20000>;
 501                 };
 502         };
 503
 504         saradc: saradc@ff100000 {
 505                 compatible = "rockchip,rk3399-saradc";
 506                 reg = <0x0 0xff100000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 508                 #io-channel-cells = <1>;
 509                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 510                 clock-names = "saradc", "apb_pclk";
 511                 status = "disabled";
 512         };
 513
 514         i2c0: i2c@ff3c0000 {
 515                 compatible = "rockchip,rk3399-i2c";
 516                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 517                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 518                 clock-names = "i2c", "pclk";
 519                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c0_xfer>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 status = "disabled";
 525         };
 526
 527         i2c1: i2c@ff110000 {
 528                 compatible = "rockchip,rk3399-i2c";
 529                 reg = <0x0 0xff110000 0x0 0x1000>;
 530                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 531                 clock-names = "i2c", "pclk";
 532                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2c1_xfer>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 status = "disabled";
 538         };
 539
 540         i2c2: i2c@ff120000 {
 541                 compatible = "rockchip,rk3399-i2c";
 542                 reg = <0x0 0xff120000 0x0 0x1000>;
 543                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 544                 clock-names = "i2c", "pclk";
 545                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c2_xfer>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         i2c3: i2c@ff130000 {
 554                 compatible = "rockchip,rk3399-i2c";
 555                 reg = <0x0 0xff130000 0x0 0x1000>;
 556                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 557                 clock-names = "i2c", "pclk";
 558                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c3_xfer>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         i2c5: i2c@ff140000 {
 567                 compatible = "rockchip,rk3399-i2c";
 568                 reg = <0x0 0xff140000 0x0 0x1000>;
 569                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 570                 clock-names = "i2c", "pclk";
 571                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c5_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c6: i2c@ff150000 {
 580                 compatible = "rockchip,rk3399-i2c";
 581                 reg = <0x0 0xff150000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 583                 clock-names = "i2c", "pclk";
 584                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2c6_xfer>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         i2c7: i2c@ff160000 {
 593                 compatible = "rockchip,rk3399-i2c";
 594                 reg = <0x0 0xff160000 0x0 0x1000>;
 595                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 596                 clock-names = "i2c", "pclk";
 597                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&i2c7_xfer>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         uart0: serial@ff180000 {
 606                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 607                 reg = <0x0 0xff180000 0x0 0x100>;
 608                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 609                 clock-names = "baudclk", "apb_pclk";
 610                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 611                 reg-shift = <2>;
 612                 reg-io-width = <4>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 615                 status = "disabled";
 616         };
 617
 618         uart1: serial@ff190000 {
 619                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 620                 reg = <0x0 0xff190000 0x0 0x100>;
 621                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 622                 clock-names = "baudclk", "apb_pclk";
 623                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 624                 reg-shift = <2>;
 625                 reg-io-width = <4>;
 626                 pinctrl-names = "default";
 627                 pinctrl-0 = <&uart1_xfer>;
 628                 status = "disabled";
 629         };
 630
 631         uart2: serial@ff1a0000 {
 632                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 633                 reg = <0x0 0xff1a0000 0x0 0x100>;
 634                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 635                 clock-names = "baudclk", "apb_pclk";
 636                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 637                 reg-shift = <2>;
 638                 reg-io-width = <4>;
 639                 pinctrl-names = "default";
 640                 pinctrl-0 = <&uart2c_xfer>;
 641                 status = "disabled";
 642         };
 643
 644         uart3: serial@ff1b0000 {
 645                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 646                 reg = <0x0 0xff1b0000 0x0 0x100>;
 647                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 648                 clock-names = "baudclk", "apb_pclk";
 649                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 650                 reg-shift = <2>;
 651                 reg-io-width = <4>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 654                 status = "disabled";
 655         };
 656
 657         spi0: spi@ff1c0000 {
 658                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 659                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 660                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 661                 clock-names = "spiclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 status = "disabled";
 668         };
 669
 670         spi1: spi@ff1d0000 {
 671                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 672                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 673                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 674                 clock-names = "spiclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 status = "disabled";
 681         };
 682
 683         spi2: spi@ff1e0000 {
 684                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 685                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 686                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 687                 clock-names = "spiclk", "apb_pclk";
 688                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693                 status = "disabled";
 694         };
 695
 696         spi4: spi@ff1f0000 {
 697                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 698                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 699                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 700                 clock-names = "spiclk", "apb_pclk";
 701                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 704                 #address-cells = <1>;
 705                 #size-cells = <0>;
 706                 status = "disabled";
 707         };
 708
 709         spi5: spi@ff200000 {
 710                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 711                 reg = <0x0 0xff200000 0x0 0x1000>;
 712                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 713                 clock-names = "spiclk", "apb_pclk";
 714                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 status = "disabled";
 720         };
 721
 722         thermal-zones {
 723                 soc_thermal: soc-thermal {
 724                         polling-delay-passive = <20>; /* milliseconds */
 725                         polling-delay = <1000>; /* milliseconds */
 726                         sustainable-power = <1600>; /* milliwatts */
 727
 728                         thermal-sensors = <&tsadc 0>;
 729
 730                         trips {
 731                                 threshold: trip-point@0 {
 732                                         temperature = <70000>; /* millicelsius */
 733                                         hysteresis = <2000>; /* millicelsius */
 734                                         type = "passive";
 735                                 };
 736                                 target: trip-point@1 {
 737                                         temperature = <85000>; /* millicelsius */
 738                                         hysteresis = <2000>; /* millicelsius */
 739                                         type = "passive";
 740                                 };
 741                                 soc_crit: soc-crit {
 742                                         temperature = <95000>; /* millicelsius */
 743                                         hysteresis = <2000>; /* millicelsius */
 744                                         type = "critical";
 745                                 };
 746                         };
 747
 748                         cooling-maps {
 749                                 map0 {
 750                                         trip = <&target>;
 751                                         cooling-device =
 752                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 753                                         contribution = <10240>;
 754                                 };
 755                                 map1 {
 756                                         trip = <&target>;
 757                                         cooling-device =
 758                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 759                                         contribution = <1024>;
 760                                 };
 761                                 map2 {
 762                                         trip = <&target>;
 763                                         cooling-device =
 764                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 765                                         contribution = <10240>;
 766                                 };
 767                         };
 768                 };
 769
 770                 gpu_thermal: gpu-thermal {
 771                         polling-delay-passive = <100>; /* milliseconds */
 772                         polling-delay = <1000>; /* milliseconds */
 773
 774                         thermal-sensors = <&tsadc 1>;
 775                 };
 776         };
 777
 778         tsadc: tsadc@ff260000 {
 779                 compatible = "rockchip,rk3399-tsadc";
 780                 reg = <0x0 0xff260000 0x0 0x100>;
 781                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 782                 rockchip,grf = <&grf>;
 783                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 784                 clock-names = "tsadc", "apb_pclk";
 785                 assigned-clocks = <&cru SCLK_TSADC>;
 786                 assigned-clock-rates = <750000>;
 787                 resets = <&cru SRST_TSADC>;
 788                 reset-names = "tsadc-apb";
 789                 pinctrl-names = "init", "default", "sleep";
 790                 pinctrl-0 = <&otp_gpio>;
 791                 pinctrl-1 = <&otp_out>;
 792                 pinctrl-2 = <&otp_gpio>;
 793                 #thermal-sensor-cells = <1>;
 794                 rockchip,hw-tshut-temp = <95000>;
 795                 status = "disabled";
 796         };
 797
 798         qos_gpu: qos_gpu@ffae0000 {
 799                 compatible = "syscon";
 800                 reg = <0x0 0xffae0000 0x0 0x20>;
 801         };
 802         qos_video_m0: qos_video_m0@ffab8000 {
 803                 compatible = "syscon";
 804                 reg = <0x0 0xffab8000 0x0 0x20>;
 805         };
 806         qos_video_m1_r: qos_video_m1_r@ffac0000 {
 807                 compatible = "syscon";
 808                 reg = <0x0 0xffac0000 0x0 0x20>;
 809         };
 810         qos_video_m1_w: qos_video_m1_w@ffac0080 {
 811                 compatible = "syscon";
 812                 reg = <0x0 0xffac0080 0x0 0x20>;
 813         };
 814         qos_rga_r: qos_rga_r@ffab0000 {
 815                 compatible = "syscon";
 816                 reg = <0x0 0xffab0000 0x0 0x20>;
 817         };
 818         qos_rga_w: qos_rga_w@ffab0080 {
 819                 compatible = "syscon";
 820                 reg = <0x0 0xffab0080 0x0 0x20>;
 821         };
 822         qos_iep: qos_iep@ffa98000 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffa98000 0x0 0x20>;
 825         };
 826         qos_vop_big_r: qos_vop_big_r@ffac8000 {
 827                 compatible = "syscon";
 828                 reg = <0x0 0xffac8000 0x0 0x20>;
 829         };
 830         qos_vop_big_w: qos_vop_big_w@ffac8080 {
 831                 compatible = "syscon";
 832                 reg = <0x0 0xffac8080 0x0 0x20>;
 833         };
 834         qos_vop_little: qos_vop_little@ffad0000 {
 835                 compatible = "syscon";
 836                 reg = <0x0 0xffad0000 0x0 0x20>;
 837         };
 838         qos_isp0_m0: qos_isp0_m0@ffaa0000 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffaa0000 0x0 0x20>;
 841         };
 842         qos_isp0_m1: qos_isp0_m1@ffaa0080 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffaa0080 0x0 0x20>;
 845         };
 846         qos_isp1_m0: qos_isp1_m0@ffaa8000 {
 847                 compatible = "syscon";
 848                 reg = <0x0 0xffaa8000 0x0 0x20>;
 849         };
 850         qos_isp1_m1: qos_isp1_m1@ffaa8080 {
 851                 compatible = "syscon";
 852                 reg = <0x0 0xffaa8080 0x0 0x20>;
 853         };
 854         qos_hdcp: qos_hdcp@ffa90000 {
 855                 compatible = "syscon";
 856                 reg = <0x0 0xffa90000 0x0 0x20>;
 857         };
 858
 859         pmu: power-management@ff310000 {
 860                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 861                 reg = <0x0 0xff310000 0x0 0x1000>;
 862
 863                 power: power-controller {
 864                         status = "okay";
 865                         compatible = "rockchip,rk3399-power-controller";
 866                         #power-domain-cells = <1>;
 867                         #address-cells = <1>;
 868                         #size-cells = <0>;
 869
 870
 871                         pd_vdu {
 872                                 reg = <RK3399_PD_VDU>;
 873                                 clocks = <&cru ACLK_VDU>,
 874                                          <&cru HCLK_VDU>;
 875                                 pm_qos = <&qos_video_m1_r>,
 876                                          <&qos_video_m1_w>;
 877                         };
 878                         pd_vcodec {
 879                                 reg = <RK3399_PD_VCODEC>;
 880                                 clocks = <&cru ACLK_VCODEC>,
 881                                          <&cru HCLK_VCODEC>;
 882                                 pm_qos = <&qos_video_m0>;
 883                         };
 884                         pd_iep {
 885                                 reg = <RK3399_PD_IEP>;
 886                                 clocks = <&cru ACLK_IEP>,
 887                                          <&cru HCLK_IEP>;
 888                                 pm_qos = <&qos_iep>;
 889                         };
 890                         pd_rga {
 891                                 reg = <RK3399_PD_RGA>;
 892                                 clocks = <&cru ACLK_RGA>,
 893                                          <&cru HCLK_RGA>;
 894                                 pm_qos = <&qos_rga_r>,
 895                                          <&qos_rga_w>;
 896                         };
 897                         pd_vio {
 898                                 reg = <RK3399_PD_VIO>;
 899                                 #address-cells = <1>;
 900                                 #size-cells = <0>;
 901
 902                                 pd_isp0 {
 903                                         reg = <RK3399_PD_ISP0>;
 904                                         clocks = <&cru ACLK_ISP0>,
 905                                                  <&cru HCLK_ISP0>;
 906                                         pm_qos = <&qos_isp0_m0>,
 907                                                  <&qos_isp0_m1>;
 908                                 };
 909                                 pd_isp1 {
 910                                         reg = <RK3399_PD_ISP1>;
 911                                         clocks = <&cru ACLK_ISP1>,
 912                                                  <&cru HCLK_ISP1>;
 913                                         pm_qos = <&qos_isp1_m0>,
 914                                                  <&qos_isp1_m1>;
 915                                 };
 916                                 pd_hdcp {
 917                                         reg = <RK3399_PD_HDCP>;
 918                                         clocks = <&cru ACLK_HDCP>,
 919                                                  <&cru HCLK_HDCP>,
 920                                                  <&cru PCLK_HDCP>;
 921                                         pm_qos = <&qos_hdcp>;
 922                                 };
 923                                 pd_vo {
 924                                         reg = <RK3399_PD_VO>;
 925                                         #address-cells = <1>;
 926                                         #size-cells = <0>;
 927
 928                                         pd_vopb {
 929                                                 reg = <RK3399_PD_VOPB>;
 930                                                 clocks = <&cru ACLK_VOP0>,
 931                                                          <&cru HCLK_VOP0>;
 932                                                 pm_qos = <&qos_vop_big_r>,
 933                                                          <&qos_vop_big_w>;
 934                                         };
 935                                         pd_vopl {
 936                                                 reg = <RK3399_PD_VOPL>;
 937                                                 clocks = <&cru ACLK_VOP1>,
 938                                                          <&cru HCLK_VOP1>;
 939                                                 pm_qos = <&qos_vop_little>;
 940                                         };
 941                                 };
 942                         };
 943                         pd_gpu {
 944                                 reg = <RK3399_PD_GPU>;
 945                                 clocks = <&cru ACLK_GPU>;
 946                                 pm_qos = <&qos_gpu>;
 947                         };
 948                 };
 949         };
 950
 951         pmugrf: syscon@ff320000 {
 952                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 953                 reg = <0x0 0xff320000 0x0 0x1000>;
 954
 955                 reboot-mode {
 956                         compatible = "syscon-reboot-mode";
 957                         offset = <0x300>;
 958                         mode-normal = <BOOT_NORMAL>;
 959                         mode-recovery = <BOOT_RECOVERY>;
 960                         mode-bootloader = <BOOT_FASTBOOT>;
 961                         mode-loader = <BOOT_LOADER>;
 962                 };
 963         };
 964
 965         spi3: spi@ff350000 {
 966                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 967                 reg = <0x0 0xff350000 0x0 0x1000>;
 968                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 969                 clock-names = "spiclk", "apb_pclk";
 970                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 971                 pinctrl-names = "default";
 972                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 973                 #address-cells = <1>;
 974                 #size-cells = <0>;
 975                 status = "disabled";
 976         };
 977
 978         uart4: serial@ff370000 {
 979                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 980                 reg = <0x0 0xff370000 0x0 0x100>;
 981                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 982                 clock-names = "baudclk", "apb_pclk";
 983                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 984                 reg-shift = <2>;
 985                 reg-io-width = <4>;
 986                 pinctrl-names = "default";
 987                 pinctrl-0 = <&uart4_xfer>;
 988                 status = "disabled";
 989         };
 990
 991         i2c4: i2c@ff3d0000 {
 992                 compatible = "rockchip,rk3399-i2c";
 993                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 994                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 995                 clock-names = "i2c", "pclk";
 996                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 997                 pinctrl-names = "default";
 998                 pinctrl-0 = <&i2c4_xfer>;
 999                 #address-cells = <1>;
1000                 #size-cells = <0>;
1001                 status = "disabled";
1002         };
1003
1004         i2c8: i2c@ff3e0000 {
1005                 compatible = "rockchip,rk3399-i2c";
1006                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1007                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1008                 clock-names = "i2c", "pclk";
1009                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1010                 pinctrl-names = "default";
1011                 pinctrl-0 = <&i2c8_xfer>;
1012                 #address-cells = <1>;
1013                 #size-cells = <0>;
1014                 status = "disabled";
1015         };
1016
1017         pcie0: pcie@f8000000 {
1018                 compatible = "rockchip,rk3399-pcie";
1019                 #address-cells = <3>;
1020                 #size-cells = <2>;
1021                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1022                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1023                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1024                               "hclk_pcie", "clk_pciephy_ref";
1025                 bus-range = <0x0 0x1>;
1026                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1027                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1028                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1029                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1030                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1031                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1032                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1033                       < 0x0 0xfd000000 0x0 0x1000000 >;
1034                 reg-name = "axi-base", "apb-base";
1035                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1036                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1037                          <&cru SRST_PCIE_PIPE>;
1038                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1039                               "mgmt-sticky-rst", "pipe-rst";
1040                 rockchip,grf = <&grf>;
1041                 pcie-conf = <0xe220>;
1042                 pcie-status = <0xe2a4>;
1043                 pcie-laneoff = <0xe214>;
1044                 msi-parent = <&its>;
1045                 #interrupt-cells = <1>;
1046                 interrupt-map-mask = <0 0 0 7>;
1047                 interrupt-map = <0 0 0 1 &pcie0 1>,
1048                                 <0 0 0 2 &pcie0 2>,
1049                                 <0 0 0 3 &pcie0 3>,
1050                                 <0 0 0 4 &pcie0 4>;
1051                 status = "disabled";
1052                 pcie_intc: interrupt-controller {
1053                         interrupt-controller;
1054                         #address-cells = <0>;
1055                         #interrupt-cells = <1>;
1056                 };
1057         };
1058
1059         pwm0: pwm@ff420000 {
1060                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1061                 reg = <0x0 0xff420000 0x0 0x10>;
1062                 #pwm-cells = <3>;
1063                 pinctrl-names = "default";
1064                 pinctrl-0 = <&pwm0_pin>;
1065                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1066                 clock-names = "pwm";
1067                 status = "disabled";
1068         };
1069
1070         pwm1: pwm@ff420010 {
1071                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1072                 reg = <0x0 0xff420010 0x0 0x10>;
1073                 #pwm-cells = <3>;
1074                 pinctrl-names = "default";
1075                 pinctrl-0 = <&pwm1_pin>;
1076                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1077                 clock-names = "pwm";
1078                 status = "disabled";
1079         };
1080
1081         pwm2: pwm@ff420020 {
1082                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1083                 reg = <0x0 0xff420020 0x0 0x10>;
1084                 #pwm-cells = <3>;
1085                 pinctrl-names = "default";
1086                 pinctrl-0 = <&pwm2_pin>;
1087                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1088                 clock-names = "pwm";
1089                 status = "disabled";
1090         };
1091
1092         pwm3: pwm@ff420030 {
1093                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1094                 reg = <0x0 0xff420030 0x0 0x10>;
1095                 #pwm-cells = <3>;
1096                 pinctrl-names = "default";
1097                 pinctrl-0 = <&pwm3a_pin>;
1098                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1099                 clock-names = "pwm";
1100                 status = "disabled";
1101         };
1102
1103         rga: rga@ff680000 {
1104                 compatible = "rockchip,rk3399-rga";
1105                 reg = <0x0 0xff680000 0x0 0x10000>;
1106                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1107                 interrupt-names = "rga";
1108                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1109                 clock-names = "aclk", "hclk", "sclk";
1110                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1111                 reset-names = "core", "axi", "ahb";
1112                 status = "disabled";
1113         };
1114
1115         pmucru: pmu-clock-controller@ff750000 {
1116                 compatible = "rockchip,rk3399-pmucru";
1117                 reg = <0x0 0xff750000 0x0 0x1000>;
1118                 #clock-cells = <1>;
1119                 #reset-cells = <1>;
1120                 assigned-clocks = <&pmucru PLL_PPLL>;
1121                 assigned-clock-rates = <676000000>;
1122         };
1123
1124         cru: clock-controller@ff760000 {
1125                 compatible = "rockchip,rk3399-cru";
1126                 reg = <0x0 0xff760000 0x0 0x1000>;
1127                 #clock-cells = <1>;
1128                 #reset-cells = <1>;
1129                 assigned-clocks =
1130                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1131                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1132                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1133                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1134                         <&cru PLL_NPLL>,
1135                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1136                         <&cru PCLK_PERIHP>,
1137                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1138                         <&cru PCLK_PERILP0>,
1139                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1140                 assigned-clock-rates =
1141                          <400000000>,  <200000000>,
1142                          <400000000>,  <200000000>,
1143                          <816000000>, <816000000>,
1144                          <594000000>,  <800000000>,
1145                         <1000000000>,
1146                          <150000000>,   <75000000>,
1147                           <37500000>,
1148                          <100000000>,  <100000000>,
1149                           <50000000>,
1150                          <100000000>,   <50000000>;
1151         };
1152
1153         grf: syscon@ff770000 {
1154                 compatible = "rockchip,rk3399-grf", "syscon";
1155                 reg = <0x0 0xff770000 0x0 0x10000>;
1156         };
1157
1158         watchdog@ff840000 {
1159                 compatible = "snps,dw-wdt";
1160                 reg = <0x0 0xff840000 0x0 0x100>;
1161                 clocks = <&cru PCLK_WDT>;
1162                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1163         };
1164
1165         rktimer: rktimer@ff850000 {
1166                 compatible = "rockchip,rk3399-timer";
1167                 reg = <0x0 0xff850000 0x0 0x1000>;
1168                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1169                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1170                 clock-names = "pclk", "timer";
1171         };
1172
1173         spdif: spdif@ff870000 {
1174                 compatible = "rockchip,rk3399-spdif";
1175                 reg = <0x0 0xff870000 0x0 0x1000>;
1176                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1177                 dmas = <&dmac_bus 7>;
1178                 dma-names = "tx";
1179                 clock-names = "mclk", "hclk";
1180                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1181                 pinctrl-names = "default";
1182                 pinctrl-0 = <&spdif_bus>;
1183                 status = "disabled";
1184         };
1185
1186         i2s0: i2s@ff880000 {
1187                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1188                 reg = <0x0 0xff880000 0x0 0x1000>;
1189                 rockchip,grf = <&grf>;
1190                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1191                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1192                 dma-names = "tx", "rx";
1193                 clock-names = "i2s_clk", "i2s_hclk";
1194                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1195                 pinctrl-names = "default";
1196                 pinctrl-0 = <&i2s0_8ch_bus>;
1197                 status = "disabled";
1198         };
1199
1200         i2s1: i2s@ff890000 {
1201                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1202                 reg = <0x0 0xff890000 0x0 0x1000>;
1203                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1204                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1205                 dma-names = "tx", "rx";
1206                 clock-names = "i2s_clk", "i2s_hclk";
1207                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1208                 pinctrl-names = "default";
1209                 pinctrl-0 = <&i2s1_2ch_bus>;
1210                 status = "disabled";
1211         };
1212
1213         i2s2: i2s@ff8a0000 {
1214                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1215                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1216                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1217                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1218                 dma-names = "tx", "rx";
1219                 clock-names = "i2s_clk", "i2s_hclk";
1220                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1221                 status = "disabled";
1222         };
1223
1224         gpu: gpu@ff9a0000 {
1225                 compatible = "arm,malit860",
1226                              "arm,malit86x",
1227                              "arm,malit8xx",
1228                              "arm,mali-midgard";
1229
1230                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1231
1232                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1233                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1234                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1235                 interrupt-names = "GPU", "JOB", "MMU";
1236
1237                 clocks = <&cru ACLK_GPU>;
1238                 clock-names = "clk_mali";
1239                 #cooling-cells = <2>; /* min followed by max */
1240                 operating-points-v2 = <&gpu_opp_table>;
1241                 power-domains = <&power RK3399_PD_GPU>;
1242                 power-off-delay-ms = <200>;
1243                 status = "disabled";
1244
1245                 power_model {
1246                         compatible = "arm,mali-simple-power-model";
1247                         voltage = <900>;
1248                         frequency = <500>;
1249                         static-power = <300>;
1250                         dynamic-power = <1780>;
1251                         ts = <32000 4700 (-80) 2>;
1252                         thermal-zone = "gpu-thermal";
1253                 };
1254         };
1255
1256         gpu_opp_table: gpu_opp_table {
1257                 compatible = "operating-points-v2";
1258                 opp-shared;
1259
1260                 opp@200000000 {
1261                         opp-hz = /bits/ 64 <200000000>;
1262                         opp-microvolt = <900000>;
1263                 };
1264                 opp@300000000 {
1265                         opp-hz = /bits/ 64 <300000000>;
1266                         opp-microvolt = <900000>;
1267                 };
1268                 opp@400000000 {
1269                         opp-hz = /bits/ 64 <400000000>;
1270                         opp-microvolt = <900000>;
1271                 };
1272
1273         };
1274
1275         vopl: vop@ff8f0000 {
1276                 compatible = "rockchip,rk3399-vop-lit";
1277                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1278                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1279                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1280                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1281                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1282                 reset-names = "axi", "ahb", "dclk";
1283                 power-domains = <&power RK3399_PD_VOPL>;
1284                 iommus = <&vopl_mmu>;
1285                 status = "disabled";
1286
1287                 vopl_out: port {
1288                         #address-cells = <1>;
1289                         #size-cells = <0>;
1290
1291                         vopl_out_mipi: endpoint@0 {
1292                                 reg = <0>;
1293                                 remote-endpoint = <&mipi_in_vopl>;
1294                         };
1295
1296                         vopl_out_edp: endpoint@1 {
1297                                 reg = <1>;
1298                                 remote-endpoint = <&edp_in_vopl>;
1299                         };
1300                 };
1301         };
1302
1303         vopl_mmu: iommu@ff8f3f00 {
1304                 compatible = "rockchip,iommu";
1305                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1306                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1307                 interrupt-names = "vopl_mmu";
1308                 #iommu-cells = <0>;
1309                 status = "disabled";
1310         };
1311
1312         vopb: vop@ff900000 {
1313                 compatible = "rockchip,rk3399-vop-big";
1314                 reg = <0x0 0xff900000 0x0 0x3efc>;
1315                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1316                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1317                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1318                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1319                 reset-names = "axi", "ahb", "dclk";
1320                 power-domains = <&power RK3399_PD_VOPB>;
1321                 iommus = <&vopb_mmu>;
1322                 status = "disabled";
1323
1324                 vopb_out: port {
1325                         #address-cells = <1>;
1326                         #size-cells = <0>;
1327
1328                         vopb_out_edp: endpoint@0 {
1329                                 reg = <0>;
1330                                 remote-endpoint = <&edp_in_vopb>;
1331                         };
1332
1333                         vopb_out_mipi: endpoint@1 {
1334                                 reg = <1>;
1335                                 remote-endpoint = <&mipi_in_vopb>;
1336                         };
1337                 };
1338         };
1339
1340         vopb_mmu: iommu@ff903f00 {
1341                 compatible = "rockchip,iommu";
1342                 reg = <0x0 0xff903f00 0x0 0x100>;
1343                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1344                 interrupt-names = "vopb_mmu";
1345                 #iommu-cells = <0>;
1346                 status = "disabled";
1347         };
1348
1349         mipi_dsi: mipi@ff960000 {
1350                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1351                 reg = <0x0 0xff960000 0x0 0x8000>;
1352                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1353                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1354                          <&cru SCLK_DPHY_TX0_CFG>;
1355                 clock-names = "ref", "pclk", "phy_cfg";
1356                 power-domains = <&power RK3399_PD_VIO>;
1357                 rockchip,grf = <&grf>;
1358                 #address-cells = <1>;
1359                 #size-cells = <0>;
1360                 status = "disabled";
1361
1362                 ports {
1363                         #address-cells = <1>;
1364                         #size-cells = <0>;
1365                         reg = <1>;
1366
1367                         mipi_in: port {
1368                                 #address-cells = <1>;
1369                                 #size-cells = <0>;
1370
1371                                 mipi_in_vopb: endpoint@0 {
1372                                         reg = <0>;
1373                                         remote-endpoint = <&vopb_out_mipi>;
1374                                 };
1375                                 mipi_in_vopl: endpoint@1 {
1376                                         reg = <1>;
1377                                         remote-endpoint = <&vopl_out_mipi>;
1378                                 };
1379                         };
1380                 };
1381         };
1382
1383         edp: edp@ff970000 {
1384                 compatible = "rockchip,rk3399-edp";
1385                 reg = <0x0 0xff970000 0x0 0x8000>;
1386                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1387                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1388                 clock-names = "dp", "pclk";
1389                 resets = <&cru SRST_P_EDP_CTRL>;
1390                 reset-names = "dp";
1391                 rockchip,grf = <&grf>;
1392                 status = "disabled";
1393                 pinctrl-names = "default";
1394                 pinctrl-0 = <&edp_hpd>;
1395
1396                 ports {
1397                         #address-cells = <1>;
1398                         #size-cells = <0>;
1399
1400                         edp_in: port@0 {
1401                                 reg = <0>;
1402                                 #address-cells = <1>;
1403                                 #size-cells = <0>;
1404
1405                                 edp_in_vopb: endpoint@0 {
1406                                         reg = <0>;
1407                                         remote-endpoint = <&vopb_out_edp>;
1408                                 };
1409
1410                                 edp_in_vopl: endpoint@1 {
1411                                         reg = <1>;
1412                                         remote-endpoint = <&vopl_out_edp>;
1413                                 };
1414                         };
1415                 };
1416         };
1417
1418         display_subsystem: display-subsystem {
1419                 compatible = "rockchip,display-subsystem";
1420                 ports = <&vopl_out>, <&vopb_out>;
1421                 status = "disabled";
1422         };
1423
1424         pinctrl: pinctrl {
1425                 compatible = "rockchip,rk3399-pinctrl";
1426                 rockchip,grf = <&grf>;
1427                 rockchip,pmu = <&pmugrf>;
1428                 #address-cells = <0x2>;
1429                 #size-cells = <0x2>;
1430                 ranges;
1431
1432                 gpio0: gpio0@ff720000 {
1433                         compatible = "rockchip,gpio-bank";
1434                         reg = <0x0 0xff720000 0x0 0x100>;
1435                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1436                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1437
1438                         gpio-controller;
1439                         #gpio-cells = <0x2>;
1440
1441                         interrupt-controller;
1442                         #interrupt-cells = <0x2>;
1443                 };
1444
1445                 gpio1: gpio1@ff730000 {
1446                         compatible = "rockchip,gpio-bank";
1447                         reg = <0x0 0xff730000 0x0 0x100>;
1448                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1449                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1450
1451                         gpio-controller;
1452                         #gpio-cells = <0x2>;
1453
1454                         interrupt-controller;
1455                         #interrupt-cells = <0x2>;
1456                 };
1457
1458                 gpio2: gpio2@ff780000 {
1459                         compatible = "rockchip,gpio-bank";
1460                         reg = <0x0 0xff780000 0x0 0x100>;
1461                         clocks = <&cru PCLK_GPIO2>;
1462                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1463
1464                         gpio-controller;
1465                         #gpio-cells = <0x2>;
1466
1467                         interrupt-controller;
1468                         #interrupt-cells = <0x2>;
1469                 };
1470
1471                 gpio3: gpio3@ff788000 {
1472                         compatible = "rockchip,gpio-bank";
1473                         reg = <0x0 0xff788000 0x0 0x100>;
1474                         clocks = <&cru PCLK_GPIO3>;
1475                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1476
1477                         gpio-controller;
1478                         #gpio-cells = <0x2>;
1479
1480                         interrupt-controller;
1481                         #interrupt-cells = <0x2>;
1482                 };
1483
1484                 gpio4: gpio4@ff790000 {
1485                         compatible = "rockchip,gpio-bank";
1486                         reg = <0x0 0xff790000 0x0 0x100>;
1487                         clocks = <&cru PCLK_GPIO4>;
1488                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1489
1490                         gpio-controller;
1491                         #gpio-cells = <0x2>;
1492
1493                         interrupt-controller;
1494                         #interrupt-cells = <0x2>;
1495                 };
1496
1497                 pcfg_pull_up: pcfg-pull-up {
1498                         bias-pull-up;
1499                 };
1500
1501                 pcfg_pull_down: pcfg-pull-down {
1502                         bias-pull-down;
1503                 };
1504
1505                 pcfg_pull_none: pcfg-pull-none {
1506                         bias-disable;
1507                 };
1508
1509                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1510                         bias-disable;
1511                         drive-strength = <12>;
1512                 };
1513
1514                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1515                         bias-pull-up;
1516                         drive-strength = <8>;
1517                 };
1518
1519                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1520                         bias-pull-down;
1521                         drive-strength = <4>;
1522                 };
1523
1524                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1525                         bias-pull-up;
1526                         drive-strength = <2>;
1527                 };
1528
1529                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1530                         bias-pull-down;
1531                         drive-strength = <12>;
1532                 };
1533
1534                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1535                         bias-disable;
1536                         drive-strength = <13>;
1537                 };
1538
1539                 emmc {
1540                         emmc_pwr: emmc-pwr {
1541                                 rockchip,pins =
1542                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1543                         };
1544                 };
1545
1546                 gmac {
1547                         rgmii_pins: rgmii-pins {
1548                                 rockchip,pins =
1549                                         /* mac_txclk */
1550                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1551                                         /* mac_rxclk */
1552                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1553                                         /* mac_mdio */
1554                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1555                                         /* mac_txen */
1556                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1557                                         /* mac_clk */
1558                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1559                                         /* mac_rxdv */
1560                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1561                                         /* mac_mdc */
1562                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1563                                         /* mac_rxd1 */
1564                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1565                                         /* mac_rxd0 */
1566                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1567                                         /* mac_txd1 */
1568                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1569                                         /* mac_txd0 */
1570                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1571                                         /* mac_rxd3 */
1572                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1573                                         /* mac_rxd2 */
1574                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1575                                         /* mac_txd3 */
1576                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1577                                         /* mac_txd2 */
1578                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1579                         };
1580
1581                         rmii_pins: rmii-pins {
1582                                 rockchip,pins =
1583                                         /* mac_mdio */
1584                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1585                                         /* mac_txen */
1586                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1587                                         /* mac_clk */
1588                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1589                                         /* mac_rxer */
1590                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1591                                         /* mac_rxdv */
1592                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1593                                         /* mac_mdc */
1594                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1595                                         /* mac_rxd1 */
1596                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1597                                         /* mac_rxd0 */
1598                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1599                                         /* mac_txd1 */
1600                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1601                                         /* mac_txd0 */
1602                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1603                         };
1604                 };
1605
1606                 i2c0 {
1607                         i2c0_xfer: i2c0-xfer {
1608                                 rockchip,pins =
1609                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1610                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1611                         };
1612                 };
1613
1614                 i2c1 {
1615                         i2c1_xfer: i2c1-xfer {
1616                                 rockchip,pins =
1617                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1618                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1619                         };
1620                 };
1621
1622                 i2c2 {
1623                         i2c2_xfer: i2c2-xfer {
1624                                 rockchip,pins =
1625                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1626                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1627                         };
1628                 };
1629
1630                 i2c3 {
1631                         i2c3_xfer: i2c3-xfer {
1632                                 rockchip,pins =
1633                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1634                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1635                         };
1636
1637                         i2c3_gpio: i2c3_gpio {
1638                                 rockchip,pins =
1639                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1640                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1641                         };
1642
1643                 };
1644
1645                 i2c4 {
1646                         i2c4_xfer: i2c4-xfer {
1647                                 rockchip,pins =
1648                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1649                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1650                         };
1651                 };
1652
1653                 i2c5 {
1654                         i2c5_xfer: i2c5-xfer {
1655                                 rockchip,pins =
1656                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1657                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1658                         };
1659                 };
1660
1661                 i2c6 {
1662                         i2c6_xfer: i2c6-xfer {
1663                                 rockchip,pins =
1664                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1665                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1666                         };
1667                 };
1668
1669                 i2c7 {
1670                         i2c7_xfer: i2c7-xfer {
1671                                 rockchip,pins =
1672                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1673                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1674                         };
1675                 };
1676
1677                 i2c8 {
1678                         i2c8_xfer: i2c8-xfer {
1679                                 rockchip,pins =
1680                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1681                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1682                         };
1683                 };
1684
1685                 i2s0 {
1686                         i2s0_8ch_bus: i2s0-8ch-bus {
1687                                 rockchip,pins =
1688                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1689                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1690                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1691                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1692                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1693                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1694                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1695                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1696                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1697                         };
1698                 };
1699
1700                 i2s1 {
1701                         i2s1_2ch_bus: i2s1-2ch-bus {
1702                                 rockchip,pins =
1703                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1704                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1705                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1706                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1707                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1708                         };
1709                 };
1710
1711                 sdio0 {
1712                         sdio0_bus1: sdio0-bus1 {
1713                                 rockchip,pins =
1714                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1715                         };
1716
1717                         sdio0_bus4: sdio0-bus4 {
1718                                 rockchip,pins =
1719                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1720                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1721                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1722                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1723                         };
1724
1725                         sdio0_cmd: sdio0-cmd {
1726                                 rockchip,pins =
1727                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1728                         };
1729
1730                         sdio0_clk: sdio0-clk {
1731                                 rockchip,pins =
1732                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1733                         };
1734
1735                         sdio0_cd: sdio0-cd {
1736                                 rockchip,pins =
1737                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1738                         };
1739
1740                         sdio0_pwr: sdio0-pwr {
1741                                 rockchip,pins =
1742                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1743                         };
1744
1745                         sdio0_bkpwr: sdio0-bkpwr {
1746                                 rockchip,pins =
1747                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1748                         };
1749
1750                         sdio0_wp: sdio0-wp {
1751                                 rockchip,pins =
1752                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1753                         };
1754
1755                         sdio0_int: sdio0-int {
1756                                 rockchip,pins =
1757                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1758                         };
1759                 };
1760
1761                 sdmmc {
1762                         sdmmc_bus1: sdmmc-bus1 {
1763                                 rockchip,pins =
1764                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1765                         };
1766
1767                         sdmmc_bus4: sdmmc-bus4 {
1768                                 rockchip,pins =
1769                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1770                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1771                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1772                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1773                         };
1774
1775                         sdmmc_clk: sdmmc-clk {
1776                                 rockchip,pins =
1777                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1778                         };
1779
1780                         sdmmc_cmd: sdmmc-cmd {
1781                                 rockchip,pins =
1782                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1783                         };
1784
1785                         sdmmc_cd: sdmcc-cd {
1786                                 rockchip,pins =
1787                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1788                         };
1789
1790                         sdmmc_wp: sdmmc-wp {
1791                                 rockchip,pins =
1792                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1793                         };
1794                 };
1795
1796                 spdif {
1797                         spdif_bus: spdif-bus {
1798                                 rockchip,pins =
1799                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1800                         };
1801
1802                         spdif_bus_1: spdif-bus-1 {
1803                                 rockchip,pins =
1804                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
1805                         };
1806                 };
1807
1808                 spi0 {
1809                         spi0_clk: spi0-clk {
1810                                 rockchip,pins =
1811                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1812                         };
1813                         spi0_cs0: spi0-cs0 {
1814                                 rockchip,pins =
1815                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1816                         };
1817                         spi0_cs1: spi0-cs1 {
1818                                 rockchip,pins =
1819                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1820                         };
1821                         spi0_tx: spi0-tx {
1822                                 rockchip,pins =
1823                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1824                         };
1825                         spi0_rx: spi0-rx {
1826                                 rockchip,pins =
1827                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1828                         };
1829                 };
1830
1831                 spi1 {
1832                         spi1_clk: spi1-clk {
1833                                 rockchip,pins =
1834                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1835                         };
1836                         spi1_cs0: spi1-cs0 {
1837                                 rockchip,pins =
1838                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1839                         };
1840                         spi1_rx: spi1-rx {
1841                                 rockchip,pins =
1842                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1843                         };
1844                         spi1_tx: spi1-tx {
1845                                 rockchip,pins =
1846                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1847                         };
1848                 };
1849
1850                 spi2 {
1851                         spi2_clk: spi2-clk {
1852                                 rockchip,pins =
1853                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1854                         };
1855                         spi2_cs0: spi2-cs0 {
1856                                 rockchip,pins =
1857                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1858                         };
1859                         spi2_rx: spi2-rx {
1860                                 rockchip,pins =
1861                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1862                         };
1863                         spi2_tx: spi2-tx {
1864                                 rockchip,pins =
1865                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1866                         };
1867                 };
1868
1869                 spi3 {
1870                         spi3_clk: spi3-clk {
1871                                 rockchip,pins =
1872                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1873                         };
1874                         spi3_cs0: spi3-cs0 {
1875                                 rockchip,pins =
1876                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1877                         };
1878                         spi3_rx: spi3-rx {
1879                                 rockchip,pins =
1880                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1881                         };
1882                         spi3_tx: spi3-tx {
1883                                 rockchip,pins =
1884                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1885                         };
1886                 };
1887
1888                 spi4 {
1889                         spi4_clk: spi4-clk {
1890                                 rockchip,pins =
1891                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1892                         };
1893                         spi4_cs0: spi4-cs0 {
1894                                 rockchip,pins =
1895                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1896                         };
1897                         spi4_rx: spi4-rx {
1898                                 rockchip,pins =
1899                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1900                         };
1901                         spi4_tx: spi4-tx {
1902                                 rockchip,pins =
1903                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1904                         };
1905                 };
1906
1907                 spi5 {
1908                         spi5_clk: spi5-clk {
1909                                 rockchip,pins =
1910                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1911                         };
1912                         spi5_cs0: spi5-cs0 {
1913                                 rockchip,pins =
1914                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1915                         };
1916                         spi5_rx: spi5-rx {
1917                                 rockchip,pins =
1918                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1919                         };
1920                         spi5_tx: spi5-tx {
1921                                 rockchip,pins =
1922                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1923                         };
1924                 };
1925
1926                 tsadc {
1927                         otp_gpio: otp-gpio {
1928                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1929                         };
1930
1931                         otp_out: otp-out {
1932                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1933                         };
1934                 };
1935
1936                 uart0 {
1937                         uart0_xfer: uart0-xfer {
1938                                 rockchip,pins =
1939                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1940                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1941                         };
1942
1943                         uart0_cts: uart0-cts {
1944                                 rockchip,pins =
1945                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1946                         };
1947
1948                         uart0_rts: uart0-rts {
1949                                 rockchip,pins =
1950                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1951                         };
1952                 };
1953
1954                 uart1 {
1955                         uart1_xfer: uart1-xfer {
1956                                 rockchip,pins =
1957                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1958                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1959                         };
1960                 };
1961
1962                 uart2a {
1963                         uart2a_xfer: uart2a-xfer {
1964                                 rockchip,pins =
1965                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1966                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1967                         };
1968                 };
1969
1970                 uart2b {
1971                         uart2b_xfer: uart2b-xfer {
1972                                 rockchip,pins =
1973                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1974                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1975                         };
1976                 };
1977
1978                 uart2c {
1979                         uart2c_xfer: uart2c-xfer {
1980                                 rockchip,pins =
1981                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1982                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1983                         };
1984                 };
1985
1986                 uart3 {
1987                         uart3_xfer: uart3-xfer {
1988                                 rockchip,pins =
1989                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1990                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1991                         };
1992
1993                         uart3_cts: uart3-cts {
1994                                 rockchip,pins =
1995                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1996                         };
1997
1998                         uart3_rts: uart3-rts {
1999                                 rockchip,pins =
2000                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2001                         };
2002                 };
2003
2004                 uart4 {
2005                         uart4_xfer: uart4-xfer {
2006                                 rockchip,pins =
2007                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2008                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2009                         };
2010                 };
2011
2012                 uarthdcp {
2013                         uarthdcp_xfer: uarthdcp-xfer {
2014                                 rockchip,pins =
2015                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2016                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2017                         };
2018                 };
2019
2020                 pwm0 {
2021                         pwm0_pin: pwm0-pin {
2022                                 rockchip,pins =
2023                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2024                         };
2025
2026                         vop0_pwm_pin: vop0-pwm-pin {
2027                                 rockchip,pins =
2028                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2029                         };
2030                 };
2031
2032                 pwm1 {
2033                         pwm1_pin: pwm1-pin {
2034                                 rockchip,pins =
2035                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2036                         };
2037
2038                         vop1_pwm_pin: vop1-pwm-pin {
2039                                 rockchip,pins =
2040                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2041                         };
2042                 };
2043
2044                 pwm2 {
2045                         pwm2_pin: pwm2-pin {
2046                                 rockchip,pins =
2047                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2048                         };
2049                 };
2050
2051                 pwm3a {
2052                         pwm3a_pin: pwm3a-pin {
2053                                 rockchip,pins =
2054                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2055                         };
2056                 };
2057
2058                 pwm3b {
2059                         pwm3b_pin: pwm3b-pin {
2060                                 rockchip,pins =
2061                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2062                         };
2063                 };
2064
2065                 edp {
2066                         edp_hpd: edp-hpd {
2067                                 rockchip,pins =
2068                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2069                         };
2070                 };
2071
2072                 hdmi {
2073                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2074                                 rockchip,pins =
2075                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2076                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2077                         };
2078
2079                         hdmi_cec: hdmi-cec {
2080                                 rockchip,pins =
2081                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2082                         };
2083                 };
2084
2085                 pcie {
2086                         pcie_clkreqn: pci-clkreqn {
2087                                 rockchip,pins =
2088                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2089                         };
2090
2091                         pcie_clkreqnb: pci-clkreqnb {
2092                                 rockchip,pins =
2093                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2094                         };
2095                 };
2096         };
2097 };