arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71         };
  72
  73         cpus {
  74                 #address-cells = <2>;
  75                 #size-cells = <0>;
  76
  77                 cpu-map {
  78                         cluster0 {
  79                                 core0 {
  80                                         cpu = <&cpu_l0>;
  81                                 };
  82                                 core1 {
  83                                         cpu = <&cpu_l1>;
  84                                 };
  85                                 core2 {
  86                                         cpu = <&cpu_l2>;
  87                                 };
  88                                 core3 {
  89                                         cpu = <&cpu_l3>;
  90                                 };
  91                         };
  92
  93                         cluster1 {
  94                                 core0 {
  95                                         cpu = <&cpu_b0>;
  96                                 };
  97                                 core1 {
  98                                         cpu = <&cpu_b1>;
  99                                 };
 100                         };
 101                 };
 102
 103                 cpu_l0: cpu@0 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a53", "arm,armv8";
 106                         reg = <0x0 0x0>;
 107
 108                         #cooling-cells = <2>; /* min followed by max */
 109                 };
 110
 111                 cpu_l1: cpu@1 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x1>;
 115                 };
 116
 117                 cpu_l2: cpu@2 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a53", "arm,armv8";
 120                         reg = <0x0 0x2>;
 121                 };
 122
 123                 cpu_l3: cpu@3 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53", "arm,armv8";
 126                         reg = <0x0 0x3>;
 127                 };
 128
 129                 cpu_b0: cpu@100 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a72", "arm,armv8";
 132                         reg = <0x0 0x100>;
 133
 134                         #cooling-cells = <2>; /* min followed by max */
 135                 };
 136
 137                 cpu_b1: cpu@101 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a72", "arm,armv8";
 140                         reg = <0x0 0x101>;
 141                 };
 142         };
 143
 144         timer {
 145                 compatible = "arm,armv8-timer";
 146                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 150         };
 151
 152         xin24m: xin24m {
 153                 compatible = "fixed-clock";
 154                 #clock-cells = <0>;
 155                 clock-frequency = <24000000>;
 156                 clock-output-names = "xin24m";
 157         };
 158
 159         gic: interrupt-controller@fee00000 {
 160                 compatible = "arm,gic-v3";
 161                 #interrupt-cells = <3>;
 162                 #address-cells = <2>;
 163                 #size-cells = <2>;
 164                 ranges;
 165                 interrupt-controller;
 166
 167                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 168                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 169                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 170                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 171                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 172                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 173                 its: interrupt-controller@fee20000 {
 174                         compatible = "arm,gic-v3-its";
 175                         msi-controller;
 176                         reg = <0x0 0xfee20000 0x0 0x20000>;
 177                 };
 178         };
 179
 180         amba {
 181                 compatible = "arm,amba-bus";
 182                 #address-cells = <2>;
 183                 #size-cells = <2>;
 184                 ranges;
 185
 186                 dmac_bus: dma-controller@ff6d0000 {
 187                         compatible = "arm,pl330", "arm,primecell";
 188                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 189                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 191                         #dma-cells = <1>;
 192                         clocks = <&cru ACLK_DMAC0_PERILP>;
 193                         clock-names = "apb_pclk";
 194                 };
 195
 196                 dmac_peri: dma-controller@ff6e0000 {
 197                         compatible = "arm,pl330", "arm,primecell";
 198                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 199                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 201                         #dma-cells = <1>;
 202                         clocks = <&cru ACLK_DMAC1_PERILP>;
 203                         clock-names = "apb_pclk";
 204                 };
 205         };
 206
 207         saradc: saradc@ff100000 {
 208                 compatible = "rockchip,rk3399-saradc";
 209                 reg = <0x0 0xff100000 0x0 0x100>;
 210                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 211                 #io-channel-cells = <1>;
 212                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 213                 clock-names = "saradc", "apb_pclk";
 214                 status = "disabled";
 215         };
 216
 217         i2c0: i2c@ff3c0000 {
 218                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 219                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 220                 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
 221                 clock-names = "i2c", "i2c_sclk";
 222                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&i2c0_xfer>;
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 status = "disabled";
 228         };
 229
 230         i2c1: i2c@ff110000 {
 231                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 232                 reg = <0x0 0xff110000 0x0 0x1000>;
 233                 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
 234                 clock-names = "i2c", "i2c_sclk";
 235                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&i2c1_xfer>;
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 status = "disabled";
 241         };
 242
 243         i2c2: i2c@ff120000 {
 244                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 245                 reg = <0x0 0xff120000 0x0 0x1000>;
 246                 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
 247                 clock-names = "i2c", "i2c_sclk";
 248                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 249                 pinctrl-names = "default";
 250                 pinctrl-0 = <&i2c2_xfer>;
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 status = "disabled";
 254         };
 255
 256         i2c3: i2c@ff130000 {
 257                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 258                 reg = <0x0 0xff130000 0x0 0x1000>;
 259                 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
 260                 clock-names = "i2c", "i2c_sclk";
 261                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&i2c3_xfer>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 status = "disabled";
 267         };
 268
 269         i2c5: i2c@ff140000 {
 270                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 271                 reg = <0x0 0xff140000 0x0 0x1000>;
 272                 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
 273                 clock-names = "i2c", "i2c_sclk";
 274                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&i2c5_xfer>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 status = "disabled";
 280         };
 281
 282         i2c6: i2c@ff150000 {
 283                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 284                 reg = <0x0 0xff150000 0x0 0x1000>;
 285                 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
 286                 clock-names = "i2c", "i2c_sclk";
 287                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&i2c6_xfer>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 status = "disabled";
 293         };
 294
 295         i2c7: i2c@ff160000 {
 296                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 297                 reg = <0x0 0xff160000 0x0 0x1000>;
 298                 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
 299                 clock-names = "i2c", "i2c_sclk";
 300                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 301                 pinctrl-names = "default";
 302                 pinctrl-0 = <&i2c7_xfer>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 status = "disabled";
 306         };
 307
 308         emmc_phy: phy {
 309                 compatible = "rockchip,rk3399-emmc-phy";
 310                 reg-offset = <0xf780>;
 311                 #phy-cells = <0>;
 312                 rockchip,grf = <&grf>;
 313                 status = "disabled";
 314         };
 315
 316         sdio0: dwmmc@fe310000 {
 317                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 318                 reg = <0x0 0xfe310000 0x0 0x4000>;
 319                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 320                 clock-freq-min-max = <400000 150000000>;
 321                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 322                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 323                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 324                 fifo-depth = <0x100>;
 325                 status = "disabled";
 326         };
 327
 328         sdmmc: dwmmc@fe320000 {
 329                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 330                 reg = <0x0 0xfe320000 0x0 0x4000>;
 331                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 332                 clock-freq-min-max = <400000 150000000>;
 333                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 334                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 335                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 336                 fifo-depth = <0x100>;
 337                 status = "disabled";
 338         };
 339
 340         sdhci: sdhci@fe330000 {
 341                 compatible = "arasan,sdhci-5.1";
 342                 reg = <0x0 0xfe330000 0x0 0x10000>;
 343                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 344                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 345                 clock-names = "clk_xin", "clk_ahb";
 346                 phys = <&emmc_phy>;
 347                 phy-names = "phy_arasan";
 348                 status = "disabled";
 349         };
 350
 351         uart0: serial@ff180000 {
 352                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 353                 reg = <0x0 0xff180000 0x0 0x100>;
 354                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 355                 clock-names = "baudclk", "apb_pclk";
 356                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 357                 reg-shift = <2>;
 358                 reg-io-width = <4>;
 359                 status = "disabled";
 360         };
 361
 362         uart1: serial@ff190000 {
 363                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 364                 reg = <0x0 0xff190000 0x0 0x100>;
 365                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 366                 clock-names = "baudclk", "apb_pclk";
 367                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 368                 reg-shift = <2>;
 369                 reg-io-width = <4>;
 370                 status = "disabled";
 371         };
 372
 373         uart2: serial@ff1a0000 {
 374                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 375                 reg = <0x0 0xff1a0000 0x0 0x100>;
 376                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 377                 clock-names = "baudclk", "apb_pclk";
 378                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 379                 reg-shift = <2>;
 380                 reg-io-width = <4>;
 381                 status = "disabled";
 382         };
 383
 384         uart3: serial@ff1b0000 {
 385                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 386                 reg = <0x0 0xff1b0000 0x0 0x100>;
 387                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 388                 clock-names = "baudclk", "apb_pclk";
 389                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 390                 reg-shift = <2>;
 391                 reg-io-width = <4>;
 392                 status = "disabled";
 393         };
 394
 395         spi0: spi@ff1c0000 {
 396                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 397                 reg = <0x0 0xff110000 0x0 0x1000>;
 398                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 399                 clock-names = "spiclk", "apb_pclk";
 400                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 status = "disabled";
 406         };
 407
 408         spi1: spi@ff1d0000 {
 409                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 410                 reg = <0x0 0xff120000 0x0 0x1000>;
 411                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 412                 clock-names = "spiclk", "apb_pclk";
 413                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 status = "disabled";
 419         };
 420
 421         spi2: spi@ff1e0000 {
 422                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 423                 reg = <0x0 0xff130000 0x0 0x1000>;
 424                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 425                 clock-names = "spiclk", "apb_pclk";
 426                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 status = "disabled";
 432         };
 433
 434         spi4: spi@ff1f0000 {
 435                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 436                 reg = <0x0 0xff120000 0x0 0x1000>;
 437                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 438                 clock-names = "spiclk", "apb_pclk";
 439                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 status = "disabled";
 445         };
 446
 447         spi5: spi@ff200000 {
 448                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 449                 reg = <0x0 0xff130000 0x0 0x1000>;
 450                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 451                 clock-names = "spiclk", "apb_pclk";
 452                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 status = "disabled";
 458         };
 459
 460         thermal-zones {
 461                 #include "rk3368-thermal.dtsi"
 462         };
 463
 464         tsadc: tsadc@ff260000 {
 465                 compatible = "rockchip,rk3399-tsadc";
 466                 reg = <0x0 0xff260000 0x0 0x100>;
 467                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 469                 clock-names = "tsadc", "apb_pclk";
 470                 resets = <&cru SRST_TSADC>;
 471                 reset-names = "tsadc-apb";
 472                 pinctrl-names = "init", "default", "sleep";
 473                 pinctrl-0 = <&otp_gpio>;
 474                 pinctrl-1 = <&otp_out>;
 475                 pinctrl-2 = <&otp_gpio>;
 476                 #thermal-sensor-cells = <1>;
 477                 rockchip,hw-tshut-temp = <95000>;
 478                 status = "disabled";
 479         };
 480
 481         pmugrf: syscon@ff320000 {
 482                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 483                 reg = <0x0 0xff320000 0x0 0x1000>;
 484         };
 485
 486         spi3: spi@ff350000 {
 487                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 488                 reg = <0x0 0xff110000 0x0 0x1000>;
 489                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 490                 clock-names = "spiclk", "apb_pclk";
 491                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 494                 #address-cells = <1>;
 495                 #size-cells = <0>;
 496                 status = "disabled";
 497         };
 498
 499         uart4: serial@ff370000 {
 500                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 501                 reg = <0x0 0xff370000 0x0 0x100>;
 502                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 503                 clock-names = "baudclk", "apb_pclk";
 504                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 505                 reg-shift = <2>;
 506                 reg-io-width = <4>;
 507                 status = "disabled";
 508         };
 509
 510         usb_host0_echi: usb@fe380000 {
 511                 compatible = "generic-ehci";
 512                 reg = <0x0 0xfe380000 0x0 0x20000>;
 513                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 514                 clocks = <&cru HCLK_HOST0>;
 515                 clock-names = "hclk_host0";
 516                 status = "disabled";
 517         };
 518
 519         usb_host0_ohci: usb@fe3a0000 {
 520                 compatible = "generic-ohci";
 521                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 522                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 523                 clocks = <&cru HCLK_HOST0>;
 524                 clock-names = "hclk_host0";
 525                 status = "disabled";
 526         };
 527
 528         usb_host1_echi: usb@fe3c0000 {
 529                 compatible = "generic-ehci";
 530                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 531                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&cru HCLK_HOST1>;
 533                 clock-names = "hclk_host1";
 534                 status = "disabled";
 535         };
 536
 537         usb_host1_ohci: usb@fe3e0000 {
 538                 compatible = "generic-ohci";
 539                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 540                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&cru HCLK_HOST1>;
 542                 clock-names = "hclk_host1";
 543                 status = "disabled";
 544         };
 545
 546         i2c4: i2c@ff3d0000 {
 547                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 548                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 549                 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
 550                 clock-names = "i2c", "i2c_sclk";
 551                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&i2c4_xfer>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 status = "disabled";
 557         };
 558
 559         i2c8: i2c@ff3e0000 {
 560                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 561                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 562                 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
 563                 clock-names = "i2c", "i2c_sclk";
 564                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&i2c8_xfer>;
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 status = "disabled";
 570         };
 571
 572         pwm0: pwm@ff420000 {
 573                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 574                 reg = <0x0 0xff420000 0x0 0x10>;
 575                 #pwm-cells = <3>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&pwm0_pin>;
 578                 clocks = <&cru PCLK_RKPWM_PMU>;
 579                 clock-names = "pwm";
 580                 status = "disabled";
 581         };
 582
 583         pwm1: pwm@ff420010 {
 584                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 585                 reg = <0x0 0xff420010 0x0 0x10>;
 586                 #pwm-cells = <3>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&pwm1_pin>;
 589                 clocks = <&cru PCLK_RKPWM_PMU>;
 590                 clock-names = "pwm";
 591                 status = "disabled";
 592         };
 593
 594         pwm2: pwm@ff420020 {
 595                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 596                 reg = <0x0 0xff420020 0x0 0x10>;
 597                 #pwm-cells = <3>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&pwm2_pin>;
 600                 clocks = <&cru PCLK_RKPWM_PMU>;
 601                 clock-names = "pwm";
 602                 status = "disabled";
 603         };
 604
 605         pwm3: pwm@ff420030 {
 606                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 607                 reg = <0x0 0xff420030 0x0 0x10>;
 608                 #pwm-cells = <3>;
 609                 pinctrl-names = "default";
 610                 pinctrl-0 = <&pwm3a_pin>;
 611                 clocks = <&cru PCLK_RKPWM_PMU>;
 612                 clock-names = "pwm";
 613                 status = "disabled";
 614         };
 615
 616         pmu: power-management@ff731000 {
 617                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 618                 reg = <0x0 0xff310000 0x0 0x1000>;
 619
 620                 power: power-controller {
 621                         status = "disabled";
 622                         compatible = "rockchip,rk3399-power-controller";
 623                         #power-domain-cells = <1>;
 624                         #address-cells = <1>;
 625                         #size-cells = <0>;
 626
 627                         pd_center {
 628                                 reg = <RK3399_PD_CENTER>;
 629                                 #address-cells = <1>;
 630                                 #size-cells = <0>;
 631
 632                                 pd_vdu {
 633                                         reg = <RK3399_PD_VDU>;
 634                                 };
 635                                 pd_vcodec {
 636                                         reg = <RK3399_PD_VCODEC>;
 637                                 };
 638                                 pd_iep {
 639                                         reg = <RK3399_PD_IEP>;
 640                                 };
 641                                 pd_rga {
 642                                         reg = <RK3399_PD_RGA>;
 643                                 };
 644                         };
 645                         pd_vio {
 646                                 reg = <RK3399_PD_VIO>;
 647                                 #address-cells = <1>;
 648                                 #size-cells = <0>;
 649
 650                                 pd_isp0 {
 651                                         reg = <RK3399_PD_ISP0>;
 652                                 };
 653                                 pd_isp1 {
 654                                         reg = <RK3399_PD_ISP1>;
 655                                 };
 656                                 pd_hdcp {
 657                                         reg = <RK3399_PD_HDCP>;
 658                                 };
 659                                 pd_vo {
 660                                         reg = <RK3399_PD_VO>;
 661                                         #address-cells = <1>;
 662                                         #size-cells = <0>;
 663
 664                                         pd_vopb {
 665                                                 reg = <RK3399_PD_VOPB>;
 666                                         };
 667                                         pd_vopl {
 668                                                 reg = <RK3399_PD_VOPL>;
 669                                         };
 670                                 };
 671                         };
 672                         pd_gpu {
 673                                 reg = <RK3399_PD_GPU>;
 674                         };
 675                 };
 676         };
 677
 678         pmucru: pmu-clock-controller@ff750000 {
 679                 compatible = "rockchip,rk3399-pmucru";
 680                 reg = <0x0 0xff750000 0x0 0x1000>;
 681                 rockchip,grf = <&pmugrf>;
 682                 #clock-cells = <1>;
 683                 #reset-cells = <1>;
 684         };
 685
 686         cru: clock-controller@ff760000 {
 687                 compatible = "rockchip,rk3399-cru";
 688                 reg = <0x0 0xff760000 0x0 0x1000>;
 689                 rockchip,grf = <&grf>;
 690                 #clock-cells = <1>;
 691                 #reset-cells = <1>;
 692         };
 693
 694         grf: syscon@ff770000 {
 695                 compatible = "rockchip,rk3399-grf", "syscon";
 696                 reg = <0x0 0xff770000 0x0 0x10000>;
 697         };
 698
 699         spdif: spdif@ff870000 {
 700                 compatible = "rockchip,rk3399-spdif";
 701                 reg = <0x0 0xff870000 0x0 0x1000>;
 702                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 703                 dmas = <&dmac_bus 7>;
 704                 dma-names = "tx";
 705                 clock-names = "hclk", "mclk";
 706                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 707                 pinctrl-names = "default";
 708                 pinctrl-0 = <&spdif_bus>;
 709                 status = "disabled";
 710         };
 711
 712         i2s0: i2s@ff880000 {
 713                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 714                 reg = <0x0 0xff880000 0x0 0x1000>;
 715                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 716                 #address-cells = <1>;
 717                 #size-cells = <0>;
 718                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 719                 dma-names = "tx", "rx";
 720                 clock-names = "i2s_hclk", "i2s_clk";
 721                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 722                 pinctrl-names = "default";
 723                 pinctrl-0 = <&i2s0_8ch_bus>;
 724                 status = "disabled";
 725         };
 726
 727         i2s1: i2s@ff890000 {
 728                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 729                 reg = <0x0 0xff890000 0x0 0x1000>;
 730                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 731                 #address-cells = <1>;
 732                 #size-cells = <0>;
 733                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 734                 dma-names = "tx", "rx";
 735                 clock-names = "i2s_hclk", "i2s_clk";
 736                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 737                 pinctrl-names = "default";
 738                 pinctrl-0 = <&i2s1_2ch_bus>;
 739                 status = "disabled";
 740         };
 741
 742         i2s2: i2s@ff8a0000 {
 743                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 744                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 745                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 746                 #address-cells = <1>;
 747                 #size-cells = <0>;
 748                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 749                 dma-names = "tx", "rx";
 750                 clock-names = "i2s_hclk", "i2s_clk";
 751                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 752                 status = "disabled";
 753         };
 754
 755         pinctrl: pinctrl {
 756                 compatible = "rockchip,rk3399-pinctrl";
 757                 rockchip,grf = <&grf>;
 758                 rockchip,pmu = <&pmugrf>;
 759                 #address-cells = <0x2>;
 760                 #size-cells = <0x2>;
 761                 ranges;
 762
 763                 gpio0: gpio0@ff720000 {
 764                         compatible = "rockchip,gpio-bank";
 765                         reg = <0x0 0xff720000 0x0 0x100>;
 766                         clocks = <&xin24m>;
 767                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 768
 769                         gpio-controller;
 770                         #gpio-cells = <0x2>;
 771
 772                         interrupt-controller;
 773                         #interrupt-cells = <0x2>;
 774                 };
 775
 776                 gpio1: gpio1@ff730000 {
 777                         compatible = "rockchip,gpio-bank";
 778                         reg = <0x0 0xff730000 0x0 0x100>;
 779                         clocks = <&xin24m>;
 780                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 781
 782                         gpio-controller;
 783                         #gpio-cells = <0x2>;
 784
 785                         interrupt-controller;
 786                         #interrupt-cells = <0x2>;
 787                 };
 788
 789                 gpio2: gpio2@ff780000 {
 790                         compatible = "rockchip,gpio-bank";
 791                         reg = <0x0 0xff780000 0x0 0x100>;
 792                         clocks = <&xin24m>;
 793                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 794
 795                         gpio-controller;
 796                         #gpio-cells = <0x2>;
 797
 798                         interrupt-controller;
 799                         #interrupt-cells = <0x2>;
 800                 };
 801
 802                 gpio3: gpio3@ff788000 {
 803                         compatible = "rockchip,gpio-bank";
 804                         reg = <0x0 0xff788000 0x0 0x100>;
 805                         clocks = <&xin24m>;
 806                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 807
 808                         gpio-controller;
 809                         #gpio-cells = <0x2>;
 810
 811                         interrupt-controller;
 812                         #interrupt-cells = <0x2>;
 813                 };
 814
 815                 gpio4: gpio4@ff790000 {
 816                         compatible = "rockchip,gpio-bank";
 817                         reg = <0x0 0xff790000 0x0 0x100>;
 818                         clocks = <&xin24m>;
 819                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 820
 821                         gpio-controller;
 822                         #gpio-cells = <0x2>;
 823
 824                         interrupt-controller;
 825                         #interrupt-cells = <0x2>;
 826                 };
 827
 828                 pcfg_pull_up: pcfg-pull-up {
 829                         bias-pull-up;
 830                 };
 831
 832                 pcfg_pull_down: pcfg-pull-down {
 833                         bias-pull-down;
 834                 };
 835
 836                 pcfg_pull_none: pcfg-pull-none {
 837                         bias-disable;
 838                 };
 839
 840                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 841                         bias-disable;
 842                         drive-strength = <12>;
 843                 };
 844
 845                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 846                         bias-pull-up;
 847                         drive-strength = <8>;
 848                 };
 849
 850                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 851                         bias-pull-down;
 852                         drive-strength = <4>;
 853                 };
 854
 855                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 856                         bias-pull-up;
 857                         drive-strength = <2>;
 858                 };
 859
 860                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 861                         bias-pull-down;
 862                         drive-strength = <12>;
 863                 };
 864
 865                 emmc {
 866                         emmc_pwr: emmc-pwr {
 867                                 rockchip,pins =
 868                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 869                         };
 870                 };
 871
 872                 gmac {
 873                         rgmii_pins: rgmii-pins {
 874                                 rockchip,pins =
 875                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 876                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 877                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 878                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 879                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 880                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 881                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 882                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 883                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 884                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 885                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 886                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 887                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 888                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 889                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 890                         };
 891
 892                         rmii_pins: rmii-pins {
 893                                 rockchip,pins =
 894                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 895                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 896                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 897                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 898                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 899                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 900                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 901                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 902                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 903                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 904                         };
 905                 };
 906
 907                 i2c0 {
 908                         i2c0_xfer: i2c0-xfer {
 909                                 rockchip,pins =
 910                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 911                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 912                         };
 913                 };
 914
 915                 i2c1 {
 916                         i2c1_xfer: i2c1-xfer {
 917                                 rockchip,pins =
 918                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 919                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 920                         };
 921                 };
 922
 923                 i2c2 {
 924                         i2c2_xfer: i2c2-xfer {
 925                                 rockchip,pins =
 926                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 927                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 928                         };
 929                 };
 930
 931                 i2c3 {
 932                         i2c3_xfer: i2c3-xfer {
 933                                 rockchip,pins =
 934                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 935                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 936                         };
 937                 };
 938
 939                 i2c4 {
 940                         i2c4_xfer: i2c4-xfer {
 941                                 rockchip,pins =
 942                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 943                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 944                         };
 945                 };
 946
 947                 i2c5 {
 948                         i2c5_xfer: i2c5-xfer {
 949                                 rockchip,pins =
 950                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 951                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 952                         };
 953                 };
 954
 955                 i2c6 {
 956                         i2c6_xfer: i2c6-xfer {
 957                                 rockchip,pins =
 958                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 959                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 960                         };
 961                 };
 962
 963                 i2c7 {
 964                         i2c7_xfer: i2c7-xfer {
 965                                 rockchip,pins =
 966                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 967                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 968                         };
 969                 };
 970
 971                 i2c8 {
 972                         i2c8_xfer: i2c8-xfer {
 973                                 rockchip,pins =
 974                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 975                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 976                         };
 977                 };
 978
 979                 i2s0 {
 980                         i2s0_8ch_bus: i2s0-8ch-bus {
 981                                 rockchip,pins =
 982                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 983                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 984                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 985                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 986                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 987                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 988                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 989                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 990                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 991                         };
 992                 };
 993
 994                 i2s1 {
 995                         i2s1_2ch_bus: i2s1-2ch-bus {
 996                                 rockchip,pins =
 997                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 998                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 999                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1000                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1001                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1002                         };
1003                 };
1004
1005                 sdio0 {
1006                         sdio0_bus1: sdio0-bus1 {
1007                                 rockchip,pins =
1008                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1009                         };
1010
1011                         sdio0_bus4: sdio0-bus4 {
1012                                 rockchip,pins =
1013                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1014                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1015                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1016                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1017                         };
1018
1019                         sdio0_cmd: sdio0-cmd {
1020                                 rockchip,pins =
1021                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1022                         };
1023
1024                         sdio0_clk: sdio0-clk {
1025                                 rockchip,pins =
1026                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1027                         };
1028
1029                         sdio0_cd: sdio0-cd {
1030                                 rockchip,pins =
1031                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1032                         };
1033
1034                         sdio0_pwr: sdio0-pwr {
1035                                 rockchip,pins =
1036                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1037                         };
1038
1039                         sdio0_bkpwr: sdio0-bkpwr {
1040                                 rockchip,pins =
1041                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1042                         };
1043
1044                         sdio0_wp: sdio0-wp {
1045                                 rockchip,pins =
1046                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1047                         };
1048
1049                         sdio0_int: sdio0-int {
1050                                 rockchip,pins =
1051                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1052                         };
1053                 };
1054
1055                 sdmmc {
1056                         sdmmc_bus1: sdmmc-bus1 {
1057                                 rockchip,pins =
1058                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1059                         };
1060
1061                         sdmmc_bus4: sdmmc-bus4 {
1062                                 rockchip,pins =
1063                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1064                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1065                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1066                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1067                         };
1068
1069                         sdmmc_clk: sdmmc-clk {
1070                                 rockchip,pins =
1071                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1072                         };
1073
1074                         sdmmc_cmd: sdmmc-cmd {
1075                                 rockchip,pins =
1076                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1077                         };
1078
1079                         sdmmc_cd: sdmcc-cd {
1080                                 rockchip,pins =
1081                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1082                         };
1083
1084                         sdmmc_wp: sdmmc-wp {
1085                                 rockchip,pins =
1086                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1087                         };
1088                 };
1089
1090                 spdif {
1091                         spdif_bus: spdif-bus {
1092                                 rockchip,pins =
1093                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1094                         };
1095                 };
1096
1097                 spi0 {
1098                         spi0_clk: spi0-clk {
1099                                 rockchip,pins =
1100                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1101                         };
1102                         spi0_cs0: spi0-cs0 {
1103                                 rockchip,pins =
1104                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1105                         };
1106                         spi0_cs1: spi0-cs1 {
1107                                 rockchip,pins =
1108                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1109                         };
1110                         spi0_tx: spi0-tx {
1111                                 rockchip,pins =
1112                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1113                         };
1114                         spi0_rx: spi0-rx {
1115                                 rockchip,pins =
1116                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1117                         };
1118                 };
1119
1120                 spi1 {
1121                         spi1_clk: spi1-clk {
1122                                 rockchip,pins =
1123                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1124                         };
1125                         spi1_cs0: spi1-cs0 {
1126                                 rockchip,pins =
1127                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1128                         };
1129                         spi1_rx: spi1-rx {
1130                                 rockchip,pins =
1131                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1132                         };
1133                         spi1_tx: spi1-tx {
1134                                 rockchip,pins =
1135                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1136                         };
1137                 };
1138
1139                 spi2 {
1140                         spi2_clk: spi2-clk {
1141                                 rockchip,pins =
1142                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1143                         };
1144                         spi2_cs0: spi2-cs0 {
1145                                 rockchip,pins =
1146                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1147                         };
1148                         spi2_rx: spi2-rx {
1149                                 rockchip,pins =
1150                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1151                         };
1152                         spi2_tx: spi2-tx {
1153                                 rockchip,pins =
1154                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1155                         };
1156                 };
1157
1158                 spi3 {
1159                         spi3_clk: spi3-clk {
1160                                 rockchip,pins =
1161                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1162                         };
1163                         spi3_cs0: spi3-cs0 {
1164                                 rockchip,pins =
1165                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1166                         };
1167                         spi3_rx: spi3-rx {
1168                                 rockchip,pins =
1169                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1170                         };
1171                         spi3_tx: spi3-tx {
1172                                 rockchip,pins =
1173                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1174                         };
1175                 };
1176
1177                 spi4 {
1178                         spi4_clk: spi4-clk {
1179                                 rockchip,pins =
1180                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1181                         };
1182                         spi4_cs0: spi4-cs0 {
1183                                 rockchip,pins =
1184                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1185                         };
1186                         spi4_rx: spi4-rx {
1187                                 rockchip,pins =
1188                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1189                         };
1190                         spi4_tx: spi4-tx {
1191                                 rockchip,pins =
1192                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1193                         };
1194                 };
1195
1196                 spi5 {
1197                         spi5_clk: spi5-clk {
1198                                 rockchip,pins =
1199                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1200                         };
1201                         spi5_cs0: spi5-cs0 {
1202                                 rockchip,pins =
1203                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1204                         };
1205                         spi5_rx: spi5-rx {
1206                                 rockchip,pins =
1207                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1208                         };
1209                         spi5_tx: spi5-tx {
1210                                 rockchip,pins =
1211                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1212                         };
1213                 };
1214
1215                 tsadc {
1216                         otp_gpio: otp-gpio {
1217                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1218                         };
1219
1220                         otp_out: otp-out {
1221                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1222                         };
1223                 };
1224
1225                 uart0 {
1226                         uart0_xfer: uart0-xfer {
1227                                 rockchip,pins =
1228                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1229                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1230                         };
1231
1232                         uart0_cts: uart0-cts {
1233                                 rockchip,pins =
1234                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1235                         };
1236
1237                         uart0_rts: uart0-rts {
1238                                 rockchip,pins =
1239                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1240                         };
1241                 };
1242
1243                 uart1 {
1244                         uart1_xfer: uart1-xfer {
1245                                 rockchip,pins =
1246                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1247                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1248                         };
1249                 };
1250
1251                 uart2a {
1252                         uart2a_xfer: uart2a-xfer {
1253                                 rockchip,pins =
1254                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1255                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1256                         };
1257                 };
1258
1259                 uart2b {
1260                         uart2b_xfer: uart2b-xfer {
1261                                 rockchip,pins =
1262                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1263                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1264                         };
1265                 };
1266
1267                 uart2c {
1268                         uart2c_xfer: uart2c-xfer {
1269                                 rockchip,pins =
1270                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1271                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1272                         };
1273                 };
1274
1275                 uart3 {
1276                         uart3_xfer: uart3-xfer {
1277                                 rockchip,pins =
1278                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1279                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1280                         };
1281
1282                         uart3_cts: uart3-cts {
1283                                 rockchip,pins =
1284                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1285                         };
1286
1287                         uart3_rts: uart3-rts {
1288                                 rockchip,pins =
1289                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1290                         };
1291                 };
1292
1293                 uart4 {
1294                         uart4_xfer: uart4-xfer {
1295                                 rockchip,pins =
1296                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1297                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1298                         };
1299                 };
1300
1301                 uarthdcp {
1302                         uarthdcp_xfer: uarthdcp-xfer {
1303                                 rockchip,pins =
1304                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1305                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1306                         };
1307                 };
1308
1309                 pwm0 {
1310                         pwm0_pin: pwm0-pin {
1311                                 rockchip,pins =
1312                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1313                         };
1314
1315                         vop0_pwm_pin: vop0-pwm-pin {
1316                                 rockchip,pins =
1317                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1318                         };
1319                 };
1320
1321                 pwm1 {
1322                         pwm1_pin: pwm1-pin {
1323                                 rockchip,pins =
1324                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1325                         };
1326
1327                         vop1_pwm_pin: vop1-pwm-pin {
1328                                 rockchip,pins =
1329                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 pwm2 {
1334                         pwm2_pin: pwm2-pin {
1335                                 rockchip,pins =
1336                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1337                         };
1338                 };
1339
1340                 pwm3a {
1341                         pwm3a_pin: pwm3a-pin {
1342                                 rockchip,pins =
1343                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345                 };
1346
1347                 pwm3b {
1348                         pwm3b_pin: pwm3b-pin {
1349                                 rockchip,pins =
1350                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1351                         };
1352                 };
1353         };
1354 };