arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 124                 };
 125
 126                 cpu_l1: cpu@1 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x1>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 135                 };
 136
 137                 cpu_l2: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 144                         operating-points-v2 = <&cluster0_opp>;
 145                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 146                 };
 147
 148                 cpu_l3: cpu@3 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a53", "arm,armv8";
 151                         reg = <0x0 0x3>;
 152                         enable-method = "psci";
 153                         clocks = <&cru ARMCLKL>;
 154                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 157                 };
 158
 159                 cpu_b0: cpu@100 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a72", "arm,armv8";
 162                         reg = <0x0 0x100>;
 163                         enable-method = "psci";
 164                         #cooling-cells = <2>; /* min followed by max */
 165                         dynamic-power-coefficient = <436>;
 166                         clocks = <&cru ARMCLKB>;
 167                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 170                 };
 171
 172                 cpu_b1: cpu@101 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a72", "arm,armv8";
 175                         reg = <0x0 0x101>;
 176                         enable-method = "psci";
 177                         clocks = <&cru ARMCLKB>;
 178                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 179                         operating-points-v2 = <&cluster1_opp>;
 180                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 181                 };
 182
 183                 idle-states {
 184                         entry-method = "psci";
 185
 186                         CPU_SLEEP: cpu-sleep {
 187                                 compatible = "arm,idle-state";
 188                                 local-timer-stop;
 189                                 arm,psci-suspend-param = <0x0010000>;
 190                                 entry-latency-us = <120>;
 191                                 exit-latency-us = <250>;
 192                                 min-residency-us = <900>;
 193                         };
 194
 195                         CLUSTER_SLEEP: cluster-sleep {
 196                                 compatible = "arm,idle-state";
 197                                 local-timer-stop;
 198                                 arm,psci-suspend-param = <0x1010000>;
 199                                 entry-latency-us = <400>;
 200                                 exit-latency-us = <500>;
 201                                 min-residency-us = <2000>;
 202                         };
 203                 };
 204
 205                 /include/ "rk3399-sched-energy.dtsi"
 206
 207         };
 208
 209         cluster0_opp: opp_table0 {
 210                 compatible = "operating-points-v2";
 211                 opp-shared;
 212
 213                 opp@408000000 {
 214                         opp-hz = /bits/ 64 <408000000>;
 215                         opp-microvolt = <800000>;
 216                         clock-latency-ns = <40000>;
 217                 };
 218                 opp@600000000 {
 219                         opp-hz = /bits/ 64 <600000000>;
 220                         opp-microvolt = <800000>;
 221                 };
 222                 opp@816000000 {
 223                         opp-hz = /bits/ 64 <816000000>;
 224                         opp-microvolt = <800000>;
 225                 };
 226                 opp@1008000000 {
 227                         opp-hz = /bits/ 64 <1008000000>;
 228                         opp-microvolt = <875000>;
 229                 };
 230                 opp@1200000000 {
 231                         opp-hz = /bits/ 64 <1200000000>;
 232                         opp-microvolt = <925000>;
 233                 };
 234                 opp@1416000000 {
 235                         opp-hz = /bits/ 64 <1416000000>;
 236                         opp-microvolt = <1025000>;
 237                 };
 238         };
 239
 240         cluster1_opp: opp_table1 {
 241                 compatible = "operating-points-v2";
 242                 opp-shared;
 243
 244                 opp@408000000 {
 245                         opp-hz = /bits/ 64 <408000000>;
 246                         opp-microvolt = <800000>;
 247                         clock-latency-ns = <40000>;
 248                 };
 249                 opp@600000000 {
 250                         opp-hz = /bits/ 64 <600000000>;
 251                         opp-microvolt = <800000>;
 252                 };
 253                 opp@816000000 {
 254                         opp-hz = /bits/ 64 <816000000>;
 255                         opp-microvolt = <800000>;
 256                 };
 257                 opp@1008000000 {
 258                         opp-hz = /bits/ 64 <1008000000>;
 259                         opp-microvolt = <850000>;
 260                 };
 261                 opp@1200000000 {
 262                         opp-hz = /bits/ 64 <1200000000>;
 263                         opp-microvolt = <925000>;
 264                 };
 265         };
 266
 267         cpu_avs: cpu-avs {
 268                 cluster0-avs {
 269                         cluster-id = <0>;
 270                         min-volt = <800000>; /* uV */
 271                         min-freq = <408000>; /* KHz */
 272                         leakage-adjust-volt = <
 273                         /*  mA        mA         uV */
 274                             0         254        0
 275                         >;
 276                         nvmem-cells = <&cpul_leakage>;
 277                         nvmem-cell-names = "cpu_leakage";
 278                 };
 279                 cluster1-avs {
 280                         cluster-id = <1>;
 281                         min-volt = <800000>; /* uV */
 282                         min-freq = <408000>; /* KHz */
 283                         leakage-adjust-volt = <
 284                         /*  mA        mA         uV */
 285                             0         254        0
 286                         >;
 287                         nvmem-cells = <&cpub_leakage>;
 288                         nvmem-cell-names = "cpu_leakage";
 289                 };
 290         };
 291
 292         timer {
 293                 compatible = "arm,armv8-timer";
 294                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 295                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 296                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 297                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 298         };
 299
 300         pmu_a53 {
 301                 compatible = "arm,cortex-a53-pmu";
 302                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 303         };
 304
 305         pmu_a72 {
 306                 compatible = "arm,cortex-a72-pmu";
 307                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 308         };
 309
 310         xin24m: xin24m {
 311                 compatible = "fixed-clock";
 312                 #clock-cells = <0>;
 313                 clock-frequency = <24000000>;
 314                 clock-output-names = "xin24m";
 315         };
 316
 317         amba {
 318                 compatible = "arm,amba-bus";
 319                 #address-cells = <2>;
 320                 #size-cells = <2>;
 321                 ranges;
 322
 323                 dmac_bus: dma-controller@ff6d0000 {
 324                         compatible = "arm,pl330", "arm,primecell";
 325                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 326                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 327                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 328                         #dma-cells = <1>;
 329                         clocks = <&cru ACLK_DMAC0_PERILP>;
 330                         clock-names = "apb_pclk";
 331                         peripherals-req-type-burst;
 332                 };
 333
 334                 dmac_peri: dma-controller@ff6e0000 {
 335                         compatible = "arm,pl330", "arm,primecell";
 336                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 337                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 338                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 339                         #dma-cells = <1>;
 340                         clocks = <&cru ACLK_DMAC1_PERILP>;
 341                         clock-names = "apb_pclk";
 342                         peripherals-req-type-burst;
 343                 };
 344         };
 345
 346         gmac: eth@fe300000 {
 347                 compatible = "rockchip,rk3399-gmac";
 348                 reg = <0x0 0xfe300000 0x0 0x10000>;
 349                 rockchip,grf = <&grf>;
 350                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 351                 interrupt-names = "macirq";
 352                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 353                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 354                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 355                          <&cru PCLK_GMAC>;
 356                 clock-names = "stmmaceth", "mac_clk_rx",
 357                               "mac_clk_tx", "clk_mac_ref",
 358                               "clk_mac_refout", "aclk_mac",
 359                               "pclk_mac";
 360                 resets = <&cru SRST_A_GMAC>;
 361                 reset-names = "stmmaceth";
 362                 power-domains = <&power RK3399_PD_GMAC>;
 363                 status = "disabled";
 364         };
 365
 366         sdio0: dwmmc@fe310000 {
 367                 compatible = "rockchip,rk3399-dw-mshc",
 368                              "rockchip,rk3288-dw-mshc";
 369                 reg = <0x0 0xfe310000 0x0 0x4000>;
 370                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 371                 clock-freq-min-max = <400000 150000000>;
 372                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 373                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 374                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 375                 fifo-depth = <0x100>;
 376                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 377                 status = "disabled";
 378         };
 379
 380         sdmmc: dwmmc@fe320000 {
 381                 compatible = "rockchip,rk3399-dw-mshc",
 382                              "rockchip,rk3288-dw-mshc";
 383                 reg = <0x0 0xfe320000 0x0 0x4000>;
 384                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 385                 clock-freq-min-max = <400000 150000000>;
 386                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 387                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 388                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 389                 fifo-depth = <0x100>;
 390                 power-domains = <&power RK3399_PD_SD>;
 391                 status = "disabled";
 392         };
 393
 394         sdhci: sdhci@fe330000 {
 395                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 396                 reg = <0x0 0xfe330000 0x0 0x10000>;
 397                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 398                 arasan,soc-ctl-syscon = <&grf>;
 399                 assigned-clocks = <&cru SCLK_EMMC>;
 400                 assigned-clock-rates = <200000000>;
 401                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 402                 clock-names = "clk_xin", "clk_ahb";
 403                 clock-output-names = "emmc_cardclock";
 404                 #clock-cells = <0>;
 405                 phys = <&emmc_phy>;
 406                 phy-names = "phy_arasan";
 407                 power-domains = <&power RK3399_PD_EMMC>;
 408                 status = "disabled";
 409         };
 410
 411         usb_host0_ehci: usb@fe380000 {
 412                 compatible = "generic-ehci";
 413                 reg = <0x0 0xfe380000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 415                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 416                          <&cru SCLK_USBPHY0_480M_SRC>;
 417                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 418                 phys = <&u2phy0_host>;
 419                 phy-names = "usb";
 420                 power-domains = <&power RK3399_PD_PERIHP>;
 421                 status = "disabled";
 422         };
 423
 424         usb_host0_ohci: usb@fe3a0000 {
 425                 compatible = "generic-ohci";
 426                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 427                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 428                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 429                          <&cru SCLK_USBPHY0_480M_SRC>;
 430                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 431                 phys = <&u2phy0_host>;
 432                 phy-names = "usb";
 433                 power-domains = <&power RK3399_PD_PERIHP>;
 434                 status = "disabled";
 435         };
 436
 437         usb_host1_ehci: usb@fe3c0000 {
 438                 compatible = "generic-ehci";
 439                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 440                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 441                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 442                          <&cru SCLK_USBPHY1_480M_SRC>;
 443                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 444                 phys = <&u2phy1_host>;
 445                 phy-names = "usb";
 446                 power-domains = <&power RK3399_PD_PERIHP>;
 447                 status = "disabled";
 448         };
 449
 450         usb_host1_ohci: usb@fe3e0000 {
 451                 compatible = "generic-ohci";
 452                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 453                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 454                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 455                          <&cru SCLK_USBPHY1_480M_SRC>;
 456                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 457                 phys = <&u2phy1_host>;
 458                 phy-names = "usb";
 459                 power-domains = <&power RK3399_PD_PERIHP>;
 460                 status = "disabled";
 461         };
 462
 463         usbdrd3_0: usb@fe800000 {
 464                 compatible = "rockchip,rk3399-dwc3";
 465                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 466                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 467                 clock-names = "ref_clk", "suspend_clk",
 468                               "bus_clk", "grf_clk";
 469                 power-domains = <&power RK3399_PD_USB3>;
 470                 resets = <&cru SRST_A_USB3_OTG0>;
 471                 reset-names = "usb3-otg";
 472                 #address-cells = <2>;
 473                 #size-cells = <2>;
 474                 ranges;
 475                 status = "disabled";
 476                 usbdrd_dwc3_0: dwc3@fe800000 {
 477                         compatible = "snps,dwc3";
 478                         reg = <0x0 0xfe800000 0x0 0x100000>;
 479                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 480                         dr_mode = "otg";
 481                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 482                         phy-names = "usb2-phy", "usb3-phy";
 483                         phy_type = "utmi_wide";
 484                         snps,dis_enblslpm_quirk;
 485                         snps,dis-u2-freeclk-exists-quirk;
 486                         snps,dis_u2_susphy_quirk;
 487                         snps,dis-del-phy-power-chg-quirk;
 488                         snps,xhci-slow-suspend-quirk;
 489                         status = "disabled";
 490                 };
 491         };
 492
 493         usbdrd3_1: usb@fe900000 {
 494                 compatible = "rockchip,rk3399-dwc3";
 495                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 496                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 497                 clock-names = "ref_clk", "suspend_clk",
 498                               "bus_clk", "grf_clk";
 499                 power-domains = <&power RK3399_PD_USB3>;
 500                 resets = <&cru SRST_A_USB3_OTG1>;
 501                 reset-names = "usb3-otg";
 502                 #address-cells = <2>;
 503                 #size-cells = <2>;
 504                 ranges;
 505                 status = "disabled";
 506                 usbdrd_dwc3_1: dwc3@fe900000 {
 507                         compatible = "snps,dwc3";
 508                         reg = <0x0 0xfe900000 0x0 0x100000>;
 509                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 510                         dr_mode = "host";
 511                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 512                         phy-names = "usb2-phy", "usb3-phy";
 513                         phy_type = "utmi_wide";
 514                         snps,dis_enblslpm_quirk;
 515                         snps,dis-u2-freeclk-exists-quirk;
 516                         snps,dis_u2_susphy_quirk;
 517                         snps,dis-del-phy-power-chg-quirk;
 518                         snps,xhci-slow-suspend-quirk;
 519                         status = "disabled";
 520                 };
 521         };
 522
 523         gic: interrupt-controller@fee00000 {
 524                 compatible = "arm,gic-v3";
 525                 #interrupt-cells = <4>;
 526                 #address-cells = <2>;
 527                 #size-cells = <2>;
 528                 ranges;
 529                 interrupt-controller;
 530
 531                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 532                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 533                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 534                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 535                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 536                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 537                 its: interrupt-controller@fee20000 {
 538                         compatible = "arm,gic-v3-its";
 539                         msi-controller;
 540                         reg = <0x0 0xfee20000 0x0 0x20000>;
 541                 };
 542
 543                 ppi-partitions {
 544                         part0: interrupt-partition-0 {
 545                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 546                         };
 547
 548                         part1: interrupt-partition-1 {
 549                                 affinity = <&cpu_b0 &cpu_b1>;
 550                         };
 551                 };
 552         };
 553
 554         saradc: saradc@ff100000 {
 555                 compatible = "rockchip,rk3399-saradc";
 556                 reg = <0x0 0xff100000 0x0 0x100>;
 557                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 558                 #io-channel-cells = <1>;
 559                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 560                 clock-names = "saradc", "apb_pclk";
 561                 resets = <&cru SRST_P_SARADC>;
 562                 reset-names = "saradc-apb";
 563                 status = "disabled";
 564         };
 565
 566         i2c0: i2c@ff3c0000 {
 567                 compatible = "rockchip,rk3399-i2c";
 568                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 569                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 570                 clock-names = "i2c", "pclk";
 571                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c0_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c1: i2c@ff110000 {
 580                 compatible = "rockchip,rk3399-i2c";
 581                 reg = <0x0 0xff110000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 583                 clock-names = "i2c", "pclk";
 584                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2c1_xfer>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         i2c2: i2c@ff120000 {
 593                 compatible = "rockchip,rk3399-i2c";
 594                 reg = <0x0 0xff120000 0x0 0x1000>;
 595                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 596                 clock-names = "i2c", "pclk";
 597                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&i2c2_xfer>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         i2c3: i2c@ff130000 {
 606                 compatible = "rockchip,rk3399-i2c";
 607                 reg = <0x0 0xff130000 0x0 0x1000>;
 608                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 609                 clock-names = "i2c", "pclk";
 610                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&i2c3_xfer>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 status = "disabled";
 616         };
 617
 618         i2c5: i2c@ff140000 {
 619                 compatible = "rockchip,rk3399-i2c";
 620                 reg = <0x0 0xff140000 0x0 0x1000>;
 621                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 622                 clock-names = "i2c", "pclk";
 623                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&i2c5_xfer>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 status = "disabled";
 629         };
 630
 631         i2c6: i2c@ff150000 {
 632                 compatible = "rockchip,rk3399-i2c";
 633                 reg = <0x0 0xff150000 0x0 0x1000>;
 634                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 635                 clock-names = "i2c", "pclk";
 636                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&i2c6_xfer>;
 639                 #address-cells = <1>;
 640                 #size-cells = <0>;
 641                 status = "disabled";
 642         };
 643
 644         i2c7: i2c@ff160000 {
 645                 compatible = "rockchip,rk3399-i2c";
 646                 reg = <0x0 0xff160000 0x0 0x1000>;
 647                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 648                 clock-names = "i2c", "pclk";
 649                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&i2c7_xfer>;
 652                 #address-cells = <1>;
 653                 #size-cells = <0>;
 654                 status = "disabled";
 655         };
 656
 657         uart0: serial@ff180000 {
 658                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 659                 reg = <0x0 0xff180000 0x0 0x100>;
 660                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 661                 clock-names = "baudclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 663                 reg-shift = <2>;
 664                 reg-io-width = <4>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 667                 status = "disabled";
 668         };
 669
 670         uart1: serial@ff190000 {
 671                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 672                 reg = <0x0 0xff190000 0x0 0x100>;
 673                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 674                 clock-names = "baudclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 676                 reg-shift = <2>;
 677                 reg-io-width = <4>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&uart1_xfer>;
 680                 status = "disabled";
 681         };
 682
 683         uart2: serial@ff1a0000 {
 684                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 685                 reg = <0x0 0xff1a0000 0x0 0x100>;
 686                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 687                 clock-names = "baudclk", "apb_pclk";
 688                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 689                 reg-shift = <2>;
 690                 reg-io-width = <4>;
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&uart2c_xfer>;
 693                 status = "disabled";
 694         };
 695
 696         uart3: serial@ff1b0000 {
 697                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 698                 reg = <0x0 0xff1b0000 0x0 0x100>;
 699                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 700                 clock-names = "baudclk", "apb_pclk";
 701                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 702                 reg-shift = <2>;
 703                 reg-io-width = <4>;
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 706                 status = "disabled";
 707         };
 708
 709         spi0: spi@ff1c0000 {
 710                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 711                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 712                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 713                 clock-names = "spiclk", "apb_pclk";
 714                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 status = "disabled";
 720         };
 721
 722         spi1: spi@ff1d0000 {
 723                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 724                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 725                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 726                 clock-names = "spiclk", "apb_pclk";
 727                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 728                 pinctrl-names = "default";
 729                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 730                 #address-cells = <1>;
 731                 #size-cells = <0>;
 732                 status = "disabled";
 733         };
 734
 735         spi2: spi@ff1e0000 {
 736                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 737                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 738                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 739                 clock-names = "spiclk", "apb_pclk";
 740                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 741                 pinctrl-names = "default";
 742                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 743                 #address-cells = <1>;
 744                 #size-cells = <0>;
 745                 status = "disabled";
 746         };
 747
 748         spi4: spi@ff1f0000 {
 749                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 750                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 751                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 752                 clock-names = "spiclk", "apb_pclk";
 753                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 754                 pinctrl-names = "default";
 755                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 756                 #address-cells = <1>;
 757                 #size-cells = <0>;
 758                 status = "disabled";
 759         };
 760
 761         spi5: spi@ff200000 {
 762                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 763                 reg = <0x0 0xff200000 0x0 0x1000>;
 764                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 765                 clock-names = "spiclk", "apb_pclk";
 766                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 767                 pinctrl-names = "default";
 768                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 769                 #address-cells = <1>;
 770                 #size-cells = <0>;
 771                 status = "disabled";
 772         };
 773
 774         thermal-zones {
 775                 soc_thermal: soc-thermal {
 776                         polling-delay-passive = <20>; /* milliseconds */
 777                         polling-delay = <1000>; /* milliseconds */
 778                         sustainable-power = <1000>; /* milliwatts */
 779
 780                         thermal-sensors = <&tsadc 0>;
 781
 782                         trips {
 783                                 threshold: trip-point@0 {
 784                                         temperature = <70000>; /* millicelsius */
 785                                         hysteresis = <2000>; /* millicelsius */
 786                                         type = "passive";
 787                                 };
 788                                 target: trip-point@1 {
 789                                         temperature = <85000>; /* millicelsius */
 790                                         hysteresis = <2000>; /* millicelsius */
 791                                         type = "passive";
 792                                 };
 793                                 soc_crit: soc-crit {
 794                                         temperature = <95000>; /* millicelsius */
 795                                         hysteresis = <2000>; /* millicelsius */
 796                                         type = "critical";
 797                                 };
 798                         };
 799
 800                         cooling-maps {
 801                                 map0 {
 802                                         trip = <&target>;
 803                                         cooling-device =
 804                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 805                                         contribution = <4096>;
 806                                 };
 807                                 map1 {
 808                                         trip = <&target>;
 809                                         cooling-device =
 810                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 811                                         contribution = <1024>;
 812                                 };
 813                                 map2 {
 814                                         trip = <&target>;
 815                                         cooling-device =
 816                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 817                                         contribution = <4096>;
 818                                 };
 819                         };
 820                 };
 821
 822                 gpu_thermal: gpu-thermal {
 823                         polling-delay-passive = <100>; /* milliseconds */
 824                         polling-delay = <1000>; /* milliseconds */
 825
 826                         thermal-sensors = <&tsadc 1>;
 827                 };
 828         };
 829
 830         tsadc: tsadc@ff260000 {
 831                 compatible = "rockchip,rk3399-tsadc";
 832                 reg = <0x0 0xff260000 0x0 0x100>;
 833                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 834                 rockchip,grf = <&grf>;
 835                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 836                 clock-names = "tsadc", "apb_pclk";
 837                 assigned-clocks = <&cru SCLK_TSADC>;
 838                 assigned-clock-rates = <750000>;
 839                 resets = <&cru SRST_TSADC>;
 840                 reset-names = "tsadc-apb";
 841                 pinctrl-names = "init", "default", "sleep";
 842                 pinctrl-0 = <&otp_gpio>;
 843                 pinctrl-1 = <&otp_out>;
 844                 pinctrl-2 = <&otp_gpio>;
 845                 #thermal-sensor-cells = <1>;
 846                 rockchip,hw-tshut-temp = <95000>;
 847                 status = "disabled";
 848         };
 849
 850         qos_emmc: qos@ffa58000 {
 851                 compatible = "syscon";
 852                 reg = <0x0 0xffa58000 0x0 0x20>;
 853         };
 854
 855         qos_gmac: qos@ffa5c000 {
 856                 compatible = "syscon";
 857                 reg = <0x0 0xffa5c000 0x0 0x20>;
 858         };
 859
 860         qos_pcie: qos@ffa60080 {
 861                 compatible = "syscon";
 862                 reg = <0x0 0xffa60080 0x0 0x20>;
 863         };
 864
 865         qos_usb_host0: qos@ffa60100 {
 866                 compatible = "syscon";
 867                 reg = <0x0 0xffa60100 0x0 0x20>;
 868         };
 869
 870         qos_usb_host1: qos@ffa60180 {
 871                 compatible = "syscon";
 872                 reg = <0x0 0xffa60180 0x0 0x20>;
 873         };
 874
 875         qos_usb_otg0: qos@ffa70000 {
 876                 compatible = "syscon";
 877                 reg = <0x0 0xffa70000 0x0 0x20>;
 878         };
 879
 880         qos_usb_otg1: qos@ffa70080 {
 881                 compatible = "syscon";
 882                 reg = <0x0 0xffa70080 0x0 0x20>;
 883         };
 884
 885         qos_sd: qos@ffa74000 {
 886                 compatible = "syscon";
 887                 reg = <0x0 0xffa74000 0x0 0x20>;
 888         };
 889
 890         qos_sdioaudio: qos@ffa76000 {
 891                 compatible = "syscon";
 892                 reg = <0x0 0xffa76000 0x0 0x20>;
 893         };
 894
 895         qos_hdcp: qos@ffa90000 {
 896                 compatible = "syscon";
 897                 reg = <0x0 0xffa90000 0x0 0x20>;
 898         };
 899
 900         qos_iep: qos@ffa98000 {
 901                 compatible = "syscon";
 902                 reg = <0x0 0xffa98000 0x0 0x20>;
 903         };
 904
 905         qos_isp0_m0: qos@ffaa0000 {
 906                 compatible = "syscon";
 907                 reg = <0x0 0xffaa0000 0x0 0x20>;
 908         };
 909
 910         qos_isp0_m1: qos@ffaa0080 {
 911                 compatible = "syscon";
 912                 reg = <0x0 0xffaa0080 0x0 0x20>;
 913         };
 914
 915         qos_isp1_m0: qos@ffaa8000 {
 916                 compatible = "syscon";
 917                 reg = <0x0 0xffaa8000 0x0 0x20>;
 918         };
 919
 920         qos_isp1_m1: qos@ffaa8080 {
 921                 compatible = "syscon";
 922                 reg = <0x0 0xffaa8080 0x0 0x20>;
 923         };
 924
 925         qos_rga_r: qos@ffab0000 {
 926                 compatible = "syscon";
 927                 reg = <0x0 0xffab0000 0x0 0x20>;
 928         };
 929
 930         qos_rga_w: qos@ffab0080 {
 931                 compatible = "syscon";
 932                 reg = <0x0 0xffab0080 0x0 0x20>;
 933         };
 934
 935         qos_video_m0: qos@ffab8000 {
 936                 compatible = "syscon";
 937                 reg = <0x0 0xffab8000 0x0 0x20>;
 938         };
 939
 940         qos_video_m1_r: qos@ffac0000 {
 941                 compatible = "syscon";
 942                 reg = <0x0 0xffac0000 0x0 0x20>;
 943         };
 944
 945         qos_video_m1_w: qos@ffac0080 {
 946                 compatible = "syscon";
 947                 reg = <0x0 0xffac0080 0x0 0x20>;
 948         };
 949
 950         qos_vop_big_r: qos@ffac8000 {
 951                 compatible = "syscon";
 952                 reg = <0x0 0xffac8000 0x0 0x20>;
 953         };
 954
 955         qos_vop_big_w: qos@ffac8080 {
 956                 compatible = "syscon";
 957                 reg = <0x0 0xffac8080 0x0 0x20>;
 958         };
 959
 960         qos_vop_little: qos@ffad0000 {
 961                 compatible = "syscon";
 962                 reg = <0x0 0xffad0000 0x0 0x20>;
 963         };
 964
 965         qos_perihp: qos@ffad8080 {
 966                 compatible = "syscon";
 967                 reg = <0x0 0xffad8080 0x0 0x20>;
 968         };
 969
 970         qos_gpu: qos@ffae0000 {
 971                 compatible = "syscon";
 972                 reg = <0x0 0xffae0000 0x0 0x20>;
 973         };
 974
 975         pmu: power-management@ff310000 {
 976                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 977                 reg = <0x0 0xff310000 0x0 0x1000>;
 978
 979                 /*
 980                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 981                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 982                  * Some of the power domains are grouped together for every
 983                  * voltage domain.
 984                  * The detail contents as below.
 985                  */
 986                 power: power-controller {
 987                         compatible = "rockchip,rk3399-power-controller";
 988                         #power-domain-cells = <1>;
 989                         #address-cells = <1>;
 990                         #size-cells = <0>;
 991
 992                         /* These power domains are grouped by VD_CENTER */
 993                         pd_iep@RK3399_PD_IEP {
 994                                 reg = <RK3399_PD_IEP>;
 995                                 clocks = <&cru ACLK_IEP>,
 996                                          <&cru HCLK_IEP>;
 997                                 pm_qos = <&qos_iep>;
 998                         };
 999                         pd_rga@RK3399_PD_RGA {
1000                                 reg = <RK3399_PD_RGA>;
1001                                 clocks = <&cru ACLK_RGA>,
1002                                          <&cru HCLK_RGA>;
1003                                 pm_qos = <&qos_rga_r>,
1004                                          <&qos_rga_w>;
1005                         };
1006                         pd_vcodec@RK3399_PD_VCODEC {
1007                                 reg = <RK3399_PD_VCODEC>;
1008                                 clocks = <&cru ACLK_VCODEC>,
1009                                          <&cru HCLK_VCODEC>;
1010                                 pm_qos = <&qos_video_m0>;
1011                         };
1012                         pd_vdu@RK3399_PD_VDU {
1013                                 reg = <RK3399_PD_VDU>;
1014                                 clocks = <&cru ACLK_VDU>,
1015                                          <&cru HCLK_VDU>;
1016                                 pm_qos = <&qos_video_m1_r>,
1017                                          <&qos_video_m1_w>;
1018                         };
1019
1020                         /* These power domains are grouped by VD_GPU */
1021                         pd_gpu@RK3399_PD_GPU {
1022                                 reg = <RK3399_PD_GPU>;
1023                                 clocks = <&cru ACLK_GPU>;
1024                                 pm_qos = <&qos_gpu>;
1025                         };
1026
1027                         /* These power domains are grouped by VD_LOGIC */
1028                         pd_edp@RK3399_PD_EDP {
1029                                 reg = <RK3399_PD_EDP>;
1030                                 clocks = <&cru PCLK_EDP_CTRL>;
1031                         };
1032                         pd_emmc@RK3399_PD_EMMC {
1033                                 reg = <RK3399_PD_EMMC>;
1034                                 clocks = <&cru ACLK_EMMC>;
1035                                 pm_qos = <&qos_emmc>;
1036                         };
1037                         pd_gmac@RK3399_PD_GMAC {
1038                                 reg = <RK3399_PD_GMAC>;
1039                                 clocks = <&cru ACLK_GMAC>;
1040                                 pm_qos = <&qos_gmac>;
1041                         };
1042                         pd_perihp@RK3399_PD_PERIHP {
1043                                 reg = <RK3399_PD_PERIHP>;
1044                                 #address-cells = <1>;
1045                                 #size-cells = <0>;
1046                                 clocks = <&cru ACLK_PERIHP>;
1047                                 pm_qos = <&qos_perihp>,
1048                                          <&qos_pcie>,
1049                                          <&qos_usb_host0>,
1050                                          <&qos_usb_host1>;
1051
1052                                 pd_sd@RK3399_PD_SD {
1053                                         reg = <RK3399_PD_SD>;
1054                                         clocks = <&cru HCLK_SDMMC>,
1055                                                  <&cru SCLK_SDMMC>;
1056                                         pm_qos = <&qos_sd>;
1057                                 };
1058                         };
1059                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1060                                 reg = <RK3399_PD_SDIOAUDIO>;
1061                                 clocks = <&cru HCLK_SDIO>;
1062                                 pm_qos = <&qos_sdioaudio>;
1063                         };
1064                         pd_usb3@RK3399_PD_USB3 {
1065                                 reg = <RK3399_PD_USB3>;
1066                                 clocks = <&cru ACLK_USB3>;
1067                                 pm_qos = <&qos_usb_otg0>,
1068                                          <&qos_usb_otg1>;
1069                         };
1070                         pd_vio@RK3399_PD_VIO {
1071                                 reg = <RK3399_PD_VIO>;
1072                                 #address-cells = <1>;
1073                                 #size-cells = <0>;
1074
1075                                 pd_hdcp@RK3399_PD_HDCP {
1076                                         reg = <RK3399_PD_HDCP>;
1077                                         clocks = <&cru ACLK_HDCP>,
1078                                                  <&cru HCLK_HDCP>,
1079                                                  <&cru PCLK_HDCP>;
1080                                         pm_qos = <&qos_hdcp>;
1081                                 };
1082                                 pd_isp0@RK3399_PD_ISP0 {
1083                                         reg = <RK3399_PD_ISP0>;
1084                                         clocks = <&cru ACLK_ISP0>,
1085                                                  <&cru HCLK_ISP0>;
1086                                         pm_qos = <&qos_isp0_m0>,
1087                                                  <&qos_isp0_m1>;
1088                                 };
1089                                 pd_isp1@RK3399_PD_ISP1 {
1090                                         reg = <RK3399_PD_ISP1>;
1091                                         clocks = <&cru ACLK_ISP1>,
1092                                                  <&cru HCLK_ISP1>;
1093                                         pm_qos = <&qos_isp1_m0>,
1094                                                  <&qos_isp1_m1>;
1095                                 };
1096                                 pd_tcpc0@RK3399_PD_TCPC0 {
1097                                         reg = <RK3399_PD_TCPD0>;
1098                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1099                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1100                                 };
1101                                 pd_tcpc1@RK3399_PD_TCPC1 {
1102                                         reg = <RK3399_PD_TCPD1>;
1103                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1104                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1105                                 };
1106                                 pd_vo@RK3399_PD_VO {
1107                                         reg = <RK3399_PD_VO>;
1108                                         #address-cells = <1>;
1109                                         #size-cells = <0>;
1110
1111                                         pd_vopb@RK3399_PD_VOPB {
1112                                                 reg = <RK3399_PD_VOPB>;
1113                                                 clocks = <&cru ACLK_VOP0>,
1114                                                          <&cru HCLK_VOP0>;
1115                                                 pm_qos = <&qos_vop_big_r>,
1116                                                          <&qos_vop_big_w>;
1117                                         };
1118                                         pd_vopl@RK3399_PD_VOPL {
1119                                                 reg = <RK3399_PD_VOPL>;
1120                                                 clocks = <&cru ACLK_VOP1>,
1121                                                          <&cru HCLK_VOP1>;
1122                                                 pm_qos = <&qos_vop_little>;
1123                                         };
1124                                 };
1125                         };
1126                 };
1127         };
1128
1129         pmugrf: syscon@ff320000 {
1130                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1131                 reg = <0x0 0xff320000 0x0 0x1000>;
1132
1133                 reboot-mode {
1134                         compatible = "syscon-reboot-mode";
1135                         offset = <0x300>;
1136                         mode-bootloader = <BOOT_LOADER>;
1137                         mode-charge = <BOOT_CHARGING>;
1138                         mode-fastboot = <BOOT_FASTBOOT>;
1139                         mode-loader = <BOOT_LOADER>;
1140                         mode-normal = <BOOT_NORMAL>;
1141                         mode-recovery = <BOOT_RECOVERY>;
1142                         mode-ums = <BOOT_UMS>;
1143                 };
1144         };
1145
1146         spi3: spi@ff350000 {
1147                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1148                 reg = <0x0 0xff350000 0x0 0x1000>;
1149                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1150                 clock-names = "spiclk", "apb_pclk";
1151                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1152                 pinctrl-names = "default";
1153                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1154                 #address-cells = <1>;
1155                 #size-cells = <0>;
1156                 status = "disabled";
1157         };
1158
1159         uart4: serial@ff370000 {
1160                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1161                 reg = <0x0 0xff370000 0x0 0x100>;
1162                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1163                 clock-names = "baudclk", "apb_pclk";
1164                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1165                 reg-shift = <2>;
1166                 reg-io-width = <4>;
1167                 pinctrl-names = "default";
1168                 pinctrl-0 = <&uart4_xfer>;
1169                 status = "disabled";
1170         };
1171
1172         i2c4: i2c@ff3d0000 {
1173                 compatible = "rockchip,rk3399-i2c";
1174                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1175                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1176                 clock-names = "i2c", "pclk";
1177                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1178                 pinctrl-names = "default";
1179                 pinctrl-0 = <&i2c4_xfer>;
1180                 #address-cells = <1>;
1181                 #size-cells = <0>;
1182                 status = "disabled";
1183         };
1184
1185         i2c8: i2c@ff3e0000 {
1186                 compatible = "rockchip,rk3399-i2c";
1187                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1188                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1189                 clock-names = "i2c", "pclk";
1190                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1191                 pinctrl-names = "default";
1192                 pinctrl-0 = <&i2c8_xfer>;
1193                 #address-cells = <1>;
1194                 #size-cells = <0>;
1195                 status = "disabled";
1196         };
1197
1198         pcie_phy: phy@e220 {
1199                 compatible = "rockchip,rk3399-pcie-phy";
1200                 #phy-cells = <0>;
1201                 rockchip,grf = <&grf>;
1202                 clocks = <&cru SCLK_PCIEPHY_REF>;
1203                 clock-names = "refclk";
1204                 resets = <&cru SRST_PCIEPHY>;
1205                 reset-names = "phy";
1206                 status = "disabled";
1207         };
1208
1209         pcie0: pcie@f8000000 {
1210                 compatible = "rockchip,rk3399-pcie";
1211                 #address-cells = <3>;
1212                 #size-cells = <2>;
1213                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1214                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1215                 clock-names = "aclk", "aclk-perf",
1216                               "hclk", "pm";
1217                 bus-range = <0x0 0x1>;
1218                 msi-map = <0x0 &its 0x0 0x1000>;
1219                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1220                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1221                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1222                 interrupt-names = "sys", "legacy", "client";
1223                 #interrupt-cells = <1>;
1224                 interrupt-map-mask = <0 0 0 7>;
1225                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1226                                 <0 0 0 2 &pcie0_intc 1>,
1227                                 <0 0 0 3 &pcie0_intc 2>,
1228                                 <0 0 0 4 &pcie0_intc 3>;
1229                 phys = <&pcie_phy>;
1230                 phy-names = "pcie-phy";
1231                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1232                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1233                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1234                       <0x0 0xfd000000 0x0 0x1000000>;
1235                 reg-names = "axi-base", "apb-base";
1236                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1237                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1238                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1239                 status = "disabled";
1240                 pcie0_intc: interrupt-controller {
1241                         interrupt-controller;
1242                         #address-cells = <0>;
1243                         #interrupt-cells = <1>;
1244                 };
1245         };
1246
1247         pwm0: pwm@ff420000 {
1248                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1249                 reg = <0x0 0xff420000 0x0 0x10>;
1250                 #pwm-cells = <3>;
1251                 pinctrl-names = "default";
1252                 pinctrl-0 = <&pwm0_pin>;
1253                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1254                 clock-names = "pwm";
1255                 status = "disabled";
1256         };
1257
1258         pwm1: pwm@ff420010 {
1259                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1260                 reg = <0x0 0xff420010 0x0 0x10>;
1261                 #pwm-cells = <3>;
1262                 pinctrl-names = "default";
1263                 pinctrl-0 = <&pwm1_pin>;
1264                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1265                 clock-names = "pwm";
1266                 status = "disabled";
1267         };
1268
1269         pwm2: pwm@ff420020 {
1270                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1271                 reg = <0x0 0xff420020 0x0 0x10>;
1272                 #pwm-cells = <3>;
1273                 pinctrl-names = "default";
1274                 pinctrl-0 = <&pwm2_pin>;
1275                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1276                 clock-names = "pwm";
1277                 status = "disabled";
1278         };
1279
1280         pwm3: pwm@ff420030 {
1281                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1282                 reg = <0x0 0xff420030 0x0 0x10>;
1283                 #pwm-cells = <3>;
1284                 pinctrl-names = "default";
1285                 pinctrl-0 = <&pwm3a_pin>;
1286                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1287                 clock-names = "pwm";
1288                 status = "disabled";
1289         };
1290
1291         dfi: dfi@ff630000 {
1292                 reg = <0x00 0xff630000 0x00 0x4000>;
1293                 compatible = "rockchip,rk3399-dfi";
1294                 rockchip,pmu = <&pmugrf>;
1295                 clocks = <&cru PCLK_DDR_MON>;
1296                 clock-names = "pclk_ddr_mon";
1297                 status = "disabled";
1298         };
1299
1300         dmc: dmc {
1301                 compatible = "rockchip,rk3399-dmc";
1302                 devfreq-events = <&dfi>;
1303                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1304                 clocks = <&cru SCLK_DDRCLK>;
1305                 clock-names = "dmc_clk";
1306                 ddr_timing = <&ddr_timing>;
1307                 operating-points-v2 = <&dmc_opp_table>;
1308                 status = "disabled";
1309         };
1310
1311         dmc_opp_table: dmc_opp_table {
1312                 compatible = "operating-points-v2";
1313
1314                 opp00 {
1315                         opp-hz = /bits/ 64 <666000000>;
1316                         opp-microvolt = <900000>;
1317                 };
1318         };
1319
1320         rga: rga@ff680000 {
1321                 compatible = "rockchip,rk3399-rga";
1322                 reg = <0x0 0xff680000 0x0 0x10000>;
1323                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1324                 interrupt-names = "rga";
1325                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1326                 clock-names = "aclk", "hclk", "sclk";
1327                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1328                 reset-names = "core", "axi", "ahb";
1329                 power-domains = <&power RK3399_PD_RGA>;
1330                 status = "disabled";
1331         };
1332
1333         efuse0: efuse@ff690000 {
1334                 compatible = "rockchip,rk3399-efuse";
1335                 reg = <0x0 0xff690000 0x0 0x80>;
1336                 #address-cells = <1>;
1337                 #size-cells = <1>;
1338                 clocks = <&cru PCLK_EFUSE1024NS>;
1339                 clock-names = "pclk_efuse";
1340
1341                 /* Data cells */
1342                 cpul_leakage: cpul-leakage {
1343                         reg = <0x1a 0x1>;
1344                 };
1345                 cpub_leakage: cpub-leakage {
1346                         reg = <0x17 0x1>;
1347                 };
1348                 gpu_leakage: gpu-leakage {
1349                         reg = <0x18 0x1>;
1350                 };
1351                 center_leakage: center-leakage {
1352                         reg = <0x19 0x1>;
1353                 };
1354                 logic_leakage: logic-leakage {
1355                         reg = <0x1b 0x1>;
1356                 };
1357                 wafer_info: wafer-info {
1358                         reg = <0x1c 0x1>;
1359                 };
1360         };
1361
1362         pmucru: pmu-clock-controller@ff750000 {
1363                 compatible = "rockchip,rk3399-pmucru";
1364                 reg = <0x0 0xff750000 0x0 0x1000>;
1365                 #clock-cells = <1>;
1366                 #reset-cells = <1>;
1367                 assigned-clocks = <&pmucru PLL_PPLL>;
1368                 assigned-clock-rates = <676000000>;
1369         };
1370
1371         cru: clock-controller@ff760000 {
1372                 compatible = "rockchip,rk3399-cru";
1373                 reg = <0x0 0xff760000 0x0 0x1000>;
1374                 #clock-cells = <1>;
1375                 #reset-cells = <1>;
1376                 assigned-clocks =
1377                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1378                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1379                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1380                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1381                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1382                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1383                         <&cru PCLK_PERIHP>,
1384                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1385                         <&cru PCLK_PERILP0>,
1386                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1387                 assigned-clock-rates =
1388                          <400000000>,  <200000000>,
1389                          <400000000>,  <200000000>,
1390                          <816000000>, <816000000>,
1391                          <594000000>,  <800000000>,
1392                          <200000000>, <1000000000>,
1393                          <150000000>,   <75000000>,
1394                           <37500000>,
1395                          <100000000>,  <100000000>,
1396                           <50000000>,
1397                          <100000000>,   <50000000>;
1398         };
1399
1400         grf: syscon@ff770000 {
1401                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1402                 reg = <0x0 0xff770000 0x0 0x10000>;
1403                 #address-cells = <1>;
1404                 #size-cells = <1>;
1405
1406                 emmc_phy: phy@f780 {
1407                         compatible = "rockchip,rk3399-emmc-phy";
1408                         reg = <0xf780 0x24>;
1409                         clocks = <&sdhci>;
1410                         clock-names = "emmcclk";
1411                         #phy-cells = <0>;
1412                         status = "disabled";
1413                 };
1414
1415                 u2phy0: usb2-phy@e450 {
1416                         compatible = "rockchip,rk3399-usb2phy";
1417                         reg = <0xe450 0x10>;
1418                         clocks = <&cru SCLK_USB2PHY0_REF>;
1419                         clock-names = "phyclk";
1420                         #clock-cells = <0>;
1421                         clock-output-names = "clk_usbphy0_480m";
1422                         status = "disabled";
1423
1424                         u2phy0_otg: otg-port {
1425                                 #phy-cells = <0>;
1426                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1427                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1428                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1429                                 interrupt-names = "otg-bvalid", "otg-id",
1430                                                   "linestate";
1431                                 status = "disabled";
1432                         };
1433
1434                         u2phy0_host: host-port {
1435                                 #phy-cells = <0>;
1436                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1437                                 interrupt-names = "linestate";
1438                                 status = "disabled";
1439                         };
1440                 };
1441
1442                 u2phy1: usb2-phy@e460 {
1443                         compatible = "rockchip,rk3399-usb2phy";
1444                         reg = <0xe460 0x10>;
1445                         clocks = <&cru SCLK_USB2PHY1_REF>;
1446                         clock-names = "phyclk";
1447                         #clock-cells = <0>;
1448                         clock-output-names = "clk_usbphy1_480m";
1449                         status = "disabled";
1450
1451                         u2phy1_otg: otg-port {
1452                                 #phy-cells = <0>;
1453                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1454                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1455                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1456                                 interrupt-names = "otg-bvalid", "otg-id",
1457                                                   "linestate";
1458                                 status = "disabled";
1459                         };
1460
1461                         u2phy1_host: host-port {
1462                                 #phy-cells = <0>;
1463                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1464                                 interrupt-names = "linestate";
1465                                 status = "disabled";
1466                         };
1467                 };
1468         };
1469
1470         tcphy0: phy@ff7c0000 {
1471                 compatible = "rockchip,rk3399-typec-phy";
1472                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1473                 rockchip,grf = <&grf>;
1474                 #phy-cells = <1>;
1475                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1476                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1477                 clock-names = "tcpdcore", "tcpdphy-ref";
1478                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1479                 assigned-clock-rates = <50000000>;
1480                 power-domains = <&power RK3399_PD_TCPD0>;
1481                 resets = <&cru SRST_UPHY0>,
1482                          <&cru SRST_UPHY0_PIPE_L00>,
1483                          <&cru SRST_P_UPHY0_TCPHY>;
1484                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1485                 rockchip,typec-conn-dir = <0xe580 0 16>;
1486                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1487                 rockchip,usb3-host-disable = <0x2434 0 16>;
1488                 rockchip,usb3-host-port = <0x2434 12 28>;
1489                 rockchip,external-psm = <0xe588 14 30>;
1490                 rockchip,pipe-status = <0xe5c0 0 0>;
1491                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1492                 status = "disabled";
1493
1494                 tcphy0_dp: dp-port {
1495                         #phy-cells = <0>;
1496                 };
1497
1498                 tcphy0_usb3: usb3-port {
1499                         #phy-cells = <0>;
1500                 };
1501         };
1502
1503         tcphy1: phy@ff800000 {
1504                 compatible = "rockchip,rk3399-typec-phy";
1505                 reg = <0x0 0xff800000 0x0 0x40000>;
1506                 rockchip,grf = <&grf>;
1507                 #phy-cells = <1>;
1508                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1509                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1510                 clock-names = "tcpdcore", "tcpdphy-ref";
1511                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1512                 assigned-clock-rates = <50000000>;
1513                 power-domains = <&power RK3399_PD_TCPD1>;
1514                 resets = <&cru SRST_UPHY1>,
1515                          <&cru SRST_UPHY1_PIPE_L00>,
1516                          <&cru SRST_P_UPHY1_TCPHY>;
1517                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1518                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1519                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1520                 rockchip,usb3-host-disable = <0x2444 0 16>;
1521                 rockchip,usb3-host-port = <0x2444 12 28>;
1522                 rockchip,external-psm = <0xe594 14 30>;
1523                 rockchip,pipe-status = <0xe5c0 16 16>;
1524                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1525                 status = "disabled";
1526
1527                 tcphy1_dp: dp-port {
1528                         #phy-cells = <0>;
1529                 };
1530
1531                 tcphy1_usb3: usb3-port {
1532                         #phy-cells = <0>;
1533                 };
1534         };
1535
1536         watchdog@ff848000 {
1537                 compatible = "snps,dw-wdt";
1538                 reg = <0x0 0xff848000 0x0 0x100>;
1539                 clocks = <&cru PCLK_WDT>;
1540                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1541         };
1542
1543         rktimer: rktimer@ff850000 {
1544                 compatible = "rockchip,rk3399-timer";
1545                 reg = <0x0 0xff850000 0x0 0x1000>;
1546                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1547                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1548                 clock-names = "pclk", "timer";
1549         };
1550
1551         spdif: spdif@ff870000 {
1552                 compatible = "rockchip,rk3399-spdif";
1553                 reg = <0x0 0xff870000 0x0 0x1000>;
1554                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1555                 dmas = <&dmac_bus 7>;
1556                 dma-names = "tx";
1557                 clock-names = "mclk", "hclk";
1558                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1559                 pinctrl-names = "default";
1560                 pinctrl-0 = <&spdif_bus>;
1561                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1562                 status = "disabled";
1563         };
1564
1565         i2s0: i2s@ff880000 {
1566                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1567                 reg = <0x0 0xff880000 0x0 0x1000>;
1568                 rockchip,grf = <&grf>;
1569                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1570                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1571                 dma-names = "tx", "rx";
1572                 clock-names = "i2s_clk", "i2s_hclk";
1573                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1574                 pinctrl-names = "default";
1575                 pinctrl-0 = <&i2s0_8ch_bus>;
1576                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1577                 status = "disabled";
1578         };
1579
1580         i2s1: i2s@ff890000 {
1581                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1582                 reg = <0x0 0xff890000 0x0 0x1000>;
1583                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1584                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1585                 dma-names = "tx", "rx";
1586                 clock-names = "i2s_clk", "i2s_hclk";
1587                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1588                 pinctrl-names = "default";
1589                 pinctrl-0 = <&i2s1_2ch_bus>;
1590                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1591                 status = "disabled";
1592         };
1593
1594         i2s2: i2s@ff8a0000 {
1595                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1596                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1597                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1598                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1599                 dma-names = "tx", "rx";
1600                 clock-names = "i2s_clk", "i2s_hclk";
1601                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1602                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1603                 status = "disabled";
1604         };
1605
1606         gpu: gpu@ff9a0000 {
1607                 compatible = "arm,malit860",
1608                              "arm,malit86x",
1609                              "arm,malit8xx",
1610                              "arm,mali-midgard";
1611
1612                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1613
1614                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1615                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1616                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1617                 interrupt-names = "GPU", "JOB", "MMU";
1618
1619                 clocks = <&cru ACLK_GPU>;
1620                 clock-names = "clk_mali";
1621                 #cooling-cells = <2>; /* min followed by max */
1622                 operating-points-v2 = <&gpu_opp_table>;
1623                 power-domains = <&power RK3399_PD_GPU>;
1624                 power-off-delay-ms = <200>;
1625                 status = "disabled";
1626
1627                 gpu_power_model: power_model {
1628                         compatible = "arm,mali-simple-power-model";
1629                         voltage = <900>;
1630                         frequency = <500>;
1631                         static-power = <300>;
1632                         dynamic-power = <396>;
1633                         ts = <32000 4700 (-80) 2>;
1634                         thermal-zone = "gpu-thermal";
1635                 };
1636         };
1637
1638         gpu_opp_table: gpu_opp_table {
1639                 compatible = "operating-points-v2";
1640                 opp-shared;
1641
1642                 opp@200000000 {
1643                         opp-hz = /bits/ 64 <200000000>;
1644                         opp-microvolt = <900000>;
1645                 };
1646                 opp@300000000 {
1647                         opp-hz = /bits/ 64 <300000000>;
1648                         opp-microvolt = <900000>;
1649                 };
1650                 opp@400000000 {
1651                         opp-hz = /bits/ 64 <400000000>;
1652                         opp-microvolt = <900000>;
1653                 };
1654
1655         };
1656
1657         vopl: vop@ff8f0000 {
1658                 compatible = "rockchip,rk3399-vop-lit";
1659                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1660                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1661                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1662                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1663                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1664                 reset-names = "axi", "ahb", "dclk";
1665                 power-domains = <&power RK3399_PD_VOPL>;
1666                 iommus = <&vopl_mmu>;
1667                 status = "disabled";
1668
1669                 vopl_out: port {
1670                         #address-cells = <1>;
1671                         #size-cells = <0>;
1672
1673                         vopl_out_mipi: endpoint@0 {
1674                                 reg = <0>;
1675                                 remote-endpoint = <&mipi_in_vopl>;
1676                         };
1677
1678                         vopl_out_edp: endpoint@1 {
1679                                 reg = <1>;
1680                                 remote-endpoint = <&edp_in_vopl>;
1681                         };
1682
1683                         vopl_out_hdmi: endpoint@2 {
1684                                 reg = <2>;
1685                                 remote-endpoint = <&hdmi_in_vopl>;
1686                         };
1687                 };
1688         };
1689
1690         vop1_pwm: voppwm@ff8f01a0 {
1691                 compatible = "rockchip,vop-pwm";
1692                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1693                 #pwm-cells = <3>;
1694                 pinctrl-names = "default";
1695                 pinctrl-0 = <&vop1_pwm_pin>;
1696                 clocks = <&cru SCLK_VOP1_PWM>;
1697                 clock-names = "pwm";
1698                 status = "disabled";
1699         };
1700
1701         vopl_mmu: iommu@ff8f3f00 {
1702                 compatible = "rockchip,iommu";
1703                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1704                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1705                 interrupt-names = "vopl_mmu";
1706                 #iommu-cells = <0>;
1707                 status = "disabled";
1708         };
1709
1710         vopb: vop@ff900000 {
1711                 compatible = "rockchip,rk3399-vop-big";
1712                 reg = <0x0 0xff900000 0x0 0x3efc>;
1713                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1714                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1715                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1716                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1717                 reset-names = "axi", "ahb", "dclk";
1718                 power-domains = <&power RK3399_PD_VOPB>;
1719                 iommus = <&vopb_mmu>;
1720                 status = "disabled";
1721
1722                 vopb_out: port {
1723                         #address-cells = <1>;
1724                         #size-cells = <0>;
1725
1726                         vopb_out_edp: endpoint@0 {
1727                                 reg = <0>;
1728                                 remote-endpoint = <&edp_in_vopb>;
1729                         };
1730
1731                         vopb_out_mipi: endpoint@1 {
1732                                 reg = <1>;
1733                                 remote-endpoint = <&mipi_in_vopb>;
1734                         };
1735
1736                         vopb_out_hdmi: endpoint@2 {
1737                                 reg = <2>;
1738                                 remote-endpoint = <&hdmi_in_vopb>;
1739                         };
1740                 };
1741         };
1742
1743         vop0_pwm: voppwm@ff9001a0 {
1744                 compatible = "rockchip,vop-pwm";
1745                 reg = <0x0 0xff9001a0 0x0 0x10>;
1746                 #pwm-cells = <3>;
1747                 pinctrl-names = "default";
1748                 pinctrl-0 = <&vop0_pwm_pin>;
1749                 clocks = <&cru SCLK_VOP0_PWM>;
1750                 clock-names = "pwm";
1751                 status = "disabled";
1752         };
1753
1754         vopb_mmu: iommu@ff903f00 {
1755                 compatible = "rockchip,iommu";
1756                 reg = <0x0 0xff903f00 0x0 0x100>;
1757                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1758                 interrupt-names = "vopb_mmu";
1759                 #iommu-cells = <0>;
1760                 status = "disabled";
1761         };
1762
1763         hdmi: hdmi@ff940000 {
1764                 compatible = "rockchip,rk3399-dw-hdmi";
1765                 reg = <0x0 0xff940000 0x0 0x20000>;
1766                 reg-io-width = <4>;
1767                 rockchip,grf = <&grf>;
1768                 power-domains = <&power RK3399_PD_HDCP>;
1769                 pinctrl-names = "default";
1770                 pinctrl-0 = <&hdmi_i2c_xfer>;
1771                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1772                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1773                 clock-names = "iahb", "isfr", "vpll", "grf";
1774                 status = "disabled";
1775
1776                 ports {
1777                         hdmi_in: port {
1778                                 #address-cells = <1>;
1779                                 #size-cells = <0>;
1780                                 hdmi_in_vopb: endpoint@0 {
1781                                         reg = <0>;
1782                                         remote-endpoint = <&vopb_out_hdmi>;
1783                                 };
1784                                 hdmi_in_vopl: endpoint@1 {
1785                                         reg = <1>;
1786                                         remote-endpoint = <&vopl_out_hdmi>;
1787                                 };
1788                         };
1789                 };
1790         };
1791
1792         mipi_dsi: mipi@ff960000 {
1793                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1794                 reg = <0x0 0xff960000 0x0 0x8000>;
1795                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1796                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1797                          <&cru SCLK_DPHY_TX0_CFG>;
1798                 clock-names = "ref", "pclk", "phy_cfg";
1799                 power-domains = <&power RK3399_PD_VIO>;
1800                 rockchip,grf = <&grf>;
1801                 #address-cells = <1>;
1802                 #size-cells = <0>;
1803                 status = "disabled";
1804
1805                 ports {
1806                         #address-cells = <1>;
1807                         #size-cells = <0>;
1808                         reg = <1>;
1809
1810                         mipi_in: port {
1811                                 #address-cells = <1>;
1812                                 #size-cells = <0>;
1813
1814                                 mipi_in_vopb: endpoint@0 {
1815                                         reg = <0>;
1816                                         remote-endpoint = <&vopb_out_mipi>;
1817                                 };
1818                                 mipi_in_vopl: endpoint@1 {
1819                                         reg = <1>;
1820                                         remote-endpoint = <&vopl_out_mipi>;
1821                                 };
1822                         };
1823                 };
1824         };
1825
1826         edp: edp@ff970000 {
1827                 compatible = "rockchip,rk3399-edp";
1828                 reg = <0x0 0xff970000 0x0 0x8000>;
1829                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1830                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1831                 clock-names = "dp", "pclk";
1832                 power-domains = <&power RK3399_PD_EDP>;
1833                 resets = <&cru SRST_P_EDP_CTRL>;
1834                 reset-names = "dp";
1835                 rockchip,grf = <&grf>;
1836                 status = "disabled";
1837                 pinctrl-names = "default";
1838                 pinctrl-0 = <&edp_hpd>;
1839
1840                 ports {
1841                         #address-cells = <1>;
1842                         #size-cells = <0>;
1843
1844                         edp_in: port@0 {
1845                                 reg = <0>;
1846                                 #address-cells = <1>;
1847                                 #size-cells = <0>;
1848
1849                                 edp_in_vopb: endpoint@0 {
1850                                         reg = <0>;
1851                                         remote-endpoint = <&vopb_out_edp>;
1852                                 };
1853
1854                                 edp_in_vopl: endpoint@1 {
1855                                         reg = <1>;
1856                                         remote-endpoint = <&vopl_out_edp>;
1857                                 };
1858                         };
1859                 };
1860         };
1861
1862         display_subsystem: display-subsystem {
1863                 compatible = "rockchip,display-subsystem";
1864                 ports = <&vopl_out>, <&vopb_out>;
1865                 status = "disabled";
1866         };
1867
1868         pinctrl: pinctrl {
1869                 compatible = "rockchip,rk3399-pinctrl";
1870                 rockchip,grf = <&grf>;
1871                 rockchip,pmu = <&pmugrf>;
1872                 #address-cells = <0x2>;
1873                 #size-cells = <0x2>;
1874                 ranges;
1875
1876                 gpio0: gpio0@ff720000 {
1877                         compatible = "rockchip,gpio-bank";
1878                         reg = <0x0 0xff720000 0x0 0x100>;
1879                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1880                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1881
1882                         gpio-controller;
1883                         #gpio-cells = <0x2>;
1884
1885                         interrupt-controller;
1886                         #interrupt-cells = <0x2>;
1887                 };
1888
1889                 gpio1: gpio1@ff730000 {
1890                         compatible = "rockchip,gpio-bank";
1891                         reg = <0x0 0xff730000 0x0 0x100>;
1892                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1893                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1894
1895                         gpio-controller;
1896                         #gpio-cells = <0x2>;
1897
1898                         interrupt-controller;
1899                         #interrupt-cells = <0x2>;
1900                 };
1901
1902                 gpio2: gpio2@ff780000 {
1903                         compatible = "rockchip,gpio-bank";
1904                         reg = <0x0 0xff780000 0x0 0x100>;
1905                         clocks = <&cru PCLK_GPIO2>;
1906                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1907
1908                         gpio-controller;
1909                         #gpio-cells = <0x2>;
1910
1911                         interrupt-controller;
1912                         #interrupt-cells = <0x2>;
1913                 };
1914
1915                 gpio3: gpio3@ff788000 {
1916                         compatible = "rockchip,gpio-bank";
1917                         reg = <0x0 0xff788000 0x0 0x100>;
1918                         clocks = <&cru PCLK_GPIO3>;
1919                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1920
1921                         gpio-controller;
1922                         #gpio-cells = <0x2>;
1923
1924                         interrupt-controller;
1925                         #interrupt-cells = <0x2>;
1926                 };
1927
1928                 gpio4: gpio4@ff790000 {
1929                         compatible = "rockchip,gpio-bank";
1930                         reg = <0x0 0xff790000 0x0 0x100>;
1931                         clocks = <&cru PCLK_GPIO4>;
1932                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1933
1934                         gpio-controller;
1935                         #gpio-cells = <0x2>;
1936
1937                         interrupt-controller;
1938                         #interrupt-cells = <0x2>;
1939                 };
1940
1941                 pcfg_pull_up: pcfg-pull-up {
1942                         bias-pull-up;
1943                 };
1944
1945                 pcfg_pull_down: pcfg-pull-down {
1946                         bias-pull-down;
1947                 };
1948
1949                 pcfg_pull_none: pcfg-pull-none {
1950                         bias-disable;
1951                 };
1952
1953                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1954                         bias-pull-up;
1955                         drive-strength = <20>;
1956                 };
1957
1958                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1959                         bias-disable;
1960                         drive-strength = <20>;
1961                 };
1962
1963                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1964                         bias-disable;
1965                         drive-strength = <18>;
1966                 };
1967
1968                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1969                         bias-disable;
1970                         drive-strength = <12>;
1971                 };
1972
1973                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1974                         bias-pull-up;
1975                         drive-strength = <8>;
1976                 };
1977
1978                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1979                         bias-pull-down;
1980                         drive-strength = <4>;
1981                 };
1982
1983                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1984                         bias-pull-up;
1985                         drive-strength = <2>;
1986                 };
1987
1988                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1989                         bias-pull-down;
1990                         drive-strength = <12>;
1991                 };
1992
1993                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1994                         bias-disable;
1995                         drive-strength = <13>;
1996                 };
1997
1998                 pcfg_output_high: pcfg-output-high {
1999                         output-high;
2000                 };
2001
2002                 pcfg_output_low: pcfg-output-low {
2003                         output-low;
2004                 };
2005
2006                 pcfg_input: pcfg-input {
2007                         input-enable;
2008                 };
2009
2010                 emmc {
2011                         emmc_pwr: emmc-pwr {
2012                                 rockchip,pins =
2013                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2014                         };
2015                 };
2016
2017                 gmac {
2018                         rgmii_pins: rgmii-pins {
2019                                 rockchip,pins =
2020                                         /* mac_txclk */
2021                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2022                                         /* mac_rxclk */
2023                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2024                                         /* mac_mdio */
2025                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2026                                         /* mac_txen */
2027                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2028                                         /* mac_clk */
2029                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2030                                         /* mac_rxdv */
2031                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2032                                         /* mac_mdc */
2033                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2034                                         /* mac_rxd1 */
2035                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2036                                         /* mac_rxd0 */
2037                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2038                                         /* mac_txd1 */
2039                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2040                                         /* mac_txd0 */
2041                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2042                                         /* mac_rxd3 */
2043                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2044                                         /* mac_rxd2 */
2045                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2046                                         /* mac_txd3 */
2047                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2048                                         /* mac_txd2 */
2049                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2050                         };
2051
2052                         rmii_pins: rmii-pins {
2053                                 rockchip,pins =
2054                                         /* mac_mdio */
2055                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2056                                         /* mac_txen */
2057                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2058                                         /* mac_clk */
2059                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2060                                         /* mac_rxer */
2061                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2062                                         /* mac_rxdv */
2063                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2064                                         /* mac_mdc */
2065                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2066                                         /* mac_rxd1 */
2067                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2068                                         /* mac_rxd0 */
2069                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2070                                         /* mac_txd1 */
2071                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2072                                         /* mac_txd0 */
2073                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2074                         };
2075                 };
2076
2077                 i2c0 {
2078                         i2c0_xfer: i2c0-xfer {
2079                                 rockchip,pins =
2080                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2081                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2082                         };
2083                 };
2084
2085                 i2c1 {
2086                         i2c1_xfer: i2c1-xfer {
2087                                 rockchip,pins =
2088                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2089                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2090                         };
2091                 };
2092
2093                 i2c2 {
2094                         i2c2_xfer: i2c2-xfer {
2095                                 rockchip,pins =
2096                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2097                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2098                         };
2099                 };
2100
2101                 i2c3 {
2102                         i2c3_xfer: i2c3-xfer {
2103                                 rockchip,pins =
2104                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2105                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2106                         };
2107
2108                         i2c3_gpio: i2c3_gpio {
2109                                 rockchip,pins =
2110                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2111                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2112                         };
2113
2114                 };
2115
2116                 i2c4 {
2117                         i2c4_xfer: i2c4-xfer {
2118                                 rockchip,pins =
2119                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2120                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2121                         };
2122                 };
2123
2124                 i2c5 {
2125                         i2c5_xfer: i2c5-xfer {
2126                                 rockchip,pins =
2127                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2128                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2129                         };
2130                 };
2131
2132                 i2c6 {
2133                         i2c6_xfer: i2c6-xfer {
2134                                 rockchip,pins =
2135                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2136                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2137                         };
2138                 };
2139
2140                 i2c7 {
2141                         i2c7_xfer: i2c7-xfer {
2142                                 rockchip,pins =
2143                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2144                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2145                         };
2146                 };
2147
2148                 i2c8 {
2149                         i2c8_xfer: i2c8-xfer {
2150                                 rockchip,pins =
2151                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2152                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2153                         };
2154                 };
2155
2156                 i2s0 {
2157                         i2s0_8ch_bus: i2s0-8ch-bus {
2158                                 rockchip,pins =
2159                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2160                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2161                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2162                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2163                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2164                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2165                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2166                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2167                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2168                         };
2169                 };
2170
2171                 i2s1 {
2172                         i2s1_2ch_bus: i2s1-2ch-bus {
2173                                 rockchip,pins =
2174                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2175                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2176                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2177                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2178                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2179                         };
2180                 };
2181
2182                 sdio0 {
2183                         sdio0_bus1: sdio0-bus1 {
2184                                 rockchip,pins =
2185                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2186                         };
2187
2188                         sdio0_bus4: sdio0-bus4 {
2189                                 rockchip,pins =
2190                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2191                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2192                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2193                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2194                         };
2195
2196                         sdio0_cmd: sdio0-cmd {
2197                                 rockchip,pins =
2198                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2199                         };
2200
2201                         sdio0_clk: sdio0-clk {
2202                                 rockchip,pins =
2203                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2204                         };
2205
2206                         sdio0_cd: sdio0-cd {
2207                                 rockchip,pins =
2208                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2209                         };
2210
2211                         sdio0_pwr: sdio0-pwr {
2212                                 rockchip,pins =
2213                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2214                         };
2215
2216                         sdio0_bkpwr: sdio0-bkpwr {
2217                                 rockchip,pins =
2218                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2219                         };
2220
2221                         sdio0_wp: sdio0-wp {
2222                                 rockchip,pins =
2223                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2224                         };
2225
2226                         sdio0_int: sdio0-int {
2227                                 rockchip,pins =
2228                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2229                         };
2230                 };
2231
2232                 sdmmc {
2233                         sdmmc_bus1: sdmmc-bus1 {
2234                                 rockchip,pins =
2235                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2236                         };
2237
2238                         sdmmc_bus4: sdmmc-bus4 {
2239                                 rockchip,pins =
2240                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2241                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2242                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2243                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2244                         };
2245
2246                         sdmmc_clk: sdmmc-clk {
2247                                 rockchip,pins =
2248                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2249                         };
2250
2251                         sdmmc_cmd: sdmmc-cmd {
2252                                 rockchip,pins =
2253                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2254                         };
2255
2256                         sdmmc_cd: sdmcc-cd {
2257                                 rockchip,pins =
2258                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2259                         };
2260
2261                         sdmmc_wp: sdmmc-wp {
2262                                 rockchip,pins =
2263                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2264                         };
2265                 };
2266
2267                 spdif {
2268                         spdif_bus: spdif-bus {
2269                                 rockchip,pins =
2270                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2271                         };
2272
2273                         spdif_bus_1: spdif-bus-1 {
2274                                 rockchip,pins =
2275                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2276                         };
2277                 };
2278
2279                 spi0 {
2280                         spi0_clk: spi0-clk {
2281                                 rockchip,pins =
2282                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2283                         };
2284                         spi0_cs0: spi0-cs0 {
2285                                 rockchip,pins =
2286                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2287                         };
2288                         spi0_cs1: spi0-cs1 {
2289                                 rockchip,pins =
2290                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2291                         };
2292                         spi0_tx: spi0-tx {
2293                                 rockchip,pins =
2294                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2295                         };
2296                         spi0_rx: spi0-rx {
2297                                 rockchip,pins =
2298                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2299                         };
2300                 };
2301
2302                 spi1 {
2303                         spi1_clk: spi1-clk {
2304                                 rockchip,pins =
2305                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2306                         };
2307                         spi1_cs0: spi1-cs0 {
2308                                 rockchip,pins =
2309                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2310                         };
2311                         spi1_rx: spi1-rx {
2312                                 rockchip,pins =
2313                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2314                         };
2315                         spi1_tx: spi1-tx {
2316                                 rockchip,pins =
2317                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2318                         };
2319                 };
2320
2321                 spi2 {
2322                         spi2_clk: spi2-clk {
2323                                 rockchip,pins =
2324                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2325                         };
2326                         spi2_cs0: spi2-cs0 {
2327                                 rockchip,pins =
2328                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2329                         };
2330                         spi2_rx: spi2-rx {
2331                                 rockchip,pins =
2332                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2333                         };
2334                         spi2_tx: spi2-tx {
2335                                 rockchip,pins =
2336                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2337                         };
2338                 };
2339
2340                 spi3 {
2341                         spi3_clk: spi3-clk {
2342                                 rockchip,pins =
2343                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2344                         };
2345                         spi3_cs0: spi3-cs0 {
2346                                 rockchip,pins =
2347                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2348                         };
2349                         spi3_rx: spi3-rx {
2350                                 rockchip,pins =
2351                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2352                         };
2353                         spi3_tx: spi3-tx {
2354                                 rockchip,pins =
2355                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2356                         };
2357                 };
2358
2359                 spi4 {
2360                         spi4_clk: spi4-clk {
2361                                 rockchip,pins =
2362                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2363                         };
2364                         spi4_cs0: spi4-cs0 {
2365                                 rockchip,pins =
2366                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2367                         };
2368                         spi4_rx: spi4-rx {
2369                                 rockchip,pins =
2370                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2371                         };
2372                         spi4_tx: spi4-tx {
2373                                 rockchip,pins =
2374                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2375                         };
2376                 };
2377
2378                 spi5 {
2379                         spi5_clk: spi5-clk {
2380                                 rockchip,pins =
2381                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2382                         };
2383                         spi5_cs0: spi5-cs0 {
2384                                 rockchip,pins =
2385                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2386                         };
2387                         spi5_rx: spi5-rx {
2388                                 rockchip,pins =
2389                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2390                         };
2391                         spi5_tx: spi5-tx {
2392                                 rockchip,pins =
2393                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2394                         };
2395                 };
2396
2397                 tsadc {
2398                         otp_gpio: otp-gpio {
2399                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2400                         };
2401
2402                         otp_out: otp-out {
2403                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2404                         };
2405                 };
2406
2407                 uart0 {
2408                         uart0_xfer: uart0-xfer {
2409                                 rockchip,pins =
2410                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2411                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2412                         };
2413
2414                         uart0_cts: uart0-cts {
2415                                 rockchip,pins =
2416                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2417                         };
2418
2419                         uart0_rts: uart0-rts {
2420                                 rockchip,pins =
2421                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2422                         };
2423                 };
2424
2425                 uart1 {
2426                         uart1_xfer: uart1-xfer {
2427                                 rockchip,pins =
2428                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2429                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2430                         };
2431                 };
2432
2433                 uart2a {
2434                         uart2a_xfer: uart2a-xfer {
2435                                 rockchip,pins =
2436                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2437                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2438                         };
2439                 };
2440
2441                 uart2b {
2442                         uart2b_xfer: uart2b-xfer {
2443                                 rockchip,pins =
2444                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2445                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2446                         };
2447                 };
2448
2449                 uart2c {
2450                         uart2c_xfer: uart2c-xfer {
2451                                 rockchip,pins =
2452                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2453                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2454                         };
2455                 };
2456
2457                 uart3 {
2458                         uart3_xfer: uart3-xfer {
2459                                 rockchip,pins =
2460                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2461                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2462                         };
2463
2464                         uart3_cts: uart3-cts {
2465                                 rockchip,pins =
2466                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2467                         };
2468
2469                         uart3_rts: uart3-rts {
2470                                 rockchip,pins =
2471                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2472                         };
2473                 };
2474
2475                 uart4 {
2476                         uart4_xfer: uart4-xfer {
2477                                 rockchip,pins =
2478                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2479                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2480                         };
2481                 };
2482
2483                 uarthdcp {
2484                         uarthdcp_xfer: uarthdcp-xfer {
2485                                 rockchip,pins =
2486                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2487                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2488                         };
2489                 };
2490
2491                 pwm0 {
2492                         pwm0_pin: pwm0-pin {
2493                                 rockchip,pins =
2494                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2495                         };
2496
2497                         vop0_pwm_pin: vop0-pwm-pin {
2498                                 rockchip,pins =
2499                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2500                         };
2501                 };
2502
2503                 pwm1 {
2504                         pwm1_pin: pwm1-pin {
2505                                 rockchip,pins =
2506                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2507                         };
2508
2509                         vop1_pwm_pin: vop1-pwm-pin {
2510                                 rockchip,pins =
2511                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2512                         };
2513                 };
2514
2515                 pwm2 {
2516                         pwm2_pin: pwm2-pin {
2517                                 rockchip,pins =
2518                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2519                         };
2520                 };
2521
2522                 pwm3a {
2523                         pwm3a_pin: pwm3a-pin {
2524                                 rockchip,pins =
2525                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2526                         };
2527                 };
2528
2529                 pwm3b {
2530                         pwm3b_pin: pwm3b-pin {
2531                                 rockchip,pins =
2532                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2533                         };
2534                 };
2535
2536                 edp {
2537                         edp_hpd: edp-hpd {
2538                                 rockchip,pins =
2539                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2540                         };
2541                 };
2542
2543                 hdmi {
2544                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2545                                 rockchip,pins =
2546                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2547                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2548                         };
2549
2550                         hdmi_cec: hdmi-cec {
2551                                 rockchip,pins =
2552                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2553                         };
2554                 };
2555
2556                 pcie {
2557                         pcie_clkreqn: pci-clkreqn {
2558                                 rockchip,pins =
2559                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2560                         };
2561
2562                         pcie_clkreqnb: pci-clkreqnb {
2563                                 rockchip,pins =
2564                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2565                         };
2566                 };
2567         };
2568 };