arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 124                 };
 125
 126                 cpu_l1: cpu@1 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x1>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 135                 };
 136
 137                 cpu_l2: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 144                         operating-points-v2 = <&cluster0_opp>;
 145                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 146                 };
 147
 148                 cpu_l3: cpu@3 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a53", "arm,armv8";
 151                         reg = <0x0 0x3>;
 152                         enable-method = "psci";
 153                         clocks = <&cru ARMCLKL>;
 154                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 157                 };
 158
 159                 cpu_b0: cpu@100 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a72", "arm,armv8";
 162                         reg = <0x0 0x100>;
 163                         enable-method = "psci";
 164                         #cooling-cells = <2>; /* min followed by max */
 165                         dynamic-power-coefficient = <436>;
 166                         clocks = <&cru ARMCLKB>;
 167                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 170                 };
 171
 172                 cpu_b1: cpu@101 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a72", "arm,armv8";
 175                         reg = <0x0 0x101>;
 176                         enable-method = "psci";
 177                         clocks = <&cru ARMCLKB>;
 178                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 179                         operating-points-v2 = <&cluster1_opp>;
 180                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 181                 };
 182
 183                 idle-states {
 184                         entry-method = "psci";
 185
 186                         CPU_SLEEP: cpu-sleep {
 187                                 compatible = "arm,idle-state";
 188                                 local-timer-stop;
 189                                 arm,psci-suspend-param = <0x0010000>;
 190                                 entry-latency-us = <120>;
 191                                 exit-latency-us = <250>;
 192                                 min-residency-us = <900>;
 193                         };
 194
 195                         CLUSTER_SLEEP: cluster-sleep {
 196                                 compatible = "arm,idle-state";
 197                                 local-timer-stop;
 198                                 arm,psci-suspend-param = <0x1010000>;
 199                                 entry-latency-us = <400>;
 200                                 exit-latency-us = <500>;
 201                                 min-residency-us = <2000>;
 202                         };
 203                 };
 204
 205                 /include/ "rk3399-sched-energy.dtsi"
 206
 207         };
 208
 209         cluster0_opp: opp_table0 {
 210                 compatible = "operating-points-v2";
 211                 opp-shared;
 212
 213                 opp@408000000 {
 214                         opp-hz = /bits/ 64 <408000000>;
 215                         opp-microvolt = <800000>;
 216                         clock-latency-ns = <40000>;
 217                 };
 218                 opp@600000000 {
 219                         opp-hz = /bits/ 64 <600000000>;
 220                         opp-microvolt = <800000>;
 221                 };
 222                 opp@816000000 {
 223                         opp-hz = /bits/ 64 <816000000>;
 224                         opp-microvolt = <800000>;
 225                 };
 226                 opp@1008000000 {
 227                         opp-hz = /bits/ 64 <1008000000>;
 228                         opp-microvolt = <875000>;
 229                 };
 230                 opp@1200000000 {
 231                         opp-hz = /bits/ 64 <1200000000>;
 232                         opp-microvolt = <925000>;
 233                 };
 234                 opp@1416000000 {
 235                         opp-hz = /bits/ 64 <1416000000>;
 236                         opp-microvolt = <1025000>;
 237                 };
 238         };
 239
 240         cluster1_opp: opp_table1 {
 241                 compatible = "operating-points-v2";
 242                 opp-shared;
 243
 244                 opp@408000000 {
 245                         opp-hz = /bits/ 64 <408000000>;
 246                         opp-microvolt = <800000>;
 247                         clock-latency-ns = <40000>;
 248                 };
 249                 opp@600000000 {
 250                         opp-hz = /bits/ 64 <600000000>;
 251                         opp-microvolt = <800000>;
 252                 };
 253                 opp@816000000 {
 254                         opp-hz = /bits/ 64 <816000000>;
 255                         opp-microvolt = <800000>;
 256                 };
 257                 opp@1008000000 {
 258                         opp-hz = /bits/ 64 <1008000000>;
 259                         opp-microvolt = <850000>;
 260                 };
 261                 opp@1200000000 {
 262                         opp-hz = /bits/ 64 <1200000000>;
 263                         opp-microvolt = <925000>;
 264                 };
 265         };
 266
 267         cpu_avs: cpu-avs {
 268                 cluster0-avs {
 269                         cluster-id = <0>;
 270                         min-volt = <800000>; /* uV */
 271                         min-freq = <408000>; /* KHz */
 272                         leakage-adjust-volt = <
 273                         /*  mA        mA         uV */
 274                             0         254        0
 275                         >;
 276                         nvmem-cells = <&cpul_leakage>;
 277                         nvmem-cell-names = "cpu_leakage";
 278                 };
 279                 cluster1-avs {
 280                         cluster-id = <1>;
 281                         min-volt = <800000>; /* uV */
 282                         min-freq = <408000>; /* KHz */
 283                         leakage-adjust-volt = <
 284                         /*  mA        mA         uV */
 285                             0         254        0
 286                         >;
 287                         nvmem-cells = <&cpub_leakage>;
 288                         nvmem-cell-names = "cpu_leakage";
 289                 };
 290         };
 291
 292         timer {
 293                 compatible = "arm,armv8-timer";
 294                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 295                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 296                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 297                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 298         };
 299
 300         pmu_a53 {
 301                 compatible = "arm,cortex-a53-pmu";
 302                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 303         };
 304
 305         pmu_a72 {
 306                 compatible = "arm,cortex-a72-pmu";
 307                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 308         };
 309
 310         xin24m: xin24m {
 311                 compatible = "fixed-clock";
 312                 #clock-cells = <0>;
 313                 clock-frequency = <24000000>;
 314                 clock-output-names = "xin24m";
 315         };
 316
 317         amba {
 318                 compatible = "arm,amba-bus";
 319                 #address-cells = <2>;
 320                 #size-cells = <2>;
 321                 ranges;
 322
 323                 dmac_bus: dma-controller@ff6d0000 {
 324                         compatible = "arm,pl330", "arm,primecell";
 325                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 326                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 327                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 328                         #dma-cells = <1>;
 329                         clocks = <&cru ACLK_DMAC0_PERILP>;
 330                         clock-names = "apb_pclk";
 331                         peripherals-req-type-burst;
 332                 };
 333
 334                 dmac_peri: dma-controller@ff6e0000 {
 335                         compatible = "arm,pl330", "arm,primecell";
 336                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 337                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 338                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 339                         #dma-cells = <1>;
 340                         clocks = <&cru ACLK_DMAC1_PERILP>;
 341                         clock-names = "apb_pclk";
 342                         peripherals-req-type-burst;
 343                 };
 344         };
 345
 346         gmac: eth@fe300000 {
 347                 compatible = "rockchip,rk3399-gmac";
 348                 reg = <0x0 0xfe300000 0x0 0x10000>;
 349                 rockchip,grf = <&grf>;
 350                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 351                 interrupt-names = "macirq";
 352                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 353                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 354                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 355                          <&cru PCLK_GMAC>;
 356                 clock-names = "stmmaceth", "mac_clk_rx",
 357                               "mac_clk_tx", "clk_mac_ref",
 358                               "clk_mac_refout", "aclk_mac",
 359                               "pclk_mac";
 360                 resets = <&cru SRST_A_GMAC>;
 361                 reset-names = "stmmaceth";
 362                 power-domains = <&power RK3399_PD_GMAC>;
 363                 status = "disabled";
 364         };
 365
 366         sdio0: dwmmc@fe310000 {
 367                 compatible = "rockchip,rk3399-dw-mshc",
 368                              "rockchip,rk3288-dw-mshc";
 369                 reg = <0x0 0xfe310000 0x0 0x4000>;
 370                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 371                 clock-freq-min-max = <400000 150000000>;
 372                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 373                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 374                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 375                 fifo-depth = <0x100>;
 376                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 377                 status = "disabled";
 378         };
 379
 380         sdmmc: dwmmc@fe320000 {
 381                 compatible = "rockchip,rk3399-dw-mshc",
 382                              "rockchip,rk3288-dw-mshc";
 383                 reg = <0x0 0xfe320000 0x0 0x4000>;
 384                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 385                 clock-freq-min-max = <400000 150000000>;
 386                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 387                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 388                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 389                 fifo-depth = <0x100>;
 390                 power-domains = <&power RK3399_PD_SD>;
 391                 status = "disabled";
 392         };
 393
 394         sdhci: sdhci@fe330000 {
 395                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 396                 reg = <0x0 0xfe330000 0x0 0x10000>;
 397                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 398                 arasan,soc-ctl-syscon = <&grf>;
 399                 assigned-clocks = <&cru SCLK_EMMC>;
 400                 assigned-clock-rates = <200000000>;
 401                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 402                 clock-names = "clk_xin", "clk_ahb";
 403                 clock-output-names = "emmc_cardclock";
 404                 #clock-cells = <0>;
 405                 phys = <&emmc_phy>;
 406                 phy-names = "phy_arasan";
 407                 power-domains = <&power RK3399_PD_EMMC>;
 408                 status = "disabled";
 409         };
 410
 411         usb_host0_ehci: usb@fe380000 {
 412                 compatible = "generic-ehci";
 413                 reg = <0x0 0xfe380000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 415                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 416                          <&cru SCLK_USBPHY0_480M_SRC>;
 417                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 418                 phys = <&u2phy0_host>;
 419                 phy-names = "usb";
 420                 power-domains = <&power RK3399_PD_PERIHP>;
 421                 status = "disabled";
 422         };
 423
 424         usb_host0_ohci: usb@fe3a0000 {
 425                 compatible = "generic-ohci";
 426                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 427                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 428                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 429                          <&cru SCLK_USBPHY0_480M_SRC>;
 430                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 431                 phys = <&u2phy0_host>;
 432                 phy-names = "usb";
 433                 power-domains = <&power RK3399_PD_PERIHP>;
 434                 status = "disabled";
 435         };
 436
 437         usb_host1_ehci: usb@fe3c0000 {
 438                 compatible = "generic-ehci";
 439                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 440                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 441                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 442                          <&cru SCLK_USBPHY1_480M_SRC>;
 443                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 444                 phys = <&u2phy1_host>;
 445                 phy-names = "usb";
 446                 power-domains = <&power RK3399_PD_PERIHP>;
 447                 status = "disabled";
 448         };
 449
 450         usb_host1_ohci: usb@fe3e0000 {
 451                 compatible = "generic-ohci";
 452                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 453                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 454                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 455                          <&cru SCLK_USBPHY1_480M_SRC>;
 456                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 457                 phys = <&u2phy1_host>;
 458                 phy-names = "usb";
 459                 power-domains = <&power RK3399_PD_PERIHP>;
 460                 status = "disabled";
 461         };
 462
 463         usbdrd3_0: usb@fe800000 {
 464                 compatible = "rockchip,rk3399-dwc3";
 465                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 466                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 467                 clock-names = "ref_clk", "suspend_clk",
 468                               "bus_clk", "grf_clk";
 469                 power-domains = <&power RK3399_PD_USB3>;
 470                 resets = <&cru SRST_A_USB3_OTG0>;
 471                 reset-names = "usb3-otg";
 472                 #address-cells = <2>;
 473                 #size-cells = <2>;
 474                 ranges;
 475                 status = "disabled";
 476                 usbdrd_dwc3_0: dwc3@fe800000 {
 477                         compatible = "snps,dwc3";
 478                         reg = <0x0 0xfe800000 0x0 0x100000>;
 479                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 480                         dr_mode = "otg";
 481                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 482                         phy-names = "usb2-phy", "usb3-phy";
 483                         phy_type = "utmi_wide";
 484                         snps,dis_enblslpm_quirk;
 485                         snps,dis-u2-freeclk-exists-quirk;
 486                         snps,dis_u2_susphy_quirk;
 487                         snps,dis-del-phy-power-chg-quirk;
 488                         snps,xhci-slow-suspend-quirk;
 489                         status = "disabled";
 490                 };
 491         };
 492
 493         usbdrd3_1: usb@fe900000 {
 494                 compatible = "rockchip,rk3399-dwc3";
 495                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 496                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 497                 clock-names = "ref_clk", "suspend_clk",
 498                               "bus_clk", "grf_clk";
 499                 power-domains = <&power RK3399_PD_USB3>;
 500                 resets = <&cru SRST_A_USB3_OTG1>;
 501                 reset-names = "usb3-otg";
 502                 #address-cells = <2>;
 503                 #size-cells = <2>;
 504                 ranges;
 505                 status = "disabled";
 506                 usbdrd_dwc3_1: dwc3@fe900000 {
 507                         compatible = "snps,dwc3";
 508                         reg = <0x0 0xfe900000 0x0 0x100000>;
 509                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 510                         dr_mode = "host";
 511                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 512                         phy-names = "usb2-phy", "usb3-phy";
 513                         phy_type = "utmi_wide";
 514                         snps,dis_enblslpm_quirk;
 515                         snps,dis-u2-freeclk-exists-quirk;
 516                         snps,dis_u2_susphy_quirk;
 517                         snps,dis-del-phy-power-chg-quirk;
 518                         snps,xhci-slow-suspend-quirk;
 519                         status = "disabled";
 520                 };
 521         };
 522
 523         gic: interrupt-controller@fee00000 {
 524                 compatible = "arm,gic-v3";
 525                 #interrupt-cells = <4>;
 526                 #address-cells = <2>;
 527                 #size-cells = <2>;
 528                 ranges;
 529                 interrupt-controller;
 530
 531                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 532                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 533                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 534                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 535                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 536                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 537                 its: interrupt-controller@fee20000 {
 538                         compatible = "arm,gic-v3-its";
 539                         msi-controller;
 540                         reg = <0x0 0xfee20000 0x0 0x20000>;
 541                 };
 542
 543                 ppi-partitions {
 544                         part0: interrupt-partition-0 {
 545                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 546                         };
 547
 548                         part1: interrupt-partition-1 {
 549                                 affinity = <&cpu_b0 &cpu_b1>;
 550                         };
 551                 };
 552         };
 553
 554         saradc: saradc@ff100000 {
 555                 compatible = "rockchip,rk3399-saradc";
 556                 reg = <0x0 0xff100000 0x0 0x100>;
 557                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 558                 #io-channel-cells = <1>;
 559                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 560                 clock-names = "saradc", "apb_pclk";
 561                 status = "disabled";
 562         };
 563
 564         i2c0: i2c@ff3c0000 {
 565                 compatible = "rockchip,rk3399-i2c";
 566                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 567                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 568                 clock-names = "i2c", "pclk";
 569                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&i2c0_xfer>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 status = "disabled";
 575         };
 576
 577         i2c1: i2c@ff110000 {
 578                 compatible = "rockchip,rk3399-i2c";
 579                 reg = <0x0 0xff110000 0x0 0x1000>;
 580                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 581                 clock-names = "i2c", "pclk";
 582                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&i2c1_xfer>;
 585                 #address-cells = <1>;
 586                 #size-cells = <0>;
 587                 status = "disabled";
 588         };
 589
 590         i2c2: i2c@ff120000 {
 591                 compatible = "rockchip,rk3399-i2c";
 592                 reg = <0x0 0xff120000 0x0 0x1000>;
 593                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 594                 clock-names = "i2c", "pclk";
 595                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 596                 pinctrl-names = "default";
 597                 pinctrl-0 = <&i2c2_xfer>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 status = "disabled";
 601         };
 602
 603         i2c3: i2c@ff130000 {
 604                 compatible = "rockchip,rk3399-i2c";
 605                 reg = <0x0 0xff130000 0x0 0x1000>;
 606                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 607                 clock-names = "i2c", "pclk";
 608                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 609                 pinctrl-names = "default";
 610                 pinctrl-0 = <&i2c3_xfer>;
 611                 #address-cells = <1>;
 612                 #size-cells = <0>;
 613                 status = "disabled";
 614         };
 615
 616         i2c5: i2c@ff140000 {
 617                 compatible = "rockchip,rk3399-i2c";
 618                 reg = <0x0 0xff140000 0x0 0x1000>;
 619                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 620                 clock-names = "i2c", "pclk";
 621                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 622                 pinctrl-names = "default";
 623                 pinctrl-0 = <&i2c5_xfer>;
 624                 #address-cells = <1>;
 625                 #size-cells = <0>;
 626                 status = "disabled";
 627         };
 628
 629         i2c6: i2c@ff150000 {
 630                 compatible = "rockchip,rk3399-i2c";
 631                 reg = <0x0 0xff150000 0x0 0x1000>;
 632                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 633                 clock-names = "i2c", "pclk";
 634                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 635                 pinctrl-names = "default";
 636                 pinctrl-0 = <&i2c6_xfer>;
 637                 #address-cells = <1>;
 638                 #size-cells = <0>;
 639                 status = "disabled";
 640         };
 641
 642         i2c7: i2c@ff160000 {
 643                 compatible = "rockchip,rk3399-i2c";
 644                 reg = <0x0 0xff160000 0x0 0x1000>;
 645                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 646                 clock-names = "i2c", "pclk";
 647                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 648                 pinctrl-names = "default";
 649                 pinctrl-0 = <&i2c7_xfer>;
 650                 #address-cells = <1>;
 651                 #size-cells = <0>;
 652                 status = "disabled";
 653         };
 654
 655         uart0: serial@ff180000 {
 656                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 657                 reg = <0x0 0xff180000 0x0 0x100>;
 658                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 659                 clock-names = "baudclk", "apb_pclk";
 660                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 661                 reg-shift = <2>;
 662                 reg-io-width = <4>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 665                 status = "disabled";
 666         };
 667
 668         uart1: serial@ff190000 {
 669                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 670                 reg = <0x0 0xff190000 0x0 0x100>;
 671                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 672                 clock-names = "baudclk", "apb_pclk";
 673                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 674                 reg-shift = <2>;
 675                 reg-io-width = <4>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&uart1_xfer>;
 678                 status = "disabled";
 679         };
 680
 681         uart2: serial@ff1a0000 {
 682                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 683                 reg = <0x0 0xff1a0000 0x0 0x100>;
 684                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 685                 clock-names = "baudclk", "apb_pclk";
 686                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 687                 reg-shift = <2>;
 688                 reg-io-width = <4>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&uart2c_xfer>;
 691                 status = "disabled";
 692         };
 693
 694         uart3: serial@ff1b0000 {
 695                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 696                 reg = <0x0 0xff1b0000 0x0 0x100>;
 697                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 698                 clock-names = "baudclk", "apb_pclk";
 699                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 700                 reg-shift = <2>;
 701                 reg-io-width = <4>;
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 704                 status = "disabled";
 705         };
 706
 707         spi0: spi@ff1c0000 {
 708                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 709                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 710                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 711                 clock-names = "spiclk", "apb_pclk";
 712                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 713                 pinctrl-names = "default";
 714                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 715                 #address-cells = <1>;
 716                 #size-cells = <0>;
 717                 status = "disabled";
 718         };
 719
 720         spi1: spi@ff1d0000 {
 721                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 722                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 723                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 724                 clock-names = "spiclk", "apb_pclk";
 725                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 726                 pinctrl-names = "default";
 727                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 728                 #address-cells = <1>;
 729                 #size-cells = <0>;
 730                 status = "disabled";
 731         };
 732
 733         spi2: spi@ff1e0000 {
 734                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 735                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 736                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 737                 clock-names = "spiclk", "apb_pclk";
 738                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 739                 pinctrl-names = "default";
 740                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 741                 #address-cells = <1>;
 742                 #size-cells = <0>;
 743                 status = "disabled";
 744         };
 745
 746         spi4: spi@ff1f0000 {
 747                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 748                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 749                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 750                 clock-names = "spiclk", "apb_pclk";
 751                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 752                 pinctrl-names = "default";
 753                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 754                 #address-cells = <1>;
 755                 #size-cells = <0>;
 756                 status = "disabled";
 757         };
 758
 759         spi5: spi@ff200000 {
 760                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 761                 reg = <0x0 0xff200000 0x0 0x1000>;
 762                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 763                 clock-names = "spiclk", "apb_pclk";
 764                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 765                 pinctrl-names = "default";
 766                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 767                 #address-cells = <1>;
 768                 #size-cells = <0>;
 769                 status = "disabled";
 770         };
 771
 772         thermal-zones {
 773                 soc_thermal: soc-thermal {
 774                         polling-delay-passive = <20>; /* milliseconds */
 775                         polling-delay = <1000>; /* milliseconds */
 776                         sustainable-power = <1000>; /* milliwatts */
 777
 778                         thermal-sensors = <&tsadc 0>;
 779
 780                         trips {
 781                                 threshold: trip-point@0 {
 782                                         temperature = <70000>; /* millicelsius */
 783                                         hysteresis = <2000>; /* millicelsius */
 784                                         type = "passive";
 785                                 };
 786                                 target: trip-point@1 {
 787                                         temperature = <85000>; /* millicelsius */
 788                                         hysteresis = <2000>; /* millicelsius */
 789                                         type = "passive";
 790                                 };
 791                                 soc_crit: soc-crit {
 792                                         temperature = <95000>; /* millicelsius */
 793                                         hysteresis = <2000>; /* millicelsius */
 794                                         type = "critical";
 795                                 };
 796                         };
 797
 798                         cooling-maps {
 799                                 map0 {
 800                                         trip = <&target>;
 801                                         cooling-device =
 802                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 803                                         contribution = <4096>;
 804                                 };
 805                                 map1 {
 806                                         trip = <&target>;
 807                                         cooling-device =
 808                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 809                                         contribution = <1024>;
 810                                 };
 811                                 map2 {
 812                                         trip = <&target>;
 813                                         cooling-device =
 814                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 815                                         contribution = <4096>;
 816                                 };
 817                         };
 818                 };
 819
 820                 gpu_thermal: gpu-thermal {
 821                         polling-delay-passive = <100>; /* milliseconds */
 822                         polling-delay = <1000>; /* milliseconds */
 823
 824                         thermal-sensors = <&tsadc 1>;
 825                 };
 826         };
 827
 828         tsadc: tsadc@ff260000 {
 829                 compatible = "rockchip,rk3399-tsadc";
 830                 reg = <0x0 0xff260000 0x0 0x100>;
 831                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 832                 rockchip,grf = <&grf>;
 833                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 834                 clock-names = "tsadc", "apb_pclk";
 835                 assigned-clocks = <&cru SCLK_TSADC>;
 836                 assigned-clock-rates = <750000>;
 837                 resets = <&cru SRST_TSADC>;
 838                 reset-names = "tsadc-apb";
 839                 pinctrl-names = "init", "default", "sleep";
 840                 pinctrl-0 = <&otp_gpio>;
 841                 pinctrl-1 = <&otp_out>;
 842                 pinctrl-2 = <&otp_gpio>;
 843                 #thermal-sensor-cells = <1>;
 844                 rockchip,hw-tshut-temp = <95000>;
 845                 status = "disabled";
 846         };
 847
 848         qos_emmc: qos@ffa58000 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffa58000 0x0 0x20>;
 851         };
 852
 853         qos_gmac: qos@ffa5c000 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffa5c000 0x0 0x20>;
 856         };
 857
 858         qos_pcie: qos@ffa60080 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffa60080 0x0 0x20>;
 861         };
 862
 863         qos_usb_host0: qos@ffa60100 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffa60100 0x0 0x20>;
 866         };
 867
 868         qos_usb_host1: qos@ffa60180 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffa60180 0x0 0x20>;
 871         };
 872
 873         qos_usb_otg0: qos@ffa70000 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffa70000 0x0 0x20>;
 876         };
 877
 878         qos_usb_otg1: qos@ffa70080 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffa70080 0x0 0x20>;
 881         };
 882
 883         qos_sd: qos@ffa74000 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffa74000 0x0 0x20>;
 886         };
 887
 888         qos_sdioaudio: qos@ffa76000 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffa76000 0x0 0x20>;
 891         };
 892
 893         qos_hdcp: qos@ffa90000 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffa90000 0x0 0x20>;
 896         };
 897
 898         qos_iep: qos@ffa98000 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffa98000 0x0 0x20>;
 901         };
 902
 903         qos_isp0_m0: qos@ffaa0000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffaa0000 0x0 0x20>;
 906         };
 907
 908         qos_isp0_m1: qos@ffaa0080 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffaa0080 0x0 0x20>;
 911         };
 912
 913         qos_isp1_m0: qos@ffaa8000 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffaa8000 0x0 0x20>;
 916         };
 917
 918         qos_isp1_m1: qos@ffaa8080 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffaa8080 0x0 0x20>;
 921         };
 922
 923         qos_rga_r: qos@ffab0000 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffab0000 0x0 0x20>;
 926         };
 927
 928         qos_rga_w: qos@ffab0080 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffab0080 0x0 0x20>;
 931         };
 932
 933         qos_video_m0: qos@ffab8000 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffab8000 0x0 0x20>;
 936         };
 937
 938         qos_video_m1_r: qos@ffac0000 {
 939                 compatible = "syscon";
 940                 reg = <0x0 0xffac0000 0x0 0x20>;
 941         };
 942
 943         qos_video_m1_w: qos@ffac0080 {
 944                 compatible = "syscon";
 945                 reg = <0x0 0xffac0080 0x0 0x20>;
 946         };
 947
 948         qos_vop_big_r: qos@ffac8000 {
 949                 compatible = "syscon";
 950                 reg = <0x0 0xffac8000 0x0 0x20>;
 951         };
 952
 953         qos_vop_big_w: qos@ffac8080 {
 954                 compatible = "syscon";
 955                 reg = <0x0 0xffac8080 0x0 0x20>;
 956         };
 957
 958         qos_vop_little: qos@ffad0000 {
 959                 compatible = "syscon";
 960                 reg = <0x0 0xffad0000 0x0 0x20>;
 961         };
 962
 963         qos_perihp: qos@ffad8080 {
 964                 compatible = "syscon";
 965                 reg = <0x0 0xffad8080 0x0 0x20>;
 966         };
 967
 968         qos_gpu: qos@ffae0000 {
 969                 compatible = "syscon";
 970                 reg = <0x0 0xffae0000 0x0 0x20>;
 971         };
 972
 973         pmu: power-management@ff310000 {
 974                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 975                 reg = <0x0 0xff310000 0x0 0x1000>;
 976
 977                 /*
 978                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 979                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 980                  * Some of the power domains are grouped together for every
 981                  * voltage domain.
 982                  * The detail contents as below.
 983                  */
 984                 power: power-controller {
 985                         compatible = "rockchip,rk3399-power-controller";
 986                         #power-domain-cells = <1>;
 987                         #address-cells = <1>;
 988                         #size-cells = <0>;
 989
 990                         /* These power domains are grouped by VD_CENTER */
 991                         pd_iep@RK3399_PD_IEP {
 992                                 reg = <RK3399_PD_IEP>;
 993                                 clocks = <&cru ACLK_IEP>,
 994                                          <&cru HCLK_IEP>;
 995                                 pm_qos = <&qos_iep>;
 996                         };
 997                         pd_rga@RK3399_PD_RGA {
 998                                 reg = <RK3399_PD_RGA>;
 999                                 clocks = <&cru ACLK_RGA>,
1000                                          <&cru HCLK_RGA>;
1001                                 pm_qos = <&qos_rga_r>,
1002                                          <&qos_rga_w>;
1003                         };
1004                         pd_vcodec@RK3399_PD_VCODEC {
1005                                 reg = <RK3399_PD_VCODEC>;
1006                                 clocks = <&cru ACLK_VCODEC>,
1007                                          <&cru HCLK_VCODEC>;
1008                                 pm_qos = <&qos_video_m0>;
1009                         };
1010                         pd_vdu@RK3399_PD_VDU {
1011                                 reg = <RK3399_PD_VDU>;
1012                                 clocks = <&cru ACLK_VDU>,
1013                                          <&cru HCLK_VDU>;
1014                                 pm_qos = <&qos_video_m1_r>,
1015                                          <&qos_video_m1_w>;
1016                         };
1017
1018                         /* These power domains are grouped by VD_GPU */
1019                         pd_gpu@RK3399_PD_GPU {
1020                                 reg = <RK3399_PD_GPU>;
1021                                 clocks = <&cru ACLK_GPU>;
1022                                 pm_qos = <&qos_gpu>;
1023                         };
1024
1025                         /* These power domains are grouped by VD_LOGIC */
1026                         pd_edp@RK3399_PD_EDP {
1027                                 reg = <RK3399_PD_EDP>;
1028                                 clocks = <&cru PCLK_EDP_CTRL>;
1029                         };
1030                         pd_emmc@RK3399_PD_EMMC {
1031                                 reg = <RK3399_PD_EMMC>;
1032                                 clocks = <&cru ACLK_EMMC>;
1033                                 pm_qos = <&qos_emmc>;
1034                         };
1035                         pd_gmac@RK3399_PD_GMAC {
1036                                 reg = <RK3399_PD_GMAC>;
1037                                 clocks = <&cru ACLK_GMAC>;
1038                                 pm_qos = <&qos_gmac>;
1039                         };
1040                         pd_perihp@RK3399_PD_PERIHP {
1041                                 reg = <RK3399_PD_PERIHP>;
1042                                 #address-cells = <1>;
1043                                 #size-cells = <0>;
1044                                 clocks = <&cru ACLK_PERIHP>;
1045                                 pm_qos = <&qos_perihp>,
1046                                          <&qos_pcie>,
1047                                          <&qos_usb_host0>,
1048                                          <&qos_usb_host1>;
1049
1050                                 pd_sd@RK3399_PD_SD {
1051                                         reg = <RK3399_PD_SD>;
1052                                         clocks = <&cru HCLK_SDMMC>,
1053                                                  <&cru SCLK_SDMMC>;
1054                                         pm_qos = <&qos_sd>;
1055                                 };
1056                         };
1057                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1058                                 reg = <RK3399_PD_SDIOAUDIO>;
1059                                 clocks = <&cru HCLK_SDIO>;
1060                                 pm_qos = <&qos_sdioaudio>;
1061                         };
1062                         pd_usb3@RK3399_PD_USB3 {
1063                                 reg = <RK3399_PD_USB3>;
1064                                 clocks = <&cru ACLK_USB3>;
1065                                 pm_qos = <&qos_usb_otg0>,
1066                                          <&qos_usb_otg1>;
1067                         };
1068                         pd_vio@RK3399_PD_VIO {
1069                                 reg = <RK3399_PD_VIO>;
1070                                 #address-cells = <1>;
1071                                 #size-cells = <0>;
1072
1073                                 pd_hdcp@RK3399_PD_HDCP {
1074                                         reg = <RK3399_PD_HDCP>;
1075                                         clocks = <&cru ACLK_HDCP>,
1076                                                  <&cru HCLK_HDCP>,
1077                                                  <&cru PCLK_HDCP>;
1078                                         pm_qos = <&qos_hdcp>;
1079                                 };
1080                                 pd_isp0@RK3399_PD_ISP0 {
1081                                         reg = <RK3399_PD_ISP0>;
1082                                         clocks = <&cru ACLK_ISP0>,
1083                                                  <&cru HCLK_ISP0>;
1084                                         pm_qos = <&qos_isp0_m0>,
1085                                                  <&qos_isp0_m1>;
1086                                 };
1087                                 pd_isp1@RK3399_PD_ISP1 {
1088                                         reg = <RK3399_PD_ISP1>;
1089                                         clocks = <&cru ACLK_ISP1>,
1090                                                  <&cru HCLK_ISP1>;
1091                                         pm_qos = <&qos_isp1_m0>,
1092                                                  <&qos_isp1_m1>;
1093                                 };
1094                                 pd_tcpc0@RK3399_PD_TCPC0 {
1095                                         reg = <RK3399_PD_TCPD0>;
1096                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1097                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1098                                 };
1099                                 pd_tcpc1@RK3399_PD_TCPC1 {
1100                                         reg = <RK3399_PD_TCPD1>;
1101                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1102                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1103                                 };
1104                                 pd_vo@RK3399_PD_VO {
1105                                         reg = <RK3399_PD_VO>;
1106                                         #address-cells = <1>;
1107                                         #size-cells = <0>;
1108
1109                                         pd_vopb@RK3399_PD_VOPB {
1110                                                 reg = <RK3399_PD_VOPB>;
1111                                                 clocks = <&cru ACLK_VOP0>,
1112                                                          <&cru HCLK_VOP0>;
1113                                                 pm_qos = <&qos_vop_big_r>,
1114                                                          <&qos_vop_big_w>;
1115                                         };
1116                                         pd_vopl@RK3399_PD_VOPL {
1117                                                 reg = <RK3399_PD_VOPL>;
1118                                                 clocks = <&cru ACLK_VOP1>,
1119                                                          <&cru HCLK_VOP1>;
1120                                                 pm_qos = <&qos_vop_little>;
1121                                         };
1122                                 };
1123                         };
1124                 };
1125         };
1126
1127         pmugrf: syscon@ff320000 {
1128                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1129                 reg = <0x0 0xff320000 0x0 0x1000>;
1130
1131                 reboot-mode {
1132                         compatible = "syscon-reboot-mode";
1133                         offset = <0x300>;
1134                         mode-bootloader = <BOOT_LOADER>;
1135                         mode-charge = <BOOT_CHARGING>;
1136                         mode-fastboot = <BOOT_FASTBOOT>;
1137                         mode-loader = <BOOT_LOADER>;
1138                         mode-normal = <BOOT_NORMAL>;
1139                         mode-recovery = <BOOT_RECOVERY>;
1140                         mode-ums = <BOOT_UMS>;
1141                 };
1142         };
1143
1144         spi3: spi@ff350000 {
1145                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1146                 reg = <0x0 0xff350000 0x0 0x1000>;
1147                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1148                 clock-names = "spiclk", "apb_pclk";
1149                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1150                 pinctrl-names = "default";
1151                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1152                 #address-cells = <1>;
1153                 #size-cells = <0>;
1154                 status = "disabled";
1155         };
1156
1157         uart4: serial@ff370000 {
1158                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1159                 reg = <0x0 0xff370000 0x0 0x100>;
1160                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1161                 clock-names = "baudclk", "apb_pclk";
1162                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1163                 reg-shift = <2>;
1164                 reg-io-width = <4>;
1165                 pinctrl-names = "default";
1166                 pinctrl-0 = <&uart4_xfer>;
1167                 status = "disabled";
1168         };
1169
1170         i2c4: i2c@ff3d0000 {
1171                 compatible = "rockchip,rk3399-i2c";
1172                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1173                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1174                 clock-names = "i2c", "pclk";
1175                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1176                 pinctrl-names = "default";
1177                 pinctrl-0 = <&i2c4_xfer>;
1178                 #address-cells = <1>;
1179                 #size-cells = <0>;
1180                 status = "disabled";
1181         };
1182
1183         i2c8: i2c@ff3e0000 {
1184                 compatible = "rockchip,rk3399-i2c";
1185                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1186                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1187                 clock-names = "i2c", "pclk";
1188                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1189                 pinctrl-names = "default";
1190                 pinctrl-0 = <&i2c8_xfer>;
1191                 #address-cells = <1>;
1192                 #size-cells = <0>;
1193                 status = "disabled";
1194         };
1195
1196         pcie_phy: phy@e220 {
1197                 compatible = "rockchip,rk3399-pcie-phy";
1198                 #phy-cells = <0>;
1199                 rockchip,grf = <&grf>;
1200                 clocks = <&cru SCLK_PCIEPHY_REF>;
1201                 clock-names = "refclk";
1202                 resets = <&cru SRST_PCIEPHY>;
1203                 reset-names = "phy";
1204                 status = "disabled";
1205         };
1206
1207         pcie0: pcie@f8000000 {
1208                 compatible = "rockchip,rk3399-pcie";
1209                 #address-cells = <3>;
1210                 #size-cells = <2>;
1211                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1212                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1213                 clock-names = "aclk", "aclk-perf",
1214                               "hclk", "pm";
1215                 bus-range = <0x0 0x1>;
1216                 msi-map = <0x0 &its 0x0 0x1000>;
1217                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1218                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1219                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1220                 interrupt-names = "sys", "legacy", "client";
1221                 #interrupt-cells = <1>;
1222                 interrupt-map-mask = <0 0 0 7>;
1223                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1224                                 <0 0 0 2 &pcie0_intc 1>,
1225                                 <0 0 0 3 &pcie0_intc 2>,
1226                                 <0 0 0 4 &pcie0_intc 3>;
1227                 phys = <&pcie_phy>;
1228                 phy-names = "pcie-phy";
1229                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1230                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1231                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1232                       <0x0 0xfd000000 0x0 0x1000000>;
1233                 reg-names = "axi-base", "apb-base";
1234                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1235                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1236                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1237                 status = "disabled";
1238                 pcie0_intc: interrupt-controller {
1239                         interrupt-controller;
1240                         #address-cells = <0>;
1241                         #interrupt-cells = <1>;
1242                 };
1243         };
1244
1245         pwm0: pwm@ff420000 {
1246                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1247                 reg = <0x0 0xff420000 0x0 0x10>;
1248                 #pwm-cells = <3>;
1249                 pinctrl-names = "default";
1250                 pinctrl-0 = <&pwm0_pin>;
1251                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1252                 clock-names = "pwm";
1253                 status = "disabled";
1254         };
1255
1256         pwm1: pwm@ff420010 {
1257                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1258                 reg = <0x0 0xff420010 0x0 0x10>;
1259                 #pwm-cells = <3>;
1260                 pinctrl-names = "default";
1261                 pinctrl-0 = <&pwm1_pin>;
1262                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1263                 clock-names = "pwm";
1264                 status = "disabled";
1265         };
1266
1267         pwm2: pwm@ff420020 {
1268                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1269                 reg = <0x0 0xff420020 0x0 0x10>;
1270                 #pwm-cells = <3>;
1271                 pinctrl-names = "default";
1272                 pinctrl-0 = <&pwm2_pin>;
1273                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1274                 clock-names = "pwm";
1275                 status = "disabled";
1276         };
1277
1278         pwm3: pwm@ff420030 {
1279                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1280                 reg = <0x0 0xff420030 0x0 0x10>;
1281                 #pwm-cells = <3>;
1282                 pinctrl-names = "default";
1283                 pinctrl-0 = <&pwm3a_pin>;
1284                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1285                 clock-names = "pwm";
1286                 status = "disabled";
1287         };
1288
1289         dfi: dfi@ff630000 {
1290                 reg = <0x00 0xff630000 0x00 0x4000>;
1291                 compatible = "rockchip,rk3399-dfi";
1292                 rockchip,pmu = <&pmugrf>;
1293                 clocks = <&cru PCLK_DDR_MON>;
1294                 clock-names = "pclk_ddr_mon";
1295                 status = "disabled";
1296         };
1297
1298         dmc: dmc {
1299                 compatible = "rockchip,rk3399-dmc";
1300                 devfreq-events = <&dfi>;
1301                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1302                 clocks = <&cru SCLK_DDRCLK>;
1303                 clock-names = "dmc_clk";
1304                 ddr_timing = <&ddr_timing>;
1305                 operating-points-v2 = <&dmc_opp_table>;
1306                 status = "disabled";
1307         };
1308
1309         dmc_opp_table: dmc_opp_table {
1310                 compatible = "operating-points-v2";
1311
1312                 opp00 {
1313                         opp-hz = /bits/ 64 <666000000>;
1314                         opp-microvolt = <900000>;
1315                 };
1316         };
1317
1318         rga: rga@ff680000 {
1319                 compatible = "rockchip,rk3399-rga";
1320                 reg = <0x0 0xff680000 0x0 0x10000>;
1321                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1322                 interrupt-names = "rga";
1323                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1324                 clock-names = "aclk", "hclk", "sclk";
1325                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1326                 reset-names = "core", "axi", "ahb";
1327                 power-domains = <&power RK3399_PD_RGA>;
1328                 status = "disabled";
1329         };
1330
1331         efuse0: efuse@ff690000 {
1332                 compatible = "rockchip,rk3399-efuse";
1333                 reg = <0x0 0xff690000 0x0 0x80>;
1334                 #address-cells = <1>;
1335                 #size-cells = <1>;
1336                 clocks = <&cru PCLK_EFUSE1024NS>;
1337                 clock-names = "pclk_efuse";
1338
1339                 /* Data cells */
1340                 cpul_leakage: cpul-leakage {
1341                         reg = <0x1a 0x1>;
1342                 };
1343                 cpub_leakage: cpub-leakage {
1344                         reg = <0x17 0x1>;
1345                 };
1346                 gpu_leakage: gpu-leakage {
1347                         reg = <0x18 0x1>;
1348                 };
1349                 center_leakage: center-leakage {
1350                         reg = <0x19 0x1>;
1351                 };
1352                 logic_leakage: logic-leakage {
1353                         reg = <0x1b 0x1>;
1354                 };
1355                 wafer_info: wafer-info {
1356                         reg = <0x1c 0x1>;
1357                 };
1358         };
1359
1360         pmucru: pmu-clock-controller@ff750000 {
1361                 compatible = "rockchip,rk3399-pmucru";
1362                 reg = <0x0 0xff750000 0x0 0x1000>;
1363                 #clock-cells = <1>;
1364                 #reset-cells = <1>;
1365                 assigned-clocks = <&pmucru PLL_PPLL>;
1366                 assigned-clock-rates = <676000000>;
1367         };
1368
1369         cru: clock-controller@ff760000 {
1370                 compatible = "rockchip,rk3399-cru";
1371                 reg = <0x0 0xff760000 0x0 0x1000>;
1372                 #clock-cells = <1>;
1373                 #reset-cells = <1>;
1374                 assigned-clocks =
1375                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1376                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1377                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1378                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1379                         <&cru PLL_NPLL>,
1380                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1381                         <&cru PCLK_PERIHP>,
1382                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1383                         <&cru PCLK_PERILP0>,
1384                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1385                 assigned-clock-rates =
1386                          <400000000>,  <200000000>,
1387                          <400000000>,  <200000000>,
1388                          <816000000>, <816000000>,
1389                          <594000000>,  <800000000>,
1390                         <1000000000>,
1391                          <150000000>,   <75000000>,
1392                           <37500000>,
1393                          <100000000>,  <100000000>,
1394                           <50000000>,
1395                          <100000000>,   <50000000>;
1396         };
1397
1398         grf: syscon@ff770000 {
1399                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1400                 reg = <0x0 0xff770000 0x0 0x10000>;
1401                 #address-cells = <1>;
1402                 #size-cells = <1>;
1403
1404                 emmc_phy: phy@f780 {
1405                         compatible = "rockchip,rk3399-emmc-phy";
1406                         reg = <0xf780 0x24>;
1407                         clocks = <&sdhci>;
1408                         clock-names = "emmcclk";
1409                         #phy-cells = <0>;
1410                         status = "disabled";
1411                 };
1412
1413                 u2phy0: usb2-phy@e450 {
1414                         compatible = "rockchip,rk3399-usb2phy";
1415                         reg = <0xe450 0x10>;
1416                         clocks = <&cru SCLK_USB2PHY0_REF>;
1417                         clock-names = "phyclk";
1418                         #clock-cells = <0>;
1419                         clock-output-names = "clk_usbphy0_480m";
1420                         status = "disabled";
1421
1422                         u2phy0_otg: otg-port {
1423                                 #phy-cells = <0>;
1424                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1425                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1426                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1427                                 interrupt-names = "otg-bvalid", "otg-id",
1428                                                   "linestate";
1429                                 status = "disabled";
1430                         };
1431
1432                         u2phy0_host: host-port {
1433                                 #phy-cells = <0>;
1434                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1435                                 interrupt-names = "linestate";
1436                                 status = "disabled";
1437                         };
1438                 };
1439
1440                 u2phy1: usb2-phy@e460 {
1441                         compatible = "rockchip,rk3399-usb2phy";
1442                         reg = <0xe460 0x10>;
1443                         clocks = <&cru SCLK_USB2PHY1_REF>;
1444                         clock-names = "phyclk";
1445                         #clock-cells = <0>;
1446                         clock-output-names = "clk_usbphy1_480m";
1447                         status = "disabled";
1448
1449                         u2phy1_otg: otg-port {
1450                                 #phy-cells = <0>;
1451                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1452                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1453                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1454                                 interrupt-names = "otg-bvalid", "otg-id",
1455                                                   "linestate";
1456                                 status = "disabled";
1457                         };
1458
1459                         u2phy1_host: host-port {
1460                                 #phy-cells = <0>;
1461                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1462                                 interrupt-names = "linestate";
1463                                 status = "disabled";
1464                         };
1465                 };
1466         };
1467
1468         tcphy0: phy@ff7c0000 {
1469                 compatible = "rockchip,rk3399-typec-phy";
1470                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1471                 rockchip,grf = <&grf>;
1472                 #phy-cells = <1>;
1473                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1474                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1475                 clock-names = "tcpdcore", "tcpdphy-ref";
1476                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1477                 assigned-clock-rates = <50000000>;
1478                 resets = <&cru SRST_UPHY0>,
1479                          <&cru SRST_UPHY0_PIPE_L00>,
1480                          <&cru SRST_P_UPHY0_TCPHY>;
1481                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1482                 rockchip,typec-conn-dir = <0xe580 0 16>;
1483                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1484                 rockchip,usb3-host-disable = <0x2434 0 16>;
1485                 rockchip,usb3-host-port = <0x2434 12 28>;
1486                 rockchip,external-psm = <0xe588 14 30>;
1487                 rockchip,pipe-status = <0xe5c0 0 0>;
1488                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1489                 status = "disabled";
1490
1491                 tcphy0_dp: dp-port {
1492                         #phy-cells = <0>;
1493                 };
1494
1495                 tcphy0_usb3: usb3-port {
1496                         #phy-cells = <0>;
1497                 };
1498         };
1499
1500         tcphy1: phy@ff800000 {
1501                 compatible = "rockchip,rk3399-typec-phy";
1502                 reg = <0x0 0xff800000 0x0 0x40000>;
1503                 rockchip,grf = <&grf>;
1504                 #phy-cells = <1>;
1505                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1506                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1507                 clock-names = "tcpdcore", "tcpdphy-ref";
1508                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1509                 assigned-clock-rates = <50000000>;
1510                 resets = <&cru SRST_UPHY1>,
1511                          <&cru SRST_UPHY1_PIPE_L00>,
1512                          <&cru SRST_P_UPHY1_TCPHY>;
1513                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1514                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1515                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1516                 rockchip,usb3-host-disable = <0x2444 0 16>;
1517                 rockchip,usb3-host-port = <0x2444 12 28>;
1518                 rockchip,external-psm = <0xe594 14 30>;
1519                 rockchip,pipe-status = <0xe5c0 16 16>;
1520                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1521                 status = "disabled";
1522
1523                 tcphy1_dp: dp-port {
1524                         #phy-cells = <0>;
1525                 };
1526
1527                 tcphy1_usb3: usb3-port {
1528                         #phy-cells = <0>;
1529                 };
1530         };
1531
1532         watchdog@ff848000 {
1533                 compatible = "snps,dw-wdt";
1534                 reg = <0x0 0xff848000 0x0 0x100>;
1535                 clocks = <&cru PCLK_WDT>;
1536                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1537         };
1538
1539         rktimer: rktimer@ff850000 {
1540                 compatible = "rockchip,rk3399-timer";
1541                 reg = <0x0 0xff850000 0x0 0x1000>;
1542                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1543                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1544                 clock-names = "pclk", "timer";
1545         };
1546
1547         spdif: spdif@ff870000 {
1548                 compatible = "rockchip,rk3399-spdif";
1549                 reg = <0x0 0xff870000 0x0 0x1000>;
1550                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1551                 dmas = <&dmac_bus 7>;
1552                 dma-names = "tx";
1553                 clock-names = "mclk", "hclk";
1554                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1555                 pinctrl-names = "default";
1556                 pinctrl-0 = <&spdif_bus>;
1557                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1558                 status = "disabled";
1559         };
1560
1561         i2s0: i2s@ff880000 {
1562                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1563                 reg = <0x0 0xff880000 0x0 0x1000>;
1564                 rockchip,grf = <&grf>;
1565                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1566                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1567                 dma-names = "tx", "rx";
1568                 clock-names = "i2s_clk", "i2s_hclk";
1569                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1570                 pinctrl-names = "default";
1571                 pinctrl-0 = <&i2s0_8ch_bus>;
1572                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1573                 status = "disabled";
1574         };
1575
1576         i2s1: i2s@ff890000 {
1577                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1578                 reg = <0x0 0xff890000 0x0 0x1000>;
1579                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1580                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1581                 dma-names = "tx", "rx";
1582                 clock-names = "i2s_clk", "i2s_hclk";
1583                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1584                 pinctrl-names = "default";
1585                 pinctrl-0 = <&i2s1_2ch_bus>;
1586                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1587                 status = "disabled";
1588         };
1589
1590         i2s2: i2s@ff8a0000 {
1591                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1592                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1593                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1594                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1595                 dma-names = "tx", "rx";
1596                 clock-names = "i2s_clk", "i2s_hclk";
1597                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1598                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1599                 status = "disabled";
1600         };
1601
1602         gpu: gpu@ff9a0000 {
1603                 compatible = "arm,malit860",
1604                              "arm,malit86x",
1605                              "arm,malit8xx",
1606                              "arm,mali-midgard";
1607
1608                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1609
1610                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1611                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1612                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1613                 interrupt-names = "GPU", "JOB", "MMU";
1614
1615                 clocks = <&cru ACLK_GPU>;
1616                 clock-names = "clk_mali";
1617                 #cooling-cells = <2>; /* min followed by max */
1618                 operating-points-v2 = <&gpu_opp_table>;
1619                 power-domains = <&power RK3399_PD_GPU>;
1620                 power-off-delay-ms = <200>;
1621                 status = "disabled";
1622
1623                 gpu_power_model: power_model {
1624                         compatible = "arm,mali-simple-power-model";
1625                         voltage = <900>;
1626                         frequency = <500>;
1627                         static-power = <300>;
1628                         dynamic-power = <396>;
1629                         ts = <32000 4700 (-80) 2>;
1630                         thermal-zone = "gpu-thermal";
1631                 };
1632         };
1633
1634         gpu_opp_table: gpu_opp_table {
1635                 compatible = "operating-points-v2";
1636                 opp-shared;
1637
1638                 opp@200000000 {
1639                         opp-hz = /bits/ 64 <200000000>;
1640                         opp-microvolt = <900000>;
1641                 };
1642                 opp@300000000 {
1643                         opp-hz = /bits/ 64 <300000000>;
1644                         opp-microvolt = <900000>;
1645                 };
1646                 opp@400000000 {
1647                         opp-hz = /bits/ 64 <400000000>;
1648                         opp-microvolt = <900000>;
1649                 };
1650
1651         };
1652
1653         vopl: vop@ff8f0000 {
1654                 compatible = "rockchip,rk3399-vop-lit";
1655                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1656                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1657                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1658                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1659                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1660                 reset-names = "axi", "ahb", "dclk";
1661                 power-domains = <&power RK3399_PD_VOPL>;
1662                 iommus = <&vopl_mmu>;
1663                 status = "disabled";
1664
1665                 vopl_out: port {
1666                         #address-cells = <1>;
1667                         #size-cells = <0>;
1668
1669                         vopl_out_mipi: endpoint@0 {
1670                                 reg = <0>;
1671                                 remote-endpoint = <&mipi_in_vopl>;
1672                         };
1673
1674                         vopl_out_edp: endpoint@1 {
1675                                 reg = <1>;
1676                                 remote-endpoint = <&edp_in_vopl>;
1677                         };
1678
1679                         vopl_out_hdmi: endpoint@2 {
1680                                 reg = <2>;
1681                                 remote-endpoint = <&hdmi_in_vopl>;
1682                         };
1683                 };
1684         };
1685
1686         vop1_pwm: voppwm@ff8f01a0 {
1687                 compatible = "rockchip,vop-pwm";
1688                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1689                 #pwm-cells = <3>;
1690                 pinctrl-names = "default";
1691                 pinctrl-0 = <&vop1_pwm_pin>;
1692                 clocks = <&cru SCLK_VOP1_PWM>;
1693                 clock-names = "pwm";
1694                 status = "disabled";
1695         };
1696
1697         vopl_mmu: iommu@ff8f3f00 {
1698                 compatible = "rockchip,iommu";
1699                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1700                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1701                 interrupt-names = "vopl_mmu";
1702                 #iommu-cells = <0>;
1703                 status = "disabled";
1704         };
1705
1706         vopb: vop@ff900000 {
1707                 compatible = "rockchip,rk3399-vop-big";
1708                 reg = <0x0 0xff900000 0x0 0x3efc>;
1709                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1710                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1711                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1712                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1713                 reset-names = "axi", "ahb", "dclk";
1714                 power-domains = <&power RK3399_PD_VOPB>;
1715                 iommus = <&vopb_mmu>;
1716                 status = "disabled";
1717
1718                 vopb_out: port {
1719                         #address-cells = <1>;
1720                         #size-cells = <0>;
1721
1722                         vopb_out_edp: endpoint@0 {
1723                                 reg = <0>;
1724                                 remote-endpoint = <&edp_in_vopb>;
1725                         };
1726
1727                         vopb_out_mipi: endpoint@1 {
1728                                 reg = <1>;
1729                                 remote-endpoint = <&mipi_in_vopb>;
1730                         };
1731
1732                         vopb_out_hdmi: endpoint@2 {
1733                                 reg = <2>;
1734                                 remote-endpoint = <&hdmi_in_vopb>;
1735                         };
1736                 };
1737         };
1738
1739         vop0_pwm: voppwm@ff9001a0 {
1740                 compatible = "rockchip,vop-pwm";
1741                 reg = <0x0 0xff9001a0 0x0 0x10>;
1742                 #pwm-cells = <3>;
1743                 pinctrl-names = "default";
1744                 pinctrl-0 = <&vop0_pwm_pin>;
1745                 clocks = <&cru SCLK_VOP0_PWM>;
1746                 clock-names = "pwm";
1747                 status = "disabled";
1748         };
1749
1750         vopb_mmu: iommu@ff903f00 {
1751                 compatible = "rockchip,iommu";
1752                 reg = <0x0 0xff903f00 0x0 0x100>;
1753                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1754                 interrupt-names = "vopb_mmu";
1755                 #iommu-cells = <0>;
1756                 status = "disabled";
1757         };
1758
1759         hdmi: hdmi@ff940000 {
1760                 compatible = "rockchip,rk3399-dw-hdmi";
1761                 reg = <0x0 0xff940000 0x0 0x20000>;
1762                 reg-io-width = <4>;
1763                 rockchip,grf = <&grf>;
1764                 power-domains = <&power RK3399_PD_HDCP>;
1765                 pinctrl-names = "default";
1766                 pinctrl-0 = <&hdmi_i2c_xfer>;
1767                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1768                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1769                 clock-names = "iahb", "isfr", "vpll", "grf";
1770                 status = "disabled";
1771
1772                 ports {
1773                         hdmi_in: port {
1774                                 #address-cells = <1>;
1775                                 #size-cells = <0>;
1776                                 hdmi_in_vopb: endpoint@0 {
1777                                         reg = <0>;
1778                                         remote-endpoint = <&vopb_out_hdmi>;
1779                                 };
1780                                 hdmi_in_vopl: endpoint@1 {
1781                                         reg = <1>;
1782                                         remote-endpoint = <&vopl_out_hdmi>;
1783                                 };
1784                         };
1785                 };
1786         };
1787
1788         mipi_dsi: mipi@ff960000 {
1789                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1790                 reg = <0x0 0xff960000 0x0 0x8000>;
1791                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1792                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1793                          <&cru SCLK_DPHY_TX0_CFG>;
1794                 clock-names = "ref", "pclk", "phy_cfg";
1795                 power-domains = <&power RK3399_PD_VIO>;
1796                 rockchip,grf = <&grf>;
1797                 #address-cells = <1>;
1798                 #size-cells = <0>;
1799                 status = "disabled";
1800
1801                 ports {
1802                         #address-cells = <1>;
1803                         #size-cells = <0>;
1804                         reg = <1>;
1805
1806                         mipi_in: port {
1807                                 #address-cells = <1>;
1808                                 #size-cells = <0>;
1809
1810                                 mipi_in_vopb: endpoint@0 {
1811                                         reg = <0>;
1812                                         remote-endpoint = <&vopb_out_mipi>;
1813                                 };
1814                                 mipi_in_vopl: endpoint@1 {
1815                                         reg = <1>;
1816                                         remote-endpoint = <&vopl_out_mipi>;
1817                                 };
1818                         };
1819                 };
1820         };
1821
1822         edp: edp@ff970000 {
1823                 compatible = "rockchip,rk3399-edp";
1824                 reg = <0x0 0xff970000 0x0 0x8000>;
1825                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1826                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1827                 clock-names = "dp", "pclk";
1828                 power-domains = <&power RK3399_PD_EDP>;
1829                 resets = <&cru SRST_P_EDP_CTRL>;
1830                 reset-names = "dp";
1831                 rockchip,grf = <&grf>;
1832                 status = "disabled";
1833                 pinctrl-names = "default";
1834                 pinctrl-0 = <&edp_hpd>;
1835
1836                 ports {
1837                         #address-cells = <1>;
1838                         #size-cells = <0>;
1839
1840                         edp_in: port@0 {
1841                                 reg = <0>;
1842                                 #address-cells = <1>;
1843                                 #size-cells = <0>;
1844
1845                                 edp_in_vopb: endpoint@0 {
1846                                         reg = <0>;
1847                                         remote-endpoint = <&vopb_out_edp>;
1848                                 };
1849
1850                                 edp_in_vopl: endpoint@1 {
1851                                         reg = <1>;
1852                                         remote-endpoint = <&vopl_out_edp>;
1853                                 };
1854                         };
1855                 };
1856         };
1857
1858         display_subsystem: display-subsystem {
1859                 compatible = "rockchip,display-subsystem";
1860                 ports = <&vopl_out>, <&vopb_out>;
1861                 status = "disabled";
1862         };
1863
1864         pinctrl: pinctrl {
1865                 compatible = "rockchip,rk3399-pinctrl";
1866                 rockchip,grf = <&grf>;
1867                 rockchip,pmu = <&pmugrf>;
1868                 #address-cells = <0x2>;
1869                 #size-cells = <0x2>;
1870                 ranges;
1871
1872                 gpio0: gpio0@ff720000 {
1873                         compatible = "rockchip,gpio-bank";
1874                         reg = <0x0 0xff720000 0x0 0x100>;
1875                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1876                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1877
1878                         gpio-controller;
1879                         #gpio-cells = <0x2>;
1880
1881                         interrupt-controller;
1882                         #interrupt-cells = <0x2>;
1883                 };
1884
1885                 gpio1: gpio1@ff730000 {
1886                         compatible = "rockchip,gpio-bank";
1887                         reg = <0x0 0xff730000 0x0 0x100>;
1888                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1889                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1890
1891                         gpio-controller;
1892                         #gpio-cells = <0x2>;
1893
1894                         interrupt-controller;
1895                         #interrupt-cells = <0x2>;
1896                 };
1897
1898                 gpio2: gpio2@ff780000 {
1899                         compatible = "rockchip,gpio-bank";
1900                         reg = <0x0 0xff780000 0x0 0x100>;
1901                         clocks = <&cru PCLK_GPIO2>;
1902                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1903
1904                         gpio-controller;
1905                         #gpio-cells = <0x2>;
1906
1907                         interrupt-controller;
1908                         #interrupt-cells = <0x2>;
1909                 };
1910
1911                 gpio3: gpio3@ff788000 {
1912                         compatible = "rockchip,gpio-bank";
1913                         reg = <0x0 0xff788000 0x0 0x100>;
1914                         clocks = <&cru PCLK_GPIO3>;
1915                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1916
1917                         gpio-controller;
1918                         #gpio-cells = <0x2>;
1919
1920                         interrupt-controller;
1921                         #interrupt-cells = <0x2>;
1922                 };
1923
1924                 gpio4: gpio4@ff790000 {
1925                         compatible = "rockchip,gpio-bank";
1926                         reg = <0x0 0xff790000 0x0 0x100>;
1927                         clocks = <&cru PCLK_GPIO4>;
1928                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1929
1930                         gpio-controller;
1931                         #gpio-cells = <0x2>;
1932
1933                         interrupt-controller;
1934                         #interrupt-cells = <0x2>;
1935                 };
1936
1937                 pcfg_pull_up: pcfg-pull-up {
1938                         bias-pull-up;
1939                 };
1940
1941                 pcfg_pull_down: pcfg-pull-down {
1942                         bias-pull-down;
1943                 };
1944
1945                 pcfg_pull_none: pcfg-pull-none {
1946                         bias-disable;
1947                 };
1948
1949                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1950                         bias-pull-up;
1951                         drive-strength = <20>;
1952                 };
1953
1954                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1955                         bias-disable;
1956                         drive-strength = <20>;
1957                 };
1958
1959                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1960                         bias-disable;
1961                         drive-strength = <18>;
1962                 };
1963
1964                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1965                         bias-disable;
1966                         drive-strength = <12>;
1967                 };
1968
1969                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1970                         bias-pull-up;
1971                         drive-strength = <8>;
1972                 };
1973
1974                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1975                         bias-pull-down;
1976                         drive-strength = <4>;
1977                 };
1978
1979                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1980                         bias-pull-up;
1981                         drive-strength = <2>;
1982                 };
1983
1984                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1985                         bias-pull-down;
1986                         drive-strength = <12>;
1987                 };
1988
1989                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1990                         bias-disable;
1991                         drive-strength = <13>;
1992                 };
1993
1994                 pcfg_output_high: pcfg-output-high {
1995                         output-high;
1996                 };
1997
1998                 pcfg_output_low: pcfg-output-low {
1999                         output-low;
2000                 };
2001
2002                 pcfg_input: pcfg-input {
2003                         input-enable;
2004                 };
2005
2006                 emmc {
2007                         emmc_pwr: emmc-pwr {
2008                                 rockchip,pins =
2009                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2010                         };
2011                 };
2012
2013                 gmac {
2014                         rgmii_pins: rgmii-pins {
2015                                 rockchip,pins =
2016                                         /* mac_txclk */
2017                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2018                                         /* mac_rxclk */
2019                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2020                                         /* mac_mdio */
2021                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2022                                         /* mac_txen */
2023                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2024                                         /* mac_clk */
2025                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2026                                         /* mac_rxdv */
2027                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2028                                         /* mac_mdc */
2029                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2030                                         /* mac_rxd1 */
2031                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2032                                         /* mac_rxd0 */
2033                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2034                                         /* mac_txd1 */
2035                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2036                                         /* mac_txd0 */
2037                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2038                                         /* mac_rxd3 */
2039                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2040                                         /* mac_rxd2 */
2041                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2042                                         /* mac_txd3 */
2043                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2044                                         /* mac_txd2 */
2045                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2046                         };
2047
2048                         rmii_pins: rmii-pins {
2049                                 rockchip,pins =
2050                                         /* mac_mdio */
2051                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2052                                         /* mac_txen */
2053                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2054                                         /* mac_clk */
2055                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2056                                         /* mac_rxer */
2057                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2058                                         /* mac_rxdv */
2059                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2060                                         /* mac_mdc */
2061                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2062                                         /* mac_rxd1 */
2063                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2064                                         /* mac_rxd0 */
2065                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2066                                         /* mac_txd1 */
2067                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2068                                         /* mac_txd0 */
2069                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2070                         };
2071                 };
2072
2073                 i2c0 {
2074                         i2c0_xfer: i2c0-xfer {
2075                                 rockchip,pins =
2076                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2077                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2078                         };
2079                 };
2080
2081                 i2c1 {
2082                         i2c1_xfer: i2c1-xfer {
2083                                 rockchip,pins =
2084                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2085                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2086                         };
2087                 };
2088
2089                 i2c2 {
2090                         i2c2_xfer: i2c2-xfer {
2091                                 rockchip,pins =
2092                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2093                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2094                         };
2095                 };
2096
2097                 i2c3 {
2098                         i2c3_xfer: i2c3-xfer {
2099                                 rockchip,pins =
2100                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2101                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2102                         };
2103
2104                         i2c3_gpio: i2c3_gpio {
2105                                 rockchip,pins =
2106                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2107                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2108                         };
2109
2110                 };
2111
2112                 i2c4 {
2113                         i2c4_xfer: i2c4-xfer {
2114                                 rockchip,pins =
2115                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2116                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2117                         };
2118                 };
2119
2120                 i2c5 {
2121                         i2c5_xfer: i2c5-xfer {
2122                                 rockchip,pins =
2123                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2124                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2125                         };
2126                 };
2127
2128                 i2c6 {
2129                         i2c6_xfer: i2c6-xfer {
2130                                 rockchip,pins =
2131                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2132                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2133                         };
2134                 };
2135
2136                 i2c7 {
2137                         i2c7_xfer: i2c7-xfer {
2138                                 rockchip,pins =
2139                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2140                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2141                         };
2142                 };
2143
2144                 i2c8 {
2145                         i2c8_xfer: i2c8-xfer {
2146                                 rockchip,pins =
2147                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2148                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2149                         };
2150                 };
2151
2152                 i2s0 {
2153                         i2s0_8ch_bus: i2s0-8ch-bus {
2154                                 rockchip,pins =
2155                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2156                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2157                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2158                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2159                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2160                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2161                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2162                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2163                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2164                         };
2165                 };
2166
2167                 i2s1 {
2168                         i2s1_2ch_bus: i2s1-2ch-bus {
2169                                 rockchip,pins =
2170                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2171                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2172                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2173                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2174                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2175                         };
2176                 };
2177
2178                 sdio0 {
2179                         sdio0_bus1: sdio0-bus1 {
2180                                 rockchip,pins =
2181                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2182                         };
2183
2184                         sdio0_bus4: sdio0-bus4 {
2185                                 rockchip,pins =
2186                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2187                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2188                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2189                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2190                         };
2191
2192                         sdio0_cmd: sdio0-cmd {
2193                                 rockchip,pins =
2194                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2195                         };
2196
2197                         sdio0_clk: sdio0-clk {
2198                                 rockchip,pins =
2199                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2200                         };
2201
2202                         sdio0_cd: sdio0-cd {
2203                                 rockchip,pins =
2204                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2205                         };
2206
2207                         sdio0_pwr: sdio0-pwr {
2208                                 rockchip,pins =
2209                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2210                         };
2211
2212                         sdio0_bkpwr: sdio0-bkpwr {
2213                                 rockchip,pins =
2214                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2215                         };
2216
2217                         sdio0_wp: sdio0-wp {
2218                                 rockchip,pins =
2219                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2220                         };
2221
2222                         sdio0_int: sdio0-int {
2223                                 rockchip,pins =
2224                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2225                         };
2226                 };
2227
2228                 sdmmc {
2229                         sdmmc_bus1: sdmmc-bus1 {
2230                                 rockchip,pins =
2231                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2232                         };
2233
2234                         sdmmc_bus4: sdmmc-bus4 {
2235                                 rockchip,pins =
2236                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2237                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2238                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2239                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2240                         };
2241
2242                         sdmmc_clk: sdmmc-clk {
2243                                 rockchip,pins =
2244                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2245                         };
2246
2247                         sdmmc_cmd: sdmmc-cmd {
2248                                 rockchip,pins =
2249                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2250                         };
2251
2252                         sdmmc_cd: sdmcc-cd {
2253                                 rockchip,pins =
2254                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2255                         };
2256
2257                         sdmmc_wp: sdmmc-wp {
2258                                 rockchip,pins =
2259                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2260                         };
2261                 };
2262
2263                 spdif {
2264                         spdif_bus: spdif-bus {
2265                                 rockchip,pins =
2266                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2267                         };
2268
2269                         spdif_bus_1: spdif-bus-1 {
2270                                 rockchip,pins =
2271                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2272                         };
2273                 };
2274
2275                 spi0 {
2276                         spi0_clk: spi0-clk {
2277                                 rockchip,pins =
2278                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2279                         };
2280                         spi0_cs0: spi0-cs0 {
2281                                 rockchip,pins =
2282                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2283                         };
2284                         spi0_cs1: spi0-cs1 {
2285                                 rockchip,pins =
2286                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2287                         };
2288                         spi0_tx: spi0-tx {
2289                                 rockchip,pins =
2290                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2291                         };
2292                         spi0_rx: spi0-rx {
2293                                 rockchip,pins =
2294                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2295                         };
2296                 };
2297
2298                 spi1 {
2299                         spi1_clk: spi1-clk {
2300                                 rockchip,pins =
2301                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2302                         };
2303                         spi1_cs0: spi1-cs0 {
2304                                 rockchip,pins =
2305                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2306                         };
2307                         spi1_rx: spi1-rx {
2308                                 rockchip,pins =
2309                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2310                         };
2311                         spi1_tx: spi1-tx {
2312                                 rockchip,pins =
2313                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2314                         };
2315                 };
2316
2317                 spi2 {
2318                         spi2_clk: spi2-clk {
2319                                 rockchip,pins =
2320                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2321                         };
2322                         spi2_cs0: spi2-cs0 {
2323                                 rockchip,pins =
2324                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2325                         };
2326                         spi2_rx: spi2-rx {
2327                                 rockchip,pins =
2328                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2329                         };
2330                         spi2_tx: spi2-tx {
2331                                 rockchip,pins =
2332                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2333                         };
2334                 };
2335
2336                 spi3 {
2337                         spi3_clk: spi3-clk {
2338                                 rockchip,pins =
2339                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2340                         };
2341                         spi3_cs0: spi3-cs0 {
2342                                 rockchip,pins =
2343                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2344                         };
2345                         spi3_rx: spi3-rx {
2346                                 rockchip,pins =
2347                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2348                         };
2349                         spi3_tx: spi3-tx {
2350                                 rockchip,pins =
2351                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2352                         };
2353                 };
2354
2355                 spi4 {
2356                         spi4_clk: spi4-clk {
2357                                 rockchip,pins =
2358                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2359                         };
2360                         spi4_cs0: spi4-cs0 {
2361                                 rockchip,pins =
2362                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2363                         };
2364                         spi4_rx: spi4-rx {
2365                                 rockchip,pins =
2366                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2367                         };
2368                         spi4_tx: spi4-tx {
2369                                 rockchip,pins =
2370                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2371                         };
2372                 };
2373
2374                 spi5 {
2375                         spi5_clk: spi5-clk {
2376                                 rockchip,pins =
2377                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2378                         };
2379                         spi5_cs0: spi5-cs0 {
2380                                 rockchip,pins =
2381                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2382                         };
2383                         spi5_rx: spi5-rx {
2384                                 rockchip,pins =
2385                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2386                         };
2387                         spi5_tx: spi5-tx {
2388                                 rockchip,pins =
2389                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2390                         };
2391                 };
2392
2393                 tsadc {
2394                         otp_gpio: otp-gpio {
2395                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2396                         };
2397
2398                         otp_out: otp-out {
2399                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2400                         };
2401                 };
2402
2403                 uart0 {
2404                         uart0_xfer: uart0-xfer {
2405                                 rockchip,pins =
2406                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2407                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2408                         };
2409
2410                         uart0_cts: uart0-cts {
2411                                 rockchip,pins =
2412                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2413                         };
2414
2415                         uart0_rts: uart0-rts {
2416                                 rockchip,pins =
2417                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2418                         };
2419                 };
2420
2421                 uart1 {
2422                         uart1_xfer: uart1-xfer {
2423                                 rockchip,pins =
2424                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2425                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2426                         };
2427                 };
2428
2429                 uart2a {
2430                         uart2a_xfer: uart2a-xfer {
2431                                 rockchip,pins =
2432                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2433                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2434                         };
2435                 };
2436
2437                 uart2b {
2438                         uart2b_xfer: uart2b-xfer {
2439                                 rockchip,pins =
2440                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2441                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2442                         };
2443                 };
2444
2445                 uart2c {
2446                         uart2c_xfer: uart2c-xfer {
2447                                 rockchip,pins =
2448                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2449                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2450                         };
2451                 };
2452
2453                 uart3 {
2454                         uart3_xfer: uart3-xfer {
2455                                 rockchip,pins =
2456                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2457                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2458                         };
2459
2460                         uart3_cts: uart3-cts {
2461                                 rockchip,pins =
2462                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2463                         };
2464
2465                         uart3_rts: uart3-rts {
2466                                 rockchip,pins =
2467                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2468                         };
2469                 };
2470
2471                 uart4 {
2472                         uart4_xfer: uart4-xfer {
2473                                 rockchip,pins =
2474                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2475                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2476                         };
2477                 };
2478
2479                 uarthdcp {
2480                         uarthdcp_xfer: uarthdcp-xfer {
2481                                 rockchip,pins =
2482                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2483                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2484                         };
2485                 };
2486
2487                 pwm0 {
2488                         pwm0_pin: pwm0-pin {
2489                                 rockchip,pins =
2490                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2491                         };
2492
2493                         vop0_pwm_pin: vop0-pwm-pin {
2494                                 rockchip,pins =
2495                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2496                         };
2497                 };
2498
2499                 pwm1 {
2500                         pwm1_pin: pwm1-pin {
2501                                 rockchip,pins =
2502                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2503                         };
2504
2505                         vop1_pwm_pin: vop1-pwm-pin {
2506                                 rockchip,pins =
2507                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2508                         };
2509                 };
2510
2511                 pwm2 {
2512                         pwm2_pin: pwm2-pin {
2513                                 rockchip,pins =
2514                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2515                         };
2516                 };
2517
2518                 pwm3a {
2519                         pwm3a_pin: pwm3a-pin {
2520                                 rockchip,pins =
2521                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2522                         };
2523                 };
2524
2525                 pwm3b {
2526                         pwm3b_pin: pwm3b-pin {
2527                                 rockchip,pins =
2528                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2529                         };
2530                 };
2531
2532                 edp {
2533                         edp_hpd: edp-hpd {
2534                                 rockchip,pins =
2535                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2536                         };
2537                 };
2538
2539                 hdmi {
2540                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2541                                 rockchip,pins =
2542                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2543                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2544                         };
2545
2546                         hdmi_cec: hdmi-cec {
2547                                 rockchip,pins =
2548                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2549                         };
2550                 };
2551
2552                 pcie {
2553                         pcie_clkreqn: pci-clkreqn {
2554                                 rockchip,pins =
2555                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2556                         };
2557
2558                         pcie_clkreqnb: pci-clkreqnb {
2559                                 rockchip,pins =
2560                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2561                         };
2562                 };
2563         };
2564 };