arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 131                 };
 132
 133                 cpu_l2: cpu@2 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x0 0x2>;
 137                         enable-method = "psci";
 138                         clocks = <&cru ARMCLKL>;
 139                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 140                 };
 141
 142                 cpu_l3: cpu@3 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a53", "arm,armv8";
 145                         reg = <0x0 0x3>;
 146                         enable-method = "psci";
 147                         clocks = <&cru ARMCLKL>;
 148                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 149                 };
 150
 151                 cpu_b0: cpu@100 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a72", "arm,armv8";
 154                         reg = <0x0 0x100>;
 155                         enable-method = "psci";
 156                         #cooling-cells = <2>; /* min followed by max */
 157                         dynamic-power-coefficient = <436>;
 158                         clocks = <&cru ARMCLKB>;
 159                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 160                 };
 161
 162                 cpu_b1: cpu@101 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a72", "arm,armv8";
 165                         reg = <0x0 0x101>;
 166                         enable-method = "psci";
 167                         clocks = <&cru ARMCLKB>;
 168                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 169                 };
 170
 171                 idle-states {
 172                         entry-method = "psci";
 173
 174                         CPU_SLEEP: cpu-sleep {
 175                                 compatible = "arm,idle-state";
 176                                 local-timer-stop;
 177                                 arm,psci-suspend-param = <0x0010000>;
 178                                 entry-latency-us = <120>;
 179                                 exit-latency-us = <250>;
 180                                 min-residency-us = <900>;
 181                         };
 182
 183                         CLUSTER_SLEEP: cluster-sleep {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x1010000>;
 187                                 entry-latency-us = <400>;
 188                                 exit-latency-us = <500>;
 189                                 min-residency-us = <2000>;
 190                         };
 191                 };
 192         };
 193
 194         cpu_avs: cpu-avs {
 195                 cluster0-avs {
 196                         cluster-id = <0>;
 197                         min-volt = <800000>; /* uV */
 198                         min-freq = <408000>; /* KHz */
 199                         leakage-adjust-volt = <
 200                         /*  mA        mA         uV */
 201                             0         254        0
 202                         >;
 203                         nvmem-cells = <&cpul_leakage>;
 204                         nvmem-cell-names = "cpu_leakage";
 205                 };
 206                 cluster1-avs {
 207                         cluster-id = <1>;
 208                         min-volt = <800000>; /* uV */
 209                         min-freq = <408000>; /* KHz */
 210                         leakage-adjust-volt = <
 211                         /*  mA        mA         uV */
 212                             0         254        0
 213                         >;
 214                         nvmem-cells = <&cpub_leakage>;
 215                         nvmem-cell-names = "cpu_leakage";
 216                 };
 217         };
 218
 219         timer {
 220                 compatible = "arm,armv8-timer";
 221                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 222                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 223                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 224                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 225         };
 226
 227         pmu_a53 {
 228                 compatible = "arm,cortex-a53-pmu";
 229                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 230         };
 231
 232         pmu_a72 {
 233                 compatible = "arm,cortex-a72-pmu";
 234                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 235         };
 236
 237         xin24m: xin24m {
 238                 compatible = "fixed-clock";
 239                 #clock-cells = <0>;
 240                 clock-frequency = <24000000>;
 241                 clock-output-names = "xin24m";
 242         };
 243
 244         amba {
 245                 compatible = "arm,amba-bus";
 246                 #address-cells = <2>;
 247                 #size-cells = <2>;
 248                 ranges;
 249
 250                 dmac_bus: dma-controller@ff6d0000 {
 251                         compatible = "arm,pl330", "arm,primecell";
 252                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 253                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 254                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 255                         #dma-cells = <1>;
 256                         clocks = <&cru ACLK_DMAC0_PERILP>;
 257                         clock-names = "apb_pclk";
 258                         peripherals-req-type-burst;
 259                 };
 260
 261                 dmac_peri: dma-controller@ff6e0000 {
 262                         compatible = "arm,pl330", "arm,primecell";
 263                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 264                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 265                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 266                         #dma-cells = <1>;
 267                         clocks = <&cru ACLK_DMAC1_PERILP>;
 268                         clock-names = "apb_pclk";
 269                         peripherals-req-type-burst;
 270                 };
 271         };
 272
 273         gmac: eth@fe300000 {
 274                 compatible = "rockchip,rk3399-gmac";
 275                 reg = <0x0 0xfe300000 0x0 0x10000>;
 276                 rockchip,grf = <&grf>;
 277                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 278                 interrupt-names = "macirq";
 279                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 280                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 281                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 282                          <&cru PCLK_GMAC>;
 283                 clock-names = "stmmaceth", "mac_clk_rx",
 284                               "mac_clk_tx", "clk_mac_ref",
 285                               "clk_mac_refout", "aclk_mac",
 286                               "pclk_mac";
 287                 resets = <&cru SRST_A_GMAC>;
 288                 reset-names = "stmmaceth";
 289                 power-domains = <&power RK3399_PD_GMAC>;
 290                 status = "disabled";
 291         };
 292
 293         sdio0: dwmmc@fe310000 {
 294                 compatible = "rockchip,rk3399-dw-mshc",
 295                              "rockchip,rk3288-dw-mshc";
 296                 reg = <0x0 0xfe310000 0x0 0x4000>;
 297                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 298                 clock-freq-min-max = <400000 150000000>;
 299                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 300                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 301                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 302                 fifo-depth = <0x100>;
 303                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 304                 status = "disabled";
 305         };
 306
 307         sdmmc: dwmmc@fe320000 {
 308                 compatible = "rockchip,rk3399-dw-mshc",
 309                              "rockchip,rk3288-dw-mshc";
 310                 reg = <0x0 0xfe320000 0x0 0x4000>;
 311                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 312                 clock-freq-min-max = <400000 150000000>;
 313                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 314                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 315                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 316                 fifo-depth = <0x100>;
 317                 power-domains = <&power RK3399_PD_SD>;
 318                 status = "disabled";
 319         };
 320
 321         sdhci: sdhci@fe330000 {
 322                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 323                 reg = <0x0 0xfe330000 0x0 0x10000>;
 324                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 325                 arasan,soc-ctl-syscon = <&grf>;
 326                 assigned-clocks = <&cru SCLK_EMMC>;
 327                 assigned-clock-rates = <200000000>;
 328                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 329                 clock-names = "clk_xin", "clk_ahb";
 330                 clock-output-names = "emmc_cardclock";
 331                 #clock-cells = <0>;
 332                 phys = <&emmc_phy>;
 333                 phy-names = "phy_arasan";
 334                 power-domains = <&power RK3399_PD_EMMC>;
 335                 status = "disabled";
 336         };
 337
 338         usb_host0_ehci: usb@fe380000 {
 339                 compatible = "generic-ehci";
 340                 reg = <0x0 0xfe380000 0x0 0x20000>;
 341                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 343                          <&cru SCLK_USBPHY0_480M_SRC>;
 344                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 345                 phys = <&u2phy0_host>;
 346                 phy-names = "usb";
 347                 power-domains = <&power RK3399_PD_PERIHP>;
 348                 status = "disabled";
 349         };
 350
 351         usb_host0_ohci: usb@fe3a0000 {
 352                 compatible = "generic-ohci";
 353                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 354                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 355                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 356                          <&cru SCLK_USBPHY0_480M_SRC>;
 357                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 358                 phys = <&u2phy0_host>;
 359                 phy-names = "usb";
 360                 power-domains = <&power RK3399_PD_PERIHP>;
 361                 status = "disabled";
 362         };
 363
 364         usb_host1_ehci: usb@fe3c0000 {
 365                 compatible = "generic-ehci";
 366                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 367                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 368                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 369                          <&cru SCLK_USBPHY1_480M_SRC>;
 370                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 371                 phys = <&u2phy1_host>;
 372                 phy-names = "usb";
 373                 power-domains = <&power RK3399_PD_PERIHP>;
 374                 status = "disabled";
 375         };
 376
 377         usb_host1_ohci: usb@fe3e0000 {
 378                 compatible = "generic-ohci";
 379                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 380                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 381                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 382                          <&cru SCLK_USBPHY1_480M_SRC>;
 383                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 384                 phys = <&u2phy1_host>;
 385                 phy-names = "usb";
 386                 power-domains = <&power RK3399_PD_PERIHP>;
 387                 status = "disabled";
 388         };
 389
 390         usbdrd3_0: usb@fe800000 {
 391                 compatible = "rockchip,rk3399-dwc3";
 392                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 393                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 394                 clock-names = "ref_clk", "suspend_clk",
 395                               "bus_clk", "grf_clk";
 396                 power-domains = <&power RK3399_PD_USB3>;
 397                 resets = <&cru SRST_A_USB3_OTG0>;
 398                 reset-names = "usb3-otg";
 399                 #address-cells = <2>;
 400                 #size-cells = <2>;
 401                 ranges;
 402                 status = "disabled";
 403                 usbdrd_dwc3_0: dwc3@fe800000 {
 404                         compatible = "snps,dwc3";
 405                         reg = <0x0 0xfe800000 0x0 0x100000>;
 406                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 407                         dr_mode = "otg";
 408                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 409                         phy-names = "usb2-phy", "usb3-phy";
 410                         phy_type = "utmi_wide";
 411                         snps,dis_enblslpm_quirk;
 412                         snps,dis-u2-freeclk-exists-quirk;
 413                         snps,dis_u2_susphy_quirk;
 414                         snps,dis-del-phy-power-chg-quirk;
 415                         snps,xhci-slow-suspend-quirk;
 416                         status = "disabled";
 417                 };
 418         };
 419
 420         usbdrd3_1: usb@fe900000 {
 421                 compatible = "rockchip,rk3399-dwc3";
 422                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 423                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 424                 clock-names = "ref_clk", "suspend_clk",
 425                               "bus_clk", "grf_clk";
 426                 power-domains = <&power RK3399_PD_USB3>;
 427                 resets = <&cru SRST_A_USB3_OTG1>;
 428                 reset-names = "usb3-otg";
 429                 #address-cells = <2>;
 430                 #size-cells = <2>;
 431                 ranges;
 432                 status = "disabled";
 433                 usbdrd_dwc3_1: dwc3@fe900000 {
 434                         compatible = "snps,dwc3";
 435                         reg = <0x0 0xfe900000 0x0 0x100000>;
 436                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 437                         dr_mode = "host";
 438                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 439                         phy-names = "usb2-phy", "usb3-phy";
 440                         phy_type = "utmi_wide";
 441                         snps,dis_enblslpm_quirk;
 442                         snps,dis-u2-freeclk-exists-quirk;
 443                         snps,dis_u2_susphy_quirk;
 444                         snps,dis-del-phy-power-chg-quirk;
 445                         snps,xhci-slow-suspend-quirk;
 446                         status = "disabled";
 447                 };
 448         };
 449
 450         gic: interrupt-controller@fee00000 {
 451                 compatible = "arm,gic-v3";
 452                 #interrupt-cells = <4>;
 453                 #address-cells = <2>;
 454                 #size-cells = <2>;
 455                 ranges;
 456                 interrupt-controller;
 457
 458                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 459                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 460                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 461                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 462                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 463                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 464                 its: interrupt-controller@fee20000 {
 465                         compatible = "arm,gic-v3-its";
 466                         msi-controller;
 467                         reg = <0x0 0xfee20000 0x0 0x20000>;
 468                 };
 469
 470                 ppi-partitions {
 471                         part0: interrupt-partition-0 {
 472                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 473                         };
 474
 475                         part1: interrupt-partition-1 {
 476                                 affinity = <&cpu_b0 &cpu_b1>;
 477                         };
 478                 };
 479         };
 480
 481         saradc: saradc@ff100000 {
 482                 compatible = "rockchip,rk3399-saradc";
 483                 reg = <0x0 0xff100000 0x0 0x100>;
 484                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 485                 #io-channel-cells = <1>;
 486                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 487                 clock-names = "saradc", "apb_pclk";
 488                 resets = <&cru SRST_P_SARADC>;
 489                 reset-names = "saradc-apb";
 490                 status = "disabled";
 491         };
 492
 493         i2c0: i2c@ff3c0000 {
 494                 compatible = "rockchip,rk3399-i2c";
 495                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 496                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 497                 clock-names = "i2c", "pclk";
 498                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c0_xfer>;
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 status = "disabled";
 504         };
 505
 506         i2c1: i2c@ff110000 {
 507                 compatible = "rockchip,rk3399-i2c";
 508                 reg = <0x0 0xff110000 0x0 0x1000>;
 509                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 510                 clock-names = "i2c", "pclk";
 511                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c1_xfer>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 status = "disabled";
 517         };
 518
 519         i2c2: i2c@ff120000 {
 520                 compatible = "rockchip,rk3399-i2c";
 521                 reg = <0x0 0xff120000 0x0 0x1000>;
 522                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 523                 clock-names = "i2c", "pclk";
 524                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&i2c2_xfer>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 status = "disabled";
 530         };
 531
 532         i2c3: i2c@ff130000 {
 533                 compatible = "rockchip,rk3399-i2c";
 534                 reg = <0x0 0xff130000 0x0 0x1000>;
 535                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 536                 clock-names = "i2c", "pclk";
 537                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2c3_xfer>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         i2c5: i2c@ff140000 {
 546                 compatible = "rockchip,rk3399-i2c";
 547                 reg = <0x0 0xff140000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 549                 clock-names = "i2c", "pclk";
 550                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c5_xfer>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         i2c6: i2c@ff150000 {
 559                 compatible = "rockchip,rk3399-i2c";
 560                 reg = <0x0 0xff150000 0x0 0x1000>;
 561                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 562                 clock-names = "i2c", "pclk";
 563                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&i2c6_xfer>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 status = "disabled";
 569         };
 570
 571         i2c7: i2c@ff160000 {
 572                 compatible = "rockchip,rk3399-i2c";
 573                 reg = <0x0 0xff160000 0x0 0x1000>;
 574                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 575                 clock-names = "i2c", "pclk";
 576                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&i2c7_xfer>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 status = "disabled";
 582         };
 583
 584         uart0: serial@ff180000 {
 585                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 586                 reg = <0x0 0xff180000 0x0 0x100>;
 587                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 588                 clock-names = "baudclk", "apb_pclk";
 589                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 590                 reg-shift = <2>;
 591                 reg-io-width = <4>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 594                 status = "disabled";
 595         };
 596
 597         uart1: serial@ff190000 {
 598                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 599                 reg = <0x0 0xff190000 0x0 0x100>;
 600                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 601                 clock-names = "baudclk", "apb_pclk";
 602                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 603                 reg-shift = <2>;
 604                 reg-io-width = <4>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&uart1_xfer>;
 607                 status = "disabled";
 608         };
 609
 610         uart2: serial@ff1a0000 {
 611                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 612                 reg = <0x0 0xff1a0000 0x0 0x100>;
 613                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 614                 clock-names = "baudclk", "apb_pclk";
 615                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 616                 reg-shift = <2>;
 617                 reg-io-width = <4>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&uart2c_xfer>;
 620                 status = "disabled";
 621         };
 622
 623         uart3: serial@ff1b0000 {
 624                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 625                 reg = <0x0 0xff1b0000 0x0 0x100>;
 626                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 627                 clock-names = "baudclk", "apb_pclk";
 628                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 629                 reg-shift = <2>;
 630                 reg-io-width = <4>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 633                 status = "disabled";
 634         };
 635
 636         spi0: spi@ff1c0000 {
 637                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 638                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 639                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 640                 clock-names = "spiclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         spi1: spi@ff1d0000 {
 650                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 651                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 652                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 653                 clock-names = "spiclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 status = "disabled";
 660         };
 661
 662         spi2: spi@ff1e0000 {
 663                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 664                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 665                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 666                 clock-names = "spiclk", "apb_pclk";
 667                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 status = "disabled";
 673         };
 674
 675         spi4: spi@ff1f0000 {
 676                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 677                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 678                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 679                 clock-names = "spiclk", "apb_pclk";
 680                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 681                 pinctrl-names = "default";
 682                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 status = "disabled";
 686         };
 687
 688         spi5: spi@ff200000 {
 689                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 690                 reg = <0x0 0xff200000 0x0 0x1000>;
 691                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 692                 clock-names = "spiclk", "apb_pclk";
 693                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 694                 pinctrl-names = "default";
 695                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 696                 #address-cells = <1>;
 697                 #size-cells = <0>;
 698                 status = "disabled";
 699         };
 700
 701         thermal-zones {
 702                 soc_thermal: soc-thermal {
 703                         polling-delay-passive = <20>; /* milliseconds */
 704                         polling-delay = <1000>; /* milliseconds */
 705                         sustainable-power = <1000>; /* milliwatts */
 706
 707                         thermal-sensors = <&tsadc 0>;
 708
 709                         trips {
 710                                 threshold: trip-point@0 {
 711                                         temperature = <70000>; /* millicelsius */
 712                                         hysteresis = <2000>; /* millicelsius */
 713                                         type = "passive";
 714                                 };
 715                                 target: trip-point@1 {
 716                                         temperature = <85000>; /* millicelsius */
 717                                         hysteresis = <2000>; /* millicelsius */
 718                                         type = "passive";
 719                                 };
 720                                 soc_crit: soc-crit {
 721                                         temperature = <95000>; /* millicelsius */
 722                                         hysteresis = <2000>; /* millicelsius */
 723                                         type = "critical";
 724                                 };
 725                         };
 726
 727                         cooling-maps {
 728                                 map0 {
 729                                         trip = <&target>;
 730                                         cooling-device =
 731                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 732                                         contribution = <4096>;
 733                                 };
 734                                 map1 {
 735                                         trip = <&target>;
 736                                         cooling-device =
 737                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 738                                         contribution = <1024>;
 739                                 };
 740                                 map2 {
 741                                         trip = <&target>;
 742                                         cooling-device =
 743                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 744                                         contribution = <4096>;
 745                                 };
 746                         };
 747                 };
 748
 749                 gpu_thermal: gpu-thermal {
 750                         polling-delay-passive = <100>; /* milliseconds */
 751                         polling-delay = <1000>; /* milliseconds */
 752
 753                         thermal-sensors = <&tsadc 1>;
 754                 };
 755         };
 756
 757         tsadc: tsadc@ff260000 {
 758                 compatible = "rockchip,rk3399-tsadc";
 759                 reg = <0x0 0xff260000 0x0 0x100>;
 760                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 761                 rockchip,grf = <&grf>;
 762                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 763                 clock-names = "tsadc", "apb_pclk";
 764                 assigned-clocks = <&cru SCLK_TSADC>;
 765                 assigned-clock-rates = <750000>;
 766                 resets = <&cru SRST_TSADC>;
 767                 reset-names = "tsadc-apb";
 768                 pinctrl-names = "init", "default", "sleep";
 769                 pinctrl-0 = <&otp_gpio>;
 770                 pinctrl-1 = <&otp_out>;
 771                 pinctrl-2 = <&otp_gpio>;
 772                 #thermal-sensor-cells = <1>;
 773                 rockchip,hw-tshut-temp = <95000>;
 774                 status = "disabled";
 775         };
 776
 777         qos_emmc: qos@ffa58000 {
 778                 compatible = "syscon";
 779                 reg = <0x0 0xffa58000 0x0 0x20>;
 780         };
 781
 782         qos_gmac: qos@ffa5c000 {
 783                 compatible = "syscon";
 784                 reg = <0x0 0xffa5c000 0x0 0x20>;
 785         };
 786
 787         qos_pcie: qos@ffa60080 {
 788                 compatible = "syscon";
 789                 reg = <0x0 0xffa60080 0x0 0x20>;
 790         };
 791
 792         qos_usb_host0: qos@ffa60100 {
 793                 compatible = "syscon";
 794                 reg = <0x0 0xffa60100 0x0 0x20>;
 795         };
 796
 797         qos_usb_host1: qos@ffa60180 {
 798                 compatible = "syscon";
 799                 reg = <0x0 0xffa60180 0x0 0x20>;
 800         };
 801
 802         qos_usb_otg0: qos@ffa70000 {
 803                 compatible = "syscon";
 804                 reg = <0x0 0xffa70000 0x0 0x20>;
 805         };
 806
 807         qos_usb_otg1: qos@ffa70080 {
 808                 compatible = "syscon";
 809                 reg = <0x0 0xffa70080 0x0 0x20>;
 810         };
 811
 812         qos_sd: qos@ffa74000 {
 813                 compatible = "syscon";
 814                 reg = <0x0 0xffa74000 0x0 0x20>;
 815         };
 816
 817         qos_sdioaudio: qos@ffa76000 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffa76000 0x0 0x20>;
 820         };
 821
 822         qos_hdcp: qos@ffa90000 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffa90000 0x0 0x20>;
 825         };
 826
 827         qos_iep: qos@ffa98000 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffa98000 0x0 0x20>;
 830         };
 831
 832         qos_isp0_m0: qos@ffaa0000 {
 833                 compatible = "syscon";
 834                 reg = <0x0 0xffaa0000 0x0 0x20>;
 835         };
 836
 837         qos_isp0_m1: qos@ffaa0080 {
 838                 compatible = "syscon";
 839                 reg = <0x0 0xffaa0080 0x0 0x20>;
 840         };
 841
 842         qos_isp1_m0: qos@ffaa8000 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffaa8000 0x0 0x20>;
 845         };
 846
 847         qos_isp1_m1: qos@ffaa8080 {
 848                 compatible = "syscon";
 849                 reg = <0x0 0xffaa8080 0x0 0x20>;
 850         };
 851
 852         qos_rga_r: qos@ffab0000 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffab0000 0x0 0x20>;
 855         };
 856
 857         qos_rga_w: qos@ffab0080 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffab0080 0x0 0x20>;
 860         };
 861
 862         qos_video_m0: qos@ffab8000 {
 863                 compatible = "syscon";
 864                 reg = <0x0 0xffab8000 0x0 0x20>;
 865         };
 866
 867         qos_video_m1_r: qos@ffac0000 {
 868                 compatible = "syscon";
 869                 reg = <0x0 0xffac0000 0x0 0x20>;
 870         };
 871
 872         qos_video_m1_w: qos@ffac0080 {
 873                 compatible = "syscon";
 874                 reg = <0x0 0xffac0080 0x0 0x20>;
 875         };
 876
 877         qos_vop_big_r: qos@ffac8000 {
 878                 compatible = "syscon";
 879                 reg = <0x0 0xffac8000 0x0 0x20>;
 880         };
 881
 882         qos_vop_big_w: qos@ffac8080 {
 883                 compatible = "syscon";
 884                 reg = <0x0 0xffac8080 0x0 0x20>;
 885         };
 886
 887         qos_vop_little: qos@ffad0000 {
 888                 compatible = "syscon";
 889                 reg = <0x0 0xffad0000 0x0 0x20>;
 890         };
 891
 892         qos_perihp: qos@ffad8080 {
 893                 compatible = "syscon";
 894                 reg = <0x0 0xffad8080 0x0 0x20>;
 895         };
 896
 897         qos_gpu: qos@ffae0000 {
 898                 compatible = "syscon";
 899                 reg = <0x0 0xffae0000 0x0 0x20>;
 900         };
 901
 902         pmu: power-management@ff310000 {
 903                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 904                 reg = <0x0 0xff310000 0x0 0x1000>;
 905
 906                 /*
 907                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 908                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 909                  * Some of the power domains are grouped together for every
 910                  * voltage domain.
 911                  * The detail contents as below.
 912                  */
 913                 power: power-controller {
 914                         compatible = "rockchip,rk3399-power-controller";
 915                         #power-domain-cells = <1>;
 916                         #address-cells = <1>;
 917                         #size-cells = <0>;
 918
 919                         /* These power domains are grouped by VD_CENTER */
 920                         pd_iep@RK3399_PD_IEP {
 921                                 reg = <RK3399_PD_IEP>;
 922                                 clocks = <&cru ACLK_IEP>,
 923                                          <&cru HCLK_IEP>;
 924                                 pm_qos = <&qos_iep>;
 925                         };
 926                         pd_rga@RK3399_PD_RGA {
 927                                 reg = <RK3399_PD_RGA>;
 928                                 clocks = <&cru ACLK_RGA>,
 929                                          <&cru HCLK_RGA>;
 930                                 pm_qos = <&qos_rga_r>,
 931                                          <&qos_rga_w>;
 932                         };
 933                         pd_vcodec@RK3399_PD_VCODEC {
 934                                 reg = <RK3399_PD_VCODEC>;
 935                                 clocks = <&cru ACLK_VCODEC>,
 936                                          <&cru HCLK_VCODEC>;
 937                                 pm_qos = <&qos_video_m0>;
 938                         };
 939                         pd_vdu@RK3399_PD_VDU {
 940                                 reg = <RK3399_PD_VDU>;
 941                                 clocks = <&cru ACLK_VDU>,
 942                                          <&cru HCLK_VDU>;
 943                                 pm_qos = <&qos_video_m1_r>,
 944                                          <&qos_video_m1_w>;
 945                         };
 946
 947                         /* These power domains are grouped by VD_GPU */
 948                         pd_gpu@RK3399_PD_GPU {
 949                                 reg = <RK3399_PD_GPU>;
 950                                 clocks = <&cru ACLK_GPU>;
 951                                 pm_qos = <&qos_gpu>;
 952                         };
 953
 954                         /* These power domains are grouped by VD_LOGIC */
 955                         pd_edp@RK3399_PD_EDP {
 956                                 reg = <RK3399_PD_EDP>;
 957                                 clocks = <&cru PCLK_EDP_CTRL>;
 958                         };
 959                         pd_emmc@RK3399_PD_EMMC {
 960                                 reg = <RK3399_PD_EMMC>;
 961                                 clocks = <&cru ACLK_EMMC>;
 962                                 pm_qos = <&qos_emmc>;
 963                         };
 964                         pd_gmac@RK3399_PD_GMAC {
 965                                 reg = <RK3399_PD_GMAC>;
 966                                 clocks = <&cru ACLK_GMAC>,
 967                                          <&cru PCLK_GMAC>;
 968                                 pm_qos = <&qos_gmac>;
 969                         };
 970                         pd_perihp@RK3399_PD_PERIHP {
 971                                 reg = <RK3399_PD_PERIHP>;
 972                                 #address-cells = <1>;
 973                                 #size-cells = <0>;
 974                                 clocks = <&cru ACLK_PERIHP>;
 975                                 pm_qos = <&qos_perihp>,
 976                                          <&qos_pcie>,
 977                                          <&qos_usb_host0>,
 978                                          <&qos_usb_host1>;
 979
 980                                 pd_sd@RK3399_PD_SD {
 981                                         reg = <RK3399_PD_SD>;
 982                                         clocks = <&cru HCLK_SDMMC>,
 983                                                  <&cru SCLK_SDMMC>;
 984                                         pm_qos = <&qos_sd>;
 985                                 };
 986                         };
 987                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
 988                                 reg = <RK3399_PD_SDIOAUDIO>;
 989                                 clocks = <&cru HCLK_SDIO>;
 990                                 pm_qos = <&qos_sdioaudio>;
 991                         };
 992                         pd_usb3@RK3399_PD_USB3 {
 993                                 reg = <RK3399_PD_USB3>;
 994                                 clocks = <&cru ACLK_USB3>;
 995                                 pm_qos = <&qos_usb_otg0>,
 996                                          <&qos_usb_otg1>;
 997                         };
 998                         pd_vio@RK3399_PD_VIO {
 999                                 reg = <RK3399_PD_VIO>;
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002
1003                                 pd_hdcp@RK3399_PD_HDCP {
1004                                         reg = <RK3399_PD_HDCP>;
1005                                         clocks = <&cru ACLK_HDCP>,
1006                                                  <&cru HCLK_HDCP>,
1007                                                  <&cru PCLK_HDCP>;
1008                                         pm_qos = <&qos_hdcp>;
1009                                 };
1010                                 pd_isp0@RK3399_PD_ISP0 {
1011                                         reg = <RK3399_PD_ISP0>;
1012                                         clocks = <&cru ACLK_ISP0>,
1013                                                  <&cru HCLK_ISP0>;
1014                                         pm_qos = <&qos_isp0_m0>,
1015                                                  <&qos_isp0_m1>;
1016                                 };
1017                                 pd_isp1@RK3399_PD_ISP1 {
1018                                         reg = <RK3399_PD_ISP1>;
1019                                         clocks = <&cru ACLK_ISP1>,
1020                                                  <&cru HCLK_ISP1>;
1021                                         pm_qos = <&qos_isp1_m0>,
1022                                                  <&qos_isp1_m1>;
1023                                 };
1024                                 pd_tcpc0@RK3399_PD_TCPC0 {
1025                                         reg = <RK3399_PD_TCPD0>;
1026                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1027                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1028                                 };
1029                                 pd_tcpc1@RK3399_PD_TCPC1 {
1030                                         reg = <RK3399_PD_TCPD1>;
1031                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1032                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1033                                 };
1034                                 pd_vo@RK3399_PD_VO {
1035                                         reg = <RK3399_PD_VO>;
1036                                         #address-cells = <1>;
1037                                         #size-cells = <0>;
1038
1039                                         pd_vopb@RK3399_PD_VOPB {
1040                                                 reg = <RK3399_PD_VOPB>;
1041                                                 clocks = <&cru ACLK_VOP0>,
1042                                                          <&cru HCLK_VOP0>;
1043                                                 pm_qos = <&qos_vop_big_r>,
1044                                                          <&qos_vop_big_w>;
1045                                         };
1046                                         pd_vopl@RK3399_PD_VOPL {
1047                                                 reg = <RK3399_PD_VOPL>;
1048                                                 clocks = <&cru ACLK_VOP1>,
1049                                                          <&cru HCLK_VOP1>;
1050                                                 pm_qos = <&qos_vop_little>;
1051                                         };
1052                                 };
1053                         };
1054                 };
1055         };
1056
1057         pmugrf: syscon@ff320000 {
1058                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1059                 reg = <0x0 0xff320000 0x0 0x1000>;
1060
1061                 reboot-mode {
1062                         compatible = "syscon-reboot-mode";
1063                         offset = <0x300>;
1064                         mode-bootloader = <BOOT_LOADER>;
1065                         mode-charge = <BOOT_CHARGING>;
1066                         mode-fastboot = <BOOT_FASTBOOT>;
1067                         mode-loader = <BOOT_LOADER>;
1068                         mode-normal = <BOOT_NORMAL>;
1069                         mode-recovery = <BOOT_RECOVERY>;
1070                         mode-ums = <BOOT_UMS>;
1071                 };
1072
1073                 pmu_pvtm: pmu-pvtm {
1074                         compatible = "rockchip,rk3399-pmu-pvtm";
1075                         clocks = <&pmucru SCLK_PVTM_PMU>;
1076                         clock-names = "pmu";
1077                         status = "disabled";
1078                 };
1079         };
1080
1081         spi3: spi@ff350000 {
1082                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1083                 reg = <0x0 0xff350000 0x0 0x1000>;
1084                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1085                 clock-names = "spiclk", "apb_pclk";
1086                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1087                 pinctrl-names = "default";
1088                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1089                 #address-cells = <1>;
1090                 #size-cells = <0>;
1091                 status = "disabled";
1092         };
1093
1094         uart4: serial@ff370000 {
1095                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1096                 reg = <0x0 0xff370000 0x0 0x100>;
1097                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1098                 clock-names = "baudclk", "apb_pclk";
1099                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1100                 reg-shift = <2>;
1101                 reg-io-width = <4>;
1102                 pinctrl-names = "default";
1103                 pinctrl-0 = <&uart4_xfer>;
1104                 status = "disabled";
1105         };
1106
1107         i2c4: i2c@ff3d0000 {
1108                 compatible = "rockchip,rk3399-i2c";
1109                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1110                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1111                 clock-names = "i2c", "pclk";
1112                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1113                 pinctrl-names = "default";
1114                 pinctrl-0 = <&i2c4_xfer>;
1115                 #address-cells = <1>;
1116                 #size-cells = <0>;
1117                 status = "disabled";
1118         };
1119
1120         i2c8: i2c@ff3e0000 {
1121                 compatible = "rockchip,rk3399-i2c";
1122                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1123                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1124                 clock-names = "i2c", "pclk";
1125                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1126                 pinctrl-names = "default";
1127                 pinctrl-0 = <&i2c8_xfer>;
1128                 #address-cells = <1>;
1129                 #size-cells = <0>;
1130                 status = "disabled";
1131         };
1132
1133         pcie_phy: phy@e220 {
1134                 compatible = "rockchip,rk3399-pcie-phy";
1135                 #phy-cells = <0>;
1136                 rockchip,grf = <&grf>;
1137                 clocks = <&cru SCLK_PCIEPHY_REF>;
1138                 clock-names = "refclk";
1139                 resets = <&cru SRST_PCIEPHY>;
1140                 reset-names = "phy";
1141                 status = "disabled";
1142         };
1143
1144         pcie0: pcie@f8000000 {
1145                 compatible = "rockchip,rk3399-pcie";
1146                 #address-cells = <3>;
1147                 #size-cells = <2>;
1148                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1149                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1150                 clock-names = "aclk", "aclk-perf",
1151                               "hclk", "pm";
1152                 bus-range = <0x0 0x1>;
1153                 msi-map = <0x0 &its 0x0 0x1000>;
1154                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1155                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1156                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1157                 interrupt-names = "sys", "legacy", "client";
1158                 #interrupt-cells = <1>;
1159                 interrupt-map-mask = <0 0 0 7>;
1160                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1161                                 <0 0 0 2 &pcie0_intc 1>,
1162                                 <0 0 0 3 &pcie0_intc 2>,
1163                                 <0 0 0 4 &pcie0_intc 3>;
1164                 phys = <&pcie_phy>;
1165                 phy-names = "pcie-phy";
1166                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1167                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1168                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1169                       <0x0 0xfd000000 0x0 0x1000000>;
1170                 reg-names = "axi-base", "apb-base";
1171                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1172                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1173                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1174                          <&cru SRST_A_PCIE>;
1175                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1176                               "pm", "pclk", "aclk";
1177                 status = "disabled";
1178                 pcie0_intc: interrupt-controller {
1179                         interrupt-controller;
1180                         #address-cells = <0>;
1181                         #interrupt-cells = <1>;
1182                 };
1183         };
1184
1185         pwm0: pwm@ff420000 {
1186                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1187                 reg = <0x0 0xff420000 0x0 0x10>;
1188                 #pwm-cells = <3>;
1189                 pinctrl-names = "default";
1190                 pinctrl-0 = <&pwm0_pin>;
1191                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1192                 clock-names = "pwm";
1193                 status = "disabled";
1194         };
1195
1196         pwm1: pwm@ff420010 {
1197                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1198                 reg = <0x0 0xff420010 0x0 0x10>;
1199                 #pwm-cells = <3>;
1200                 pinctrl-names = "default";
1201                 pinctrl-0 = <&pwm1_pin>;
1202                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1203                 clock-names = "pwm";
1204                 status = "disabled";
1205         };
1206
1207         pwm2: pwm@ff420020 {
1208                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1209                 reg = <0x0 0xff420020 0x0 0x10>;
1210                 #pwm-cells = <3>;
1211                 pinctrl-names = "default";
1212                 pinctrl-0 = <&pwm2_pin>;
1213                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1214                 clock-names = "pwm";
1215                 status = "disabled";
1216         };
1217
1218         pwm3: pwm@ff420030 {
1219                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1220                 reg = <0x0 0xff420030 0x0 0x10>;
1221                 #pwm-cells = <3>;
1222                 pinctrl-names = "default";
1223                 pinctrl-0 = <&pwm3a_pin>;
1224                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1225                 clock-names = "pwm";
1226                 status = "disabled";
1227         };
1228
1229         dfi: dfi@ff630000 {
1230                 reg = <0x00 0xff630000 0x00 0x4000>;
1231                 compatible = "rockchip,rk3399-dfi";
1232                 rockchip,pmu = <&pmugrf>;
1233                 clocks = <&cru PCLK_DDR_MON>;
1234                 clock-names = "pclk_ddr_mon";
1235                 status = "disabled";
1236         };
1237
1238         dmc: dmc {
1239                 compatible = "rockchip,rk3399-dmc";
1240                 devfreq-events = <&dfi>;
1241                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1242                 clocks = <&cru SCLK_DDRCLK>;
1243                 clock-names = "dmc_clk";
1244                 ddr_timing = <&ddr_timing>;
1245                 status = "disabled";
1246         };
1247
1248         rga: rga@ff680000 {
1249                 compatible = "rockchip,rk3399-rga";
1250                 reg = <0x0 0xff680000 0x0 0x10000>;
1251                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1252                 interrupt-names = "rga";
1253                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1254                 clock-names = "aclk", "hclk", "sclk";
1255                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1256                 reset-names = "core", "axi", "ahb";
1257                 power-domains = <&power RK3399_PD_RGA>;
1258                 status = "disabled";
1259         };
1260
1261         efuse0: efuse@ff690000 {
1262                 compatible = "rockchip,rk3399-efuse";
1263                 reg = <0x0 0xff690000 0x0 0x80>;
1264                 #address-cells = <1>;
1265                 #size-cells = <1>;
1266                 clocks = <&cru PCLK_EFUSE1024NS>;
1267                 clock-names = "pclk_efuse";
1268
1269                 /* Data cells */
1270                 cpul_leakage: cpul-leakage {
1271                         reg = <0x1a 0x1>;
1272                 };
1273                 cpub_leakage: cpub-leakage {
1274                         reg = <0x17 0x1>;
1275                 };
1276                 gpu_leakage: gpu-leakage {
1277                         reg = <0x18 0x1>;
1278                 };
1279                 center_leakage: center-leakage {
1280                         reg = <0x19 0x1>;
1281                 };
1282                 logic_leakage: logic-leakage {
1283                         reg = <0x1b 0x1>;
1284                 };
1285                 wafer_info: wafer-info {
1286                         reg = <0x1c 0x1>;
1287                 };
1288         };
1289
1290         pmucru: pmu-clock-controller@ff750000 {
1291                 compatible = "rockchip,rk3399-pmucru";
1292                 reg = <0x0 0xff750000 0x0 0x1000>;
1293                 #clock-cells = <1>;
1294                 #reset-cells = <1>;
1295                 assigned-clocks = <&pmucru PLL_PPLL>;
1296                 assigned-clock-rates = <676000000>;
1297         };
1298
1299         cru: clock-controller@ff760000 {
1300                 compatible = "rockchip,rk3399-cru";
1301                 reg = <0x0 0xff760000 0x0 0x1000>;
1302                 #clock-cells = <1>;
1303                 #reset-cells = <1>;
1304                 assigned-clocks =
1305                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1306                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1307                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1308                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1309                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1310                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1311                         <&cru PCLK_PERIHP>,
1312                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1313                         <&cru PCLK_PERILP0>,
1314                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1315                 assigned-clock-rates =
1316                          <400000000>,  <200000000>,
1317                          <400000000>,  <200000000>,
1318                          <816000000>, <816000000>,
1319                          <594000000>,  <800000000>,
1320                          <200000000>, <1000000000>,
1321                          <150000000>,   <75000000>,
1322                           <37500000>,
1323                          <100000000>,  <100000000>,
1324                           <50000000>,
1325                          <100000000>,   <50000000>;
1326         };
1327
1328         grf: syscon@ff770000 {
1329                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1330                 reg = <0x0 0xff770000 0x0 0x10000>;
1331                 #address-cells = <1>;
1332                 #size-cells = <1>;
1333
1334                 emmc_phy: phy@f780 {
1335                         compatible = "rockchip,rk3399-emmc-phy";
1336                         reg = <0xf780 0x24>;
1337                         clocks = <&sdhci>;
1338                         clock-names = "emmcclk";
1339                         #phy-cells = <0>;
1340                         status = "disabled";
1341                 };
1342
1343                 u2phy0: usb2-phy@e450 {
1344                         compatible = "rockchip,rk3399-usb2phy";
1345                         reg = <0xe450 0x10>;
1346                         clocks = <&cru SCLK_USB2PHY0_REF>;
1347                         clock-names = "phyclk";
1348                         #clock-cells = <0>;
1349                         clock-output-names = "clk_usbphy0_480m";
1350                         status = "disabled";
1351
1352                         u2phy0_otg: otg-port {
1353                                 #phy-cells = <0>;
1354                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1355                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1356                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1357                                 interrupt-names = "otg-bvalid", "otg-id",
1358                                                   "linestate";
1359                                 status = "disabled";
1360                         };
1361
1362                         u2phy0_host: host-port {
1363                                 #phy-cells = <0>;
1364                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1365                                 interrupt-names = "linestate";
1366                                 status = "disabled";
1367                         };
1368                 };
1369
1370                 u2phy1: usb2-phy@e460 {
1371                         compatible = "rockchip,rk3399-usb2phy";
1372                         reg = <0xe460 0x10>;
1373                         clocks = <&cru SCLK_USB2PHY1_REF>;
1374                         clock-names = "phyclk";
1375                         #clock-cells = <0>;
1376                         clock-output-names = "clk_usbphy1_480m";
1377                         status = "disabled";
1378
1379                         u2phy1_otg: otg-port {
1380                                 #phy-cells = <0>;
1381                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1382                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1383                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1384                                 interrupt-names = "otg-bvalid", "otg-id",
1385                                                   "linestate";
1386                                 status = "disabled";
1387                         };
1388
1389                         u2phy1_host: host-port {
1390                                 #phy-cells = <0>;
1391                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1392                                 interrupt-names = "linestate";
1393                                 status = "disabled";
1394                         };
1395                 };
1396
1397                 pvtm: pvtm {
1398                         compatible = "rockchip,rk3399-pvtm";
1399                         clocks = <&cru SCLK_PVTM_CORE_L>,
1400                                  <&cru SCLK_PVTM_CORE_B>,
1401                                  <&cru SCLK_PVTM_GPU>,
1402                                  <&cru SCLK_PVTM_DDR>;
1403                         clock-names = "core_l", "core_b", "gpu", "ddr";
1404                         status = "disabled";
1405                 };
1406         };
1407
1408         tcphy0: phy@ff7c0000 {
1409                 compatible = "rockchip,rk3399-typec-phy";
1410                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1411                 rockchip,grf = <&grf>;
1412                 #phy-cells = <1>;
1413                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1414                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1415                 clock-names = "tcpdcore", "tcpdphy-ref";
1416                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1417                 assigned-clock-rates = <50000000>;
1418                 power-domains = <&power RK3399_PD_TCPD0>;
1419                 resets = <&cru SRST_UPHY0>,
1420                          <&cru SRST_UPHY0_PIPE_L00>,
1421                          <&cru SRST_P_UPHY0_TCPHY>;
1422                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1423                 rockchip,typec-conn-dir = <0xe580 0 16>;
1424                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1425                 rockchip,usb3-host-disable = <0x2434 0 16>;
1426                 rockchip,usb3-host-port = <0x2434 12 28>;
1427                 rockchip,external-psm = <0xe588 14 30>;
1428                 rockchip,pipe-status = <0xe5c0 0 0>;
1429                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1430                 status = "disabled";
1431
1432                 tcphy0_dp: dp-port {
1433                         #phy-cells = <0>;
1434                 };
1435
1436                 tcphy0_usb3: usb3-port {
1437                         #phy-cells = <0>;
1438                 };
1439         };
1440
1441         tcphy1: phy@ff800000 {
1442                 compatible = "rockchip,rk3399-typec-phy";
1443                 reg = <0x0 0xff800000 0x0 0x40000>;
1444                 rockchip,grf = <&grf>;
1445                 #phy-cells = <1>;
1446                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1447                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1448                 clock-names = "tcpdcore", "tcpdphy-ref";
1449                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1450                 assigned-clock-rates = <50000000>;
1451                 power-domains = <&power RK3399_PD_TCPD1>;
1452                 resets = <&cru SRST_UPHY1>,
1453                          <&cru SRST_UPHY1_PIPE_L00>,
1454                          <&cru SRST_P_UPHY1_TCPHY>;
1455                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1456                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1457                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1458                 rockchip,usb3-host-disable = <0x2444 0 16>;
1459                 rockchip,usb3-host-port = <0x2444 12 28>;
1460                 rockchip,external-psm = <0xe594 14 30>;
1461                 rockchip,pipe-status = <0xe5c0 16 16>;
1462                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1463                 status = "disabled";
1464
1465                 tcphy1_dp: dp-port {
1466                         #phy-cells = <0>;
1467                 };
1468
1469                 tcphy1_usb3: usb3-port {
1470                         #phy-cells = <0>;
1471                 };
1472         };
1473
1474         watchdog@ff848000 {
1475                 compatible = "snps,dw-wdt";
1476                 reg = <0x0 0xff848000 0x0 0x100>;
1477                 clocks = <&cru PCLK_WDT>;
1478                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1479         };
1480
1481         rktimer: rktimer@ff850000 {
1482                 compatible = "rockchip,rk3399-timer";
1483                 reg = <0x0 0xff850000 0x0 0x1000>;
1484                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1485                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1486                 clock-names = "pclk", "timer";
1487         };
1488
1489         spdif: spdif@ff870000 {
1490                 compatible = "rockchip,rk3399-spdif";
1491                 reg = <0x0 0xff870000 0x0 0x1000>;
1492                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1493                 dmas = <&dmac_bus 7>;
1494                 dma-names = "tx";
1495                 clock-names = "mclk", "hclk";
1496                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1497                 pinctrl-names = "default";
1498                 pinctrl-0 = <&spdif_bus>;
1499                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1500                 status = "disabled";
1501         };
1502
1503         i2s0: i2s@ff880000 {
1504                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1505                 reg = <0x0 0xff880000 0x0 0x1000>;
1506                 rockchip,grf = <&grf>;
1507                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1508                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1509                 dma-names = "tx", "rx";
1510                 clock-names = "i2s_clk", "i2s_hclk";
1511                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1512                 pinctrl-names = "default";
1513                 pinctrl-0 = <&i2s0_8ch_bus>;
1514                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1515                 status = "disabled";
1516         };
1517
1518         i2s1: i2s@ff890000 {
1519                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1520                 reg = <0x0 0xff890000 0x0 0x1000>;
1521                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1522                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1523                 dma-names = "tx", "rx";
1524                 clock-names = "i2s_clk", "i2s_hclk";
1525                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1526                 pinctrl-names = "default";
1527                 pinctrl-0 = <&i2s1_2ch_bus>;
1528                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1529                 status = "disabled";
1530         };
1531
1532         i2s2: i2s@ff8a0000 {
1533                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1534                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1535                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1536                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1537                 dma-names = "tx", "rx";
1538                 clock-names = "i2s_clk", "i2s_hclk";
1539                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1540                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1541                 status = "disabled";
1542         };
1543
1544         gpu: gpu@ff9a0000 {
1545                 compatible = "arm,malit860",
1546                              "arm,malit86x",
1547                              "arm,malit8xx",
1548                              "arm,mali-midgard";
1549
1550                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1551
1552                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1553                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1554                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1555                 interrupt-names = "GPU", "JOB", "MMU";
1556
1557                 clocks = <&cru ACLK_GPU>;
1558                 clock-names = "clk_mali";
1559                 #cooling-cells = <2>; /* min followed by max */
1560                 power-domains = <&power RK3399_PD_GPU>;
1561                 power-off-delay-ms = <200>;
1562                 status = "disabled";
1563
1564                 gpu_power_model: power_model {
1565                         compatible = "arm,mali-simple-power-model";
1566                         voltage = <900>;
1567                         frequency = <500>;
1568                         static-power = <300>;
1569                         dynamic-power = <396>;
1570                         ts = <32000 4700 (-80) 2>;
1571                         thermal-zone = "gpu-thermal";
1572                 };
1573         };
1574
1575         vopl: vop@ff8f0000 {
1576                 compatible = "rockchip,rk3399-vop-lit";
1577                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1578                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1579                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1580                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1581                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1582                 reset-names = "axi", "ahb", "dclk";
1583                 power-domains = <&power RK3399_PD_VOPL>;
1584                 iommus = <&vopl_mmu>;
1585                 status = "disabled";
1586
1587                 vopl_out: port {
1588                         #address-cells = <1>;
1589                         #size-cells = <0>;
1590
1591                         vopl_out_mipi: endpoint@0 {
1592                                 reg = <0>;
1593                                 remote-endpoint = <&mipi_in_vopl>;
1594                         };
1595
1596                         vopl_out_edp: endpoint@1 {
1597                                 reg = <1>;
1598                                 remote-endpoint = <&edp_in_vopl>;
1599                         };
1600
1601                         vopl_out_hdmi: endpoint@2 {
1602                                 reg = <2>;
1603                                 remote-endpoint = <&hdmi_in_vopl>;
1604                         };
1605                 };
1606         };
1607
1608         vop1_pwm: voppwm@ff8f01a0 {
1609                 compatible = "rockchip,vop-pwm";
1610                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1611                 #pwm-cells = <3>;
1612                 pinctrl-names = "default";
1613                 pinctrl-0 = <&vop1_pwm_pin>;
1614                 clocks = <&cru SCLK_VOP1_PWM>;
1615                 clock-names = "pwm";
1616                 status = "disabled";
1617         };
1618
1619         vopl_mmu: iommu@ff8f3f00 {
1620                 compatible = "rockchip,iommu";
1621                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1622                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1623                 interrupt-names = "vopl_mmu";
1624                 #iommu-cells = <0>;
1625                 status = "disabled";
1626         };
1627
1628         vopb: vop@ff900000 {
1629                 compatible = "rockchip,rk3399-vop-big";
1630                 reg = <0x0 0xff900000 0x0 0x3efc>;
1631                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1632                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1633                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1634                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1635                 reset-names = "axi", "ahb", "dclk";
1636                 power-domains = <&power RK3399_PD_VOPB>;
1637                 iommus = <&vopb_mmu>;
1638                 status = "disabled";
1639
1640                 vopb_out: port {
1641                         #address-cells = <1>;
1642                         #size-cells = <0>;
1643
1644                         vopb_out_edp: endpoint@0 {
1645                                 reg = <0>;
1646                                 remote-endpoint = <&edp_in_vopb>;
1647                         };
1648
1649                         vopb_out_mipi: endpoint@1 {
1650                                 reg = <1>;
1651                                 remote-endpoint = <&mipi_in_vopb>;
1652                         };
1653
1654                         vopb_out_hdmi: endpoint@2 {
1655                                 reg = <2>;
1656                                 remote-endpoint = <&hdmi_in_vopb>;
1657                         };
1658                 };
1659         };
1660
1661         vop0_pwm: voppwm@ff9001a0 {
1662                 compatible = "rockchip,vop-pwm";
1663                 reg = <0x0 0xff9001a0 0x0 0x10>;
1664                 #pwm-cells = <3>;
1665                 pinctrl-names = "default";
1666                 pinctrl-0 = <&vop0_pwm_pin>;
1667                 clocks = <&cru SCLK_VOP0_PWM>;
1668                 clock-names = "pwm";
1669                 status = "disabled";
1670         };
1671
1672         vopb_mmu: iommu@ff903f00 {
1673                 compatible = "rockchip,iommu";
1674                 reg = <0x0 0xff903f00 0x0 0x100>;
1675                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1676                 interrupt-names = "vopb_mmu";
1677                 #iommu-cells = <0>;
1678                 status = "disabled";
1679         };
1680
1681         isp0_mmu: iommu@ff914000 {
1682                 compatible = "rockchip,iommu";
1683                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1684                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1685                 interrupt-names = "isp0_mmu";
1686                 #iommu-cells = <0>;
1687                 status = "disabled";
1688         };
1689
1690         isp1_mmu: iommu@ff924000 {
1691                 compatible = "rockchip,iommu";
1692                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1693                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1694                 interrupt-names = "isp1_mmu";
1695                 #iommu-cells = <0>;
1696                 status = "disabled";
1697         };
1698
1699         hdmi: hdmi@ff940000 {
1700                 compatible = "rockchip,rk3399-dw-hdmi";
1701                 reg = <0x0 0xff940000 0x0 0x20000>;
1702                 reg-io-width = <4>;
1703                 rockchip,grf = <&grf>;
1704                 power-domains = <&power RK3399_PD_HDCP>;
1705                 pinctrl-names = "default";
1706                 pinctrl-0 = <&hdmi_i2c_xfer>;
1707                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1708                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1709                 clock-names = "iahb", "isfr", "vpll", "grf";
1710                 status = "disabled";
1711
1712                 ports {
1713                         hdmi_in: port {
1714                                 #address-cells = <1>;
1715                                 #size-cells = <0>;
1716                                 hdmi_in_vopb: endpoint@0 {
1717                                         reg = <0>;
1718                                         remote-endpoint = <&vopb_out_hdmi>;
1719                                 };
1720                                 hdmi_in_vopl: endpoint@1 {
1721                                         reg = <1>;
1722                                         remote-endpoint = <&vopl_out_hdmi>;
1723                                 };
1724                         };
1725                 };
1726         };
1727
1728         mipi_dsi: mipi@ff960000 {
1729                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1730                 reg = <0x0 0xff960000 0x0 0x8000>;
1731                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1732                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1733                          <&cru SCLK_DPHY_TX0_CFG>;
1734                 clock-names = "ref", "pclk", "phy_cfg";
1735                 power-domains = <&power RK3399_PD_VIO>;
1736                 rockchip,grf = <&grf>;
1737                 #address-cells = <1>;
1738                 #size-cells = <0>;
1739                 status = "disabled";
1740
1741                 ports {
1742                         #address-cells = <1>;
1743                         #size-cells = <0>;
1744                         reg = <1>;
1745
1746                         mipi_in: port {
1747                                 #address-cells = <1>;
1748                                 #size-cells = <0>;
1749
1750                                 mipi_in_vopb: endpoint@0 {
1751                                         reg = <0>;
1752                                         remote-endpoint = <&vopb_out_mipi>;
1753                                 };
1754                                 mipi_in_vopl: endpoint@1 {
1755                                         reg = <1>;
1756                                         remote-endpoint = <&vopl_out_mipi>;
1757                                 };
1758                         };
1759                 };
1760         };
1761
1762         edp: edp@ff970000 {
1763                 compatible = "rockchip,rk3399-edp";
1764                 reg = <0x0 0xff970000 0x0 0x8000>;
1765                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1766                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1767                 clock-names = "dp", "pclk";
1768                 power-domains = <&power RK3399_PD_EDP>;
1769                 resets = <&cru SRST_P_EDP_CTRL>;
1770                 reset-names = "dp";
1771                 rockchip,grf = <&grf>;
1772                 status = "disabled";
1773                 pinctrl-names = "default";
1774                 pinctrl-0 = <&edp_hpd>;
1775
1776                 ports {
1777                         #address-cells = <1>;
1778                         #size-cells = <0>;
1779
1780                         edp_in: port@0 {
1781                                 reg = <0>;
1782                                 #address-cells = <1>;
1783                                 #size-cells = <0>;
1784
1785                                 edp_in_vopb: endpoint@0 {
1786                                         reg = <0>;
1787                                         remote-endpoint = <&vopb_out_edp>;
1788                                 };
1789
1790                                 edp_in_vopl: endpoint@1 {
1791                                         reg = <1>;
1792                                         remote-endpoint = <&vopl_out_edp>;
1793                                 };
1794                         };
1795                 };
1796         };
1797
1798         display_subsystem: display-subsystem {
1799                 compatible = "rockchip,display-subsystem";
1800                 ports = <&vopl_out>, <&vopb_out>;
1801                 status = "disabled";
1802         };
1803
1804         pinctrl: pinctrl {
1805                 compatible = "rockchip,rk3399-pinctrl";
1806                 rockchip,grf = <&grf>;
1807                 rockchip,pmu = <&pmugrf>;
1808                 #address-cells = <0x2>;
1809                 #size-cells = <0x2>;
1810                 ranges;
1811
1812                 gpio0: gpio0@ff720000 {
1813                         compatible = "rockchip,gpio-bank";
1814                         reg = <0x0 0xff720000 0x0 0x100>;
1815                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1816                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1817
1818                         gpio-controller;
1819                         #gpio-cells = <0x2>;
1820
1821                         interrupt-controller;
1822                         #interrupt-cells = <0x2>;
1823                 };
1824
1825                 gpio1: gpio1@ff730000 {
1826                         compatible = "rockchip,gpio-bank";
1827                         reg = <0x0 0xff730000 0x0 0x100>;
1828                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1829                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1830
1831                         gpio-controller;
1832                         #gpio-cells = <0x2>;
1833
1834                         interrupt-controller;
1835                         #interrupt-cells = <0x2>;
1836                 };
1837
1838                 gpio2: gpio2@ff780000 {
1839                         compatible = "rockchip,gpio-bank";
1840                         reg = <0x0 0xff780000 0x0 0x100>;
1841                         clocks = <&cru PCLK_GPIO2>;
1842                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1843
1844                         gpio-controller;
1845                         #gpio-cells = <0x2>;
1846
1847                         interrupt-controller;
1848                         #interrupt-cells = <0x2>;
1849                 };
1850
1851                 gpio3: gpio3@ff788000 {
1852                         compatible = "rockchip,gpio-bank";
1853                         reg = <0x0 0xff788000 0x0 0x100>;
1854                         clocks = <&cru PCLK_GPIO3>;
1855                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1856
1857                         gpio-controller;
1858                         #gpio-cells = <0x2>;
1859
1860                         interrupt-controller;
1861                         #interrupt-cells = <0x2>;
1862                 };
1863
1864                 gpio4: gpio4@ff790000 {
1865                         compatible = "rockchip,gpio-bank";
1866                         reg = <0x0 0xff790000 0x0 0x100>;
1867                         clocks = <&cru PCLK_GPIO4>;
1868                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1869
1870                         gpio-controller;
1871                         #gpio-cells = <0x2>;
1872
1873                         interrupt-controller;
1874                         #interrupt-cells = <0x2>;
1875                 };
1876
1877                 pcfg_pull_up: pcfg-pull-up {
1878                         bias-pull-up;
1879                 };
1880
1881                 pcfg_pull_down: pcfg-pull-down {
1882                         bias-pull-down;
1883                 };
1884
1885                 pcfg_pull_none: pcfg-pull-none {
1886                         bias-disable;
1887                 };
1888
1889                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1890                         bias-pull-up;
1891                         drive-strength = <20>;
1892                 };
1893
1894                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1895                         bias-disable;
1896                         drive-strength = <20>;
1897                 };
1898
1899                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1900                         bias-disable;
1901                         drive-strength = <18>;
1902                 };
1903
1904                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1905                         bias-disable;
1906                         drive-strength = <12>;
1907                 };
1908
1909                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1910                         bias-pull-up;
1911                         drive-strength = <8>;
1912                 };
1913
1914                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1915                         bias-pull-down;
1916                         drive-strength = <4>;
1917                 };
1918
1919                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1920                         bias-pull-up;
1921                         drive-strength = <2>;
1922                 };
1923
1924                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1925                         bias-pull-down;
1926                         drive-strength = <12>;
1927                 };
1928
1929                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1930                         bias-disable;
1931                         drive-strength = <13>;
1932                 };
1933
1934                 pcfg_output_high: pcfg-output-high {
1935                         output-high;
1936                 };
1937
1938                 pcfg_output_low: pcfg-output-low {
1939                         output-low;
1940                 };
1941
1942                 pcfg_input: pcfg-input {
1943                         input-enable;
1944                 };
1945
1946                 emmc {
1947                         emmc_pwr: emmc-pwr {
1948                                 rockchip,pins =
1949                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1950                         };
1951                 };
1952
1953                 gmac {
1954                         rgmii_pins: rgmii-pins {
1955                                 rockchip,pins =
1956                                         /* mac_txclk */
1957                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1958                                         /* mac_rxclk */
1959                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1960                                         /* mac_mdio */
1961                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1962                                         /* mac_txen */
1963                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1964                                         /* mac_clk */
1965                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1966                                         /* mac_rxdv */
1967                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1968                                         /* mac_mdc */
1969                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1970                                         /* mac_rxd1 */
1971                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1972                                         /* mac_rxd0 */
1973                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1974                                         /* mac_txd1 */
1975                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1976                                         /* mac_txd0 */
1977                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1978                                         /* mac_rxd3 */
1979                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1980                                         /* mac_rxd2 */
1981                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1982                                         /* mac_txd3 */
1983                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1984                                         /* mac_txd2 */
1985                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1986                         };
1987
1988                         rmii_pins: rmii-pins {
1989                                 rockchip,pins =
1990                                         /* mac_mdio */
1991                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1992                                         /* mac_txen */
1993                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1994                                         /* mac_clk */
1995                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1996                                         /* mac_rxer */
1997                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1998                                         /* mac_rxdv */
1999                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2000                                         /* mac_mdc */
2001                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2002                                         /* mac_rxd1 */
2003                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2004                                         /* mac_rxd0 */
2005                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2006                                         /* mac_txd1 */
2007                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2008                                         /* mac_txd0 */
2009                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2010                         };
2011                 };
2012
2013                 i2c0 {
2014                         i2c0_xfer: i2c0-xfer {
2015                                 rockchip,pins =
2016                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2017                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2018                         };
2019                 };
2020
2021                 i2c1 {
2022                         i2c1_xfer: i2c1-xfer {
2023                                 rockchip,pins =
2024                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2025                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2026                         };
2027                 };
2028
2029                 i2c2 {
2030                         i2c2_xfer: i2c2-xfer {
2031                                 rockchip,pins =
2032                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2033                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2034                         };
2035                 };
2036
2037                 i2c3 {
2038                         i2c3_xfer: i2c3-xfer {
2039                                 rockchip,pins =
2040                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2041                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2042                         };
2043
2044                         i2c3_gpio: i2c3_gpio {
2045                                 rockchip,pins =
2046                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2047                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2048                         };
2049
2050                 };
2051
2052                 i2c4 {
2053                         i2c4_xfer: i2c4-xfer {
2054                                 rockchip,pins =
2055                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2056                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2057                         };
2058                 };
2059
2060                 i2c5 {
2061                         i2c5_xfer: i2c5-xfer {
2062                                 rockchip,pins =
2063                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2064                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2065                         };
2066                 };
2067
2068                 i2c6 {
2069                         i2c6_xfer: i2c6-xfer {
2070                                 rockchip,pins =
2071                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2072                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2073                         };
2074                 };
2075
2076                 i2c7 {
2077                         i2c7_xfer: i2c7-xfer {
2078                                 rockchip,pins =
2079                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2080                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2081                         };
2082                 };
2083
2084                 i2c8 {
2085                         i2c8_xfer: i2c8-xfer {
2086                                 rockchip,pins =
2087                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2088                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2089                         };
2090                 };
2091
2092                 i2s0 {
2093                         i2s0_8ch_bus: i2s0-8ch-bus {
2094                                 rockchip,pins =
2095                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2096                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2097                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2098                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2099                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2100                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2101                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2102                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2103                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2104                         };
2105                 };
2106
2107                 i2s1 {
2108                         i2s1_2ch_bus: i2s1-2ch-bus {
2109                                 rockchip,pins =
2110                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2111                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2112                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2113                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2114                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2115                         };
2116                 };
2117
2118                 sdio0 {
2119                         sdio0_bus1: sdio0-bus1 {
2120                                 rockchip,pins =
2121                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2122                         };
2123
2124                         sdio0_bus4: sdio0-bus4 {
2125                                 rockchip,pins =
2126                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2127                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2128                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2129                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2130                         };
2131
2132                         sdio0_cmd: sdio0-cmd {
2133                                 rockchip,pins =
2134                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2135                         };
2136
2137                         sdio0_clk: sdio0-clk {
2138                                 rockchip,pins =
2139                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2140                         };
2141
2142                         sdio0_cd: sdio0-cd {
2143                                 rockchip,pins =
2144                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2145                         };
2146
2147                         sdio0_pwr: sdio0-pwr {
2148                                 rockchip,pins =
2149                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2150                         };
2151
2152                         sdio0_bkpwr: sdio0-bkpwr {
2153                                 rockchip,pins =
2154                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2155                         };
2156
2157                         sdio0_wp: sdio0-wp {
2158                                 rockchip,pins =
2159                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2160                         };
2161
2162                         sdio0_int: sdio0-int {
2163                                 rockchip,pins =
2164                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2165                         };
2166                 };
2167
2168                 sdmmc {
2169                         sdmmc_bus1: sdmmc-bus1 {
2170                                 rockchip,pins =
2171                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2172                         };
2173
2174                         sdmmc_bus4: sdmmc-bus4 {
2175                                 rockchip,pins =
2176                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2177                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2178                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2179                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2180                         };
2181
2182                         sdmmc_clk: sdmmc-clk {
2183                                 rockchip,pins =
2184                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2185                         };
2186
2187                         sdmmc_cmd: sdmmc-cmd {
2188                                 rockchip,pins =
2189                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2190                         };
2191
2192                         sdmmc_cd: sdmcc-cd {
2193                                 rockchip,pins =
2194                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2195                         };
2196
2197                         sdmmc_wp: sdmmc-wp {
2198                                 rockchip,pins =
2199                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2200                         };
2201                 };
2202
2203                 spdif {
2204                         spdif_bus: spdif-bus {
2205                                 rockchip,pins =
2206                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2207                         };
2208
2209                         spdif_bus_1: spdif-bus-1 {
2210                                 rockchip,pins =
2211                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2212                         };
2213                 };
2214
2215                 spi0 {
2216                         spi0_clk: spi0-clk {
2217                                 rockchip,pins =
2218                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2219                         };
2220                         spi0_cs0: spi0-cs0 {
2221                                 rockchip,pins =
2222                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2223                         };
2224                         spi0_cs1: spi0-cs1 {
2225                                 rockchip,pins =
2226                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2227                         };
2228                         spi0_tx: spi0-tx {
2229                                 rockchip,pins =
2230                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2231                         };
2232                         spi0_rx: spi0-rx {
2233                                 rockchip,pins =
2234                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2235                         };
2236                 };
2237
2238                 spi1 {
2239                         spi1_clk: spi1-clk {
2240                                 rockchip,pins =
2241                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2242                         };
2243                         spi1_cs0: spi1-cs0 {
2244                                 rockchip,pins =
2245                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2246                         };
2247                         spi1_rx: spi1-rx {
2248                                 rockchip,pins =
2249                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2250                         };
2251                         spi1_tx: spi1-tx {
2252                                 rockchip,pins =
2253                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2254                         };
2255                 };
2256
2257                 spi2 {
2258                         spi2_clk: spi2-clk {
2259                                 rockchip,pins =
2260                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2261                         };
2262                         spi2_cs0: spi2-cs0 {
2263                                 rockchip,pins =
2264                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2265                         };
2266                         spi2_rx: spi2-rx {
2267                                 rockchip,pins =
2268                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2269                         };
2270                         spi2_tx: spi2-tx {
2271                                 rockchip,pins =
2272                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2273                         };
2274                 };
2275
2276                 spi3 {
2277                         spi3_clk: spi3-clk {
2278                                 rockchip,pins =
2279                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2280                         };
2281                         spi3_cs0: spi3-cs0 {
2282                                 rockchip,pins =
2283                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2284                         };
2285                         spi3_rx: spi3-rx {
2286                                 rockchip,pins =
2287                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2288                         };
2289                         spi3_tx: spi3-tx {
2290                                 rockchip,pins =
2291                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2292                         };
2293                 };
2294
2295                 spi4 {
2296                         spi4_clk: spi4-clk {
2297                                 rockchip,pins =
2298                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2299                         };
2300                         spi4_cs0: spi4-cs0 {
2301                                 rockchip,pins =
2302                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2303                         };
2304                         spi4_rx: spi4-rx {
2305                                 rockchip,pins =
2306                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2307                         };
2308                         spi4_tx: spi4-tx {
2309                                 rockchip,pins =
2310                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2311                         };
2312                 };
2313
2314                 spi5 {
2315                         spi5_clk: spi5-clk {
2316                                 rockchip,pins =
2317                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2318                         };
2319                         spi5_cs0: spi5-cs0 {
2320                                 rockchip,pins =
2321                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2322                         };
2323                         spi5_rx: spi5-rx {
2324                                 rockchip,pins =
2325                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2326                         };
2327                         spi5_tx: spi5-tx {
2328                                 rockchip,pins =
2329                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2330                         };
2331                 };
2332
2333                 tsadc {
2334                         otp_gpio: otp-gpio {
2335                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2336                         };
2337
2338                         otp_out: otp-out {
2339                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2340                         };
2341                 };
2342
2343                 uart0 {
2344                         uart0_xfer: uart0-xfer {
2345                                 rockchip,pins =
2346                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2347                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2348                         };
2349
2350                         uart0_cts: uart0-cts {
2351                                 rockchip,pins =
2352                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2353                         };
2354
2355                         uart0_rts: uart0-rts {
2356                                 rockchip,pins =
2357                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2358                         };
2359                 };
2360
2361                 uart1 {
2362                         uart1_xfer: uart1-xfer {
2363                                 rockchip,pins =
2364                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2365                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2366                         };
2367                 };
2368
2369                 uart2a {
2370                         uart2a_xfer: uart2a-xfer {
2371                                 rockchip,pins =
2372                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2373                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2374                         };
2375                 };
2376
2377                 uart2b {
2378                         uart2b_xfer: uart2b-xfer {
2379                                 rockchip,pins =
2380                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2381                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2382                         };
2383                 };
2384
2385                 uart2c {
2386                         uart2c_xfer: uart2c-xfer {
2387                                 rockchip,pins =
2388                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2389                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2390                         };
2391                 };
2392
2393                 uart3 {
2394                         uart3_xfer: uart3-xfer {
2395                                 rockchip,pins =
2396                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2397                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2398                         };
2399
2400                         uart3_cts: uart3-cts {
2401                                 rockchip,pins =
2402                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2403                         };
2404
2405                         uart3_rts: uart3-rts {
2406                                 rockchip,pins =
2407                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2408                         };
2409                 };
2410
2411                 uart4 {
2412                         uart4_xfer: uart4-xfer {
2413                                 rockchip,pins =
2414                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2415                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2416                         };
2417                 };
2418
2419                 uarthdcp {
2420                         uarthdcp_xfer: uarthdcp-xfer {
2421                                 rockchip,pins =
2422                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2423                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2424                         };
2425                 };
2426
2427                 pwm0 {
2428                         pwm0_pin: pwm0-pin {
2429                                 rockchip,pins =
2430                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2431                         };
2432
2433                         vop0_pwm_pin: vop0-pwm-pin {
2434                                 rockchip,pins =
2435                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2436                         };
2437                 };
2438
2439                 pwm1 {
2440                         pwm1_pin: pwm1-pin {
2441                                 rockchip,pins =
2442                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2443                         };
2444
2445                         vop1_pwm_pin: vop1-pwm-pin {
2446                                 rockchip,pins =
2447                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2448                         };
2449                 };
2450
2451                 pwm2 {
2452                         pwm2_pin: pwm2-pin {
2453                                 rockchip,pins =
2454                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2455                         };
2456                 };
2457
2458                 pwm3a {
2459                         pwm3a_pin: pwm3a-pin {
2460                                 rockchip,pins =
2461                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2462                         };
2463                 };
2464
2465                 pwm3b {
2466                         pwm3b_pin: pwm3b-pin {
2467                                 rockchip,pins =
2468                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2469                         };
2470                 };
2471
2472                 edp {
2473                         edp_hpd: edp-hpd {
2474                                 rockchip,pins =
2475                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2476                         };
2477                 };
2478
2479                 hdmi {
2480                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2481                                 rockchip,pins =
2482                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2483                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2484                         };
2485
2486                         hdmi_cec: hdmi-cec {
2487                                 rockchip,pins =
2488                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2489                         };
2490                 };
2491
2492                 pcie {
2493                         pcie_clkreqn: pci-clkreqn {
2494                                 rockchip,pins =
2495                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2496                         };
2497
2498                         pcie_clkreqnb: pci-clkreqnb {
2499                                 rockchip,pins =
2500                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2501                         };
2502                 };
2503         };
2504 };