arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/suspend/rockchip-rk3399.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52
  53 #include "rk3399-dram-default-timing.dtsi"
  54
  55 / {
  56         compatible = "rockchip,rk3399";
  57
  58         interrupt-parent = <&gic>;
  59         #address-cells = <2>;
  60         #size-cells = <2>;
  61
  62         aliases {
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 i2c6 = &i2c6;
  70                 i2c7 = &i2c7;
  71                 i2c8 = &i2c8;
  72                 serial0 = &uart0;
  73                 serial1 = &uart1;
  74                 serial2 = &uart2;
  75                 serial3 = &uart3;
  76                 serial4 = &uart4;
  77                 dsi0 = &dsi;
  78                 dsi1 = &dsi1;
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 120                 };
 121
 122                 cpu_l1: cpu@1 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x1>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 129                 };
 130
 131                 cpu_l2: cpu@2 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a53", "arm,armv8";
 134                         reg = <0x0 0x2>;
 135                         enable-method = "psci";
 136                         clocks = <&cru ARMCLKL>;
 137                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 138                 };
 139
 140                 cpu_l3: cpu@3 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a53", "arm,armv8";
 143                         reg = <0x0 0x3>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 147                 };
 148
 149                 cpu_b0: cpu@100 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a72", "arm,armv8";
 152                         reg = <0x0 0x100>;
 153                         enable-method = "psci";
 154                         #cooling-cells = <2>; /* min followed by max */
 155                         dynamic-power-coefficient = <436>;
 156                         clocks = <&cru ARMCLKB>;
 157                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 158                 };
 159
 160                 cpu_b1: cpu@101 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a72", "arm,armv8";
 163                         reg = <0x0 0x101>;
 164                         enable-method = "psci";
 165                         clocks = <&cru ARMCLKB>;
 166                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 167                 };
 168
 169                 idle-states {
 170                         entry-method = "psci";
 171
 172                         CPU_SLEEP: cpu-sleep {
 173                                 compatible = "arm,idle-state";
 174                                 local-timer-stop;
 175                                 arm,psci-suspend-param = <0x0010000>;
 176                                 entry-latency-us = <120>;
 177                                 exit-latency-us = <250>;
 178                                 min-residency-us = <900>;
 179                         };
 180
 181                         CLUSTER_SLEEP: cluster-sleep {
 182                                 compatible = "arm,idle-state";
 183                                 local-timer-stop;
 184                                 arm,psci-suspend-param = <0x1010000>;
 185                                 entry-latency-us = <400>;
 186                                 exit-latency-us = <500>;
 187                                 min-residency-us = <2000>;
 188                         };
 189                 };
 190         };
 191
 192         pmu_a53 {
 193                 compatible = "arm,cortex-a53-pmu";
 194                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 195         };
 196
 197         pmu_a72 {
 198                 compatible = "arm,cortex-a72-pmu";
 199                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 200         };
 201
 202         psci {
 203                 compatible = "arm,psci-1.0";
 204                 method = "smc";
 205         };
 206
 207         timer {
 208                 compatible = "arm,armv8-timer";
 209                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 210                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 211                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 212                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 213         };
 214
 215         xin24m: xin24m {
 216                 compatible = "fixed-clock";
 217                 clock-frequency = <24000000>;
 218                 clock-output-names = "xin24m";
 219                 #clock-cells = <0>;
 220         };
 221
 222         dummy_cpll: dummy_cpll {
 223                 compatible = "fixed-clock";
 224                 clock-frequency = <0>;
 225                 clock-output-names = "dummy_cpll";
 226                 #clock-cells = <0>;
 227         };
 228
 229         dummy_vpll: dummy_vpll {
 230                 compatible = "fixed-clock";
 231                 clock-frequency = <0>;
 232                 clock-output-names = "dummy_vpll";
 233                 #clock-cells = <0>;
 234         };
 235
 236         amba {
 237                 compatible = "arm,amba-bus";
 238                 #address-cells = <2>;
 239                 #size-cells = <2>;
 240                 ranges;
 241
 242                 dmac_bus: dma-controller@ff6d0000 {
 243                         compatible = "arm,pl330", "arm,primecell";
 244                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 245                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 246                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 247                         #dma-cells = <1>;
 248                         clocks = <&cru ACLK_DMAC0_PERILP>;
 249                         clock-names = "apb_pclk";
 250                         peripherals-req-type-burst;
 251                 };
 252
 253                 dmac_peri: dma-controller@ff6e0000 {
 254                         compatible = "arm,pl330", "arm,primecell";
 255                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 256                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 257                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 258                         #dma-cells = <1>;
 259                         clocks = <&cru ACLK_DMAC1_PERILP>;
 260                         clock-names = "apb_pclk";
 261                         peripherals-req-type-burst;
 262                 };
 263         };
 264
 265         gmac: ethernet@fe300000 {
 266                 compatible = "rockchip,rk3399-gmac";
 267                 reg = <0x0 0xfe300000 0x0 0x10000>;
 268                 rockchip,grf = <&grf>;
 269                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 270                 interrupt-names = "macirq";
 271                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 272                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 273                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 274                          <&cru PCLK_GMAC>;
 275                 clock-names = "stmmaceth", "mac_clk_rx",
 276                               "mac_clk_tx", "clk_mac_ref",
 277                               "clk_mac_refout", "aclk_mac",
 278                               "pclk_mac";
 279                 resets = <&cru SRST_A_GMAC>;
 280                 reset-names = "stmmaceth";
 281                 power-domains = <&power RK3399_PD_GMAC>;
 282                 status = "disabled";
 283         };
 284
 285         sdio0: dwmmc@fe310000 {
 286                 compatible = "rockchip,rk3399-dw-mshc",
 287                              "rockchip,rk3288-dw-mshc";
 288                 reg = <0x0 0xfe310000 0x0 0x4000>;
 289                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 290                 clock-freq-min-max = <400000 150000000>;
 291                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 292                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 293                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 294                 fifo-depth = <0x100>;
 295                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 296                 status = "disabled";
 297         };
 298
 299         sdmmc: dwmmc@fe320000 {
 300                 compatible = "rockchip,rk3399-dw-mshc",
 301                              "rockchip,rk3288-dw-mshc";
 302                 reg = <0x0 0xfe320000 0x0 0x4000>;
 303                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 304                 clock-freq-min-max = <400000 150000000>;
 305                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 306                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 307                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 308                 fifo-depth = <0x100>;
 309                 power-domains = <&power RK3399_PD_SD>;
 310                 status = "disabled";
 311         };
 312
 313         sdhci: sdhci@fe330000 {
 314                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 315                 reg = <0x0 0xfe330000 0x0 0x10000>;
 316                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 317                 arasan,soc-ctl-syscon = <&grf>;
 318                 assigned-clocks = <&cru SCLK_EMMC>;
 319                 assigned-clock-rates = <200000000>;
 320                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 321                 clock-names = "clk_xin", "clk_ahb";
 322                 clock-output-names = "emmc_cardclock";
 323                 #clock-cells = <0>;
 324                 phys = <&emmc_phy>;
 325                 phy-names = "phy_arasan";
 326                 power-domains = <&power RK3399_PD_EMMC>;
 327                 status = "disabled";
 328         };
 329
 330         usb_host0_ehci: usb@fe380000 {
 331                 compatible = "generic-ehci";
 332                 reg = <0x0 0xfe380000 0x0 0x20000>;
 333                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 334                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 335                          <&cru SCLK_USBPHY0_480M_SRC>;
 336                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 337                 phys = <&u2phy0_host>;
 338                 phy-names = "usb";
 339                 power-domains = <&power RK3399_PD_PERIHP>;
 340                 status = "disabled";
 341         };
 342
 343         usb_host0_ohci: usb@fe3a0000 {
 344                 compatible = "generic-ohci";
 345                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 346                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 347                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 348                          <&cru SCLK_USBPHY0_480M_SRC>;
 349                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 350                 phys = <&u2phy0_host>;
 351                 phy-names = "usb";
 352                 power-domains = <&power RK3399_PD_PERIHP>;
 353                 status = "disabled";
 354         };
 355
 356         usb_host1_ehci: usb@fe3c0000 {
 357                 compatible = "generic-ehci";
 358                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 359                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 360                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 361                          <&cru SCLK_USBPHY1_480M_SRC>;
 362                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 363                 phys = <&u2phy1_host>;
 364                 phy-names = "usb";
 365                 power-domains = <&power RK3399_PD_PERIHP>;
 366                 status = "disabled";
 367         };
 368
 369         usb_host1_ohci: usb@fe3e0000 {
 370                 compatible = "generic-ohci";
 371                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 372                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 373                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 374                          <&cru SCLK_USBPHY1_480M_SRC>;
 375                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 376                 phys = <&u2phy1_host>;
 377                 phy-names = "usb";
 378                 power-domains = <&power RK3399_PD_PERIHP>;
 379                 status = "disabled";
 380         };
 381
 382         usbdrd3_0: usb@fe800000 {
 383                 compatible = "rockchip,rk3399-dwc3";
 384                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 385                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 386                 clock-names = "ref_clk", "suspend_clk",
 387                               "bus_clk", "grf_clk";
 388                 power-domains = <&power RK3399_PD_USB3>;
 389                 resets = <&cru SRST_A_USB3_OTG0>;
 390                 reset-names = "usb3-otg";
 391                 #address-cells = <2>;
 392                 #size-cells = <2>;
 393                 ranges;
 394                 status = "disabled";
 395                 usbdrd_dwc3_0: dwc3@fe800000 {
 396                         compatible = "snps,dwc3";
 397                         reg = <0x0 0xfe800000 0x0 0x100000>;
 398                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 399                         dr_mode = "otg";
 400                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 401                         phy-names = "usb2-phy", "usb3-phy";
 402                         phy_type = "utmi_wide";
 403                         snps,dis_enblslpm_quirk;
 404                         snps,dis-u2-freeclk-exists-quirk;
 405                         snps,dis_u2_susphy_quirk;
 406                         snps,dis-del-phy-power-chg-quirk;
 407                         snps,tx-ipgap-linecheck-dis-quirk;
 408                         snps,xhci-slow-suspend-quirk;
 409                         snps,usb3-warm-reset-on-resume-quirk;
 410                         status = "disabled";
 411                 };
 412         };
 413
 414         usbdrd3_1: usb@fe900000 {
 415                 compatible = "rockchip,rk3399-dwc3";
 416                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 417                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 418                 clock-names = "ref_clk", "suspend_clk",
 419                               "bus_clk", "grf_clk";
 420                 power-domains = <&power RK3399_PD_USB3>;
 421                 resets = <&cru SRST_A_USB3_OTG1>;
 422                 reset-names = "usb3-otg";
 423                 #address-cells = <2>;
 424                 #size-cells = <2>;
 425                 ranges;
 426                 status = "disabled";
 427                 usbdrd_dwc3_1: dwc3@fe900000 {
 428                         compatible = "snps,dwc3";
 429                         reg = <0x0 0xfe900000 0x0 0x100000>;
 430                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 431                         dr_mode = "host";
 432                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 433                         phy-names = "usb2-phy", "usb3-phy";
 434                         phy_type = "utmi_wide";
 435                         snps,dis_enblslpm_quirk;
 436                         snps,dis-u2-freeclk-exists-quirk;
 437                         snps,dis_u2_susphy_quirk;
 438                         snps,dis-del-phy-power-chg-quirk;
 439                         snps,tx-ipgap-linecheck-dis-quirk;
 440                         snps,xhci-slow-suspend-quirk;
 441                         snps,usb3-warm-reset-on-resume-quirk;
 442                         status = "disabled";
 443                 };
 444         };
 445
 446         cdn_dp: dp@fec00000 {
 447                 compatible = "rockchip,rk3399-cdn-dp";
 448                 reg = <0x0 0xfec00000 0x0 0x100000>;
 449                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 450                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 451                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 452                 clock-names = "core-clk", "pclk", "spdif", "grf";
 453                 assigned-clocks = <&cru SCLK_DP_CORE>;
 454                 assigned-clock-rates = <100000000>;
 455                 power-domains = <&power RK3399_PD_HDCP>;
 456                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 457                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 458                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 459                 reset-names = "spdif", "dptx", "apb", "core";
 460                 rockchip,grf = <&grf>;
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 #sound-dai-cells = <1>;
 464                 status = "disabled";
 465
 466                 ports {
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469
 470                         dp_in: port {
 471                                 #address-cells = <1>;
 472                                 #size-cells = <0>;
 473                                 dp_in_vopb: endpoint@0 {
 474                                         reg = <0>;
 475                                         remote-endpoint = <&vopb_out_dp>;
 476                                 };
 477
 478                                 dp_in_vopl: endpoint@1 {
 479                                         reg = <1>;
 480                                         remote-endpoint = <&vopl_out_dp>;
 481                                 };
 482                         };
 483                 };
 484         };
 485
 486         gic: interrupt-controller@fee00000 {
 487                 compatible = "arm,gic-v3";
 488                 #interrupt-cells = <4>;
 489                 #address-cells = <2>;
 490                 #size-cells = <2>;
 491                 ranges;
 492                 interrupt-controller;
 493
 494                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 495                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 496                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 497                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 498                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 499                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 500                 its: interrupt-controller@fee20000 {
 501                         compatible = "arm,gic-v3-its";
 502                         msi-controller;
 503                         reg = <0x0 0xfee20000 0x0 0x20000>;
 504                 };
 505
 506                 ppi-partitions {
 507                         ppi_cluster0: interrupt-partition-0 {
 508                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 509                         };
 510
 511                         ppi_cluster1: interrupt-partition-1 {
 512                                 affinity = <&cpu_b0 &cpu_b1>;
 513                         };
 514                 };
 515         };
 516
 517         saradc: saradc@ff100000 {
 518                 compatible = "rockchip,rk3399-saradc";
 519                 reg = <0x0 0xff100000 0x0 0x100>;
 520                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 521                 #io-channel-cells = <1>;
 522                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 523                 clock-names = "saradc", "apb_pclk";
 524                 resets = <&cru SRST_P_SARADC>;
 525                 reset-names = "saradc-apb";
 526                 status = "disabled";
 527         };
 528
 529         i2c0: i2c@ff3c0000 {
 530                 compatible = "rockchip,rk3399-i2c";
 531                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 532                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 533                 clock-names = "i2c", "pclk";
 534                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&i2c0_xfer>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         i2c1: i2c@ff110000 {
 543                 compatible = "rockchip,rk3399-i2c";
 544                 reg = <0x0 0xff110000 0x0 0x1000>;
 545                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 546                 clock-names = "i2c", "pclk";
 547                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&i2c1_xfer>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         i2c2: i2c@ff120000 {
 556                 compatible = "rockchip,rk3399-i2c";
 557                 reg = <0x0 0xff120000 0x0 0x1000>;
 558                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 559                 clock-names = "i2c", "pclk";
 560                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c2_xfer>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         i2c3: i2c@ff130000 {
 569                 compatible = "rockchip,rk3399-i2c";
 570                 reg = <0x0 0xff130000 0x0 0x1000>;
 571                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 572                 clock-names = "i2c", "pclk";
 573                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c3_xfer>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 status = "disabled";
 579         };
 580
 581         i2c5: i2c@ff140000 {
 582                 compatible = "rockchip,rk3399-i2c";
 583                 reg = <0x0 0xff140000 0x0 0x1000>;
 584                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 585                 clock-names = "i2c", "pclk";
 586                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c5_xfer>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 status = "disabled";
 592         };
 593
 594         i2c6: i2c@ff150000 {
 595                 compatible = "rockchip,rk3399-i2c";
 596                 reg = <0x0 0xff150000 0x0 0x1000>;
 597                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 598                 clock-names = "i2c", "pclk";
 599                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&i2c6_xfer>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 status = "disabled";
 605         };
 606
 607         i2c7: i2c@ff160000 {
 608                 compatible = "rockchip,rk3399-i2c";
 609                 reg = <0x0 0xff160000 0x0 0x1000>;
 610                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 611                 clock-names = "i2c", "pclk";
 612                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&i2c7_xfer>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 status = "disabled";
 618         };
 619
 620         uart0: serial@ff180000 {
 621                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 622                 reg = <0x0 0xff180000 0x0 0x100>;
 623                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 624                 clock-names = "baudclk", "apb_pclk";
 625                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 626                 reg-shift = <2>;
 627                 reg-io-width = <4>;
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 630                 status = "disabled";
 631         };
 632
 633         uart1: serial@ff190000 {
 634                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 635                 reg = <0x0 0xff190000 0x0 0x100>;
 636                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 637                 clock-names = "baudclk", "apb_pclk";
 638                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 639                 reg-shift = <2>;
 640                 reg-io-width = <4>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&uart1_xfer>;
 643                 status = "disabled";
 644         };
 645
 646         uart2: serial@ff1a0000 {
 647                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 648                 reg = <0x0 0xff1a0000 0x0 0x100>;
 649                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 650                 clock-names = "baudclk", "apb_pclk";
 651                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 652                 reg-shift = <2>;
 653                 reg-io-width = <4>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&uart2c_xfer>;
 656                 status = "disabled";
 657         };
 658
 659         uart3: serial@ff1b0000 {
 660                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 661                 reg = <0x0 0xff1b0000 0x0 0x100>;
 662                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 663                 clock-names = "baudclk", "apb_pclk";
 664                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 665                 reg-shift = <2>;
 666                 reg-io-width = <4>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 669                 status = "disabled";
 670         };
 671
 672         spi0: spi@ff1c0000 {
 673                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 674                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 675                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 676                 clock-names = "spiclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 status = "disabled";
 683         };
 684
 685         spi1: spi@ff1d0000 {
 686                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 687                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 688                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 689                 clock-names = "spiclk", "apb_pclk";
 690                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 693                 #address-cells = <1>;
 694                 #size-cells = <0>;
 695                 status = "disabled";
 696         };
 697
 698         spi2: spi@ff1e0000 {
 699                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 700                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 701                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 702                 clock-names = "spiclk", "apb_pclk";
 703                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 706                 #address-cells = <1>;
 707                 #size-cells = <0>;
 708                 status = "disabled";
 709         };
 710
 711         spi4: spi@ff1f0000 {
 712                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 713                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 714                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 715                 clock-names = "spiclk", "apb_pclk";
 716                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 719                 #address-cells = <1>;
 720                 #size-cells = <0>;
 721                 status = "disabled";
 722         };
 723
 724         spi5: spi@ff200000 {
 725                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 726                 reg = <0x0 0xff200000 0x0 0x1000>;
 727                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 728                 clock-names = "spiclk", "apb_pclk";
 729                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 730                 pinctrl-names = "default";
 731                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 732                 #address-cells = <1>;
 733                 #size-cells = <0>;
 734                 status = "disabled";
 735         };
 736
 737         thermal_zones: thermal-zones {
 738                 soc_thermal: soc-thermal {
 739                         polling-delay-passive = <20>; /* milliseconds */
 740                         polling-delay = <1000>; /* milliseconds */
 741                         sustainable-power = <1000>; /* milliwatts */
 742
 743                         thermal-sensors = <&tsadc 0>;
 744
 745                         trips {
 746                                 threshold: trip-point@0 {
 747                                         temperature = <70000>; /* millicelsius */
 748                                         hysteresis = <2000>; /* millicelsius */
 749                                         type = "passive";
 750                                 };
 751                                 target: trip-point@1 {
 752                                         temperature = <85000>; /* millicelsius */
 753                                         hysteresis = <2000>; /* millicelsius */
 754                                         type = "passive";
 755                                 };
 756                                 soc_crit: soc-crit {
 757                                         temperature = <95000>; /* millicelsius */
 758                                         hysteresis = <2000>; /* millicelsius */
 759                                         type = "critical";
 760                                 };
 761                         };
 762
 763                         cooling-maps {
 764                                 map0 {
 765                                         trip = <&target>;
 766                                         cooling-device =
 767                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 768                                         contribution = <4096>;
 769                                 };
 770                                 map1 {
 771                                         trip = <&target>;
 772                                         cooling-device =
 773                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 774                                         contribution = <1024>;
 775                                 };
 776                                 map2 {
 777                                         trip = <&target>;
 778                                         cooling-device =
 779                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 780                                         contribution = <4096>;
 781                                 };
 782                         };
 783                 };
 784
 785                 gpu_thermal: gpu-thermal {
 786                         polling-delay-passive = <100>; /* milliseconds */
 787                         polling-delay = <1000>; /* milliseconds */
 788
 789                         thermal-sensors = <&tsadc 1>;
 790                 };
 791         };
 792
 793         tsadc: tsadc@ff260000 {
 794                 compatible = "rockchip,rk3399-tsadc";
 795                 reg = <0x0 0xff260000 0x0 0x100>;
 796                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 797                 rockchip,grf = <&grf>;
 798                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 799                 clock-names = "tsadc", "apb_pclk";
 800                 assigned-clocks = <&cru SCLK_TSADC>;
 801                 assigned-clock-rates = <750000>;
 802                 resets = <&cru SRST_TSADC>;
 803                 reset-names = "tsadc-apb";
 804                 pinctrl-names = "init", "default", "sleep";
 805                 pinctrl-0 = <&otp_gpio>;
 806                 pinctrl-1 = <&otp_out>;
 807                 pinctrl-2 = <&otp_gpio>;
 808                 #thermal-sensor-cells = <1>;
 809                 rockchip,hw-tshut-temp = <95000>;
 810                 status = "disabled";
 811         };
 812
 813         qos_emmc: qos@ffa58000 {
 814                 compatible = "syscon";
 815                 reg = <0x0 0xffa58000 0x0 0x20>;
 816         };
 817
 818         qos_gmac: qos@ffa5c000 {
 819                 compatible = "syscon";
 820                 reg = <0x0 0xffa5c000 0x0 0x20>;
 821         };
 822
 823         qos_pcie: qos@ffa60080 {
 824                 compatible = "syscon";
 825                 reg = <0x0 0xffa60080 0x0 0x20>;
 826         };
 827
 828         qos_usb_host0: qos@ffa60100 {
 829                 compatible = "syscon";
 830                 reg = <0x0 0xffa60100 0x0 0x20>;
 831         };
 832
 833         qos_usb_host1: qos@ffa60180 {
 834                 compatible = "syscon";
 835                 reg = <0x0 0xffa60180 0x0 0x20>;
 836         };
 837
 838         qos_usb_otg0: qos@ffa70000 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffa70000 0x0 0x20>;
 841         };
 842
 843         qos_usb_otg1: qos@ffa70080 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffa70080 0x0 0x20>;
 846         };
 847
 848         qos_sd: qos@ffa74000 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffa74000 0x0 0x20>;
 851         };
 852
 853         qos_sdioaudio: qos@ffa76000 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffa76000 0x0 0x20>;
 856         };
 857
 858         qos_hdcp: qos@ffa90000 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffa90000 0x0 0x20>;
 861         };
 862
 863         qos_iep: qos@ffa98000 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffa98000 0x0 0x20>;
 866         };
 867
 868         qos_isp0_m0: qos@ffaa0000 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffaa0000 0x0 0x20>;
 871         };
 872
 873         qos_isp0_m1: qos@ffaa0080 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffaa0080 0x0 0x20>;
 876         };
 877
 878         qos_isp1_m0: qos@ffaa8000 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffaa8000 0x0 0x20>;
 881         };
 882
 883         qos_isp1_m1: qos@ffaa8080 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffaa8080 0x0 0x20>;
 886         };
 887
 888         qos_rga_r: qos@ffab0000 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffab0000 0x0 0x20>;
 891         };
 892
 893         qos_rga_w: qos@ffab0080 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffab0080 0x0 0x20>;
 896         };
 897
 898         qos_video_m0: qos@ffab8000 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffab8000 0x0 0x20>;
 901         };
 902
 903         qos_video_m1_r: qos@ffac0000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffac0000 0x0 0x20>;
 906         };
 907
 908         qos_video_m1_w: qos@ffac0080 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffac0080 0x0 0x20>;
 911         };
 912
 913         qos_vop_big_r: qos@ffac8000 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffac8000 0x0 0x20>;
 916         };
 917
 918         qos_vop_big_w: qos@ffac8080 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffac8080 0x0 0x20>;
 921         };
 922
 923         qos_vop_little: qos@ffad0000 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffad0000 0x0 0x20>;
 926         };
 927
 928         qos_perihp: qos@ffad8080 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffad8080 0x0 0x20>;
 931         };
 932
 933         qos_gpu: qos@ffae0000 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffae0000 0x0 0x20>;
 936         };
 937
 938         pmu: power-management@ff310000 {
 939                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 940                 reg = <0x0 0xff310000 0x0 0x1000>;
 941
 942                 /*
 943                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 944                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 945                  * Some of the power domains are grouped together for every
 946                  * voltage domain.
 947                  * The detail contents as below.
 948                  */
 949                 power: power-controller {
 950                         compatible = "rockchip,rk3399-power-controller";
 951                         #power-domain-cells = <1>;
 952                         #address-cells = <1>;
 953                         #size-cells = <0>;
 954
 955                         /* These power domains are grouped by VD_CENTER */
 956                         pd_iep@RK3399_PD_IEP {
 957                                 reg = <RK3399_PD_IEP>;
 958                                 clocks = <&cru ACLK_IEP>,
 959                                          <&cru HCLK_IEP>;
 960                                 pm_qos = <&qos_iep>;
 961                         };
 962                         pd_rga@RK3399_PD_RGA {
 963                                 reg = <RK3399_PD_RGA>;
 964                                 clocks = <&cru ACLK_RGA>,
 965                                          <&cru HCLK_RGA>;
 966                                 pm_qos = <&qos_rga_r>,
 967                                          <&qos_rga_w>;
 968                         };
 969                         pd_vcodec@RK3399_PD_VCODEC {
 970                                 reg = <RK3399_PD_VCODEC>;
 971                                 clocks = <&cru ACLK_VCODEC>,
 972                                          <&cru HCLK_VCODEC>;
 973                                 pm_qos = <&qos_video_m0>;
 974                         };
 975                         pd_vdu@RK3399_PD_VDU {
 976                                 reg = <RK3399_PD_VDU>;
 977                                 clocks = <&cru ACLK_VDU>,
 978                                          <&cru HCLK_VDU>;
 979                                 pm_qos = <&qos_video_m1_r>,
 980                                          <&qos_video_m1_w>;
 981                         };
 982
 983                         /* These power domains are grouped by VD_GPU */
 984                         pd_gpu@RK3399_PD_GPU {
 985                                 reg = <RK3399_PD_GPU>;
 986                                 clocks = <&cru ACLK_GPU>;
 987                                 pm_qos = <&qos_gpu>;
 988                         };
 989
 990                         /* These power domains are grouped by VD_LOGIC */
 991                         pd_edp@RK3399_PD_EDP {
 992                                 reg = <RK3399_PD_EDP>;
 993                                 clocks = <&cru PCLK_EDP_CTRL>;
 994                         };
 995                         pd_emmc@RK3399_PD_EMMC {
 996                                 reg = <RK3399_PD_EMMC>;
 997                                 clocks = <&cru ACLK_EMMC>;
 998                                 pm_qos = <&qos_emmc>;
 999                         };
1000                         pd_gmac@RK3399_PD_GMAC {
1001                                 reg = <RK3399_PD_GMAC>;
1002                                 clocks = <&cru ACLK_GMAC>,
1003                                          <&cru PCLK_GMAC>;
1004                                 pm_qos = <&qos_gmac>;
1005                         };
1006                         pd_perihp@RK3399_PD_PERIHP {
1007                                 reg = <RK3399_PD_PERIHP>;
1008                                 #address-cells = <1>;
1009                                 #size-cells = <0>;
1010                                 clocks = <&cru ACLK_PERIHP>;
1011                                 pm_qos = <&qos_perihp>,
1012                                          <&qos_pcie>,
1013                                          <&qos_usb_host0>,
1014                                          <&qos_usb_host1>;
1015
1016                                 pd_sd@RK3399_PD_SD {
1017                                         reg = <RK3399_PD_SD>;
1018                                         clocks = <&cru HCLK_SDMMC>,
1019                                                  <&cru SCLK_SDMMC>;
1020                                         pm_qos = <&qos_sd>;
1021                                 };
1022                         };
1023                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1024                                 reg = <RK3399_PD_SDIOAUDIO>;
1025                                 clocks = <&cru HCLK_SDIO>;
1026                                 pm_qos = <&qos_sdioaudio>;
1027                         };
1028                         pd_usb3@RK3399_PD_USB3 {
1029                                 reg = <RK3399_PD_USB3>;
1030                                 clocks = <&cru ACLK_USB3>;
1031                                 pm_qos = <&qos_usb_otg0>,
1032                                          <&qos_usb_otg1>;
1033                         };
1034                         pd_vio@RK3399_PD_VIO {
1035                                 reg = <RK3399_PD_VIO>;
1036                                 #address-cells = <1>;
1037                                 #size-cells = <0>;
1038
1039                                 pd_hdcp@RK3399_PD_HDCP {
1040                                         reg = <RK3399_PD_HDCP>;
1041                                         clocks = <&cru ACLK_HDCP>,
1042                                                  <&cru HCLK_HDCP>,
1043                                                  <&cru PCLK_HDCP>;
1044                                         pm_qos = <&qos_hdcp>;
1045                                 };
1046                                 pd_isp0@RK3399_PD_ISP0 {
1047                                         reg = <RK3399_PD_ISP0>;
1048                                         clocks = <&cru ACLK_ISP0>,
1049                                                  <&cru HCLK_ISP0>;
1050                                         pm_qos = <&qos_isp0_m0>,
1051                                                  <&qos_isp0_m1>;
1052                                 };
1053                                 pd_isp1@RK3399_PD_ISP1 {
1054                                         reg = <RK3399_PD_ISP1>;
1055                                         clocks = <&cru ACLK_ISP1>,
1056                                                  <&cru HCLK_ISP1>;
1057                                         pm_qos = <&qos_isp1_m0>,
1058                                                  <&qos_isp1_m1>;
1059                                 };
1060                                 pd_tcpc0@RK3399_PD_TCPC0 {
1061                                         reg = <RK3399_PD_TCPD0>;
1062                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1063                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1064                                 };
1065                                 pd_tcpc1@RK3399_PD_TCPC1 {
1066                                         reg = <RK3399_PD_TCPD1>;
1067                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1068                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1069                                 };
1070                                 pd_vo@RK3399_PD_VO {
1071                                         reg = <RK3399_PD_VO>;
1072                                         #address-cells = <1>;
1073                                         #size-cells = <0>;
1074
1075                                         pd_vopb@RK3399_PD_VOPB {
1076                                                 reg = <RK3399_PD_VOPB>;
1077                                                 clocks = <&cru ACLK_VOP0>,
1078                                                          <&cru HCLK_VOP0>;
1079                                                 pm_qos = <&qos_vop_big_r>,
1080                                                          <&qos_vop_big_w>;
1081                                         };
1082                                         pd_vopl@RK3399_PD_VOPL {
1083                                                 reg = <RK3399_PD_VOPL>;
1084                                                 clocks = <&cru ACLK_VOP1>,
1085                                                          <&cru HCLK_VOP1>;
1086                                                 pm_qos = <&qos_vop_little>;
1087                                         };
1088                                 };
1089                         };
1090                 };
1091         };
1092
1093         pmugrf: syscon@ff320000 {
1094                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1095                 reg = <0x0 0xff320000 0x0 0x1000>;
1096                 #address-cells = <1>;
1097                 #size-cells = <1>;
1098
1099                 pmu_io_domains: io-domains {
1100                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1101                         status = "disabled";
1102                 };
1103
1104                 reboot-mode {
1105                         compatible = "syscon-reboot-mode";
1106                         offset = <0x300>;
1107                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
1108                         mode-charge = <BOOT_CHARGING>;
1109                         mode-fastboot = <BOOT_FASTBOOT>;
1110                         mode-loader = <BOOT_BL_DOWNLOAD>;
1111                         mode-normal = <BOOT_NORMAL>;
1112                         mode-recovery = <BOOT_RECOVERY>;
1113                         mode-ums = <BOOT_UMS>;
1114                 };
1115
1116                 pmu_pvtm: pmu-pvtm {
1117                         compatible = "rockchip,rk3399-pmu-pvtm";
1118                         clocks = <&pmucru SCLK_PVTM_PMU>;
1119                         clock-names = "pmu";
1120                         status = "disabled";
1121                 };
1122         };
1123
1124         spi3: spi@ff350000 {
1125                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1126                 reg = <0x0 0xff350000 0x0 0x1000>;
1127                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1128                 clock-names = "spiclk", "apb_pclk";
1129                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1130                 pinctrl-names = "default";
1131                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1132                 #address-cells = <1>;
1133                 #size-cells = <0>;
1134                 status = "disabled";
1135         };
1136
1137         uart4: serial@ff370000 {
1138                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1139                 reg = <0x0 0xff370000 0x0 0x100>;
1140                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1141                 clock-names = "baudclk", "apb_pclk";
1142                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1143                 reg-shift = <2>;
1144                 reg-io-width = <4>;
1145                 pinctrl-names = "default";
1146                 pinctrl-0 = <&uart4_xfer>;
1147                 status = "disabled";
1148         };
1149
1150         i2c4: i2c@ff3d0000 {
1151                 compatible = "rockchip,rk3399-i2c";
1152                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1153                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1154                 clock-names = "i2c", "pclk";
1155                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1156                 pinctrl-names = "default";
1157                 pinctrl-0 = <&i2c4_xfer>;
1158                 #address-cells = <1>;
1159                 #size-cells = <0>;
1160                 status = "disabled";
1161         };
1162
1163         i2c8: i2c@ff3e0000 {
1164                 compatible = "rockchip,rk3399-i2c";
1165                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1166                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1167                 clock-names = "i2c", "pclk";
1168                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1169                 pinctrl-names = "default";
1170                 pinctrl-0 = <&i2c8_xfer>;
1171                 #address-cells = <1>;
1172                 #size-cells = <0>;
1173                 status = "disabled";
1174         };
1175
1176         pcie_phy: phy@e220 {
1177                 compatible = "rockchip,rk3399-pcie-phy";
1178                 #phy-cells = <0>;
1179                 rockchip,grf = <&grf>;
1180                 clocks = <&cru SCLK_PCIEPHY_REF>;
1181                 clock-names = "refclk";
1182                 resets = <&cru SRST_PCIEPHY>;
1183                 reset-names = "phy";
1184                 status = "disabled";
1185         };
1186
1187         pcie0: pcie@f8000000 {
1188                 compatible = "rockchip,rk3399-pcie";
1189                 #address-cells = <3>;
1190                 #size-cells = <2>;
1191                 aspm-no-l0s;
1192                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1193                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1194                 clock-names = "aclk", "aclk-perf",
1195                               "hclk", "pm";
1196                 bus-range = <0x0 0x1>;
1197                 max-link-speed = <1>;
1198                 linux,pci-domain = <0>;
1199                 msi-map = <0x0 &its 0x0 0x1000>;
1200                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1201                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1202                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1203                 interrupt-names = "sys", "legacy", "client";
1204                 #interrupt-cells = <1>;
1205                 interrupt-map-mask = <0 0 0 7>;
1206                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1207                                 <0 0 0 2 &pcie0_intc 1>,
1208                                 <0 0 0 3 &pcie0_intc 2>,
1209                                 <0 0 0 4 &pcie0_intc 3>;
1210                 phys = <&pcie_phy>;
1211                 phy-names = "pcie-phy";
1212                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1213                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1214                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1215                       <0x0 0xfd000000 0x0 0x1000000>;
1216                 reg-names = "axi-base", "apb-base";
1217                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1218                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1219                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1220                          <&cru SRST_A_PCIE>;
1221                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1222                               "pm", "pclk", "aclk";
1223                 status = "disabled";
1224                 pcie0_intc: interrupt-controller {
1225                         interrupt-controller;
1226                         #address-cells = <0>;
1227                         #interrupt-cells = <1>;
1228                 };
1229         };
1230
1231         pwm0: pwm@ff420000 {
1232                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1233                 reg = <0x0 0xff420000 0x0 0x10>;
1234                 #pwm-cells = <3>;
1235                 pinctrl-names = "default";
1236                 pinctrl-0 = <&pwm0_pin>;
1237                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1238                 clock-names = "pwm";
1239                 status = "disabled";
1240         };
1241
1242         pwm1: pwm@ff420010 {
1243                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1244                 reg = <0x0 0xff420010 0x0 0x10>;
1245                 #pwm-cells = <3>;
1246                 pinctrl-names = "default";
1247                 pinctrl-0 = <&pwm1_pin>;
1248                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1249                 clock-names = "pwm";
1250                 status = "disabled";
1251         };
1252
1253         pwm2: pwm@ff420020 {
1254                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1255                 reg = <0x0 0xff420020 0x0 0x10>;
1256                 #pwm-cells = <3>;
1257                 pinctrl-names = "default";
1258                 pinctrl-0 = <&pwm2_pin>;
1259                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1260                 clock-names = "pwm";
1261                 status = "disabled";
1262         };
1263
1264         pwm3: pwm@ff420030 {
1265                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1266                 reg = <0x0 0xff420030 0x0 0x10>;
1267                 #pwm-cells = <3>;
1268                 pinctrl-names = "default";
1269                 pinctrl-0 = <&pwm3a_pin>;
1270                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1271                 clock-names = "pwm";
1272                 status = "disabled";
1273         };
1274
1275         dfi: dfi@ff630000 {
1276                 reg = <0x00 0xff630000 0x00 0x4000>;
1277                 compatible = "rockchip,rk3399-dfi";
1278                 rockchip,pmu = <&pmugrf>;
1279                 clocks = <&cru PCLK_DDR_MON>;
1280                 clock-names = "pclk_ddr_mon";
1281                 status = "disabled";
1282         };
1283
1284         dmc: dmc {
1285                 compatible = "rockchip,rk3399-dmc";
1286                 devfreq-events = <&dfi>;
1287                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1288                 clocks = <&cru SCLK_DDRCLK>;
1289                 clock-names = "dmc_clk";
1290                 ddr_timing = <&ddr_timing>;
1291                 status = "disabled";
1292         };
1293
1294         vpu: vpu_service@ff650000 {
1295                 compatible = "rockchip,vpu_service";
1296                 rockchip,grf = <&grf>;
1297                 iommus = <&vpu_mmu>;
1298                 iommu_enabled = <1>;
1299                 reg = <0x0 0xff650000 0x0 0x800>;
1300                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1301                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1302                 interrupt-names = "irq_dec", "irq_enc";
1303                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1304                 clock-names = "aclk_vcodec", "hclk_vcodec";
1305                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1306                 reset-names = "video_h", "video_a";
1307                 power-domains = <&power RK3399_PD_VCODEC>;
1308                 name = "vpu_service";
1309                 dev_mode = <0>;
1310                 /* 0 means ion, 1 means drm */
1311                 allocator = <1>;
1312                 status = "disabled";
1313         };
1314
1315         vpu_mmu: iommu@ff650800 {
1316                 compatible = "rockchip,iommu";
1317                 reg = <0x0 0xff650800 0x0 0x40>;
1318                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1319                 interrupt-names = "vpu_mmu";
1320                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1321                 clock-names = "aclk", "hclk";
1322                 power-domains = <&power RK3399_PD_VCODEC>;
1323                 #iommu-cells = <0>;
1324         };
1325
1326         rkvdec: rkvdec@ff660000 {
1327                 compatible = "rockchip,rkvdec";
1328                 rockchip,grf = <&grf>;
1329                 iommus = <&vdec_mmu>;
1330                 iommu_enabled = <1>;
1331                 reg = <0x0 0xff660000 0x0 0x400>;
1332                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1333                 interrupt-names = "irq_dec";
1334                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1335                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1336                 clock-names = "aclk_vcodec", "hclk_vcodec",
1337                               "clk_cabac", "clk_core";
1338                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
1339                         <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
1340                         <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
1341                 reset-names = "video_h", "video_a", "video_core", "video_cabac",
1342                                 "niu_a", "niu_h";
1343                 power-domains = <&power RK3399_PD_VDU>;
1344                 dev_mode = <2>;
1345                 name = "rkvdec";
1346                 /* 0 means ion, 1 means drm */
1347                 allocator = <1>;
1348                 status = "disabled";
1349         };
1350
1351         vdec_mmu: iommu@ff660480 {
1352                 compatible = "rockchip,iommu";
1353                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1354                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1355                 interrupt-names = "vdec_mmu";
1356                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1357                 clock-names = "aclk", "hclk";
1358                 power-domains = <&power RK3399_PD_VDU>;
1359                 #iommu-cells = <0>;
1360         };
1361
1362         iep: iep@ff670000 {
1363                 compatible = "rockchip,iep";
1364                 iommu_enabled = <1>;
1365                 iommus = <&iep_mmu>;
1366                 reg = <0x0 0xff670000 0x0 0x800>;
1367                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1368                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1369                 clock-names = "aclk_iep", "hclk_iep";
1370                 power-domains = <&power RK3399_PD_IEP>;
1371                 allocator = <1>;
1372                 version = <2>;
1373                 status = "disabled";
1374         };
1375
1376         iep_mmu: iommu@ff670800 {
1377                 compatible = "rockchip,iommu";
1378                 reg = <0x0 0xff670800 0x0 0x40>;
1379                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1380                 interrupt-names = "iep_mmu";
1381                 #iommu-cells = <0>;
1382                 status = "disabled";
1383         };
1384
1385         rga: rga@ff680000 {
1386                 compatible = "rockchip,rk3399-rga";
1387                 reg = <0x0 0xff680000 0x0 0x10000>;
1388                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1389                 interrupt-names = "rga";
1390                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1391                 clock-names = "aclk", "hclk", "sclk";
1392                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1393                 reset-names = "core", "axi", "ahb";
1394                 power-domains = <&power RK3399_PD_RGA>;
1395                 status = "disabled";
1396         };
1397
1398         efuse0: efuse@ff690000 {
1399                 compatible = "rockchip,rk3399-efuse";
1400                 reg = <0x0 0xff690000 0x0 0x80>;
1401                 #address-cells = <1>;
1402                 #size-cells = <1>;
1403                 clocks = <&cru PCLK_EFUSE1024NS>;
1404                 clock-names = "pclk_efuse";
1405
1406                 /* Data cells */
1407                 efuse_id: id {
1408                         reg = <0x07 0x10>;
1409                 };
1410                 cpul_leakage: cpul-leakage {
1411                         reg = <0x1a 0x1>;
1412                 };
1413                 cpub_leakage: cpub-leakage {
1414                         reg = <0x17 0x1>;
1415                 };
1416                 gpu_leakage: gpu-leakage {
1417                         reg = <0x18 0x1>;
1418                 };
1419                 center_leakage: center-leakage {
1420                         reg = <0x19 0x1>;
1421                 };
1422                 logic_leakage: logic-leakage {
1423                         reg = <0x1b 0x1>;
1424                 };
1425                 wafer_info: wafer-info {
1426                         reg = <0x1c 0x1>;
1427                 };
1428         };
1429
1430         pmucru: pmu-clock-controller@ff750000 {
1431                 compatible = "rockchip,rk3399-pmucru";
1432                 reg = <0x0 0xff750000 0x0 0x1000>;
1433                 #clock-cells = <1>;
1434                 #reset-cells = <1>;
1435                 assigned-clocks = <&pmucru PLL_PPLL>;
1436                 assigned-clock-rates = <676000000>;
1437         };
1438
1439         cru: clock-controller@ff760000 {
1440                 compatible = "rockchip,rk3399-cru";
1441                 reg = <0x0 0xff760000 0x0 0x1000>;
1442                 #clock-cells = <1>;
1443                 #reset-cells = <1>;
1444                 assigned-clocks =
1445                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1446                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1447                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1448                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1449                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1450                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1451                         <&cru PCLK_PERIHP>,
1452                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1453                         <&cru PCLK_PERILP0>,
1454                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1455                 assigned-clock-rates =
1456                          <400000000>,  <200000000>,
1457                          <400000000>,  <200000000>,
1458                          <816000000>, <816000000>,
1459                          <594000000>,  <800000000>,
1460                          <200000000>, <1000000000>,
1461                          <150000000>,   <75000000>,
1462                           <37500000>,
1463                          <100000000>,  <100000000>,
1464                           <50000000>,
1465                          <100000000>,   <50000000>;
1466         };
1467
1468         grf: syscon@ff770000 {
1469                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1470                 reg = <0x0 0xff770000 0x0 0x10000>;
1471                 #address-cells = <1>;
1472                 #size-cells = <1>;
1473
1474                 io_domains: io-domains {
1475                         compatible = "rockchip,rk3399-io-voltage-domain";
1476                         status = "disabled";
1477                 };
1478
1479                 emmc_phy: phy@f780 {
1480                         compatible = "rockchip,rk3399-emmc-phy";
1481                         reg = <0xf780 0x24>;
1482                         clocks = <&sdhci>;
1483                         clock-names = "emmcclk";
1484                         #phy-cells = <0>;
1485                         status = "disabled";
1486                 };
1487
1488                 u2phy0: usb2-phy@e450 {
1489                         compatible = "rockchip,rk3399-usb2phy";
1490                         reg = <0xe450 0x10>;
1491                         clocks = <&cru SCLK_USB2PHY0_REF>;
1492                         clock-names = "phyclk";
1493                         #clock-cells = <0>;
1494                         clock-output-names = "clk_usbphy0_480m";
1495                         status = "disabled";
1496
1497                         u2phy0_otg: otg-port {
1498                                 #phy-cells = <0>;
1499                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1500                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1501                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1502                                 interrupt-names = "otg-bvalid", "otg-id",
1503                                                   "linestate";
1504                                 status = "disabled";
1505                         };
1506
1507                         u2phy0_host: host-port {
1508                                 #phy-cells = <0>;
1509                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1510                                 interrupt-names = "linestate";
1511                                 status = "disabled";
1512                         };
1513                 };
1514
1515                 u2phy1: usb2-phy@e460 {
1516                         compatible = "rockchip,rk3399-usb2phy";
1517                         reg = <0xe460 0x10>;
1518                         clocks = <&cru SCLK_USB2PHY1_REF>;
1519                         clock-names = "phyclk";
1520                         #clock-cells = <0>;
1521                         clock-output-names = "clk_usbphy1_480m";
1522                         status = "disabled";
1523
1524                         u2phy1_otg: otg-port {
1525                                 #phy-cells = <0>;
1526                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1527                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1528                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1529                                 interrupt-names = "otg-bvalid", "otg-id",
1530                                                   "linestate";
1531                                 status = "disabled";
1532                         };
1533
1534                         u2phy1_host: host-port {
1535                                 #phy-cells = <0>;
1536                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1537                                 interrupt-names = "linestate";
1538                                 status = "disabled";
1539                         };
1540                 };
1541
1542                 pvtm: pvtm {
1543                         compatible = "rockchip,rk3399-pvtm";
1544                         clocks = <&cru SCLK_PVTM_CORE_L>,
1545                                  <&cru SCLK_PVTM_CORE_B>,
1546                                  <&cru SCLK_PVTM_GPU>,
1547                                  <&cru SCLK_PVTM_DDR>;
1548                         clock-names = "core_l", "core_b", "gpu", "ddr";
1549                         status = "disabled";
1550                 };
1551         };
1552
1553         tcphy0: phy@ff7c0000 {
1554                 compatible = "rockchip,rk3399-typec-phy";
1555                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1556                 rockchip,grf = <&grf>;
1557                 #phy-cells = <1>;
1558                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1559                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1560                 clock-names = "tcpdcore", "tcpdphy-ref";
1561                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1562                 assigned-clock-rates = <50000000>;
1563                 power-domains = <&power RK3399_PD_TCPD0>;
1564                 resets = <&cru SRST_UPHY0>,
1565                          <&cru SRST_UPHY0_PIPE_L00>,
1566                          <&cru SRST_P_UPHY0_TCPHY>;
1567                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1568                 rockchip,typec-conn-dir = <0xe580 0 16>;
1569                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1570                 rockchip,usb3-host-disable = <0x2434 0 16>;
1571                 rockchip,usb3-host-port = <0x2434 12 28>;
1572                 rockchip,external-psm = <0xe588 14 30>;
1573                 rockchip,pipe-status = <0xe5c0 0 0>;
1574                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1575                 status = "disabled";
1576
1577                 tcphy0_dp: dp-port {
1578                         #phy-cells = <0>;
1579                 };
1580
1581                 tcphy0_usb3: usb3-port {
1582                         #phy-cells = <0>;
1583                 };
1584         };
1585
1586         tcphy1: phy@ff800000 {
1587                 compatible = "rockchip,rk3399-typec-phy";
1588                 reg = <0x0 0xff800000 0x0 0x40000>;
1589                 rockchip,grf = <&grf>;
1590                 #phy-cells = <1>;
1591                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1592                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1593                 clock-names = "tcpdcore", "tcpdphy-ref";
1594                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1595                 assigned-clock-rates = <50000000>;
1596                 power-domains = <&power RK3399_PD_TCPD1>;
1597                 resets = <&cru SRST_UPHY1>,
1598                          <&cru SRST_UPHY1_PIPE_L00>,
1599                          <&cru SRST_P_UPHY1_TCPHY>;
1600                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1601                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1602                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1603                 rockchip,usb3-host-disable = <0x2444 0 16>;
1604                 rockchip,usb3-host-port = <0x2444 12 28>;
1605                 rockchip,external-psm = <0xe594 14 30>;
1606                 rockchip,pipe-status = <0xe5c0 16 16>;
1607                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1608                 status = "disabled";
1609
1610                 tcphy1_dp: dp-port {
1611                         #phy-cells = <0>;
1612                 };
1613
1614                 tcphy1_usb3: usb3-port {
1615                         #phy-cells = <0>;
1616                 };
1617         };
1618
1619         watchdog@ff848000 {
1620                 compatible = "snps,dw-wdt";
1621                 reg = <0x0 0xff848000 0x0 0x100>;
1622                 clocks = <&cru PCLK_WDT>;
1623                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1624         };
1625
1626         rktimer: rktimer@ff850000 {
1627                 compatible = "rockchip,rk3399-timer";
1628                 reg = <0x0 0xff850000 0x0 0x1000>;
1629                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1630                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1631                 clock-names = "pclk", "timer";
1632         };
1633
1634         spdif: spdif@ff870000 {
1635                 compatible = "rockchip,rk3399-spdif";
1636                 reg = <0x0 0xff870000 0x0 0x1000>;
1637                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1638                 dmas = <&dmac_bus 7>;
1639                 dma-names = "tx";
1640                 clock-names = "mclk", "hclk";
1641                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1642                 pinctrl-names = "default";
1643                 pinctrl-0 = <&spdif_bus>;
1644                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1645                 status = "disabled";
1646         };
1647
1648         i2s0: i2s@ff880000 {
1649                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1650                 reg = <0x0 0xff880000 0x0 0x1000>;
1651                 rockchip,grf = <&grf>;
1652                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1653                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1654                 dma-names = "tx", "rx";
1655                 clock-names = "i2s_clk", "i2s_hclk";
1656                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1657                 pinctrl-names = "default";
1658                 pinctrl-0 = <&i2s0_8ch_bus>;
1659                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1660                 status = "disabled";
1661         };
1662
1663         i2s1: i2s@ff890000 {
1664                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1665                 reg = <0x0 0xff890000 0x0 0x1000>;
1666                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1667                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1668                 dma-names = "tx", "rx";
1669                 clock-names = "i2s_clk", "i2s_hclk";
1670                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1671                 pinctrl-names = "default";
1672                 pinctrl-0 = <&i2s1_2ch_bus>;
1673                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1674                 status = "disabled";
1675         };
1676
1677         i2s2: i2s@ff8a0000 {
1678                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1679                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1680                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1681                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1682                 dma-names = "tx", "rx";
1683                 clock-names = "i2s_clk", "i2s_hclk";
1684                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1685                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1686                 status = "disabled";
1687         };
1688
1689         gpu: gpu@ff9a0000 {
1690                 compatible = "arm,malit860",
1691                              "arm,malit86x",
1692                              "arm,malit8xx",
1693                              "arm,mali-midgard";
1694
1695                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1696
1697                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1698                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1699                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1700                 interrupt-names = "GPU", "JOB", "MMU";
1701
1702                 clocks = <&cru ACLK_GPU>;
1703                 clock-names = "clk_mali";
1704                 #cooling-cells = <2>; /* min followed by max */
1705                 power-domains = <&power RK3399_PD_GPU>;
1706                 power-off-delay-ms = <200>;
1707                 status = "disabled";
1708
1709                 gpu_power_model: power_model {
1710                         compatible = "arm,mali-simple-power-model";
1711                         voltage = <900>;
1712                         frequency = <500>;
1713                         static-power = <300>;
1714                         dynamic-power = <396>;
1715                         ts = <32000 4700 (-80) 2>;
1716                         thermal-zone = "gpu-thermal";
1717                 };
1718         };
1719
1720         vopl: vop@ff8f0000 {
1721                 compatible = "rockchip,rk3399-vop-lit";
1722                 reg = <0x0 0xff8f0000 0x0 0x600>,
1723                         <0x0 0xff8f1c00 0x0 0x200>,
1724                         <0x0 0xff8f2000 0x0 0x400>;
1725                 reg-names = "regs", "cabc_lut", "gamma_lut";
1726                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1727                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
1728                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1729                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1730                 reset-names = "axi", "ahb", "dclk";
1731                 power-domains = <&power RK3399_PD_VOPL>;
1732                 iommus = <&vopl_mmu>;
1733                 status = "disabled";
1734
1735                 vopl_out: port {
1736                         #address-cells = <1>;
1737                         #size-cells = <0>;
1738
1739                         vopl_out_dsi: endpoint@0 {
1740                                 reg = <0>;
1741                                 remote-endpoint = <&dsi_in_vopl>;
1742                         };
1743
1744                         vopl_out_edp: endpoint@1 {
1745                                 reg = <1>;
1746                                 remote-endpoint = <&edp_in_vopl>;
1747                         };
1748
1749                         vopl_out_hdmi: endpoint@2 {
1750                                 reg = <2>;
1751                                 remote-endpoint = <&hdmi_in_vopl>;
1752                         };
1753
1754                         vopl_out_dp: endpoint@3 {
1755                                 reg = <3>;
1756                                 remote-endpoint = <&dp_in_vopl>;
1757                         };
1758
1759                         vopl_out_dsi1: endpoint@4 {
1760                                 reg = <4>;
1761                                 remote-endpoint = <&dsi1_in_vopl>;
1762                         };
1763                 };
1764         };
1765
1766         vop1_pwm: voppwm@ff8f01a0 {
1767                 compatible = "rockchip,vop-pwm";
1768                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1769                 #pwm-cells = <3>;
1770                 pinctrl-names = "default";
1771                 pinctrl-0 = <&vop1_pwm_pin>;
1772                 clocks = <&cru SCLK_VOP1_PWM>;
1773                 clock-names = "pwm";
1774                 status = "disabled";
1775         };
1776
1777         vopl_mmu: iommu@ff8f3f00 {
1778                 compatible = "rockchip,iommu";
1779                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1780                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1781                 interrupt-names = "vopl_mmu";
1782                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1783                 clock-names = "aclk", "hclk";
1784                 power-domains = <&power RK3399_PD_VOPL>;
1785                 #iommu-cells = <0>;
1786                 status = "disabled";
1787         };
1788
1789         vopb: vop@ff900000 {
1790                 compatible = "rockchip,rk3399-vop-big";
1791                 reg = <0x0 0xff900000 0x0 0x600>,
1792                         <0x0 0xff901c00 0x0 0x200>,
1793                         <0x0 0xff902000 0x0 0x1000>;
1794                 reg-names = "regs", "cabc_lut", "gamma_lut";
1795                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1796                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
1797                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1798                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1799                 reset-names = "axi", "ahb", "dclk";
1800                 power-domains = <&power RK3399_PD_VOPB>;
1801                 iommus = <&vopb_mmu>;
1802                 status = "disabled";
1803
1804                 vopb_out: port {
1805                         #address-cells = <1>;
1806                         #size-cells = <0>;
1807
1808                         vopb_out_edp: endpoint@0 {
1809                                 reg = <0>;
1810                                 remote-endpoint = <&edp_in_vopb>;
1811                         };
1812
1813                         vopb_out_dsi: endpoint@1 {
1814                                 reg = <1>;
1815                                 remote-endpoint = <&dsi_in_vopb>;
1816                         };
1817
1818                         vopb_out_hdmi: endpoint@2 {
1819                                 reg = <2>;
1820                                 remote-endpoint = <&hdmi_in_vopb>;
1821                         };
1822
1823                         vopb_out_dp: endpoint@3 {
1824                                 reg = <3>;
1825                                 remote-endpoint = <&dp_in_vopb>;
1826                         };
1827
1828                         vopb_out_dsi1: endpoint@4 {
1829                                 reg = <4>;
1830                                 remote-endpoint = <&dsi1_in_vopb>;
1831                         };
1832                 };
1833         };
1834
1835         vop0_pwm: voppwm@ff9001a0 {
1836                 compatible = "rockchip,vop-pwm";
1837                 reg = <0x0 0xff9001a0 0x0 0x10>;
1838                 #pwm-cells = <3>;
1839                 pinctrl-names = "default";
1840                 pinctrl-0 = <&vop0_pwm_pin>;
1841                 clocks = <&cru SCLK_VOP0_PWM>;
1842                 clock-names = "pwm";
1843                 status = "disabled";
1844         };
1845
1846         vopb_mmu: iommu@ff903f00 {
1847                 compatible = "rockchip,iommu";
1848                 reg = <0x0 0xff903f00 0x0 0x100>;
1849                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1850                 interrupt-names = "vopb_mmu";
1851                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1852                 clock-names = "aclk", "hclk";
1853                 power-domains = <&power RK3399_PD_VOPB>;
1854                 #iommu-cells = <0>;
1855                 status = "disabled";
1856         };
1857
1858         isp0_mmu: iommu@ff914000 {
1859                 compatible = "rockchip,iommu";
1860                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1861                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1862                 interrupt-names = "isp0_mmu";
1863                 #iommu-cells = <0>;
1864                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1865                 clock-names = "aclk", "hclk";
1866                 power-domains = <&power RK3399_PD_ISP0>;
1867                 rk_iommu,disable_reset_quirk;
1868                 status = "disabled";
1869         };
1870
1871         isp1_mmu: iommu@ff924000 {
1872                 compatible = "rockchip,iommu";
1873                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1874                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1875                 interrupt-names = "isp1_mmu";
1876                 #iommu-cells = <0>;
1877                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1878                 clock-names = "aclk", "hclk";
1879                 power-domains = <&power RK3399_PD_ISP1>;
1880                 rk_iommu,disable_reset_quirk;
1881                 status = "disabled";
1882         };
1883
1884         hdmi: hdmi@ff940000 {
1885                 compatible = "rockchip,rk3399-dw-hdmi";
1886                 reg = <0x0 0xff940000 0x0 0x20000>;
1887                 reg-io-width = <4>;
1888                 rockchip,grf = <&grf>;
1889                 pinctrl-names = "default";
1890                 pinctrl-0 = <&hdmi_i2c_xfer>;
1891                 power-domains = <&power RK3399_PD_HDCP>;
1892                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1893                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1894                 clock-names = "iahb", "isfr", "vpll", "grf";
1895                 status = "disabled";
1896
1897                 ports {
1898                         hdmi_in: port {
1899                                 #address-cells = <1>;
1900                                 #size-cells = <0>;
1901                                 hdmi_in_vopb: endpoint@0 {
1902                                         reg = <0>;
1903                                         remote-endpoint = <&vopb_out_hdmi>;
1904                                 };
1905                                 hdmi_in_vopl: endpoint@1 {
1906                                         reg = <1>;
1907                                         remote-endpoint = <&vopl_out_hdmi>;
1908                                 };
1909                         };
1910                 };
1911         };
1912
1913         dsi: dsi@ff960000 {
1914                 compatible = "rockchip,rk3399-mipi-dsi";
1915                 reg = <0x0 0xff960000 0x0 0x8000>;
1916                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1917                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1918                          <&cru SCLK_DPHY_TX0_CFG>;
1919                 clock-names = "ref", "pclk", "phy_cfg";
1920                 resets = <&cru SRST_P_MIPI_DSI0>;
1921                 reset-names = "apb";
1922                 power-domains = <&power RK3399_PD_VIO>;
1923                 rockchip,grf = <&grf>;
1924                 #address-cells = <1>;
1925                 #size-cells = <0>;
1926                 status = "disabled";
1927
1928                 ports {
1929                         port {
1930                                 #address-cells = <1>;
1931                                 #size-cells = <0>;
1932
1933                                 dsi_in_vopb: endpoint@0 {
1934                                         reg = <0>;
1935                                         remote-endpoint = <&vopb_out_dsi>;
1936                                 };
1937
1938                                 dsi_in_vopl: endpoint@1 {
1939                                         reg = <1>;
1940                                         remote-endpoint = <&vopl_out_dsi>;
1941                                 };
1942                         };
1943                 };
1944         };
1945
1946         dsi1: dsi@ff968000 {
1947                 compatible = "rockchip,rk3399-mipi-dsi";
1948                 reg = <0x0 0xff968000 0x0 0x8000>;
1949                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1950                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1951                          <&cru SCLK_DPHY_TX1RX1_CFG>;
1952                 clock-names = "ref", "pclk", "phy_cfg";
1953                 resets = <&cru SRST_P_MIPI_DSI1>;
1954                 reset-names = "apb";
1955                 power-domains = <&power RK3399_PD_VIO>;
1956                 rockchip,grf = <&grf>;
1957                 #address-cells = <1>;
1958                 #size-cells = <0>;
1959                 status = "disabled";
1960
1961                 ports {
1962                         port {
1963                                 #address-cells = <1>;
1964                                 #size-cells = <0>;
1965
1966                                 dsi1_in_vopb: endpoint@0 {
1967                                         reg = <0>;
1968                                         remote-endpoint = <&vopb_out_dsi1>;
1969                                 };
1970
1971                                 dsi1_in_vopl: endpoint@1 {
1972                                         reg = <1>;
1973                                         remote-endpoint = <&vopl_out_dsi1>;
1974                                 };
1975                         };
1976                 };
1977         };
1978
1979         edp: edp@ff970000 {
1980                 compatible = "rockchip,rk3399-edp";
1981                 reg = <0x0 0xff970000 0x0 0x8000>;
1982                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1983                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1984                 clock-names = "dp", "pclk";
1985                 power-domains = <&power RK3399_PD_EDP>;
1986                 resets = <&cru SRST_P_EDP_CTRL>;
1987                 reset-names = "dp";
1988                 rockchip,grf = <&grf>;
1989                 status = "disabled";
1990                 pinctrl-names = "default";
1991                 pinctrl-0 = <&edp_hpd>;
1992
1993                 ports {
1994                         #address-cells = <1>;
1995                         #size-cells = <0>;
1996
1997                         edp_in: port@0 {
1998                                 reg = <0>;
1999                                 #address-cells = <1>;
2000                                 #size-cells = <0>;
2001
2002                                 edp_in_vopb: endpoint@0 {
2003                                         reg = <0>;
2004                                         remote-endpoint = <&vopb_out_edp>;
2005                                 };
2006
2007                                 edp_in_vopl: endpoint@1 {
2008                                         reg = <1>;
2009                                         remote-endpoint = <&vopl_out_edp>;
2010                                 };
2011                         };
2012                 };
2013         };
2014
2015         display_subsystem: display-subsystem {
2016                 compatible = "rockchip,display-subsystem";
2017                 ports = <&vopl_out>, <&vopb_out>;
2018                 clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
2019                 clock-names = "hdmi-tmds-pll", "default-vop-pll";
2020                 status = "disabled";
2021         };
2022
2023         pinctrl: pinctrl {
2024                 compatible = "rockchip,rk3399-pinctrl";
2025                 rockchip,grf = <&grf>;
2026                 rockchip,pmu = <&pmugrf>;
2027                 #address-cells = <0x2>;
2028                 #size-cells = <0x2>;
2029                 ranges;
2030
2031                 gpio0: gpio0@ff720000 {
2032                         compatible = "rockchip,gpio-bank";
2033                         reg = <0x0 0xff720000 0x0 0x100>;
2034                         clocks = <&pmucru PCLK_GPIO0_PMU>;
2035                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
2036
2037                         gpio-controller;
2038                         #gpio-cells = <0x2>;
2039
2040                         interrupt-controller;
2041                         #interrupt-cells = <0x2>;
2042                 };
2043
2044                 gpio1: gpio1@ff730000 {
2045                         compatible = "rockchip,gpio-bank";
2046                         reg = <0x0 0xff730000 0x0 0x100>;
2047                         clocks = <&pmucru PCLK_GPIO1_PMU>;
2048                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2049
2050                         gpio-controller;
2051                         #gpio-cells = <0x2>;
2052
2053                         interrupt-controller;
2054                         #interrupt-cells = <0x2>;
2055                 };
2056
2057                 gpio2: gpio2@ff780000 {
2058                         compatible = "rockchip,gpio-bank";
2059                         reg = <0x0 0xff780000 0x0 0x100>;
2060                         clocks = <&cru PCLK_GPIO2>;
2061                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2062
2063                         gpio-controller;
2064                         #gpio-cells = <0x2>;
2065
2066                         interrupt-controller;
2067                         #interrupt-cells = <0x2>;
2068                 };
2069
2070                 gpio3: gpio3@ff788000 {
2071                         compatible = "rockchip,gpio-bank";
2072                         reg = <0x0 0xff788000 0x0 0x100>;
2073                         clocks = <&cru PCLK_GPIO3>;
2074                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2075
2076                         gpio-controller;
2077                         #gpio-cells = <0x2>;
2078
2079                         interrupt-controller;
2080                         #interrupt-cells = <0x2>;
2081                 };
2082
2083                 gpio4: gpio4@ff790000 {
2084                         compatible = "rockchip,gpio-bank";
2085                         reg = <0x0 0xff790000 0x0 0x100>;
2086                         clocks = <&cru PCLK_GPIO4>;
2087                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2088
2089                         gpio-controller;
2090                         #gpio-cells = <0x2>;
2091
2092                         interrupt-controller;
2093                         #interrupt-cells = <0x2>;
2094                 };
2095
2096                 pcfg_pull_up: pcfg-pull-up {
2097                         bias-pull-up;
2098                 };
2099
2100                 pcfg_pull_down: pcfg-pull-down {
2101                         bias-pull-down;
2102                 };
2103
2104                 pcfg_pull_none: pcfg-pull-none {
2105                         bias-disable;
2106                 };
2107
2108                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2109                         bias-pull-up;
2110                         drive-strength = <20>;
2111                 };
2112
2113                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2114                         bias-disable;
2115                         drive-strength = <20>;
2116                 };
2117
2118                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2119                         bias-disable;
2120                         drive-strength = <18>;
2121                 };
2122
2123                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2124                         bias-disable;
2125                         drive-strength = <12>;
2126                 };
2127
2128                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2129                         bias-pull-up;
2130                         drive-strength = <8>;
2131                 };
2132
2133                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2134                         bias-pull-down;
2135                         drive-strength = <4>;
2136                 };
2137
2138                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2139                         bias-pull-up;
2140                         drive-strength = <2>;
2141                 };
2142
2143                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2144                         bias-pull-down;
2145                         drive-strength = <12>;
2146                 };
2147
2148                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2149                         bias-disable;
2150                         drive-strength = <13>;
2151                 };
2152
2153                 pcfg_output_high: pcfg-output-high {
2154                         output-high;
2155                 };
2156
2157                 pcfg_output_low: pcfg-output-low {
2158                         output-low;
2159                 };
2160
2161                 pcfg_input: pcfg-input {
2162                         input-enable;
2163                 };
2164
2165                 emmc {
2166                         emmc_pwr: emmc-pwr {
2167                                 rockchip,pins =
2168                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2169                         };
2170                 };
2171
2172                 gmac {
2173                         rgmii_pins: rgmii-pins {
2174                                 rockchip,pins =
2175                                         /* mac_txclk */
2176                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2177                                         /* mac_rxclk */
2178                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2179                                         /* mac_mdio */
2180                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2181                                         /* mac_txen */
2182                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2183                                         /* mac_clk */
2184                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2185                                         /* mac_rxdv */
2186                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2187                                         /* mac_mdc */
2188                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2189                                         /* mac_rxd1 */
2190                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2191                                         /* mac_rxd0 */
2192                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2193                                         /* mac_txd1 */
2194                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2195                                         /* mac_txd0 */
2196                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2197                                         /* mac_rxd3 */
2198                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2199                                         /* mac_rxd2 */
2200                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2201                                         /* mac_txd3 */
2202                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2203                                         /* mac_txd2 */
2204                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2205                         };
2206
2207                         rmii_pins: rmii-pins {
2208                                 rockchip,pins =
2209                                         /* mac_mdio */
2210                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2211                                         /* mac_txen */
2212                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2213                                         /* mac_clk */
2214                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2215                                         /* mac_rxer */
2216                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2217                                         /* mac_rxdv */
2218                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2219                                         /* mac_mdc */
2220                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2221                                         /* mac_rxd1 */
2222                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2223                                         /* mac_rxd0 */
2224                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2225                                         /* mac_txd1 */
2226                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2227                                         /* mac_txd0 */
2228                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2229                         };
2230                 };
2231
2232                 i2c0 {
2233                         i2c0_xfer: i2c0-xfer {
2234                                 rockchip,pins =
2235                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2236                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2237                         };
2238                 };
2239
2240                 i2c1 {
2241                         i2c1_xfer: i2c1-xfer {
2242                                 rockchip,pins =
2243                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2244                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2245                         };
2246                 };
2247
2248                 i2c2 {
2249                         i2c2_xfer: i2c2-xfer {
2250                                 rockchip,pins =
2251                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2252                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2253                         };
2254                 };
2255
2256                 i2c3 {
2257                         i2c3_xfer: i2c3-xfer {
2258                                 rockchip,pins =
2259                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2260                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2261                         };
2262
2263                         i2c3_gpio: i2c3_gpio {
2264                                 rockchip,pins =
2265                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2266                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2267                         };
2268
2269                 };
2270
2271                 i2c4 {
2272                         i2c4_xfer: i2c4-xfer {
2273                                 rockchip,pins =
2274                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2275                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2276                         };
2277                 };
2278
2279                 i2c5 {
2280                         i2c5_xfer: i2c5-xfer {
2281                                 rockchip,pins =
2282                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2283                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2284                         };
2285                 };
2286
2287                 i2c6 {
2288                         i2c6_xfer: i2c6-xfer {
2289                                 rockchip,pins =
2290                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2291                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2292                         };
2293                 };
2294
2295                 i2c7 {
2296                         i2c7_xfer: i2c7-xfer {
2297                                 rockchip,pins =
2298                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2299                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2300                         };
2301                 };
2302
2303                 i2c8 {
2304                         i2c8_xfer: i2c8-xfer {
2305                                 rockchip,pins =
2306                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2307                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2308                         };
2309                 };
2310
2311                 i2s0 {
2312                         i2s0_8ch_bus: i2s0-8ch-bus {
2313                                 rockchip,pins =
2314                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2315                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2316                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2317                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2318                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2319                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2320                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2321                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2322                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2323                         };
2324                 };
2325
2326                 i2s1 {
2327                         i2s1_2ch_bus: i2s1-2ch-bus {
2328                                 rockchip,pins =
2329                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2330                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2331                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2332                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2333                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2334                         };
2335                 };
2336
2337                 sdio0 {
2338                         sdio0_bus1: sdio0-bus1 {
2339                                 rockchip,pins =
2340                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2341                         };
2342
2343                         sdio0_bus4: sdio0-bus4 {
2344                                 rockchip,pins =
2345                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2346                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2347                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2348                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2349                         };
2350
2351                         sdio0_cmd: sdio0-cmd {
2352                                 rockchip,pins =
2353                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2354                         };
2355
2356                         sdio0_clk: sdio0-clk {
2357                                 rockchip,pins =
2358                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2359                         };
2360
2361                         sdio0_cd: sdio0-cd {
2362                                 rockchip,pins =
2363                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2364                         };
2365
2366                         sdio0_pwr: sdio0-pwr {
2367                                 rockchip,pins =
2368                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2369                         };
2370
2371                         sdio0_bkpwr: sdio0-bkpwr {
2372                                 rockchip,pins =
2373                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2374                         };
2375
2376                         sdio0_wp: sdio0-wp {
2377                                 rockchip,pins =
2378                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2379                         };
2380
2381                         sdio0_int: sdio0-int {
2382                                 rockchip,pins =
2383                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2384                         };
2385                 };
2386
2387                 sdmmc {
2388                         sdmmc_bus1: sdmmc-bus1 {
2389                                 rockchip,pins =
2390                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2391                         };
2392
2393                         sdmmc_bus4: sdmmc-bus4 {
2394                                 rockchip,pins =
2395                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2396                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2397                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2398                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2399                         };
2400
2401                         sdmmc_clk: sdmmc-clk {
2402                                 rockchip,pins =
2403                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2404                         };
2405
2406                         sdmmc_cmd: sdmmc-cmd {
2407                                 rockchip,pins =
2408                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2409                         };
2410
2411                         sdmmc_cd: sdmcc-cd {
2412                                 rockchip,pins =
2413                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2414                         };
2415
2416                         sdmmc_wp: sdmmc-wp {
2417                                 rockchip,pins =
2418                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2419                         };
2420                 };
2421
2422                 spdif {
2423                         spdif_bus: spdif-bus {
2424                                 rockchip,pins =
2425                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2426                         };
2427
2428                         spdif_bus_1: spdif-bus-1 {
2429                                 rockchip,pins =
2430                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2431                         };
2432                 };
2433
2434                 spi0 {
2435                         spi0_clk: spi0-clk {
2436                                 rockchip,pins =
2437                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2438                         };
2439                         spi0_cs0: spi0-cs0 {
2440                                 rockchip,pins =
2441                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2442                         };
2443                         spi0_cs1: spi0-cs1 {
2444                                 rockchip,pins =
2445                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2446                         };
2447                         spi0_tx: spi0-tx {
2448                                 rockchip,pins =
2449                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2450                         };
2451                         spi0_rx: spi0-rx {
2452                                 rockchip,pins =
2453                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2454                         };
2455                 };
2456
2457                 spi1 {
2458                         spi1_clk: spi1-clk {
2459                                 rockchip,pins =
2460                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2461                         };
2462                         spi1_cs0: spi1-cs0 {
2463                                 rockchip,pins =
2464                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2465                         };
2466                         spi1_rx: spi1-rx {
2467                                 rockchip,pins =
2468                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2469                         };
2470                         spi1_tx: spi1-tx {
2471                                 rockchip,pins =
2472                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2473                         };
2474                 };
2475
2476                 spi2 {
2477                         spi2_clk: spi2-clk {
2478                                 rockchip,pins =
2479                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2480                         };
2481                         spi2_cs0: spi2-cs0 {
2482                                 rockchip,pins =
2483                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2484                         };
2485                         spi2_rx: spi2-rx {
2486                                 rockchip,pins =
2487                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2488                         };
2489                         spi2_tx: spi2-tx {
2490                                 rockchip,pins =
2491                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2492                         };
2493                 };
2494
2495                 spi3 {
2496                         spi3_clk: spi3-clk {
2497                                 rockchip,pins =
2498                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2499                         };
2500                         spi3_cs0: spi3-cs0 {
2501                                 rockchip,pins =
2502                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2503                         };
2504                         spi3_rx: spi3-rx {
2505                                 rockchip,pins =
2506                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2507                         };
2508                         spi3_tx: spi3-tx {
2509                                 rockchip,pins =
2510                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2511                         };
2512                 };
2513
2514                 spi4 {
2515                         spi4_clk: spi4-clk {
2516                                 rockchip,pins =
2517                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2518                         };
2519                         spi4_cs0: spi4-cs0 {
2520                                 rockchip,pins =
2521                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2522                         };
2523                         spi4_rx: spi4-rx {
2524                                 rockchip,pins =
2525                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2526                         };
2527                         spi4_tx: spi4-tx {
2528                                 rockchip,pins =
2529                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2530                         };
2531                 };
2532
2533                 spi5 {
2534                         spi5_clk: spi5-clk {
2535                                 rockchip,pins =
2536                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2537                         };
2538                         spi5_cs0: spi5-cs0 {
2539                                 rockchip,pins =
2540                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2541                         };
2542                         spi5_rx: spi5-rx {
2543                                 rockchip,pins =
2544                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2545                         };
2546                         spi5_tx: spi5-tx {
2547                                 rockchip,pins =
2548                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2549                         };
2550                 };
2551
2552                 tsadc {
2553                         otp_gpio: otp-gpio {
2554                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2555                         };
2556
2557                         otp_out: otp-out {
2558                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2559                         };
2560                 };
2561
2562                 uart0 {
2563                         uart0_xfer: uart0-xfer {
2564                                 rockchip,pins =
2565                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2566                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2567                         };
2568
2569                         uart0_cts: uart0-cts {
2570                                 rockchip,pins =
2571                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2572                         };
2573
2574                         uart0_rts: uart0-rts {
2575                                 rockchip,pins =
2576                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2577                         };
2578                 };
2579
2580                 uart1 {
2581                         uart1_xfer: uart1-xfer {
2582                                 rockchip,pins =
2583                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2584                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2585                         };
2586                 };
2587
2588                 uart2a {
2589                         uart2a_xfer: uart2a-xfer {
2590                                 rockchip,pins =
2591                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2592                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2593                         };
2594                 };
2595
2596                 uart2b {
2597                         uart2b_xfer: uart2b-xfer {
2598                                 rockchip,pins =
2599                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2600                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2601                         };
2602                 };
2603
2604                 uart2c {
2605                         uart2c_xfer: uart2c-xfer {
2606                                 rockchip,pins =
2607                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2608                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2609                         };
2610                 };
2611
2612                 uart3 {
2613                         uart3_xfer: uart3-xfer {
2614                                 rockchip,pins =
2615                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2616                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2617                         };
2618
2619                         uart3_cts: uart3-cts {
2620                                 rockchip,pins =
2621                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2622                         };
2623
2624                         uart3_rts: uart3-rts {
2625                                 rockchip,pins =
2626                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2627                         };
2628                 };
2629
2630                 uart4 {
2631                         uart4_xfer: uart4-xfer {
2632                                 rockchip,pins =
2633                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2634                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2635                         };
2636                 };
2637
2638                 uarthdcp {
2639                         uarthdcp_xfer: uarthdcp-xfer {
2640                                 rockchip,pins =
2641                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2642                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2643                         };
2644                 };
2645
2646                 pwm0 {
2647                         pwm0_pin: pwm0-pin {
2648                                 rockchip,pins =
2649                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2650                         };
2651
2652                         vop0_pwm_pin: vop0-pwm-pin {
2653                                 rockchip,pins =
2654                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2655                         };
2656                 };
2657
2658                 pwm1 {
2659                         pwm1_pin: pwm1-pin {
2660                                 rockchip,pins =
2661                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2662                         };
2663
2664                         vop1_pwm_pin: vop1-pwm-pin {
2665                                 rockchip,pins =
2666                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2667                         };
2668                 };
2669
2670                 pwm2 {
2671                         pwm2_pin: pwm2-pin {
2672                                 rockchip,pins =
2673                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2674                         };
2675                 };
2676
2677                 pwm3a {
2678                         pwm3a_pin: pwm3a-pin {
2679                                 rockchip,pins =
2680                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2681                         };
2682                 };
2683
2684                 pwm3b {
2685                         pwm3b_pin: pwm3b-pin {
2686                                 rockchip,pins =
2687                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2688                         };
2689                 };
2690
2691                 edp {
2692                         edp_hpd: edp-hpd {
2693                                 rockchip,pins =
2694                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2695                         };
2696                 };
2697
2698                 hdmi {
2699                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2700                                 rockchip,pins =
2701                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2702                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2703                         };
2704
2705                         hdmi_cec: hdmi-cec {
2706                                 rockchip,pins =
2707                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2708                         };
2709                 };
2710
2711                 pcie {
2712                         pcie_clkreqn: pci-clkreqn {
2713                                 rockchip,pins =
2714                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2715                         };
2716
2717                         pcie_clkreqnb: pci-clkreqnb {
2718                                 rockchip,pins =
2719                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2720                         };
2721
2722                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2723                                 /*
2724                                  * Since our pcie doesn't support
2725                                  * ClockPM(CPM), we want to hack this as
2726                                  * gpio, so the EP could be able to
2727                                  * de-assert it along and make ClockPM(CPM)
2728                                  * work.
2729                                  */
2730                                 rockchip,pins =
2731                                         <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2732                         };
2733
2734                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2735                                 rockchip,pins =
2736                                         <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2737                         };
2738                 };
2739         };
2740
2741         rockchip_suspend: rockchip-suspend {
2742                 compatible = "rockchip,pm-rk3399";
2743                 status = "disabled";
2744                 rockchip,sleep-debug-en = <0>;
2745                 rockchip,virtual-poweroff = <0>;
2746                 rockchip,sleep-mode-config = <
2747                         (0
2748                         | RKPM_SLP_ARMPD
2749                         | RKPM_SLP_PERILPPD
2750                         | RKPM_SLP_DDR_RET
2751                         | RKPM_SLP_PLLPD
2752                         | RKPM_SLP_OSC_DIS
2753                         | RKPM_SLP_CENTER_PD
2754                         | RKPM_SLP_AP_PWROFF
2755                         )
2756                 >;
2757                 rockchip,wakeup-config = <
2758                         (0
2759                         | RKPM_GPIO_WKUP_EN
2760                         )
2761                 >;
2762         };
2763 };